This is an archive of the discontinued LLVM Phabricator instance.

Differential D77069

[ARM][MVE] Add patterns for VRHADD
ClosedPublic

Authored by samparker on Mar 30 2020, 9:10 AM.

Details

Reviewers
dmgreen
simon_tatham
olista01
SjoerdMeijer
Commits
rG62f97123fbef: [ARM][MVE] Add patterns for VRHADD
Summary

Add patterns which use standard add nodes along with arm vshr imm nodes.

Diff Detail

Unit TestsFailed

TimeTest
50 msLLVM.CodeGen/Thumb2::Unknown Unit Message ("")

Event Timeline

samparker created this revision.Mar 30 2020, 9:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 30 2020, 9:10 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
samparker added a parent revision: D77065: [ARM][MVE] Add VHADD and VHSUB patterns.Mar 30 2020, 9:10 AM
Harbormaster failed remote builds in B50969: Diff 253610!Mar 30 2020, 9:44 AM
SjoerdMeijer added inline comments.Mar 31 2020, 9:33 AM
llvm/lib/Target/ARM/ARMInstrMVE.td
2033

I have seen these constants like the (ARMvmovImm (i32 3585)) here before, but can't remember what they encode. Is that the constant vector of 1s? Is that worth at least a comment?

SjoerdMeijer added a comment.Mar 31 2020, 9:39 AM

Ah, I now see that Dave commented on the other ticket, that probably needs to be addressed first...

samparker updated this revision to Diff 257648.Apr 15 2020, 3:12 AM

Updated to use non wrapping adds.

dmgreen accepted this revision.Apr 16 2020, 7:20 AM

SGTM

This revision is now accepted and ready to land.Apr 16 2020, 7:20 AM
Closed by commit rG62f97123fbef: [ARM][MVE] Add patterns for VRHADD (authored by samparker). · Explain WhyApr 20 2020, 2:07 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
25 lines
test/
CodeGen/
Thumb2/
60 lines

Diff 253610

llvm/lib/Target/ARM/ARMInstrMVE.td

Show First 20 Lines • Show All 492 Lines • ▼ Show 20 Lines
defm MVE_VRHADDs8 : MVE_VRHADD<MVE_v16s8>; defm MVE_VRHADDs8 : MVE_VRHADD<MVE_v16s8>;
defm MVE_VRHADDs16 : MVE_VRHADD<MVE_v8s16>; defm MVE_VRHADDs16 : MVE_VRHADD<MVE_v8s16>;
defm MVE_VRHADDs32 : MVE_VRHADD<MVE_v4s32>; defm MVE_VRHADDs32 : MVE_VRHADD<MVE_v4s32>;
defm MVE_VRHADDu8 : MVE_VRHADD<MVE_v16u8>; defm MVE_VRHADDu8 : MVE_VRHADD<MVE_v16u8>;
defm MVE_VRHADDu16 : MVE_VRHADD<MVE_v8u16>; defm MVE_VRHADDu16 : MVE_VRHADD<MVE_v8u16>;
defm MVE_VRHADDu32 : MVE_VRHADD<MVE_v4u32>; defm MVE_VRHADDu32 : MVE_VRHADD<MVE_v4u32>;
def : Pat<(v16i8 (ARMvshrsImm (add (add (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)),
(v16i8 (ARMvmovImm (i32 3585)))),
SjoerdMeijerUnsubmitted
Not Done
ReplyInline Actions

I have seen these constants like the (ARMvmovImm (i32 3585)) here before, but can't remember what they encode. Is that the constant vector of 1s? Is that worth at least a comment?

SjoerdMeijer: I have seen these constants like the (ARMvmovImm (i32 3585)) here before, but can't remember…
(i32 1))),
(MVE_VRHADDs8 MQPR:$Qm, MQPR:$Qn)>;
def : Pat<(v8i16 (ARMvshrsImm (add (add (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn)),
(v8i16 (ARMvmovImm (i32 2049)))),
(i32 1))),
(MVE_VRHADDs16 MQPR:$Qm, MQPR:$Qn)>;
def : Pat<(v4i32 (ARMvshrsImm (add (add (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn)),
(v4i32 (ARMvmovImm (i32 1)))),
(i32 1))),
(MVE_VRHADDs32 MQPR:$Qm, MQPR:$Qn)>;
def : Pat<(v16i8 (ARMvshruImm (add (add (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)),
(v16i8 (ARMvmovImm (i32 3585)))),
(i32 1))),
(MVE_VRHADDu8 MQPR:$Qm, MQPR:$Qn)>;
def : Pat<(v8i16 (ARMvshruImm (add (add (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn)),
(v8i16 (ARMvmovImm (i32 2049)))),
(i32 1))),
(MVE_VRHADDu16 MQPR:$Qm, MQPR:$Qn)>;
def : Pat<(v4i32 (ARMvshruImm (add (add (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn)),
(v4i32 (ARMvmovImm (i32 1)))),
(i32 1))),
(MVE_VRHADDu32 MQPR:$Qm, MQPR:$Qn)>;
class MVE_VHADDSUB<string iname, string suffix, bit U, bit subtract, class MVE_VHADDSUB<string iname, string suffix, bit U, bit subtract,
bits<2> size, list<dag> pattern=[]> bits<2> size, list<dag> pattern=[]>
: MVE_int<iname, suffix, size, pattern> { : MVE_int<iname, suffix, size, pattern> {
let Inst{28} = U; let Inst{28} = U;
let Inst{25-23} = 0b110; let Inst{25-23} = 0b110;
let Inst{16} = 0b0; let Inst{16} = 0b0;
let Inst{12-10} = 0b000; let Inst{12-10} = 0b000;
▲ Show 20 Lines • Show All 492 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-halving.ll

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; CHECK-LABEL: vhsubu_v4i32: ; CHECK-LABEL: vhsubu_v4i32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: vhsub.u32 q0, q0, q1 ; CHECK-NEXT: vhsub.u32 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%sub = sub <4 x i32> %x, %y %sub = sub <4 x i32> %x, %y
%half = lshr <4 x i32> %sub, <i32 1, i32 1, i32 1, i32 1> %half = lshr <4 x i32> %sub, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %half ret <4 x i32> %half
} }
define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: vrhadds_v16i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrhadd.s8 q0, q0, q1
; CHECK-NEXT: bx lr
%add = add <16 x i8> %x, %y
%round = add <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%half = ashr <16 x i8> %round, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %half
}
define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: vrhaddu_v16i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrhadd.u8 q0, q0, q1
; CHECK-NEXT: bx lr
%add = add <16 x i8> %x, %y
%round = add <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%half = lshr <16 x i8> %round, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %half
}
define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: vrhadds_v8i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrhadd.s16 q0, q0, q1
; CHECK-NEXT: bx lr
%add = add <8 x i16> %x, %y
%round = add <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%half = ashr <8 x i16> %round, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %half
}
define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: vrhaddu_v8i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrhadd.u16 q0, q0, q1
; CHECK-NEXT: bx lr
%add = add <8 x i16> %x, %y
%round = add <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%half = lshr <8 x i16> %round, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %half
}
define arm_aapcs_vfpcc <4 x i32> @vrhadds_v4i32(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: vrhadds_v4i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrhadd.s32 q0, q0, q1
; CHECK-NEXT: bx lr
%add = add <4 x i32> %x, %y
%round = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
%half = ashr <4 x i32> %round, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %half
}
define arm_aapcs_vfpcc <4 x i32> @vrhaddu_v4i32(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: vrhaddu_v4i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrhadd.u32 q0, q0, q1
; CHECK-NEXT: bx lr
%add = add <4 x i32> %x, %y
%round = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
%half = lshr <4 x i32> %round, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %half
}