[PowerPC] Update Alignment of ReuseLoadInfo in PPCTargetLowering::LowerFP_TO_INTForReuse

[lkail]

Summary

Current PowerPC backend fails to compile the attached test case, hitting an assertion error

llvm-project/llvm/include/llvm/Support/Alignment.h:78: llvm::Align::Align(uint64_t): Assertion `Value > 0 && "Value must not be 0"' failed.

PowerPC backend wants to emit such code sequence

fctiwz ...
stfiwx ...
lfiwax ...

for LLVM IR

%b = fptosi float %a to i32
%c = sitofp i32 %b to float

on targets without VSX support(e.g. building a linux kernel). When emitting stfiwx, Alignment of ReuseLoadInfo is supposed to be updated in PPCTargetLowering::LowerFP_TO_INTForReuse so that following emit of lfiwax can know the alignment.

[lkail]

Rebased.

[lkail]

Should be fixed by 998118c3d3bd6a394c1da35f7570cce1a3145ea3, which does more checks on alignment.

[lkail]

Resubmit a new patch to get correct alignment. https://reviews.llvm.org/D77624

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
     (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
   SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
   int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
   MachinePointerInfo MPI =
       MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
 
   // Emit a store to the stack slot.
   SDValue Chain;
+  unsigned Alignment = 0;
   if (i32Stack) {
     MachineFunction &MF = DAG.getMachineFunction();
     MachineMemOperand *MMO =
       MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
+    Alignment = 4;
     SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
     Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
               DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
   } else
     Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, MPI);
 
   // Result is a load from the stack slot.  If loading 4 bytes, make sure to
   // add in a bias on big endian.
   if (Op.getValueType() == MVT::i32 && !i32Stack) {
     FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
                         DAG.getConstant(4, dl, FIPtr.getValueType()));
     MPI = MPI.getWithOffset(Subtarget.isLittleEndian() ? 0 : 4);
   }
 
   RLI.Chain = Chain;
   RLI.Ptr = FIPtr;
   RLI.MPI = MPI;
+  RLI.Alignment = Alignment;
 }
 
 /// Custom lowers floating point to integer conversions to use
 /// the direct move instructions available in ISA 2.07 to avoid the
 /// need for load/store combinations.
 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
                                                     SelectionDAG &DAG,
                                                     const SDLoc &dl) const {

llvm/test/CodeGen/PowerPC/kernel-fp-round.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -ppc-asm-full-reg-names < %s | FileCheck %s
+
+define float @test(float %arg) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fctiwz f0, f1
+; CHECK-NEXT:    addi r3, r1, -4
+; CHECK-NEXT:    stfiwx f0, 0, r3
+; CHECK-NEXT:    lfiwax f0, 0, r3
+; CHECK-NEXT:    fcfids f1, f0
+; CHECK-NEXT:    blr
+entry:
+  %conv = fptosi float %arg to i32
+  %res = sitofp i32 %conv to float
+  ret float %res
+}