[MC][AArch64] Make .reloc support arbitrary relocation types

[MaskRay]

Summary

Depends on D76746. Generalizes D61973.

[grimar]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

402–406

It looks like if (!Value) could be tested first? Value is argument and it looks a bit strange that it is tested so late to do return.

[MaskRay]

Reorder code in applyFixup. Copy a comment from ARMAskBackend.cpp

llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
         {"fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal},
         {"fixup_aarch64_movw", 5, 16, 0},
         {"fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal},
         {"fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal},
         {"fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal},
         {"fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal},
         {"fixup_aarch64_tlsdesc_call", 0, 0, 0}};
 
+    // Fixup kinds from .reloc directive are like R_AARCH64_NONE. They do not
+    // require any extra processing.
+    if (Kind >= FirstLiteralRelocationKind)
+      return MCAsmBackend::getFixupKindInfo(FK_NONE);
+
     if (Kind < FirstTargetFixupKind)
       return MCAsmBackend::getFixupKindInfo(Kind);
 
     assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
            "Invalid kind!");
     return Infos[Kind - FirstTargetFixupKind];
   }
 

 } // end anonymous namespace
 
 /// The number of bytes the fixup may change.
 static unsigned getFixupKindNumBytes(unsigned Kind) {
   switch (Kind) {
   default:
     llvm_unreachable("Unknown fixup kind!");
 
-  case FK_NONE:
   case AArch64::fixup_aarch64_tlsdesc_call:
     return 0;
 
   case FK_Data_1:
     return 1;
 
   case FK_Data_2:
   case FK_SecRel_2:
case AArch64::fixup_aarch64_pcrel_call26:
     return (Value >> 2) & 0x3ffffff;
   case FK_Data_1:
   case FK_Data_2:
   case FK_Data_4:
   case FK_Data_8:
     if (!valueFitsIntoFixupKind(Fixup.getTargetKind(), Value))
       Ctx.reportError(Fixup.getLoc(), "fixup value too large for data type!");
     LLVM_FALLTHROUGH;
-  case FK_NONE:
   case FK_SecRel_2:
   case FK_SecRel_4:
     return Value;
   }
 }
 
 Optional<MCFixupKind> AArch64AsmBackend::getFixupKind(StringRef Name) const {
-  if (TheTriple.isOSBinFormatELF() && Name == "R_AARCH64_NONE")
-    return FK_NONE;
-  return MCAsmBackend::getFixupKind(Name);
+  if (!TheTriple.isOSBinFormatELF())
+    return None;
+
+  unsigned Type = llvm::StringSwitch<unsigned>(Name)
+#define ELF_RELOC(X, Y)  .Case(#X, Y)
+#include "llvm/BinaryFormat/ELFRelocs/AArch64.def"
+#undef ELF_RELOC
+                      .Default(-1u);
+  if (Type == -1u)
+    return None;
+  return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
 }
 
 /// getFixupKindContainereSizeInBytes - The number of bytes of the
 /// container involved in big endian or 0 if the item is little endian
 unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
   if (Endian == support::little)
     return 0;
 
unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
   }
 }
 
 void AArch64AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                                    const MCValue &Target,
                                    MutableArrayRef<char> Data, uint64_t Value,
                                    bool IsResolved,
                                    const MCSubtargetInfo *STI) const {
-  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
   if (!Value)
     return; // Doesn't change encoding.
+  unsigned Kind = Fixup.getKind();
+  if (Kind >= FirstLiteralRelocationKind)
+    return;
+  unsigned NumBytes = getFixupKindNumBytes(Kind);
   MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
   MCContext &Ctx = Asm.getContext();
   int64_t SignedValue = static_cast<int64_t>(Value);
   // Apply any target-specific value adjustments.
   Value = adjustFixupValue(Fixup, Target, Value, Ctx, TheTriple, IsResolved);
 
   // Shift the value into position.
   Value <<= Info.TargetOffset;
for (uint64_t i = 0; i != Count; ++i)
     support::endian::write<uint32_t>(OS, 0xd503201f, Endian);
   return true;
 }
 
 bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
                                               const MCFixup &Fixup,
                                               const MCValue &Target) {
   unsigned Kind = Fixup.getKind();
-  if (Kind == FK_NONE)
+  if (Kind >= FirstLiteralRelocationKind)
     return true;
 
   // The ADRP instruction adds some multiple of 0x1000 to the current PC &
   // ~0xfff. This means that the required offset to reach a symbol can vary by
   // up to one step depending on where the ADRP is in memory. For example:
   //
   //     ADRP x0, there
   //  there:

llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp

static bool isNonILP32reloc(const MCFixup &Fixup,
   }
   return false;
 }
 
 unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
                                               const MCValue &Target,
                                               const MCFixup &Fixup,
                                               bool IsPCRel) const {
+  unsigned Kind = Fixup.getTargetKind();
+  if (Kind >= FirstLiteralRelocationKind)
+    return Kind - FirstLiteralRelocationKind;
   AArch64MCExpr::VariantKind RefKind =
       static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
   AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
   bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
 
   assert((!Target.getSymA() ||
           Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) &&
          "Should only be expression-level modifiers here");
 
   assert((!Target.getSymB() ||
           Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
          "Should only be expression-level modifiers here");
 
   if (IsPCRel) {
-    switch (Fixup.getTargetKind()) {
+    switch (Kind) {
     case FK_Data_1:
       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
       return ELF::R_AARCH64_NONE;
     case FK_Data_2:
       return R_CLS(PREL16);
     case FK_Data_4:
       return R_CLS(PREL32);
     case FK_Data_8:
if (IsPCRel) {
     default:
       Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
       return ELF::R_AARCH64_NONE;
     }
   } else {
     if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
       return ELF::R_AARCH64_NONE;
     switch (Fixup.getTargetKind()) {
-    case FK_NONE:
-      return ELF::R_AARCH64_NONE;
     case FK_Data_1:
       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
       return ELF::R_AARCH64_NONE;
     case FK_Data_2:
       return R_CLS(ABS16);
     case FK_Data_4:
       return R_CLS(ABS32);
     case FK_Data_8:

llvm/test/MC/AArch64/reloc-directive-err.s

+# RUN: llvm-mc -triple=aarch64 %s 2>&1 | FileCheck --check-prefix=PRINT %s
+# RUN: not llvm-mc -filetype=obj -triple=aarch64 %s -o /dev/null 2>&1 | FileCheck %s
+
+# PRINT: .reloc 0, R_INVALID, 0
+# CHECK: {{.*}}.s:[[# @LINE+1]]:11: error: unknown relocation name
+.reloc 0, R_INVALID, 0

llvm/test/MC/AArch64/reloc-directive.s

 # RUN: llvm-mc -triple=aarch64-linux-musl %s | FileCheck --check-prefix=PRINT %s
 
 # RUN: llvm-mc -filetype=obj -triple=aarch64-linux-musl %s | llvm-readobj -r | FileCheck %s
 
 # PRINT: .reloc 8, R_AARCH64_NONE, .data
 # PRINT: .reloc 4, R_AARCH64_NONE, foo+4
 # PRINT: .reloc 0, R_AARCH64_NONE, 8
+# PRINT: .reloc 0, R_AARCH64_ABS64, .data+2
+# PRINT: .reloc 0, R_AARCH64_TLSDESC, foo+3
+# PRINT: .reloc 0, R_AARCH64_IRELATIVE, 5
 .text
   ret
   nop
   nop
   .reloc 8, R_AARCH64_NONE, .data
   .reloc 4, R_AARCH64_NONE, foo+4
   .reloc 0, R_AARCH64_NONE, 8
 
+  .reloc 0, R_AARCH64_ABS64, .data+2
+  .reloc 0, R_AARCH64_TLSDESC, foo+3
+  .reloc 0, R_AARCH64_IRELATIVE, 5
+
 .data
 .globl foo
 foo:
   .word 0
   .word 0
   .word 0
 
 # CHECK:      0x8 R_AARCH64_NONE .data 0x0
 # CHECK-NEXT: 0x4 R_AARCH64_NONE foo 0x4
 # CHECK-NEXT: 0x0 R_AARCH64_NONE - 0x8
+# CHECK-NEXT: 0x0 R_AARCH64_ABS64 .data 0x2
+# CHECK-NEXT: 0x0 R_AARCH64_TLSDESC foo 0x3
+# CHECK-NEXT: 0x0 R_AARCH64_IRELATIVE - 0x5