[PowerPC][AIX] ByVal formal argument support: single register.

[sfertile]

Summary

Adds support for passing ByVal formal arguments as long as they fit in a single register.

[sfertile]

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

41–42

If no one has any objections I'll land the check prefix changes in this test and the 64-bit equivalent test as a separate NFC patch.

[sfertile]

Landed check-prefix changes as an NFC patch and rebased ontop of that.

[ZarkoCA]

I think that we may need some more struct types with varying size elements. Right now, the tests mostly will check for mostly lbz at an offset. Would be great if we see that lha or even lw is used when required. However, this may be easier to do in a patch where arguments greater than register size are used?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7068

There is already a fatal error in CC_AIX for this, would an assert be better here?

7077

This variable in the other parts of the function is called FIN, we should be consistent I think.

[jasonliu]

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

99

Do we want to add in an 0-byte by-val test?

[jasonliu]

Couple places that a "const" could be added: Count, LASize, FI, VReg.

[sfertile]

• rename local to match other uses in function.
• constify a handful of locals.

[sfertile]

I'm going to implement the suggested changes to the testing (ie a zero-sized-byval and different byval types so we are loading more then just a char). I'll do so in a separate patch which makes the changes and shows the difference in the existing tests and then I'll rebase this patch onto that.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7068

That fatal error is going to go away in the next patch implementing multiple registers on the caller side so I have a similar error here so we don't have to change this function in that patch. I can remove it if you want though.

[cebowleratibm]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6985

LLVM has alignTo, which I believe you can use.

7064

I don't object to the name TrueSize but I prefer the name ByValSize.

7065

I understand that you're likely preparing for the next patch, but I think it's simple enough to:

if (ByValSize > PtrByteSize) report_fatal_error

then skip the rounding and write the single register case. You know the StackSize is always PtrByteSize.

7092

Does this store get elided by optimization when possible?

For example:
struct S {int i;};
int foo(S s) { return s.i; }

I assume we don't want to manifest the store to the stack. It's odd to me because we don't manifest the store for the equivalent:

int foo(int i) { return i; }

[sfertile]

• Fixed assertion with zero sized byvals that new testing exposed.
• Addressed various review comments (renamed TrueSize, use alignTo, etc).

[sfertile]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7065

Rounding the byval size up is the same whether it is smaller then a single reg, or arbitrarily large. Using PtrByte size and skipping the rounding seems rather artificial, I'd rather keep this as is.

7092

No. Several of the lit test cases show where we DAG combine to extract the value from the register (see the 4-byte 32-bit test or the 8-byte 64-bit test cases) but we don't remove the dead store. We will need work that can generalize the optimization the DAG combines is doing for extracting the values from the register, and a pass to clean up the stores.

It's odd to me because we don't manifest the store for the equivalent:
int foo(int i) { return i; }

These are seemingly equivalent in C/C++ source, but consider the IR we have to generate for the 2 cases and I think the difference become apparent:

; Function Attrs: norecurse nounwind readonly
define i32 @foo(%struct.S* nocapture readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 {
entry:
  %i = getelementptr inbounds %struct.S, %struct.S* %s, i64 0, i32 0
  %0 = load i32, i32* %i, align 4, !tbaa !3
  ret i32 %0
}

; Function Attrs: norecurse nounwind readnone
define i32 @Bar(i32 returned %i) local_unnamed_addr #1 {
entry:
  ret i32 %i
}

The GEP and the load force us to store to the stack for the ByVal arg making the 2 functions that happen to be 'equivalent' in source to be non-equivalent in their IR representations.

[sfertile]

Run clang-format.

[cebowleratibm]

Summary:
-Test tidy ups
-FYI that I noted a 32-bit 8 byte aligned by-val (struct S { double d; }) that will need special handling in future
-Requested some comments in the code / tests to explain the suboptimal codegen, which otherwise looks odd.

The patch looks very close to me.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6867

Minor concern here that ValVT is a lie. I assume the consumer will ignore it when it sees the ByValSize is 0, but I'd rather it hold an invalid value than something that could be conceived as meaningful.

7092

Thanks for the explanation. I think a brief comment in the source to describe why we always need the frame object would be useful. I also made comments in the test changes where I think test comments should explain the suboptimal expected codegen. I am in favour of the patch as you've presented it in order to get AIX functional and follow up with optimization improvement later.

There is a case in 32-bit AIX:

struct S { double d; }

has 8 byte alignment (only for first member is a double) and the normal frame object location with PtrByteSize (4) alignment will not suffice. Currently that case emits an error so it doesn't need to be handled in this patch, but I mention it to you because I expect your code will need to be modified when we remove the error. You may need special handling in this case to remap the frame object location.

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

86

missing ')'. Still passes but worth tidying.

100

Also missing ')'

105

Curious to me that the optimizer didn't tidy up the stw/lbz. It's ok for now but we need to ensure the param stack writes are being elided for performance.

172

')'

175

missing trailing text?

180

')'

257

trailing text?

262

)

265

trailing text

362

dead stores at opt? If this is temporary it probably warrants a comment in the expected output.

383

)

384

)

[ZarkoCA]

IMO, the patch is pretty much done, just some test clean up.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7071

Is it possible to add a continue after line 7070 and then remove the else?

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

78

Maybe you can remove this line. I think the relevant info for the test is only the lines which show the offset and the size

[sfertile]

• split the ByVal handling into memory and register parts to remove an 'else'.
• add back some missing info for fixed stack objects in the lit test.
• remove check lines related to fixed stack objects which are not semantically meaningful.

Still working on adding the suggested comments.

[sfertile]

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

86

It's missing from %ir.arrayidx1, align 8) but I didn't think it was important to include in the test output so I truncated it to show only what I though was relevant: that the load is derefrencable. If you want I can add them all back though.

99

Yes, and adding it caught an assertion in the caller of LowerFormalArguemnts which I otherwise missed so thank you.

[sfertile]

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

105

For the 64-bit sub-targets we typically pass what would be ByVal on AIX as arrays of i64/i32 and coerce the values out which means no gep/load in the IR. On PPC32, we only pass the ByVals on the stack so no need to store the registers in the callee. The back end doesn't have anything to clean up the dead stores because we never produce them to begin with.

362

I think we have a 2 stage cleanup in relation to performance:

1. Extend the optimization that recognized how to pull the field from the register to work more generally
2. Cleanup of the dead stores when we have extracted all the needed values from the register.

The problem is to big and general to specifically call out here. Every test in this file will need to be changed when we implement that.

[sfertile]

Added a comment to describe why we must store the registers used to pas a ByVal to the stack.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
 
   if (ArgFlags.isByVal()) {
     if (ArgFlags.getNonZeroByValAlign() > PtrByteSize)
       report_fatal_error("Pass-by-value arguments with alignment greater than "
                          "register width are not supported.");
 
     const unsigned ByValSize = ArgFlags.getByValSize();
 
-    // An empty aggregate parameter takes up no storage and no registers.
-    if (ByValSize == 0)
+    // An empty aggregate parameter takes up no storage and no registers,
+    // but needs a MemLoc for a stack slot for the formal arguments side.
+    if (ByValSize == 0) {
+      State.addLoc(CCValAssign::getMem(
+          ValNo, ValVT, State.getNextStackOffset(), RegVT, LocInfo));
       return false;
+    }
 
     if (ByValSize <= PtrByteSize) {
       State.AllocateStack(PtrByteSize, PtrByteSize);
       if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) {
         State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo));
         return false;
       }
     }
ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
                            DAG.getValueType(ValVT));
   else if (Flags.isZExt())
     ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
                            DAG.getValueType(ValVT));
 
   return DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
 }
 
+static unsigned mapArgRegToOffsetAIX(unsigned Reg, const PPCFrameLowering *FL) {
+  const unsigned LASize = FL->getLinkageSize();
+
+  if (PPC::GPRCRegClass.contains(Reg)) {
+    assert(Reg >= PPC::R3 && Reg <= PPC::R10 &&
+           "Reg must be a valid argument register!");
+    return LASize + 4 * (Reg - PPC::R3);
+  }
+
+  if (PPC::G8RCRegClass.contains(Reg)) {
+    assert(Reg >= PPC::X3 && Reg <= PPC::X10 &&
+           "Reg must be a valid argument register!");
+    return LASize + 8 * (Reg - PPC::X3);
+  }
+
+  llvm_unreachable("Only general purpose registers expected.");
+}
+
 SDValue PPCTargetLowering::LowerFormalArguments_AIX(
     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 
   assert((CallConv == CallingConv::C || CallConv == CallingConv::Cold ||
           CallConv == CallingConv::Fast) &&
          "Unexpected calling convention!");
SDValue PPCTargetLowering::LowerFormalArguments_AIX(
   CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
 
   const EVT PtrVT = getPointerTy(MF.getDataLayout());
   // Reserve space for the linkage area on the stack.
   const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
   CCInfo.AllocateStack(LinkageSize, PtrByteSize);
   CCInfo.AnalyzeFormalArguments(Ins, CC_AIX);
 
+  SmallVector<SDValue, 8> MemOps;
+
   for (CCValAssign &VA : ArgLocs) {
     EVT ValVT = VA.getValVT();
     MVT LocVT = VA.getLocVT();
     ISD::ArgFlagsTy Flags = Ins[VA.getValNo()].Flags;
-    assert(!Flags.isByVal() &&
-           "Passing structure by value is unimplemented for formal arguments.");
     assert((VA.isRegLoc() || VA.isMemLoc()) &&
            "Unexpected location for function call argument.");
 
     // For compatibility with the AIX XL compiler, the float args in the
     // parameter save area are initialized even if the argument is available
     // in register.  The caller is required to initialize both the register
     // and memory, however, the callee can choose to expect it in either.
     // The memloc is dismissed here because the argument is retrieved from
     // the register.
     if (VA.isMemLoc() && VA.needsCustom())
       continue;
 
+    if (Flags.isByVal()) {
+      const unsigned ByValSize = Flags.getByValSize();
+
+      if (VA.isMemLoc()) {
+        if (ByValSize != 0)
+          report_fatal_error(
+              "ByVal arguments passed on stack not implemented yet");
+
+        const int FI = MF.getFrameInfo().CreateFixedObject(
+            PtrByteSize, VA.getLocMemOffset(), /* IsImmutable */ false,
+            /* IsAliased */ true);
+        SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
+        InVals.push_back(FIN);
+      } else {
+        if (ByValSize > PtrByteSize)
+          report_fatal_error("Formal arguments greater then register size not "
+                             "implemented yet.");
+
+        const MCPhysReg ArgReg = VA.getLocReg();
+        const PPCFrameLowering *FL = Subtarget.getFrameLowering();
+        const unsigned Offset = mapArgRegToOffsetAIX(ArgReg, FL);
+
+        const unsigned StackSize = alignTo(ByValSize, PtrByteSize);
+        const int FI = MF.getFrameInfo().CreateFixedObject(
+            StackSize, Offset, /* IsImmutable */ false, /* IsAliased */ true);
+        SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
+
+        InVals.push_back(FIN);
+
+        const unsigned VReg = MF.addLiveIn(
+            ArgReg, IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
+
+        // Since the callers side has left justified the aggregate in the
+        // register, we can simply store the entire register into the stack
+        // slot.
+        SDValue CopyFrom = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
+        SDValue Store =
+            DAG.getStore(CopyFrom.getValue(1), dl, CopyFrom, FIN,
+                         MachinePointerInfo::getFixedStack(MF, FI, 0));
+
+        MemOps.push_back(Store);
+      }
+      continue;
+    }
+
     if (VA.isRegLoc()) {
       MVT::SimpleValueType SVT = ValVT.getSimpleVT().SimpleTy;
       unsigned VReg =
           MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
       if (ValVT.isScalarInteger() &&
           (ValVT.getSizeInBits() < LocVT.getSizeInBits())) {
         ArgValue =
SDValue PPCTargetLowering::LowerFormalArguments_AIX(
   // call optimized function's reserved stack space needs to be aligned so
   // that taking the difference between two stack areas will result in an
   // aligned stack.
   CallerReservedArea =
       EnsureStackAlignment(Subtarget.getFrameLowering(), CallerReservedArea);
   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
   FuncInfo->setMinReservedArea(CallerReservedArea);
 
+  if (!MemOps.empty())
+    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
+
   return Chain;
 }
 
 SDValue PPCTargetLowering::LowerCall_AIX(
     SDValue Chain, SDValue Callee, CallFlags CFlags,
     const SmallVectorImpl<ISD::OutputArg> &Outs,
     const SmallVectorImpl<SDValue> &OutVals,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
for (unsigned I = 0, E = ArgLocs.size(); I != E;) {
 
     SDValue Arg = OutVals[VA.getValNo()];
     ISD::ArgFlagsTy Flags = Outs[VA.getValNo()].Flags;
     const MVT LocVT = VA.getLocVT();
     const MVT ValVT = VA.getValVT();
 
     if (Flags.isByVal()) {
       const unsigned ByValSize = Flags.getByValSize();
+
+      // Nothing to do for zero-sized ByVals on the caller side.
+      if (!ByValSize)
+        continue;
+
       assert(
-          VA.isRegLoc() && ByValSize > 0 && ByValSize <= PtrByteSize &&
+          VA.isRegLoc() && ByValSize <= PtrByteSize &&
           "Pass-by-value arguments are only supported in a single register.");
 
       // Loads must be a power-of-2 size and cannot be larger than the
       // ByValSize. For example: a 7 byte by-val arg requires 4, 2 and 1 byte
       // loads.
       SDValue RegVal;
       for (unsigned Bytes = 0; Bytes != ByValSize;) {
         unsigned N = PowerOf2Floor(ByValSize - Bytes);

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

 %struct.S0 = type {}
 
 %struct.S1 = type { [1 x i8] }
 @gS1 = external global %struct.S1, align 1
 
 define void @call_test_byval_1Byte() {
 entry:
   %s0 = alloca %struct.S0, align 8
-  call void @test_byval_1Byte(%struct.S0* byval(%struct.S0) align 1 %s0, %struct.S1* byval(%struct.S1) align 1 @gS1)
+  %call = call zeroext i8 @test_byval_1Byte(%struct.S0* byval(%struct.S0) align 1 %s0, %struct.S1* byval(%struct.S1) align 1 @gS1)
   ret void
 }
 
-declare void @test_byval_1Byte(%struct.S0* byval(%struct.S0) align 1, %struct.S1* byval(%struct.S1) align 1)
 
 ; CHECK-LABEL: name: call_test_byval_1Byte{{.*}}
 
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:  renamable $r[[REG:[0-9]+]] = LWZtoc @gS1, $r2 :: (load 4 from got)
 ; 32BIT-NEXT:  renamable $r3 = LBZ 0, killed renamable $r[[REG]] :: (load 1)
 ; 32BIT-NEXT:  renamable $r3 = RLWINM killed renamable $r3, 24, 0, 7
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_1Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_1Byte:
 
 ; ASM32:       stwu 1, -64(1)
 ; ASM32-NEXT:  lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM32-NEXT:  lbz 3, 0([[REG]])
 ; ASM32-NEXT:  slwi 3, 3, 24
 ; ASM32-NEXT:  bl .test_byval_1Byte
 ; ASM32-NEXT:  nop
 ; ASM32-NEXT:  addi 1, 1, 64
 
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:  renamable $x3 = LBZ8 0, killed renamable $x[[REG]] :: (load 1)
 ; 64BIT-NEXT:  renamable $x3 = RLDICR killed renamable $x3, 56, 7
 ; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_1Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       std 0, 16(1)
 ; ASM64-NEXT:  stdu 1, -128(1)
 ; ASM64-NEXT:  ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM64-NEXT:  lbz 3, 0([[REG]])
 ; ASM64-NEXT:  sldi 3, 3, 56
 ; ASM64-NEXT:  bl .test_byval_1Byte
 ; ASM64-NEXT:  nop
 ; ASM64-NEXT:  addi 1, 1, 128
 
+
+define zeroext i8 @test_byval_1Byte(%struct.S0* byval(%struct.S0) align 1 %s0, %struct.S1* byval(%struct.S1) align 1 %s) {
+entry:
+  %arrayidx = getelementptr inbounds %struct.S1, %struct.S1* %s, i32 0, i32 0, i32 0
+  %0 = load i8, i8* %arrayidx, align 1
+  ret i8 %0
+}
+
+; CHECK-LABEL: name:            test_byval_1Byte
+
+; 32BIT:       fixedStack:
+; 32BIT-NEXT:     - { id: 0, type: default, offset: 24, size: 4, alignment: 8, stack-id: default,
+; 32BIT-NEXT:         isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
+; 32BIT-NEXT:         debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; 32BIT-NEXT:     - { id: 1, type: default, offset: 24, size: 4, alignment: 8, stack-id: default,
+; 32BIT-NEXT:         isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
+; 32BIT-NEXT:         debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+
+; 32BIT:       bb.0.entry:
+; 32BIT-NEXT:    liveins: $r3
+; 32BIT:         STW killed renamable $r3, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0, align 8)
+; 32BIT-NEXT:    renamable $r3 = LBZ 0,  %fixed-stack.0 :: (dereferenceable load 1
+; 32BIT-NEXT:    BLR
+
+; 64BIT:      fixedStack:
+; 64BIT-NEXT:   - { id: 0, type: default, offset: 48, size: 8, alignment: 16, stack-id: default,
+; 64BIT-NEXT:       isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
+; 64BIT-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; 64BIT-NEXT:   - { id: 1, type: default, offset: 48, size: 8, alignment: 16, stack-id: default,
+; 64BIT-NEXT:       isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
+; 64BIT-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+
+; 64BIT:      bb.0.entry:
+; 64BIT-NEXT:   liveins: $x3
+; 64BIT:        STD killed renamable $x3, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
+; 64BIT-NEXT:   renamable $x3 = LBZ8 0, %fixed-stack.0 :: (dereferenceable load 1
+
+; CHECKASM-LABEL: .test_byval_1Byte:
+
+; ASM32:        stw 3, 24(1)
+; ASM32-NEXT:   lbz 3, 24(1)
+; ASM32-NEXT:   blr
+
+; ASM64:        std 3, 48(1)
+; ASM64-NEXT:   lbz 3, 48(1)
+; ASM64-NEXT:   blr
+
 %struct.S2 = type { [2 x i8] }
 
 @gS2 = external global %struct.S2, align 1
 
 define void @call_test_byval_2Byte() {
 entry:
-  call void @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1 @gS2)
+  %call = call zeroext i8 @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1 @gS2)
   ret void
 }
 
-declare void @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1)
-
 ; CHECK-LABEL: name: call_test_byval_2Byte{{.*}}
 
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:  renamable $r[[REG:[0-9]+]] = LWZtoc @gS2, $r2 :: (load 4 from got)
 ; 32BIT-NEXT:  renamable $r3 = LHZ 0, killed renamable $r[[REG]] :: (load 2)
 ; 32BIT-NEXT:  renamable $r3 = RLWINM killed renamable $r3, 16, 0, 15
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_2Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1

 ; ASM64-NEXT:  stdu 1, -112(1)
 ; ASM64-NEXT:  ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM64-NEXT:  lhz 3, 0([[REG]])
 ; ASM64-NEXT:  sldi 3, 3, 48
 ; ASM64-NEXT:  bl .test_byval_2Byte
 ; ASM64-NEXT:  nop
 ; ASM64-NEXT:  addi 1, 1, 112
 
-%struct.S3 = type <{ i8, i16 }>
 
+define zeroext i8 @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1 %s) {
+entry:
+  %arrayidx = getelementptr inbounds %struct.S2, %struct.S2* %s, i32 0, i32 0, i32 1
+  %0 = load i8, i8* %arrayidx, align 1
+  ret i8 %0
+}
+
+; CHECK-LABEL: name:            test_byval_2Byte
+; 32BIT:      fixedStack:
+; 32BIT-NEXT:   - { id: 0, type: default, offset: 24, size: 4, alignment: 8,
+
+; 32BIT:      bb.0.entry:
+; 32BIT-NEXT:   liveins: $r3
+; 32BIT:        STW killed renamable $r3, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0, align 8)
+; 32BIT-NEXT:   renamable $r3 = LBZ 1, %fixed-stack.0 :: (dereferenceable load 1
+
+; 64BIT:      fixedStack:
+; 64BIT-NEXT:   - { id: 0, type: default, offset: 48, size: 8, alignment: 16,
+
+; 64BIT:      bb.0.entry:
+; 64BIT-NEXT:   liveins: $x3
+; 64BIT:        STD killed renamable $x3, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
+; 64BIT-NEXT:   renamable $x3 = LBZ8 1, %fixed-stack.0 :: (dereferenceable load 1
+
+; CHECKASM-LABEL: .test_byval_2Byte:
+
+; ASM32:        stw 3, 24(1)
+; ASM32-NEXT:   lbz 3, 25(1)
+; ASM32-NEXT:   blr
+
+; ASM64:        std 3, 48(1)
+; ASM64-NEXT:   lbz 3, 49(1)
+; ASM64-NEXT:   blr
+
+
+%struct.S3 = type <{ i8, i16 }>
 @gS3 = external global %struct.S3, align 1
 
 define void @call_test_byval_3Byte() {
 entry:
-  call void @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1 @gS3)
+  %call = call zeroext i16 @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1 @gS3)
   ret void
 }
 
-declare void @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1)
-
 ; CHECK-LABEL: name: call_test_byval_3Byte{{.*}}
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:  renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS3, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $r[[REG1:[0-9]+]] = LHZ 0, killed renamable $r[[REGADDR]] :: (load 2)
 ; 32BIT-DAG:   renamable $r[[REG2:[0-9]+]] = LBZ 2, renamable $r[[REGADDR]] :: (load 1)
 ; 32BIT-DAG:   renamable $r3 = RLWINM killed renamable $r[[REG2]], 8, 16, 23

 ; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM64-DAG:   lhz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG2:[0-9]+]], 2([[REGADDR]])
 ; ASM64-DAG:   rldic 3, [[REG2]], 40, 16
 ; ASM64-DAG:   rldimi 3, [[REG1]], 48, 0
 ; ASM64-NEXT:  bl .test_byval_3Byte
 ; ASM64-NEXT:  nop
 
+
+define zeroext i16 @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1 %s) {
+entry:
+  %gep = getelementptr inbounds %struct.S3, %struct.S3* %s, i32 0, i32 1
+  %0 = load i16, i16* %gep, align 1
+  ret i16 %0
+}
+
+; CHECK-LABEL: name:            test_byval_3Byte
+
+; 32BIT:      fixedStack:
+; 32BIT-NEXT:   - { id: 0, type: default, offset: 24, size: 4, alignment: 8,
+
+; 32BIT:      bb.0.entry:
+; 32BIT-NEXT:   liveins: $r3
+; 32BIT:        STW killed renamable $r3, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0, align 8)
+; 32BIT-NEXT:   renamable $r3 = LHZ 1, %fixed-stack.0 :: (dereferenceable load 2
+
+; 64BIT:      fixedStack:
+; 64BIT-NEXT:   - { id: 0, type: default, offset: 48, size: 8, alignment: 16,
+
+; 64BIT:      bb.0.entry:
+; 64BIT-NEXT:   liveins: $x3
+; 64BIT:        STD killed renamable $x3, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
+; 64BIT-NEXT:   renamable $x3 = LHZ8 1, %fixed-stack.0 :: (dereferenceable load 2
+
+
+; CHECKASM-LABEL: .test_byval_3Byte:
+
+; ASM32:        stw 3, 24(1)
+; ASM32-NEXT:   lhz 3, 25(1)
+; ASM32-NEXT:   blr
+
+; ASM64:        std 3, 48(1)
+; ASM64-NEXT:   lhz 3, 49(1)
+; ASM64-NEXT:   blr
+
+
 %struct.S4 = type { [4 x i8] }
 %struct.S4A = type { i32 }
 
 @gS4 = external global %struct.S4, align 1
 
 define void @call_test_byval_4Byte() {
 entry:
   %s0 = alloca %struct.S0, align 8
   %s4a = alloca %struct.S4A, align 4
-  call void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1 @gS4, %struct.S0* byval(%struct.S0) align 1 %s0, %struct.S4A* byval(%struct.S4A) align 4 %s4a)
+  %call = call signext i32 @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1 @gS4, %struct.S0* byval(%struct.S0) align 1 %s0, %struct.S4A* byval(%struct.S4A) align 4 %s4a)
   ret void
 }
 
-declare void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1, %struct.S0* byval(%struct.S0) align 1, %struct.S4A* byval(%struct.S4A) align 4)
-
 ; CHECK-LABEL: name: call_test_byval_4Byte{{.*}}
 
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:  renamable $r[[REG:[0-9]+]] = LWZtoc @gS4, $r2 :: (load 4 from got)
 ; 32BIT-DAG:   renamable $r3 = LWZ 0, killed renamable $r[[REG]] :: (load 4)
 ; 32BIT-DAG:   renamable $r4 = LWZ 0, %stack.1.s4a :: (load 4 from %stack.1.s4a, align 8)
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_4Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3,  implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1

 ; ASM64-DAG:   lwz [[LD1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lwz [[LD2:[0-9]+]], 112(1)
 ; ASM64-DAG:   sldi 3, [[LD1]], 32
 ; ASM64-DAG:   sldi 4, [[LD2]], 32
 ; ASM64-NEXT:  bl .test_byval_4Byte
 ; ASM64-NEXT:  nop
 ; ASM64-NEXT:  addi 1, 1, 128
 
+
+define signext i32 @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1 %s, %struct.S0* byval(%struct.S0) align 1, %struct.S4A* byval(%struct.S4A) align 4 %s4a) {
+entry:
+  %arrayidx = getelementptr inbounds %struct.S4, %struct.S4* %s, i32 0, i32 0, i32 3
+  %gep = getelementptr inbounds %struct.S4A, %struct.S4A* %s4a, i32 0, i32 0
+  %1 = load i8, i8* %arrayidx, align 1
+  %2 = load i32, i32* %gep, align 4
+  %conv = zext i8 %1 to i32
+  %add = add nsw i32 %2, %conv
+  ret i32 %add
+}
+
+; CHECK-LABEL: name:            test_byval_4Byte
+
+; 32BIT:      fixedStack:
+; 32BIT-NEXT:   - { id: 0, type: default, offset: 28, size: 4, alignment: 4, stack-id: default,
+; 32BIT-NEXT:       isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
+; 32BIT-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; 32BIT-NEXT:   - { id: 1, type: default, offset: 28, size: 4, alignment: 4, stack-id: default,
+; 32BIT-NEXT:       isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
+; 32BIT-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; 32BIT-NEXT:   - { id: 2, type: default, offset: 24, size: 4, alignment: 8, stack-id: default,
+; 32BIT-NEXT:       isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
+; 32BIT-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+
+; 32BIT:      bb.0.entry:
+; 32BIT-NEXT:   liveins: $r3
+; 32BIT:        STW renamable $r3, 0, %fixed-stack.2 :: (store 4 into %fixed-stack.2, align 8)
+; 32BIT-DAG:    STW killed renamable $r4, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0)
+; 32BIT-DAG:    renamable $r[[SCRATCH:[0-9]+]] = RLWINM killed renamable $r3, 0, 24, 31
+; 32BIT-DAG:    renamable $r3 = nsw ADD4 renamable $r4, killed renamable $r[[SCRATCH]]
+; 32BIT:        BLR
+
+; 64BIT:      fixedStack:
+; 64BIT-NEXT: - { id: 0, type: default, offset: 56, size: 8, alignment: 8, stack-id: default,
+; 64BIT-NEXT:     isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
+; 64BIT-NEXT:     debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; 64BIT-NEXT: - { id: 1, type: default, offset: 56, size: 8, alignment: 8, stack-id: default,
+; 64BIT-NEXT:     isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
+; 64BIT-NEXT:     debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+; 64BIT-NEXT: - { id: 2, type: default, offset: 48, size: 8, alignment: 16, stack-id: default,
+; 64BIT-NEXT:     isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
+; 64BIT-NEXT:     debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+
+; 64BIT:      bb.0.entry:
+; 64BIT-NEXT:   liveins: $x3
+; 64BIT:        STD killed renamable $x3, 0, %fixed-stack.2 :: (store 8 into %fixed-stack.2, align 16)
+; 64BIT-NEXT:   STD killed renamable $x4, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0)
+; 64BIT-DAG:    renamable $r[[SCRATCH1:[0-9]+]] = LBZ 3, %fixed-stack.2 :: (dereferenceable load 1
+; 64BIT-DAG:    renamable $r[[SCRATCH2:[0-9]+]] = LWZ 0, %fixed-stack.0 :: (dereferenceable load 4
+; 64BIT-NEXT:   renamable $r[[SCRATCH3:[0-9]+]] = nsw ADD4 killed renamable $r[[SCRATCH2]], killed renamable $r[[SCRATCH1]]
+; 64BIT-NEXT:   renamable $x3 = EXTSW_32_64 killed renamable $r[[SCRATCH3]]
+; 64BIT-NEXT:   BLR8
+
+; CHECKASM-LABEL: .test_byval_4Byte:
+
+; ASM32:        stw 3, 24(1)
+; ASM32-DAG:    stw 4, 28(1)
+; ASM32-DAG:    clrlwi  [[SCRATCH:[0-9]+]], 3, 24
+; ASM32-DAG:    add 3, 4, [[SCRATCH]]
+; ASM32-NEXT:   blr
+
+; ASM64:        std 3, 48(1)
+; ASM64-NEXT:   std 4, 56(1)
+; ASM64-DAG:    lbz [[SCRATCH1:[0-9]+]], 51(1)
+; ASM64-DAG:    lwz [[SCRATCH2:[0-9]+]], 56(1)
+; ASM64-NEXT:   add [[SCRATCH3:[0-9]+]], [[SCRATCH2]], [[SCRATCH1]]
+; ASM64-NEXT:   extsw 3, [[SCRATCH3]]
+; ASM64-NEXT:   blr

llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll

 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \
 ; RUN: -mattr=-altivec -verify-machineinstrs < %s | \
 ; RUN: FileCheck %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN:  -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN: FileCheck --check-prefix=ASM %s
 
 %struct.S5 = type { [5 x i8] }
 
 @gS5 = external global %struct.S5, align 1
 
 define void @call_test_byval_5Byte() {
 entry:
-  call void @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1 @gS5)
+  %call = call zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1 @gS5)
   ret void
 }
 
-declare void @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1)
-
 ; CHECK-LABEL: name: call_test_byval_5Byte{{.*}}
 
 ; ASM-LABEL: .call_test_byval_5Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; CHECK:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; CHECK-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
 ; CHECK-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; CHECK-DAG:   renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
 ; CHECK-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
 ; CHECK-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
 ; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM:       stdu 1, -112(1)
 ; ASM-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM-DAG:   lbz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM-DAG:   rlwinm 3, [[REG2]], 24, 0, 7
 ; ASM-DAG:   rldimi 3, [[REG1]], 32, 0
 ; ASM-NEXT:  bl .test_byval_5Byte
 ; ASM-NEXT:  nop
 
+
+define zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1 %s) {
+entry:
+  %arrayidx = getelementptr inbounds %struct.S5, %struct.S5* %s, i32 0, i32 0, i32 4
+  %0 = load i8, i8* %arrayidx, align 1
+  ret i8 %0
+}
+
+; CHECK-LABEL: name:            test_byval_5Byte
+
+; CHECK:      fixedStack:
+; CHECK-NEXT:   - { id: 0, type: default, offset: 48, size: 8, alignment: 16,
+; CHECK:        bb.0.entry:
+; CHECK-NEXT:     liveins: $x3
+; CHECK:          STD killed renamable $x3, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
+; CHECK-NEXT:     renamable $x3 = LBZ8 4, %fixed-stack.0 :: (dereferenceable load 1
+
+; CHECKASM-LABEL: .test_byval_5Byte:
+
+; ASM:       std 3, 48(1)
+; ASM-NEXT:  lbz 3, 52(1)
+; ASM-NEXT:  blr
+
+
 %struct.S6 = type { [6 x i8] }
 
 @gS6 = external global %struct.S6, align 1
 
 define void @call_test_byval_6Byte() {
 entry:
-  call void @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 @gS6)
+  %call = call zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 @gS6)
   ret void
 }
 
-declare void @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1)
-
 ; CHECK-LABEL: name: call_test_byval_6Byte{{.*}}
 
 ; ASM-LABEL: .call_test_byval_6Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; CHECK:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; CHECK-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
 ; CHECK-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; CHECK-DAG:   renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
 ; CHECK-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
 ; CHECK-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
 ; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM:       stdu 1, -112(1)
 ; ASM-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM-DAG:   rlwinm 3, [[REG2]], 16, 0, 15
 ; ASM-DAG:   rldimi 3, [[REG1]], 32, 0
 ; ASM-NEXT:  bl .test_byval_6Byte
 ; ASM-NEXT:  nop
 
+
+define zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 %s) {
+entry:
+  %arrayidx = getelementptr inbounds %struct.S6, %struct.S6* %s, i32 0, i32 0, i32 5
+  %0 = load i8, i8* %arrayidx, align 1
+  ret i8 %0
+}
+
+; CHECK-LABEL: name:            test_byval_6Byte
+
+; CHECK:      fixedStack:
+; CHECK-NEXT:   - { id: 0, type: default, offset: 48, size: 8, alignment: 16,
+; CHECK:        bb.0.entry:
+; CHECK-NEXT:     liveins: $x3
+; CHECK:          STD killed renamable $x3, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
+; CHECK-NEXT:     renamable $x3 = LBZ8 5, %fixed-stack.0 :: (dereferenceable load 1
+
+; CHECKASM-LABEL: .test_byval_6Byte:
+
+; ASM:       std 3, 48(1)
+; ASM-NEXT:  lbz 3, 53(1)
+; ASM-NEXT:  blr
+
 %struct.S7 = type { [7 x i8] }
 
 @gS7 = external global %struct.S7, align 1
 
 define void @call_test_byval_7Byte() {
 entry:
-  call void @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1 @gS7)
+  %call = call zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1 @gS7)
   ret void
 }
 
-declare void @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1)
-
 ; CHECK-LABEL: name: call_test_byval_7Byte{{.*}}
 
 ; ASM-LABEL: .call_test_byval_7Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; CHECK:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; CHECK-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
 ; CHECK-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)

 ; ASM-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM-DAG:   lbz [[REG3:[0-9]+]], 6([[REGADDR]])
 ; ASM-DAG:   rlwinm 3, [[REG3]], 8, 16, 23
 ; ASM-DAG:   rlwimi 3, [[REG2]], 16, 0, 15
 ; ASM-DAG:   rldimi 3, [[REG1]], 32, 0
 ; ASM-NEXT:  bl .test_byval_7Byte
 ; ASM-NEXT:  nop
 
+
+define zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1 %s) {
+entry:
+  %arrayidx = getelementptr inbounds %struct.S7, %struct.S7* %s, i32 0, i32 0, i32 6
+  %0 = load i8, i8* %arrayidx, align 1
+  ret i8 %0
+}
+
+; CHECK-LABEL: name:            test_byval_7Byte
+
+; CHECK:      fixedStack:
+; CHECK-NEXT:   - { id: 0, type: default, offset: 48, size: 8, alignment: 16,
+; CHECK:        bb.0.entry:
+; CHECK-NEXT:     liveins: $x3
+; CHECK:          STD killed renamable $x3, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
+; CHECK-NEXT:     renamable $x3 = LBZ8 6, %fixed-stack.0 :: (dereferenceable load 1
+
+; CHECKASM-LABEL: .test_byval_7Byte:
+
+; ASM:       std 3, 48(1)
+; ASM-NEXT:  lbz 3, 54(1)
+; ASM-NEXT:  blr
+
+
 %struct.S8 = type { [8 x i8] }
 
 @gS8 = external global %struct.S8, align 1
 
 define void @call_test_byval_8Byte() {
 entry:
-  call void @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 @gS8)
+  %call = call zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 @gS8)
   ret void
 }
 
-declare void @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1)
-
 ; CHECK-LABEL: name: call_test_byval_8Byte{{.*}}
 
 ; ASM-LABEL: .call_test_byval_8Byte:
 
 ; CHECK:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; CHECK-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
 ; CHECK-NEXT:  renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
 ; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM:       stdu 1, -112(1)
 ; ASM-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM-NEXT:  ld 3, 0([[REGADDR]])
 ; ASM-NEXT:  bl .test_byval_8Byte
 ; ASM-NEXT:  nop
+
+
+define zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 %s) {
+entry:
+  %arrayidx = getelementptr inbounds %struct.S8, %struct.S8* %s, i32 0, i32 0, i32 7
+  %0 = load i8, i8* %arrayidx, align 1
+  ret i8 %0
+}
+
+; CHECK-LABEL: name:            test_byval_8Byte
+
+; CHECK:      fixedStack:
+; CHECK-NEXT:   - { id: 0, type: default, offset: 48, size: 8, alignment: 16,
+; CHECK:        bb.0.entry:
+; CHECK-NEXT:     liveins: $x3
+; CHECK:          renamable $x[[SCRATCH:[0-9]+]] = COPY $x3
+; CHECK-DAG:      renamable $x3 = RLDICL $x3, 0, 56
+; CHECK-DAG:      STD killed renamable $x[[SCRATCH]], 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
+
+
+; CHECKASM-LABEL: .test_byval_8Byte:
+
+; ASM:       mr [[SCRATCH:[0-9]+]], 3
+; ASM-DAG:   clrldi  3, 3, 56
+; ASM-DAG:   std [[SCRATCH]], 48(1)
+; ASM-NEXT:  blr