[AMDGPU] Implement wave32 DWARF register mapping

[RamNalamothu]

Summary

Implement the DWARF register mapping described in
llvm/docs/AMDGPUUsage.rst

This enables generating appropriate DWARF register numbers for
wave64 and wave32 modes.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

253–255

Ternary operator

llvm/unittests/MC/AMDGPU/CMakeLists.txt

2

Missing the file with check for AMDGPU registered target? I'm not sure exactly how that works with unit tests, but it's done for GlobalISel unit tests with AArch64

llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp

20

probably needs call_once

31

Can this be a StringRef? You also don't reuse it below. This should probably also use the full 3 component triple

34

This should be an ASSERT_TRUE(t) << Error

39

ASSERT_TRUE

45

Don't need the llvm prefixes on all of these

91

Same as above

96

Same as above

llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp

28

ASSERT_TRUE(T) << Error

92

Should probably repeat test with more combinations of wavefront size subtarget features

[RamNalamothu]

Address review comments.

[RamNalamothu]

llvm/unittests/MC/AMDGPU/CMakeLists.txt

2

Sorry didn't get you and also I didn't notice anything special here with AArch64 unit tests.

llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp

31

Using only the 2 component triple as the dwarf register mappings are agnostic to a particular OS (the 3rd component).

[arsenm]

llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp

30–39

This common setup code should be moved to a setup function, and the test should not fail on target creation failure. Otherwise this will fail when AMDGPU isn't build. unittests/CodeGen/AArch64SelectionDAGTests.cpp is a model for this

31

The second part doesn't do anything. Setting the OS is the interesting part since it does default to the host OS, so introduces potential variability

[RamNalamothu]

Address review comments.

[arsenm]

llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp

45

This isn't creating an owning reference? Why is this unique ptr?

50

The multiple OS tests aren't needed, my point was it should just be set to something sensible other than the defaulted host OS

56

This can be a regular array

80

Regular array

[RamNalamothu]

Use array for test values and eliminate memory leak.

[RamNalamothu]

llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp

45

Thanks for catching this. Fixed the memory leak.

50

May be not needed but they do test few OS flavors for sanity and I guess there is no harm in having those tests.

[arsenm]

llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp

74

These can just be const char* arrays

[scott.linder]

Thanks Ram, LGTM too. Sorry for taking so long to review.

[arsenm]

24698e526f619271705fe72bcaa928be9bc82484

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
 
 #include "AMDGPU.h"
 #include "AMDGPUCallLowering.h"
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "R600FrameLowering.h"
 #include "R600ISelLowering.h"
 #include "R600InstrInfo.h"
 #include "SIFrameLowering.h"
 #include "SIISelLowering.h"
 #include "SIInstrInfo.h"
 #include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/ADT/Triple.h"
public:
   unsigned getImplicitArgNumBytes(const Function &F) const {
     if (isMesaKernel(F))
       return 16;
     return AMDGPU::getIntegerAttribute(F, "amdgpu-implicitarg-num-bytes", 0);
   }
   uint64_t getExplicitKernArgSize(const Function &F, Align &MaxAlign) const;
   unsigned getKernArgSegmentSize(const Function &F, Align &MaxAlign) const;
 
+  /// \returns Corresponsing DWARF register number mapping flavour for the
+  /// \p WavefrontSize.
+  AMDGPUDwarfFlavour getAMDGPUDwarfFlavour() const {
+    return WavefrontSize == 32 ? AMDGPUDwarfFlavour::Wave32
+                               : AMDGPUDwarfFlavour::Wave64;
+  }
+
   virtual ~AMDGPUSubtarget() {}
 };
 
 class GCNSubtarget : public AMDGPUGenSubtargetInfo,
                      public AMDGPUSubtarget {
 
   using AMDGPUSubtarget::getMaxWavesPerEU;
 

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

 #include "AMDGPUCallLowering.h"
 #include "AMDGPUInstructionSelector.h"
 #include "AMDGPULegalizerInfo.h"
 #include "AMDGPUMacroFusion.h"
 #include "AMDGPUTargetObjectFile.h"
 #include "AMDGPUTargetTransformInfo.h"
 #include "GCNIterativeScheduler.h"
 #include "GCNSchedStrategy.h"
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "R600MachineScheduler.h"
 #include "SIMachineFunctionInfo.h"
 #include "SIMachineScheduler.h"
 #include "TargetInfo/AMDGPUTargetInfo.h"
 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
 #include "llvm/CodeGen/GlobalISel/Localizer.h"
AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
                                          Optional<Reloc::Model> RM,
                                          Optional<CodeModel::Model> CM,
                                          CodeGenOpt::Level OptLevel)
     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
                         FS, Options, getEffectiveRelocModel(RM),
                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
       TLOF(createTLOF(getTargetTriple())) {
   initAsmInfo();
+  if (TT.getArch() == Triple::amdgcn) {
+    if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
+      MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
+    else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
+      MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
+  }
 }
 
 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
 
 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
 

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h

 class MCRegisterInfo;
 class MCSubtargetInfo;
 class MCTargetOptions;
 class StringRef;
 class Target;
 class Triple;
 class raw_pwrite_stream;
 
+enum AMDGPUDwarfFlavour { Wave64 = 0, Wave32 = 1 };
+
+MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour);
+
 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
                                        const MCRegisterInfo &MRI,
                                        MCContext &Ctx);
 MCInstrInfo *createR600MCInstrInfo();
 
 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
                                      const MCRegisterInfo &MRI,
                                      MCContext &Ctx);

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   if (TT.getArch() == Triple::r600)
     InitR600MCRegisterInfo(X, 0);
   else
     InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG);
   return X;
 }
 
+MCRegisterInfo *llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour) {
+  MCRegisterInfo *X = new MCRegisterInfo();
+  InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG, DwarfFlavour);
+  return X;
+}
+
 static MCSubtargetInfo *
 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   if (TT.getArch() == Triple::r600)
     return createR600MCSubtargetInfoImpl(TT, CPU, FS);
   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

 #include "AMDGPUGenRegisterInfo.inc"
 
 static cl::opt<bool> EnableSpillSGPRToVGPR(
   "amdgpu-spill-sgpr-to-vgpr",
   cl::desc("Enable spilling VGPRs to SGPRs"),
   cl::ReallyHidden,
   cl::init(true));
 
-SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST) :
-  AMDGPUGenRegisterInfo(0),
-  ST(ST),
-  SpillSGPRToVGPR(EnableSpillSGPRToVGPR),
-  isWave32(ST.isWave32()) {
-}
+SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
+    : AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour()), ST(ST),
+      SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) {}
 
 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved,
                                            unsigned Reg) const {
   MCRegAliasIterator R(Reg, this, true);
 
   for (; R.isValid(); ++R)
     Reserved.set(*R);
 }

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

 // Pseudo-registers: Used as placeholders during isel and immediately
 // replaced, never seeing the verifier.
 def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>;
 def FP_REG : SIReg<"fp", 0>;
 def SP_REG : SIReg<"sp", 0>;
 def SCRATCH_WAVE_OFFSET_REG : SIReg<"scratch_wave_offset", 0>;
 
 // Pseudo-register to represent the program-counter DWARF register.
-def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16]> {
+def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 0]> {
   // There is no physical register corresponding to a "program counter", but
   // we need to encode the concept in debug information in order to represent
   // things like the return value in unwind information.
   let isArtificial = 1;
 }
 
 // VCC for 64-bit instructions
 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = 106;
 }
 
-def EXEC_LO : SIReg<"exec_lo", 126>, DwarfRegNum<[1]>;
+def EXEC_LO : SIReg<"exec_lo", 126>, DwarfRegNum<[1, 1]>;
 def EXEC_HI : SIReg<"exec_hi", 127>;
 
-def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17]> {
+def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = 126;
 }
 
 // 32-bit real registers, for MC only.
 // May be used with both 32-bit and 64-bit operands.
 def SRC_VCCZ : SIReg<"src_vccz", 251>;

 def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>;
 def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>;
 def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
 
 // SGPR registers
 foreach Index = 0-105 in {
   def SGPR#Index :
     SIReg <"s"#Index, Index>,
-    DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
+    DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
+                 !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
 }
 
 // VGPR registers
 foreach Index = 0-255 in {
   def VGPR#Index :
       SIReg <"v"#Index, Index>,
-      DwarfRegNum<[!add(Index, 2560)]> {
+      DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]> {
     let HWEncoding{8} = 1;
   }
 }
 
 // AccVGPR registers
 foreach Index = 0-255 in {
   def AGPR#Index :
       SIReg <"a"#Index, Index>,
-      DwarfRegNum<[!add(Index, 3072)]> {
+      DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]> {
     let HWEncoding{8} = 1;
   }
 }
 
 //===----------------------------------------------------------------------===//
 //  Groupings using register classes and tuples
 //===----------------------------------------------------------------------===//
 

llvm/unittests/MC/AMDGPU/CMakeLists.txt

+set(LLVM_LINK_COMPONENTS
+  ${LLVM_TARGETS_TO_BUILD}
+  MC
+  Support
+  )
+
+add_llvm_unittest(AMDGPUDwarfTests
+  DwarfRegMappings.cpp
+  )

llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp

+//===- llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp ----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Target/TargetMachine.h"
+#include "gtest/gtest.h"
+#include <thread>
+
+using namespace llvm;
+
+std::once_flag flag;
+
+void InitializeAMDGPUTarget() {
+  std::call_once(flag, []() {
+    LLVMInitializeAMDGPUTargetInfo();
+    LLVMInitializeAMDGPUTarget();
+    LLVMInitializeAMDGPUTargetMC();
+  });
+}
+
+std::unique_ptr<LLVMTargetMachine>
+createTargetMachine(std::string TStr, StringRef CPU, StringRef FS) {
+  InitializeAMDGPUTarget();
+
+  std::string Error;
+  const Target *T = TargetRegistry::lookupTarget(TStr, Error);
+  if (!T)
+    return nullptr;
+
+  TargetOptions Options;
+  return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
+      T->createTargetMachine(TStr, CPU, FS, Options, None, None)));
+}
+
+TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) {
+  // Test triple OS strings
+  std::vector<std::string> OSTestValues = {"", "amdhsa", "amdpal"};
+
+  for (auto OS : OSTestValues) {
+    auto TM =
+        createTargetMachine("amdgcn-amd-" + OS, "gfx1010", "+wavefrontsize64");
+    if (TM && TM->getMCRegisterInfo()) {
+      auto MRI = TM->getMCRegisterInfo();
+      // Wave64 Dwarf register mapping test numbers
+      // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
+      // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
+      // A0 => 3072, A255 => 3327
+      for (int llvmReg : {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
+        MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
+        EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
+      }
+    }
+  }
+}
+
+TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
+
+  // Test triple OS strings
+  std::vector<std::string> OSTestValues = {"", "amdhsa", "amdpal"};
+
+  for (auto OS : OSTestValues) {
+    auto TM =
+        createTargetMachine("amdgcn-amd-" + OS, "gfx1010", "+wavefrontsize32");
+    if (TM && TM->getMCRegisterInfo()) {
+      auto MRI = TM->getMCRegisterInfo();
+      // Wave32 Dwarf register mapping test numbers
+      // PC_32 => 0, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
+      // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
+      // A0 => 2048, A255 => 2303
+      for (int llvmReg : {0, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
+        MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
+        EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
+      }
+    }
+  }
+}

llvm/unittests/MC/CMakeLists.txt

 set(LLVM_LINK_COMPONENTS
   ${LLVM_TARGETS_TO_BUILD}
   MC
   MCDisassembler
   Support
   )
 
 add_llvm_unittest(MCTests
   Disassembler.cpp
   DwarfLineTables.cpp
   MCInstPrinter.cpp
   StringTableBuilderTest.cpp
   TargetRegistry.cpp
   )
+
+add_subdirectory(AMDGPU)

llvm/unittests/Target/AMDGPU/CMakeLists.txt

+include_directories(
+  ${CMAKE_SOURCE_DIR}/lib/Target/AMDGPU
+  ${CMAKE_BINARY_DIR}/lib/Target/AMDGPU
+  )
+
+set(LLVM_LINK_COMPONENTS
+  ${LLVM_TARGETS_TO_BUILD}
+  Support
+  Target
+  )
+
+add_llvm_target_unittest(AMDGPUTests
+  DwarfRegMappings.cpp
+  )

llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp

+//===- llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp ------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPUSubtarget.h"
+#include "AMDGPUTargetMachine.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Target/TargetMachine.h"
+#include "gtest/gtest.h"
+#include <thread>
+
+using namespace llvm;
+
+std::once_flag flag;
+
+void InitializeAMDGPUTarget() {
+  std::call_once(flag, []() {
+    LLVMInitializeAMDGPUTargetInfo();
+    LLVMInitializeAMDGPUTarget();
+    LLVMInitializeAMDGPUTargetMC();
+  });
+}
+
+std::unique_ptr<const GCNTargetMachine>
+createTargetMachine(std::string TStr, StringRef CPU, StringRef FS) {
+  InitializeAMDGPUTarget();
+
+  std::string Error;
+  const Target *T = TargetRegistry::lookupTarget(TStr, Error);
+  if (!T)
+    return nullptr;
+
+  TargetOptions Options;
+  return std::unique_ptr<GCNTargetMachine>(static_cast<GCNTargetMachine *>(
+      T->createTargetMachine(TStr, CPU, FS, Options, None, None)));
+}
+
+TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) {
+  // Test triple OS strings
+  std::vector<std::string> OSTestValues = {"", "amdhsa", "amdpal"};
+
+  for (auto OS : OSTestValues) {
+    auto TM =
+        createTargetMachine("amdgcn-amd-" + OS, "gfx1010", "+wavefrontsize64");
+    if (TM) {
+      GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
+                      std::string(TM->getTargetFeatureString()), *TM);
+      auto MRI = ST.getRegisterInfo();
+      if (MRI) {
+        // Wave64 Dwarf register mapping test numbers
+        // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
+        // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
+        // A0 => 3072, A255 => 3327
+        for (int llvmReg :
+             {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
+          MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
+          EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
+        }
+      }
+    }
+  }
+}
+
+TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
+
+  // Test triple OS strings
+  std::vector<std::string> OSTestValues = {"", "amdhsa", "amdpal"};
+
+  for (auto OS : OSTestValues) {
+    auto TM =
+        createTargetMachine("amdgcn-amd-" + OS, "gfx1010", "+wavefrontsize32");
+    if (TM) {
+      GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
+                      std::string(TM->getTargetFeatureString()), *TM);
+      auto MRI = ST.getRegisterInfo();
+      if (MRI) {
+        // Wave32 Dwarf register mapping test numbers
+        // PC_32 => 0, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
+        // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
+        // A0 => 2048, A255 => 2303
+        for (int llvmReg : {0, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
+          MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
+          EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
+        }
+      }
+    }
+  }
+}