[PPC][AIX] Implement variadic function handling in LowerFormalArguments_AIX

[ZarkoCA]

Summary

This patch adds support for handling of variadic functions for AIX. This includes ensuring that use and consume correct type of va_list (char *va_list) for AIX.

This patch is dependent on https://reviews.llvm.org/D76360 to emit the correct IR in 32BIT AIX.

[ZarkoCA]

Clang formatted the patch and fixed typo in testcase.

[sfertile]

As a first step, I suggest we break the clang changes and the LLVM changes into 2 separate patches.

[ZarkoCA]

• Removed 64BIT support varargs.
• Added a fatal error for 64bit varargs on AIX.
• Removed 64bit testcases

[ZarkoCA]

Removed unrelated changes in aix-cc-abi.ll

[ZarkoCA]

I will split this patch up in two. One for changes in clang specific for 32BIT AIX varargs, and a second for changes in llc for 32/64BIT varargs.

[jasonliu]

clang/lib/Basic/Targets/PPC.h

373 ↗

(On Diff #250213)

nit: add '.' to the comment while we are at it.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7197

Would it be better if we remove the "else if" and make it

if (VA.isMemloc()){
...
continue;
}

Since this matches the last if statement, and also the style in LowerCall_AIX.

7206

We could remove this definition if we have one defined outside.

7237

The style in this file is "static const" instead of "const static".

7245

This only gets used by 32bit-SVR4 target, I don't think we need to set it.

7250

start a new line before the comment.

7256

Just curious, in what scenario would we already have the GPR stored in a virtual register before we store that GPR on that stack?

llvm/test/CodeGen/PowerPC/aix-cc-abi-va_args-32.ll

9 ↗

(On Diff #250772)

I'm not seeing any attribute here, so I'm assuming every "#number" and comments about "Function Attrs" in the test could be removed.

[ZarkoCA]

Addressed comments by Jason.
Re-added 64BIT changes for LLC.
Split clang changes and made a patch specific with them https://reviews.llvm.org/D76360

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7256

I don't think we need to include that, it was a remnant from an earlier prototype I had. Thanks for pointing it out.

[ZarkoCA]

Fixed testcase breakages.

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7246

This two array gets used to in CC_AIX and here. It would be great if we only have one set of copy.

7247

Could we add an assert to make sure "array_lengthof(GPR_32) == array_lengthof(GPR_64)"
nit:
unsigned const -> const unsigned

7257

Could we do

const unsigned VReg = IsPPC64 ? MF.addLiveIn(GPR_64[GPRIndex], &PPC::G8RCRegClass)
                              : MF.addLiveIn(GPR_32[GPRIndex], &PPC::GPRCRegClass);

llvm/test/CodeGen/PowerPC/aix-cc-abi-va_args-32.ll

27 ↗

(On Diff #251111)

These tests used for loops to call va_arg mutliple times.
Maybe it's just me, but I found the test cases are much harder to read.
I would suggest maybe just unroll the for loop and generate as much as the va_arg call that you need?

For the cases below, I suppose you would want to call va_arg 9 times, and 2 times respectfully. Maybe it's not that bad. If the tests gets too long, you could consider split the tests into separate files.

33 ↗

(On Diff #251111)

a is 1, so we would only call va_arg once, despite we have 9 vaarg argument. Is this the intention of the test?

162 ↗

(On Diff #251111)

We only have 2 va_arg arguments here, but we called va_arg 8 times? I think that's undefined behavior.

[jasonliu]

llvm/test/CodeGen/PowerPC/aix-cc-abi-va_args-32.ll

1 ↗

(On Diff #251111)

Do we need '-O2' specified here and below?

15 ↗

(On Diff #251111)

These variables didn't get used anywhere.

[jasonliu]

llvm/test/CodeGen/PowerPC/aix-cc-abi-va_args-32.ll

7 ↗

(On Diff #251111)

A general comment about how to test va_arg.
I think the two test cases we have here are not enough.
On top of my head I would probably add in getting double as va_arg argument, uses of va_copy and so on.
It's probably worth checking how other targets test va_arg. Grep "va_start" in llvm/test/CodeGen would give you a lot of hit.

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7185

Do we need && !VA.needsCustom() here?

[ZarkoCA]

Addressed code comments, working on adding and fixing tests for further clarity.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7185

Yes, it's better if I add it, thanks.

7246

I agree, but the array is local to CC_AIX as far as I understand and there is not a good way to access it from here without having to modify CC_AIX. I think it would be a good to do it at a later point when it's not undergoing so much change already.

llvm/test/CodeGen/PowerPC/aix-cc-abi-va_args-32.ll

1 ↗

(On Diff #251111)

It makes the IR and assembly much cleaner and easier to read, imo.

7 ↗

(On Diff #251111)

Yes, I can clean up the tests and add more. Agreed we need more and I can simplify them so it's clear what's being tested.

15 ↗

(On Diff #251111)

Removed, but as I said earlier, I'll also do a rework of the tests.

27 ↗

(On Diff #251111)

Yes, see reply above, I will rework the tests.

33 ↗

(On Diff #251111)

a = 1 doesn't mean we call va_arg once. This is the IR for the function definition that I got using this c code (modified for this example):

a = 1;
int va_arg1(int a,...) {
...
}

The callee doesn't know how many vararg arguments will be called, just does the setup for the variadic parameter (...) in the IR.

162 ↗

(On Diff #251111)

Seem my reply above. That said, there is some confusion with respect to tests and they'll be reworked.

[ZarkoCA]

Simplified testcases.
Added testcases for variadic arguments being passed directly to the stack when all registers are used.

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7242

I'd prefer us to keep the original naming convention(GPR_32) for these two arrays, so that it's easy for us to common them up later in an NFC patch.

llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll

18

I think it would be more clear if we actually have another va_list to copy instead of just va_copying itself. The same applies to all the places we call va_copy.
Also it's not very clear to me which part in the check result actually tells me about the effect of the va_copy though.

98

llvm.stackprotector could be removed?

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll

18

Those are both good points. I'm rewriting the test and adding comments to the IR/assembly to make it clearer.

[ZarkoCA]

Rebased to include byval changes.

Fixed name of array.

Fixed up test case as per comment.

[ZarkoCA]

Fixing test case issues.

[ZarkoCA]

Fixed test cases that were breaking.

[jasonliu]

llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll

9

minor nit: I don't think these target datalayout and triple are necessary.

[ZarkoCA]

Removed data layout and target triple info from test output.

[ZarkoCA]

Rebase and ping.

[jasonliu]

Not sure if you want to wait for the feedback from @sfertile and @cebowleratibm , but I'm good with the current revision.

[jasonliu]

This is landed in https://github.com/llvm/llvm-project/commit/085689d44cb95604072d0f2b130167d9410ea155.
Not sure why it does not close automatically.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 
 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
   MachineFunction &MF = DAG.getMachineFunction();
   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
   EVT PtrVT = getPointerTy(MF.getDataLayout());
 
   SDLoc dl(Op);
 
-  if (Subtarget.isPPC64()) {
+  if (Subtarget.isPPC64() || Subtarget.isAIXABI()) {
     // vastart just stores the address of the VarArgsFrameIndex slot into the
     // memory location argument.
     SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
     const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
     return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
                         MachinePointerInfo(SV));
   }
 
SDValue PPCTargetLowering::LowerFormalArguments_AIX(
     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 
   assert((CallConv == CallingConv::C || CallConv == CallingConv::Cold ||
           CallConv == CallingConv::Fast) &&
          "Unexpected calling convention!");
 
-  if (isVarArg)
-    report_fatal_error("This call type is unimplemented on AIX.");
-
   if (getTargetMachine().Options.GuaranteedTailCallOpt)
     report_fatal_error("Tail call support is unimplemented on AIX.");
 
   if (useSoftFloat())
     report_fatal_error("Soft float support is unimplemented on AIX.");
 
   const PPCSubtarget &Subtarget =
       static_cast<const PPCSubtarget &>(DAG.getSubtarget());
   if (Subtarget.hasQPX())
     report_fatal_error("QPX support is not supported on AIX.");
 
   const bool IsPPC64 = Subtarget.isPPC64();
   const unsigned PtrByteSize = IsPPC64 ? 8 : 4;
 
   // Assign locations to all of the incoming arguments.
   SmallVector<CCValAssign, 16> ArgLocs;
   MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo &MFI = MF.getFrameInfo();
   CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
 
   const EVT PtrVT = getPointerTy(MF.getDataLayout());
   // Reserve space for the linkage area on the stack.
   const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
   CCInfo.AllocateStack(LinkageSize, PtrByteSize);
   CCInfo.AnalyzeFormalArguments(Ins, CC_AIX);
 
if (Flags.isByVal()) {
 
         const CCValAssign RL = ArgLocs[I++];
         HandleRegLoc(RL.getLocReg(), Offset);
       }
       continue;
     }
 
     EVT ValVT = VA.getValVT();
-    if (VA.isRegLoc()) {
+    if (VA.isRegLoc() && !VA.needsCustom()) {
       MVT::SimpleValueType SVT = ValVT.getSimpleVT().SimpleTy;
       unsigned VReg =
           MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
       if (ValVT.isScalarInteger() &&
           (ValVT.getSizeInBits() < LocVT.getSizeInBits())) {
         ArgValue =
             truncateScalarIntegerArg(Flags, ValVT, DAG, ArgValue, LocVT, dl);
       }
       InVals.push_back(ArgValue);
       continue;
     }
-
+    if (VA.isMemLoc()) {
       const unsigned LocSize = LocVT.getStoreSize();
       const unsigned ValSize = ValVT.getStoreSize();
-    assert((ValSize <= LocSize) && "Object size is larger than size of MemLoc");
+      assert((ValSize <= LocSize) &&
+             "Object size is larger than size of MemLoc");
       int CurArgOffset = VA.getLocMemOffset();
       // Objects are right-justified because AIX is big-endian.
       if (LocSize > ValSize)
         CurArgOffset += LocSize - ValSize;
-    MachineFrameInfo &MFI = MF.getFrameInfo();
       // Potential tail calls could cause overwriting of argument stack slots.
       const bool IsImmutable =
           !(getTargetMachine().Options.GuaranteedTailCallOpt &&
             (CallConv == CallingConv::Fast));
       int FI = MFI.CreateFixedObject(ValSize, CurArgOffset, IsImmutable);
       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
-    SDValue ArgValue = DAG.getLoad(ValVT, dl, Chain, FIN, MachinePointerInfo());
+      SDValue ArgValue =
+          DAG.getLoad(ValVT, dl, Chain, FIN, MachinePointerInfo());
       InVals.push_back(ArgValue);
+      continue;
+    }
   }
 
   // On AIX a minimum of 8 words is saved to the parameter save area.
   const unsigned MinParameterSaveArea = 8 * PtrByteSize;
   // Area that is at least reserved in the caller of this function.
   unsigned CallerReservedArea =
       std::max(CCInfo.getNextStackOffset(), LinkageSize + MinParameterSaveArea);
 
   // Set the size that is at least reserved in caller of this function. Tail
   // call optimized function's reserved stack space needs to be aligned so
   // that taking the difference between two stack areas will result in an
   // aligned stack.
   CallerReservedArea =
       EnsureStackAlignment(Subtarget.getFrameLowering(), CallerReservedArea);
   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
   FuncInfo->setMinReservedArea(CallerReservedArea);
 
+  if (isVarArg) {
+    FuncInfo->setVarArgsFrameIndex(
+        MFI.CreateFixedObject(PtrByteSize, CCInfo.getNextStackOffset(), true));
+    SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
+
+    static const MCPhysReg GPR_32[] = {PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+                                       PPC::R7, PPC::R8, PPC::R9, PPC::R10};
+
+    static const MCPhysReg GPR_64[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6,
+                                       PPC::X7, PPC::X8, PPC::X9, PPC::X10};
+    const unsigned NumGPArgRegs = array_lengthof(IsPPC64 ? GPR_64 : GPR_32);
+
+    // The fixed integer arguments of a variadic function are stored to the
+    // VarArgsFrameIndex on the stack so that they may be loaded by
+    // dereferencing the result of va_next.
+    for (unsigned GPRIndex =
+             (CCInfo.getNextStackOffset() - LinkageSize) / PtrByteSize;
+         GPRIndex < NumGPArgRegs; ++GPRIndex) {
+
+      const unsigned VReg =
+          IsPPC64 ? MF.addLiveIn(GPR_64[GPRIndex], &PPC::G8RCRegClass)
+                  : MF.addLiveIn(GPR_32[GPRIndex], &PPC::GPRCRegClass);
+
+      SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
+      SDValue Store =
+          DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
+      MemOps.push_back(Store);
+      // Increment the address for the next argument to store.
+      SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
+      FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
+    }
+  }
+
   if (!MemOps.empty())
     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
 
   return Chain;
 }
 
 SDValue PPCTargetLowering::LowerCall_AIX(
     SDValue Chain, SDValue Callee, CallFlags CFlags,

llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll

+; RUN: llc -O2 -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
+
+; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN:  -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefixes=CHECKASM,ASM32 %s
+
+  define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr  {
+  entry:
+    %arg1 = alloca i8*, align 4
+    %arg2 = alloca i8*, align 4
+    %0 = bitcast i8** %arg1 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
+    %1 = bitcast i8** %arg2 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %1)
+    call void @llvm.va_start(i8* nonnull %0)
+    call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
+    %argp.cur = load i8*, i8** %arg1, align 4
+    %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
+    store i8* %argp.next, i8** %arg1, align 4
+    %2 = bitcast i8* %argp.cur to i32*
+    %3 = load i32, i32* %2, align 4
+    %add = add nsw i32 %3, %a
+    %argp.cur2 = load i8*, i8** %arg2, align 4
+    %argp.next3 = getelementptr inbounds i8, i8* %argp.cur2, i32 4
+    store i8* %argp.next3, i8** %arg2, align 4
+    %4 = bitcast i8* %argp.cur2 to i32*
+    %5 = load i32, i32* %4, align 4
+    %mul = shl i32 %5, 1
+    %add4 = add nsw i32 %add, %mul
+    call void @llvm.va_end(i8* nonnull %0)
+    call void @llvm.va_end(i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
+    ret i32 %add4
+  }
+
+  declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+  declare void @llvm.va_start(i8*)
+  declare void @llvm.va_copy(i8*, i8*)
+  declare void @llvm.va_end(i8*)
+  declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+
+; 32BIT-LABEL:   name:            int_va_arg
+; 32BIT-LABEL;   liveins:
+; 32BIT-DAG:     - { reg: '$r3', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r4', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r5', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r6', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r7', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r8', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r9', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r10', virtual-reg: '' }
+
+; 32BIT-LABEL:   fixedStack:
+; 32BIT-DAG:     - { id: 0, type: default, offset: 28, size: 4
+
+; 32BIT-LABEL:   stack:
+; 32BIT-DAG:     - { id: 0, name: arg1, type: default, offset: 0, size: 4
+; 32BIT-DAG:     - { id: 1, name: arg2, type: default, offset: 0, size: 4
+
+; 32BIT-LABEL:   body:             |
+; 32BIT-DAG:     liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
+; 32BIT-DAG:     STW killed renamable $r4, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0)
+; 32BIT-DAG:     STW killed renamable $r5, 4, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 4)
+; 32BIT-DAG:     STW killed renamable $r6, 8, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG:     STW killed renamable $r7, 12, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG:     STW killed renamable $r8, 16, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG:     STW killed renamable $r9, 20, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG:     STW killed renamable $r10, 24, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG:     STW killed renamable $r5, 0, %stack.1.arg2 :: (store 4 into %ir.arg2)
+; 32BIT-DAG:     renamable $r5 = ADDI %fixed-stack.0, 4
+; 32BIT-DAG:     STW killed renamable $r4, 0, %stack.1.arg2 :: (store 4 into %ir.1)
+; 32BIT-DAG:     renamable $r4 = ADDI %fixed-stack.0, 0
+; 32BIT-DAG:     STW renamable $r4, 0, %stack.0.arg1 :: (store 4 into %ir.0)
+; 32BIT-DAG:     STW renamable $r5, 0, %stack.0.arg1 :: (store 4 into %ir.arg1)
+; 32BIT-DAG:     renamable $r4 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.2)
+; 32BIT-DAG:     renamable $r5 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.4)
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r4, killed renamable $r3
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4
+; 32BIT-DAG:     BLR implicit $lr, implicit $rm, implicit $r3
+
+; ASM32-LABEL:   .int_va_arg:
+; set up fixed stack frame for incoming va_args r4->r10
+; ASM32-DAG:     stw 4, 28(1)
+; ASM32-DAG:     stw 5, 32(1)
+; ASM32-DAG:     stw 6, 36(1)
+; ASM32-DAG:     stw 7, 40(1)
+; ASM32-DAG:     stw 8, 44(1)
+; ASM32-DAG:     stw 9, 48(1)
+; ASM32-DAG:     stw 10, 52(1)
+; load of arg1 from fixed stack offset
+; ASM32-DAG:     lwz [[ARG1:[0-9]+]], 28(1)
+; va_copy load of arg2 from fixed stack offset
+; ASM32-DAG:     lwz [[ARG2:[0-9]+]], 28(1)
+; ASM32-DAG:     blr
+
+  define i32 @int_stack_va_arg(i32 %one, i32 %two, i32 %three, i32 %four, i32 %five, i32 %six, i32 %seven, i32 %eight, ...) local_unnamed_addr {
+  entry:
+    %arg1 = alloca i8*, align 4
+    %arg2 = alloca i8*, align 4
+    %0 = bitcast i8** %arg1 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
+    %1 = bitcast i8** %arg2 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %1)
+    call void @llvm.va_start(i8* nonnull %0)
+    call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
+    %add = add nsw i32 %two, %one
+    %add2 = add nsw i32 %add, %three
+    %add3 = add nsw i32 %add2, %four
+    %add4 = add nsw i32 %add3, %five
+    %add5 = add nsw i32 %add4, %six
+    %add6 = add nsw i32 %add5, %seven
+    %add7 = add nsw i32 %add6, %eight
+    %argp.cur = load i8*, i8** %arg1, align 4
+    %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
+    store i8* %argp.next, i8** %arg1, align 4
+    %2 = bitcast i8* %argp.cur to i32*
+    %3 = load i32, i32* %2, align 4
+    %add8 = add nsw i32 %add7, %3
+    %argp.cur9 = load i8*, i8** %arg2, align 4
+    %argp.next10 = getelementptr inbounds i8, i8* %argp.cur9, i32 4
+    store i8* %argp.next10, i8** %arg2, align 4
+    %4 = bitcast i8* %argp.cur9 to i32*
+    %5 = load i32, i32* %4, align 4
+    %mul = shl i32 %5, 1
+    %add11 = add nsw i32 %add8, %mul
+    call void @llvm.va_end(i8* nonnull %0)
+    call void @llvm.va_end(i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
+    ret i32 %add11
+  }
+
+; 32BIT-LABEL:   name:            int_stack_va_arg
+; 32BIT-LABEL:   liveins:
+; 32BIT-DAG:     - { reg: '$r3', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r4', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r5', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r6', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r7', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r8', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r9', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r10', virtual-reg: '' }
+
+; 32BIT-LABEL:   fixedStack:
+; 32BIT-DAG:     - { id: 0, type: default, offset: 56, size: 4
+
+; 32BIT-LABEL:   stack:
+; 32BIT-DAG:     - { id: 0, name: arg1, type: default, offset: 0, size: 4
+; 32BIT-DAG:     - { id: 1, name: arg2, type: default, offset: 0, size: 4
+
+; 32BIT-LABEL:   body:             |
+; 32BIT-DAG:     liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r5
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r7
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r8
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r9
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r10
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r4, killed renamable $r3
+; 32BIT-DAG:     renamable $r4 = ADDI %fixed-stack.0, 0
+; 32BIT-DAG:     STW killed renamable $r4, 0, %stack.0.arg1 :: (store 4 into %ir.arg1)
+; 32BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r4
+; 32BIT-DAG:     renamable $r4 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.4, align 8)
+; 32BIT-DAG:     renamable $r11 = LI 4
+; 32BIT-DAG:     BLR implicit $lr, implicit $rm, implicit $r3
+
+; ASM32-LABEL:   .int_stack_va_arg:
+; ASM32-DAG:     add 3, 4, 3
+; ASM32-DAG:     add 3, 3, 5
+; ASM32-DAG:     add 3, 3, 6
+; ASM32-DAG:     add 3, 3, 7
+; ASM32-DAG:     add 3, 3, 8
+; ASM32-DAG:     add 3, 3, 9
+; ASM32-DAG:     add 3, 3, 10
+; ASM32-DAG:     lwz [[ARG1:[0-9]+]], 56(1)
+; ASM32-DAG:     li [[ARG2:[0-9]+]], [[ARG1]]
+; ASM32-DAG:     add 3, 3, [[ARG1:[0-9]+]]
+; ASM32-DAG:     add 3, 3, [[ARG2:[0-9]+]]
+; ASM32-DAG:     blr
+
+  define double @double_va_arg(double %a, ...) local_unnamed_addr  {
+  entry:
+    %arg1 = alloca i8*, align 4
+    %arg2 = alloca i8*, align 4
+    %0 = bitcast i8** %arg1 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
+    %1 = bitcast i8** %arg2 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %1)
+    call void @llvm.va_start(i8* nonnull %0)
+    call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
+    %argp.cur = load i8*, i8** %arg1, align 4
+    %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 8
+    store i8* %argp.next, i8** %arg1, align 4
+    %2 = bitcast i8* %argp.cur to double*
+    %3 = load double, double* %2, align 4
+    %add = fadd double %3, %a
+    %argp.cur2 = load i8*, i8** %arg2, align 4
+    %argp.next3 = getelementptr inbounds i8, i8* %argp.cur2, i32 8
+    store i8* %argp.next3, i8** %arg2, align 4
+    %4 = bitcast i8* %argp.cur2 to double*
+    %5 = load double, double* %4, align 4
+    %mul = fmul double %5, 2.000000e+00
+    %add4 = fadd double %add, %mul
+    call void @llvm.va_end(i8* nonnull %0)
+    call void @llvm.va_end(i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
+    ret double %add4
+  }
+
+; 32BIT-LABEL:   name:            double_va_arg
+; 32BIT-LABEL:   liveins:
+; 32BIT-DAG:     - { reg: '$f1', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r5', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r6', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r7', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r8', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r9', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$r10', virtual-reg: '' }
+
+; 32BIT-LABEL:   fixedStack:
+; 32BIT-DAG:     - { id: 0, type: default, offset: 32, size: 4
+
+; 32BIT-LABEL:   stack:
+; 32BIT-DAG:     - { id: 0, name: arg1, type: default, offset: 0, size: 4
+; 32BIT-DAG:     - { id: 1, name: arg2, type: default, offset: 0, size: 4
+
+; 32BIT-LABEL:   body:             |
+; 32BIT-DAG:     liveins: $f1, $r5, $r6, $r7, $r8, $r9, $r10
+; 32BIT-DAG:     renamable $r3 = ADDI %fixed-stack.0, 0
+; 32BIT-DAG:     STW renamable $r5, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0, align 16)
+; 32BIT-DAG:     STW renamable $r6, 4, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 4)
+; 32BIT-DAG:     STW killed renamable $r7, 8, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 8, align 8)
+; 32BIT-DAG:     STW killed renamable $r8, 12, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG:     STW killed renamable $r9, 16, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 16, align 16)
+; 32BIT-DAG:     STW killed renamable $r10, 20, %fixed-stack.0 :: (store 4)
+; 32BIT-DAG:     STW renamable $r3, 0, %stack.0.arg1 :: (store 4 into %ir.0)
+; 32BIT-DAG:     STW killed renamable $r3, 0, %stack.1.arg2 :: (store 4 into %ir.1)
+; 32BIT-DAG:     BLR implicit $lr, implicit $rm, implicit $f1
+
+; ASM32-LABEL:  .double_va_arg:
+; ASM32-DAG:    stw 5, 32(1)
+; ASM32-DAG:    stw 6, 36(1)
+; ASM32-DAG:    stw 7, 40(1)
+; ASM32-DAG:    stw 8, 44(1)
+; ASM32-DAG:    stw 9, 48(1)
+; ASM32-DAG:    stw 10, 52(1)
+; ASM32-DAG:    stw [[ARG1A:[0-9]+]], -12(1)
+; ASM32-DAG:    stw [[ARG1B:[0-9]+]], -16(1)
+; ASM32-DAG:    stw [[ARG2A:[0-9]+]], -20(1)
+; ASM32-DAG:    stw [[ARG2B:[0-9]+]], -24(1)
+; ASM32-DAG:    lfd [[ARG1:[0-9]+]], -16(1)
+; ASM32-DAG:    fadd 0, [[ARG1]], 1
+; ASM32-DAG:    fadd 1, 1, 1
+; ASM32-DAG:    lfd [[ARG2:[0-9]+]], -24(1)
+; ASM32-DAG:    fadd 1, 0, [[ARG2]]
+; ASM32-DAG:    blr
+
+  define double @double_stack_va_arg(double %one, double %two, double %three, double %four, double %five, double %six, double %seven, double %eight, double %nine, double %ten, double %eleven, double %twelve, double %thirteen, ...) local_unnamed_addr  {
+  entry:
+    %arg1 = alloca i8*, align 4
+    %arg2 = alloca i8*, align 4
+    %0 = bitcast i8** %arg1 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
+    %1 = bitcast i8** %arg2 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %1)
+    call void @llvm.va_start(i8* nonnull %0)
+    call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
+    %add = fadd double %one, %two
+    %add2 = fadd double %add, %three
+    %add3 = fadd double %add2, %four
+    %add4 = fadd double %add3, %five
+    %add5 = fadd double %add4, %six
+    %add6 = fadd double %add5, %seven
+    %add7 = fadd double %add6, %eight
+    %add8 = fadd double %add7, %nine
+    %add9 = fadd double %add8, %ten
+    %add10 = fadd double %add9, %eleven
+    %add11 = fadd double %add10, %twelve
+    %add12 = fadd double %add11, %thirteen
+    %2 = bitcast i8** %arg1 to double**
+    %argp.cur1 = load double*, double** %2, align 4
+    %3 = load double, double* %argp.cur1, align 4
+    %add13 = fadd double %add12, %3
+    %4 = bitcast i8** %arg2 to double**
+    %argp.cur142 = load double*, double** %4, align 4
+    %5 = load double, double* %argp.cur142, align 4
+    %mul = fmul double %5, 2.000000e+00
+    %add16 = fadd double %add13, %mul
+    call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
+    ret double %add16
+  }
+
+; 32BIT-LABEL:   name:            double_stack_va_arg
+; 32BIT-LABEL:   liveins:
+; 32BIT-DAG:     - { reg: '$f1', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f2', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f3', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f4', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f5', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f6', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f7', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f8', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f9', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f10', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f11', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f12', virtual-reg: '' }
+; 32BIT-DAG:     - { reg: '$f13', virtual-reg: '' }
+
+; 32BIT-LABEL:   fixedStack:
+; 32BIT-DAG:     - { id: 0, type: default, offset: 128, size: 4
+
+; 32BIT-LABEL:   stack:
+; 32BIT-DAG:     - { id: 0, name: arg1, type: default, offset: 0, size: 4, alignment: 4,
+; 32BIT-DAG:     - { id: 1, name: arg2, type: default, offset: 0, size: 4, alignment: 4,
+; 32BIT-DAG:     - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8,
+; 32BIT-DAG:     - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8,
+
+; 32BIT-LABEL:   body:             |
+; 32BIT-DAG:     liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
+; 32BIT-DAG:     renamable $r3 = ADDI %fixed-stack.0, 0
+; 32BIT-DAG:     STW killed renamable $r3, 0, %stack.0.arg1 :: (store 4 into %ir.0)
+; 32BIT-DAG:     renamable $r3 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.argp.cur142, align 16)
+; 32BIT-DAG:     renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f4, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f5, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f6, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f7, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f8, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f9, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f10, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f11, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f12, implicit $rm
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f13, implicit $rm
+; 32BIT-DAG:     renamable $r4 = LWZ 4, %fixed-stack.0 :: (load 4 from %ir.argp.cur1 + 4)
+; 32BIT-DAG:     STW renamable $r4, 4, %stack.2 :: (store 4 into %stack.2 + 4)
+; 32BIT-DAG:     renamable $f1 = LFD 0, %stack.2 :: (load 8 from %stack.2)
+; 32BIT-DAG:     STW killed renamable $r3, 0, %stack.3 :: (store 4 into %stack.3, align 8)
+; 32BIT-DAG:     STW killed renamable $r4, 4, %stack.3 :: (store 4 into %stack.3 + 4)
+; 32BIT-DAG:     renamable $f2 = LFD 0, %stack.3 :: (load 8 from %stack.3)
+; 32BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
+; 32BIT-DAG:     STW renamable $r3, 0, %stack.2 :: (store 4 into %stack.2, align 8)
+; 32BIT-DAG:     renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
+; 32BIT-DAG:     BLR implicit $lr, implicit $rm, implicit $f1
+
+; ASM32-LABEL:  .double_stack_va_arg:
+; ASM32-DAG:    fadd 0, 1, 2
+; ASM32-DAG:    fadd 0, 0, 3
+; ASM32-DAG:    fadd 0, 0, 4
+; ASM32-DAG:    fadd 0, 0, 5
+; ASM32-DAG:    fadd 0, 0, 6
+; ASM32-DAG:    fadd 0, 0, 7
+; ASM32-DAG:    fadd 0, 0, 8
+; ASM32-DAG:    fadd 0, 0, 9
+; ASM32-DAG:    fadd 0, 0, 10
+; ASM32-DAG:    fadd 0, 0, 11
+; ASM32-DAG:    fadd 0, 0, 12
+; ASM32-DAG:    fadd 0, 0, 13
+; ASM32-DAG:    lwz [[ARG1:[0-9]+]], 128(1)
+; ASM32-DAG:    lwz [[ARG2:[0-9]+]], 132(1)
+; ASM32-DAG:    lfd [[ARG1:[0-9]+]], -16(1)
+; ASM32-DAG:    lfd [[ARG2:[0-9]+]], -24(1)
+; ASM32-DAG:    fadd 0, 0, [[ARG1]]
+; ASM32-DAG:    fadd [[ARG1]], 0, [[ARG2]]
+; ASM32-DAG:    blr

llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll

+; RUN: llc -O2 -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
+
+; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefixes=CHECKASM,ASM64 %s
+
+  define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr  {
+  entry:
+    %arg1 = alloca i8*, align 8
+    %arg2 = alloca i8*, align 8
+    %0 = bitcast i8** %arg1 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+    %1 = bitcast i8** %arg2 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %1)
+    call void @llvm.va_start(i8* nonnull %0)
+    call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
+    %2 = va_arg i8** %arg1, i32
+    %add = add nsw i32 %2, %a
+    %3 = va_arg i8** %arg2, i32
+    %mul = shl i32 %3, 1
+    %add3 = add nsw i32 %add, %mul
+    call void @llvm.va_end(i8* nonnull %0)
+    call void @llvm.va_end(i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+    ret i32 %add3
+  }
+
+  declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+  declare void @llvm.va_start(i8*)
+  declare void @llvm.va_copy(i8*, i8*)
+  declare void @llvm.va_end(i8*)
+  declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+
+; 64BIT-LABEL:   name:            int_va_arg
+; 64BIT-LABEL:   liveins:
+; 64BIT-DAG:     - { reg: '$x3', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x4', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x5', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x6', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x7', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x8', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x9', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x10', virtual-reg: '' }
+
+; 64BIT-LABEL:   fixedStack:
+; 64BIT-DAG:     - { id: 0, type: default, offset: 56, size: 8
+
+; 64BIT-LABEL:   stack:
+; 64BIT-DAG:     - { id: 0, name: arg1, type: default, offset: 0, size: 8
+; 64BIT-DAG:     - { id: 1, name: arg2, type: default, offset: 0, size: 8
+
+; 64BIT-LABEL:   body:             |
+; 64BIT-DAG:     bb.0.entry:
+; 64BIT-DAG:     liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+; 64BIT-DAG:     STD killed renamable $x4, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0)
+; 64BIT-DAG:     STD killed renamable $x5, 8, %fixed-stack.0 :: (store 8 into %fixed-stack.0 + 8)
+; 64BIT-DAG:     STD killed renamable $x6, 16, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG:     STD killed renamable $x7, 24, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG:     STD killed renamable $x8, 32, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG:     STD killed renamable $x9, 40, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG:     STD killed renamable $x10, 48, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG:     renamable $x11 = ADDI8 %fixed-stack.0, 0
+; 64BIT-DAG:     STD renamable $x11, 0, %stack.1.arg2 :: (store 8 into %ir.1)
+; 64BIT-DAG:     renamable $x4 = LD 0, %stack.1.arg2 :: (load 8 from %ir.arg2)
+; 64BIT-DAG:     renamable $x7 = ADDI8 renamable $x4, 4
+; 64BIT-DAG:     renamable $x5 = ADDI8 %fixed-stack.0, 4
+; 64BIT-DAG:     renamable $r6 = LWZ 0, %fixed-stack.0 :: (load 4 from %fixed-stack.0, align 8)
+; 64BIT-DAG:     STD killed renamable $x11, 0, %stack.0.arg1 :: (store 8 into %ir.0)
+; 64BIT-DAG:     STD killed renamable $x5, 0, %stack.0.arg1 :: (store 8 into %ir.arg1)
+; 64BIT-DAG:     STD killed renamable $x7, 0, %stack.1.arg2 :: (store 8 into %ir.arg2)
+; 64BIT-DAG:     renamable $r4 = LWZ 0, killed renamable $x4 :: (load 4)
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r6, renamable $r3, implicit killed $x3
+; 64BIT-DAG:     renamable $r4 = RLWINM killed renamable $r4, 1, 0, 30
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4, implicit-def $x3
+; 64BIT-DAG:     BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+; ASM64-LABEL:   .int_va_arg:
+; ASM64-DAG:     std 4, 56(1)
+; ASM64-DAG:     addi 4, 1, 56
+; ASM64-DAG:     std 4, -16(1)
+; ASM64-DAG:     std 4, -8(1)
+; ASM64-DAG:     ld 4, -16(1)
+; ASM64-DAG:     std 5, 64(1)
+; ASM64-DAG:     addi 5, 1, 60
+; ASM64-DAG:     std 5, -8(1)
+; ASM64-DAG:     addi 5, 4, 4
+; ASM64-DAG:     std 6, 72(1)
+; ASM64-DAG:     std 7, 80(1)
+; ASM64-DAG:     std 8, 88(1)
+; ASM64-DAG:     std 9, 96(1)
+; ASM64-DAG:     std 10, 104(1)
+; ASM64-DAG:     std 5, -16(1)
+; ASM64-DAG:     lwz 11, 56(1)
+; ASM64-DAG:     lwz 4, 0(4)
+; ASM64-DAG:     add 3, 11, 3
+; ASM64-DAG:     slwi 4, 4, 1
+; ASM64-DAG:     add 3, 3, 4
+; ASM64-DAG:     blr
+
+  define i32 @int_stack_va_arg(i32 %one, i32 %two, i32 %three, i32 %four, i32 %five, i32 %six, i32 %seven, i32 %eight, ...) local_unnamed_addr {
+  entry:
+    %arg1 = alloca i8*, align 8
+    %arg2 = alloca i8*, align 8
+    %0 = bitcast i8** %arg1 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+    %1 = bitcast i8** %arg2 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %1)
+    call void @llvm.va_start(i8* nonnull %0)
+    call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
+    %add = add nsw i32 %two, %one
+    %add2 = add nsw i32 %add, %three
+    %add3 = add nsw i32 %add2, %four
+    %add4 = add nsw i32 %add3, %five
+    %add5 = add nsw i32 %add4, %six
+    %add6 = add nsw i32 %add5, %seven
+    %add7 = add nsw i32 %add6, %eight
+    %2 = va_arg i8** %arg1, i32
+    %add8 = add nsw i32 %add7, %2
+    %3 = va_arg i8** %arg2, i32
+    %mul = shl i32 %3, 1
+    %add10 = add nsw i32 %add8, %mul
+    call void @llvm.va_end(i8* nonnull %0)
+    call void @llvm.va_end(i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+    ret i32 %add10
+  }
+
+; 64BIT-LABEL:    name:            int_stack_va_arg
+; 64BIT-LABEL:    liveins:
+; 64BIT-DAG:       - { reg: '$x3', virtual-reg: '' }
+; 64BIT-DAG:       - { reg: '$x4', virtual-reg: '' }
+; 64BIT-DAG:       - { reg: '$x5', virtual-reg: '' }
+; 64BIT-DAG:       - { reg: '$x6', virtual-reg: '' }
+; 64BIT-DAG:       - { reg: '$x7', virtual-reg: '' }
+; 64BIT-DAG:       - { reg: '$x8', virtual-reg: '' }
+; 64BIT-DAG:       - { reg: '$x9', virtual-reg: '' }
+; 64BIT-DAG:       - { reg: '$x10', virtual-reg: '' }
+
+; 64BIT-LABEL:   fixedStack:
+; 64BIT-DAG:     - { id: 0, type: default, offset: 112, size: 8, alignment: 16, stack-id: default,
+
+; 64BIT-LABEL:   stack:
+; 64BIT-DAG:     - { id: 0, name: arg1, type: default, offset: 0, size: 8, alignment: 8,
+; 64BIT-DAG:     - { id: 1, name: arg2, type: default, offset: 0, size: 8, alignment: 8,
+
+; 64BIT-LABEL:   body:             |
+; 64BIT-DAG:     liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+; 64BIT-DAG:     renamable $r11 = LWZ 0, %fixed-stack.0 :: (load 4 from %fixed-stack.0, align 16)
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 renamable $r4, renamable $r3, implicit killed $x3, implicit killed $x4
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r6, implicit killed $x6
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r7, implicit killed $x7
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r8, implicit killed $x8
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r9, implicit killed $x9
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r10, implicit killed $x10
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r11
+; 64BIT-DAG:     renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4, implicit-def $x3
+; 64BIT-DAG:     BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+; ASM64-LABEL:   .int_stack_va_arg:
+; ASM64-DAG:     add 3, 4, 3
+; ASM64-DAG:     add 3, 3, 5
+; ASM64-DAG:     add 3, 3, 6
+; ASM64-DAG:     add 3, 3, 7
+; ASM64-DAG:     add 3, 3, 8
+; ASM64-DAG:     add 3, 3, 9
+; ASM64-DAG:     add 3, 3, 10
+; ASM64-DAG:     lwz 11, 112(1)
+; ASM64-DAG:     slwi 4, 11, 1
+; ASM64-DAG:     add 3, 3, 11
+; ASM64-DAG:     add 3, 3, 4
+; ASM64-DAG:     blr
+
+  define double @double_va_arg(double %a, ...) local_unnamed_addr  {
+  entry:
+    %arg1 = alloca i8*, align 8
+    %arg2 = alloca i8*, align 8
+    %0 = bitcast i8** %arg1 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+    %1 = bitcast i8** %arg2 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %1)
+    call void @llvm.va_start(i8* nonnull %0)
+    call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
+    %2 = va_arg i8** %arg1, double
+    %add = fadd double %2, %a
+    %3 = va_arg i8** %arg2, double
+    %mul = fmul double %3, 2.000000e+00
+    %add3 = fadd double %add, %mul
+    call void @llvm.va_end(i8* nonnull %0)
+    call void @llvm.va_end(i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+    ret double %add3
+  }
+
+; 64BIT-LABEL:   name:            double_va_arg
+; 64BIT-LABEL:   liveins:
+; 64BIT-DAG:     - { reg: '$f1', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x4', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x5', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x6', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x7', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x8', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x9', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$x10', virtual-reg: '' }
+
+; 64BIT-LABEL:   fixedStack:
+; 64BIT-DAG:     - { id: 0, type: default, offset: 56, size: 8
+
+; 64BIT-LABEL:   stack:
+; 64BIT-DAG:     - { id: 0, name: arg1, type: default, offset: 0, size: 8
+; 64BIT-DAG:     - { id: 1, name: arg2, type: default, offset: 0, size: 8
+
+; 64BIT-LABEL:   body:             |
+; 64BIT-DAG:     liveins: $f1, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+; 64BIT-DAG:     renamable $x3 = ADDI8 %fixed-stack.0, 0
+; 64BIT-DAG:     STD killed renamable $x4, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0)
+; 64BIT-DAG:     STD killed renamable $x5, 8, %fixed-stack.0 :: (store 8 into %fixed-stack.0 + 8)
+; 64BIT-DAG:     STD killed renamable $x6, 16, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG:     STD killed renamable $x7, 24, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG:     STD killed renamable $x8, 32, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG:     STD killed renamable $x9, 40, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG:     STD killed renamable $x10, 48, %fixed-stack.0 :: (store 8)
+; 64BIT-DAG:     STD renamable $x3, 0, %stack.1.arg2 :: (store 8 into %ir.1)
+; 64BIT-DAG:     renamable $x4 = LD 0, %stack.1.arg2 :: (load 8 from %ir.arg2)
+; 64BIT-DAG:     renamable $x5 = ADDI8 %fixed-stack.0, 8
+; 64BIT-DAG:     STD killed renamable $x3, 0, %stack.0.arg1 :: (store 8 into %ir.0)
+; 64BIT-DAG:     STD killed renamable $x5, 0, %stack.0.arg1 :: (store 8 into %ir.arg1)
+; 64BIT-DAG:     renamable $f0 = LFD 0, %fixed-stack.0 :: (load 8)
+; 64BIT-DAG:     renamable $x3 = ADDI8 renamable $x4, 8
+; 64BIT-DAG:     STD killed renamable $x3, 0, %stack.1.arg2 :: (store 8 into %ir.arg2)
+; 64BIT-DAG:     renamable $f2 = LFD 0, killed renamable $x4 :: (load 8)
+; 64BIT-DAG:     renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
+; 64BIT-DAG:     renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
+; 64BIT-DAG:     renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
+; 64BIT-DAG:     BLR8 implicit $lr8, implicit $rm, implicit $f1
+
+; ASM64-LABEL:  .double_va_arg:
+; ASM64-DAG:    addi 3, 1, 56
+; ASM64-DAG:    std 4, 56(1)
+; ASM64-DAG:    std 3, -8(1)
+; ASM64-DAG:    std 3, -16(1)
+; ASM64-DAG:    addi 3, 1, 64
+; ASM64-DAG:    std 3, -8(1)
+; ASM64-DAG:    ld 3, -16(1)
+; ASM64-DAG:    lfd 0, 56(1)
+; ASM64-DAG:    addi 4, 3, 8
+; ASM64-DAG:    std 5, 64(1)
+; ASM64-DAG:    fadd 0, 0, 1
+; ASM64-DAG:    std 6, 72(1)
+; ASM64-DAG:    std 7, 80(1)
+; ASM64-DAG:    std 8, 88(1)
+; ASM64-DAG:    std 9, 96(1)
+; ASM64-DAG:    std 10, 104(1)
+; ASM64-DAG:    std 4, -16(1)
+; ASM64-DAG:    lfd 1, 0(3)
+; ASM64-DAG:    fadd 1, 1, 1
+; ASM64-DAG:    fadd 1, 0, 1
+; ASM64-DAG:    blr
+
+  define double @double_stack_va_arg(double %one, double %two, double %three, double %four, double %five, double %six, double %seven, double %eight, double %nine, double %ten, double %eleven, double %twelve, double %thirteen, ...) local_unnamed_addr  {
+  entry:
+    %arg1 = alloca i8*, align 8
+    %arg2 = alloca i8*, align 8
+    %0 = bitcast i8** %arg1 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+    %1 = bitcast i8** %arg2 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %1)
+    call void @llvm.va_start(i8* nonnull %0)
+    call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
+    %add = fadd double %one, %two
+    %add2 = fadd double %add, %three
+    %add3 = fadd double %add2, %four
+    %add4 = fadd double %add3, %five
+    %add5 = fadd double %add4, %six
+    %add6 = fadd double %add5, %seven
+    %add7 = fadd double %add6, %eight
+    %add8 = fadd double %add7, %nine
+    %add9 = fadd double %add8, %ten
+    %add10 = fadd double %add9, %eleven
+    %add11 = fadd double %add10, %twelve
+    %add12 = fadd double %add11, %thirteen
+    %2 = va_arg i8** %arg1, double
+    %add13 = fadd double %add12, %2
+    %3 = va_arg i8** %arg2, double
+    %mul = fmul double %3, 2.000000e+00
+    %add15 = fadd double %add13, %mul
+    call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %1)
+    call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+    ret double %add15
+  }
+
+
+; 64BIT-LABEL:   name:            double_stack_va_arg
+; 64BIT-LABEL:   liveins:
+; 64BIT-DAG:     - { reg: '$f1', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f2', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f3', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f4', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f5', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f6', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f7', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f8', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f9', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f10', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f11', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f12', virtual-reg: '' }
+; 64BIT-DAG:     - { reg: '$f13', virtual-reg: '' }
+
+; 64BIT-LABEL:   fixedStack:
+; 64BIT-DAG:       - { id: 0, type: default, offset: 152, size: 8
+
+; 64BIT-LABEL:   stack:
+; 64BIT-DAG:       - { id: 0, name: arg1, type: default, offset: 0, size: 8
+; 64BIT-DAG:       - { id: 1, name: arg2, type: default, offset: 0, size: 8
+
+; 64BIT-LABEL:     body:             |
+; 64BIT-DAG:       liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
+; 64BIT-DAG:       renamable $f0 = LFD 0, %fixed-stack.0 :: (load 8)
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f5, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f6, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f7, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f8, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f9, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f10, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f11, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f12, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f13, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, renamable $f0, implicit $rm
+; 64BIT-DAG:       renamable $f0 = nofpexcept FADD killed renamable $f0, renamable $f0, implicit $rm
+; 64BIT-DAG:       renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm
+; 64BIT-DAG:       BLR8 implicit $lr8, implicit $rm, implicit $f1
+
+; ASM64-LABEL:   .double_stack_va_arg:
+; ASM64-DAG:     fadd 1, 1, 2
+; ASM64-DAG:     fadd 1, 1, 3
+; ASM64-DAG:     fadd 1, 1, 4
+; ASM64-DAG:     fadd 1, 1, 5
+; ASM64-DAG:     fadd 1, 1, 6
+; ASM64-DAG:     fadd 1, 1, 7
+; ASM64-DAG:     fadd 1, 1, 8
+; ASM64-DAG:     fadd 1, 1, 9
+; ASM64-DAG:     fadd 1, 1, 10
+; ASM64-DAG:     fadd 1, 1, 11
+; ASM64-DAG:     fadd 1, 1, 12
+; ASM64-DAG:     fadd 1, 1, 13
+; ASM64-DAG:     lfd 0, 152(1)
+; ASM64-DAG:     fadd 1, 1, 0
+; ASM64-DAG:     fadd 0, 0, 0
+; ASM64-DAG:     fadd 1, 1, 0
+; ASM64-DAG:     blr