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Differential D75713

[llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:`
ClosedPublic

Authored by MaskRay on Mar 5 2020, 3:54 PM.

Details

Reviewers
adalava
Bdragon28
rupprecht
jhenderson
• espindola
Commits
rG71e2ca6e3210: [llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:`
Summary

The new behavior matches GNU objdump. A pair of angle brackets makes tests slightly easier.

.foo: is not unique and thus cannot be in a CHECK-LABEL: directive.
Without -LABEL, the CHECK line can match the Disassembly of section
line and causes the next CHECK-NEXT: to fail.

Disassembly of section .foo:

0000000000001634 .foo:

Bdragon: <> has metalinguistic connotation

Diff Detail

Event Timeline

MaskRay created this revision.Mar 5 2020, 3:54 PM
Herald added a reviewer: jhenderson. · View Herald TranscriptMar 5 2020, 3:54 PM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added a subscriber: llvm-commits. · View Herald Transcript
MaskRay added a comment.EditedMar 5 2020, 3:55 PM

There are a large number of tests which need to be fixed. I'll not add them in the review.

As an example:

diff --git a/llvm/test/MC/ELF/relax-arith2.s b/llvm/test/MC/ELF/relax-arith2.s
index ac71a678bc4..9a1153b350d 100644
--- a/llvm/test/MC/ELF/relax-arith2.s
+++ b/llvm/test/MC/ELF/relax-arith2.s
@@ -24,7 +24,7 @@ bar:
 
 // CHECK:      Disassembly of section and:
 // CHECK-EMPTY:
-// CHECK-NEXT: and:
+// CHECK-NEXT: <and>:
 // CHECK-NEXT:   0: 66 83 e3 7f                   andw $127, %bx
 // CHECK-NEXT:   4: 66 83 24 25 00 00 00 00 00    andw $0, 0
 // CHECK-NEXT:   d: 83 e3 01                      andl $1, %ebx
rupprecht accepted this revision.Mar 5 2020, 4:12 PM
This revision is now accepted and ready to land.Mar 5 2020, 4:12 PM
Harbormaster failed remote builds in B48280: Diff 248622!Mar 5 2020, 4:26 PM
MaskRay updated this revision to Diff 248636.Mar 5 2020, 5:38 PM

Update tests

Herald added a reviewer: • espindola. · View Herald TranscriptMar 5 2020, 5:38 PM
Herald added subscribers: kerbowa, luismarques, apazos and 40 others. · View Herald Transcript
Closed by commit rG71e2ca6e3210: [llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:` (authored by MaskRay). · Explain WhyMar 5 2020, 6:35 PM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: • wuzish. · View Herald TranscriptMar 5 2020, 6:35 PM
Harbormaster completed remote builds in B48288: Diff 248636.Mar 5 2020, 7:39 PM
jhenderson mentioned this in D75631: [llvm-objdump] Fix reliability of call target disassembling.Mar 6 2020, 1:04 AM
MaskRay mentioned this in rGc3de1d0b1f99: [gold][test] Fix tests after D75713 and D74749.Mar 6 2020, 1:50 PM
MaskRay mentioned this in D70720: [llvm-objdump] Display locations of variables alongside disassembly.Mar 13 2020, 9:18 AM

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Diff 248636

lld/test/COFF/arm64-thunks.s

Show All 20 Linesfunc1:
.space 1 .space 1
.section .text$c, "xr" .section .text$c, "xr"
.space 0x8000 .space 0x8000
.section .text$d, "xr" .section .text$d, "xr"
.align 2 .align 2
func2: func2:
ret ret
// DISASM: 0000000140001000 .text: // DISASM: 0000000140001000 <.text>:
// DISASM: 140001000: 40 00 00 36 tbz w0, #0, #8 <.text+0x8> // DISASM: 140001000: 40 00 00 36 tbz w0, #0, #8 <.text+0x8>
// DISASM: 140001004: c0 03 5f d6 ret // DISASM: 140001004: c0 03 5f d6 ret
// DISASM: 140001008: 50 00 00 90 adrp x16, #32768 // DISASM: 140001008: 50 00 00 90 adrp x16, #32768
// DISASM: 14000100c: 10 52 00 91 add x16, x16, #20 // DISASM: 14000100c: 10 52 00 91 add x16, x16, #20
// DISASM: 140001010: 00 02 1f d6 br x16 // DISASM: 140001010: 00 02 1f d6 br x16
// DISASM: 140009014: 60 00 00 36 tbz w0, #0, #12 <.text+0x8020> // DISASM: 140009014: 60 00 00 36 tbz w0, #0, #12 <.text+0x8020>
// DISASM: 140009018: c0 03 5f d6 ret // DISASM: 140009018: c0 03 5f d6 ret
// DISASM: 140009020: 50 00 00 90 adrp x16, #32768 // DISASM: 140009020: 50 00 00 90 adrp x16, #32768
// DISASM: 140009024: 10 b2 00 91 add x16, x16, #44 // DISASM: 140009024: 10 b2 00 91 add x16, x16, #44
// DISASM: 140009028: 00 02 1f d6 br x16 // DISASM: 140009028: 00 02 1f d6 br x16
// DISASM: 14001102c: c0 03 5f d6 ret // DISASM: 14001102c: c0 03 5f d6 ret

lld/test/COFF/armnt-branch24t.test

# REQUIRES: arm # REQUIRES: arm
# RUN: yaml2obj < %s > %t.obj # RUN: yaml2obj < %s > %t.obj
# RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix BEFORE # RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix BEFORE
# RUN: lld-link /entry:function /subsystem:console /out:%t.exe %t.obj # RUN: lld-link /entry:function /subsystem:console /out:%t.exe %t.obj
# RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix AFTER # RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix AFTER
# BEFORE: Disassembly of section .text: # BEFORE: Disassembly of section .text:
# BEFORE-EMPTY: # BEFORE-EMPTY:
# BEFORE: 0: 70 47 bx lr # BEFORE: 0: 70 47 bx lr
# BEFORE: 2: 00 bf nop # BEFORE: 2: 00 bf nop
# BEFORE: 4: 20 20 movs r0, #32 # BEFORE: 4: 20 20 movs r0, #32
# BEFORE: 6: 00 f0 00 b8 b.w #0 # BEFORE: 6: 00 f0 00 b8 b.w #0
# AFTER: Disassembly of section .text: # AFTER: Disassembly of section .text:
# AFTER-EMPTY: # AFTER-EMPTY:
# AFTER: .text: # AFTER: <.text>:
# AFTER: 1000: 70 47 bx lr # AFTER: 1000: 70 47 bx lr
# AFTER: 1002: 00 bf nop # AFTER: 1002: 00 bf nop
# AFTER: 1004: 20 20 movs r0, #32 # AFTER: 1004: 20 20 movs r0, #32
# AFTER: 1006: ff f7 fb bf b.w #-10 # AFTER: 1006: ff f7 fb bf b.w #-10
--- !COFF --- !COFF
header: header:
Machine: IMAGE_FILE_MACHINE_ARMNT Machine: IMAGE_FILE_MACHINE_ARMNT
Show All 36 Lines

lld/test/COFF/autoimport-refptr.s

Show All 14 Lines
# IMPORTS-NEXT: Name: autoimport-refptr.s.tmp-lib.dll # IMPORTS-NEXT: Name: autoimport-refptr.s.tmp-lib.dll
# IMPORTS-NEXT: ImportLookupTableRVA: 0x2050 # IMPORTS-NEXT: ImportLookupTableRVA: 0x2050
# IMPORTS-NEXT: ImportAddressTableRVA: 0x2060 # IMPORTS-NEXT: ImportAddressTableRVA: 0x2060
# IMPORTS-NEXT: Symbol: variable (0) # IMPORTS-NEXT: Symbol: variable (0)
# IMPORTS-NEXT: } # IMPORTS-NEXT: }
# DISASM: Disassembly of section .text: # DISASM: Disassembly of section .text:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM: .text: # DISASM: <.text>:
# Relative offset at 0x1002 pointing at the IAT at 0x2060 # Relative offset at 0x1002 pointing at the IAT at 0x2060
# DISASM: 140001000: 48 8b 05 59 10 00 00 movq 4185(%rip), %rax # DISASM: 140001000: 48 8b 05 59 10 00 00 movq 4185(%rip), %rax
# DISASM: 140001007: 8b 00 movl (%rax), %eax # DISASM: 140001007: 8b 00 movl (%rax), %eax
# Relative offset at 0x100b pointing at the .refptr.localvar stub at # Relative offset at 0x100b pointing at the .refptr.localvar stub at
# 0x2000 # 0x2000
# DISASM: 140001009: 48 8b 0d f0 0f 00 00 movq 4080(%rip), %rcx # DISASM: 140001009: 48 8b 0d f0 0f 00 00 movq 4080(%rip), %rcx
# DISASM: 140001010: 03 01 addl (%rcx), %eax # DISASM: 140001010: 03 01 addl (%rcx), %eax
# DISASM: 140001012: c3 retq # DISASM: 140001012: c3 retq
Show All 35 Lines

lld/test/COFF/autoimport-x86.s

Show All 15 Lines
# IMPORTS-NEXT: Name: autoimport-x86.s.tmp-lib.dll # IMPORTS-NEXT: Name: autoimport-x86.s.tmp-lib.dll
# IMPORTS-NEXT: ImportLookupTableRVA: 0x2070 # IMPORTS-NEXT: ImportLookupTableRVA: 0x2070
# IMPORTS-NEXT: ImportAddressTableRVA: 0x2080 # IMPORTS-NEXT: ImportAddressTableRVA: 0x2080
# IMPORTS-NEXT: Symbol: variable (0) # IMPORTS-NEXT: Symbol: variable (0)
# IMPORTS-NEXT: } # IMPORTS-NEXT: }
# DISASM: Disassembly of section .text: # DISASM: Disassembly of section .text:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM: main: # DISASM: <main>:
# Relative offset at 0x1002 pointing at the IAT at 0x2080. # Relative offset at 0x1002 pointing at the IAT at 0x2080.
# DISASM: 140001000: 8b 05 7a 10 00 00 movl 4218(%rip), %eax # DISASM: 140001000: 8b 05 7a 10 00 00 movl 4218(%rip), %eax
# DISASM: 140001006: c3 retq # DISASM: 140001006: c3 retq
# Runtime pseudo reloc list header consisting of 0x0, 0x0, 0x1. # Runtime pseudo reloc list header consisting of 0x0, 0x0, 0x1.
# First runtime pseudo reloc, with import from 0x2080, # First runtime pseudo reloc, with import from 0x2080,
# applied at 0x1002, with a size of 32 bits. # applied at 0x1002, with a size of 32 bits.
# Second runtime pseudo reloc, with import from 0x2080, # Second runtime pseudo reloc, with import from 0x2080,
Show All 27 Lines

lld/test/COFF/imports.test

# REQUIRES: x86 # REQUIRES: x86
# Verify that the lld can handle .lib files and emit .idata sections. # Verify that the lld can handle .lib files and emit .idata sections.
# #
# RUN: lld-link /out:%t.exe /entry:main /subsystem:console \ # RUN: lld-link /out:%t.exe /entry:main /subsystem:console \
# RUN: %p/Inputs/hello64.obj %p/Inputs/std64.lib # RUN: %p/Inputs/hello64.obj %p/Inputs/std64.lib
# RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=TEXT %s # RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=TEXT %s
# RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORT %s # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORT %s
# RUN: lld-link /out:%t.exe /entry:main /subsystem:console \ # RUN: lld-link /out:%t.exe /entry:main /subsystem:console \
# RUN: %p/Inputs/hello64.obj %p/Inputs/std64.lib /include:ExitProcess # RUN: %p/Inputs/hello64.obj %p/Inputs/std64.lib /include:ExitProcess
# RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=TEXT %s # RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=TEXT %s
# RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORT %s # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORT %s
TEXT: Disassembly of section .text: TEXT: Disassembly of section .text:
TEXT-EMPTY: TEXT-EMPTY:
TEXT-NEXT: .text: TEXT-NEXT: <.text>:
TEXT-NEXT: subq $40, %rsp TEXT-NEXT: subq $40, %rsp
TEXT-NEXT: movq $0, %rcx TEXT-NEXT: movq $0, %rcx
TEXT-NEXT: leaq 8180(%rip), %rdx TEXT-NEXT: leaq 8180(%rip), %rdx
TEXT-NEXT: leaq 8167(%rip), %r8 TEXT-NEXT: leaq 8167(%rip), %r8
TEXT-NEXT: movl $0, %r9d TEXT-NEXT: movl $0, %r9d
TEXT-NEXT: callq 60 TEXT-NEXT: callq 60
TEXT-NEXT: movl $0, %ecx TEXT-NEXT: movl $0, %ecx
TEXT-NEXT: callq 18 TEXT-NEXT: callq 18
Show All 26 Lines

lld/test/COFF/lto-comdat.ll

Show All 37 Lines
; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck -check-prefix=TEXT-10 %s ; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck -check-prefix=TEXT-10 %s
; RUN: lld-link /out:%T/comdat-main.exe /entry:main /subsystem:console %T/comdat-main.lto.obj %T/comdat.lib ; RUN: lld-link /out:%T/comdat-main.exe /entry:main /subsystem:console %T/comdat-main.lto.obj %T/comdat.lib
; RUN: llvm-readobj --file-headers %T/comdat-main.exe | FileCheck -check-prefix=HEADERS-10 %s ; RUN: llvm-readobj --file-headers %T/comdat-main.exe | FileCheck -check-prefix=HEADERS-10 %s
; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck -check-prefix=TEXT-10 %s ; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck -check-prefix=TEXT-10 %s
; HEADERS-11: AddressOfEntryPoint: 0x1000 ; HEADERS-11: AddressOfEntryPoint: 0x1000
; TEXT-11: Disassembly of section .text: ; TEXT-11: Disassembly of section .text:
; TEXT-11-EMPTY: ; TEXT-11-EMPTY:
; TEXT-11-NEXT: .text: ; TEXT-11-NEXT: <.text>:
; TEXT-11-NEXT: xorl %eax, %eax ; TEXT-11-NEXT: xorl %eax, %eax
; TEXT-11-NEXT: retq ; TEXT-11-NEXT: retq
; HEADERS-01: AddressOfEntryPoint: 0x1000 ; HEADERS-01: AddressOfEntryPoint: 0x1000
; TEXT-01: Disassembly of section .text: ; TEXT-01: Disassembly of section .text:
; TEXT-01-EMPTY: ; TEXT-01-EMPTY:
; TEXT-01-NEXT: .text: ; TEXT-01-NEXT: <.text>:
; TEXT-01-NEXT: subq $40, %rsp ; TEXT-01-NEXT: subq $40, %rsp
; TEXT-01-NEXT: callq 23 ; TEXT-01-NEXT: callq 23
; TEXT-01-NEXT: callq 18 ; TEXT-01-NEXT: callq 18
; TEXT-01-NEXT: callq 13 ; TEXT-01-NEXT: callq 13
; TEXT-01-NEXT: xorl %eax, %eax ; TEXT-01-NEXT: xorl %eax, %eax
; TEXT-01-NEXT: addq $40, %rsp ; TEXT-01-NEXT: addq $40, %rsp
; TEXT-01: retq ; TEXT-01: retq
; TEXT-01-NOT: callq ; TEXT-01-NOT: callq
; TEXT-01: retq ; TEXT-01: retq
; TEXT-01: int3 ; TEXT-01: int3
; TEXT-01: int3 ; TEXT-01: int3
; TEXT-01: int3 ; TEXT-01: int3
; TEXT-01-NOT: {{.}} ; TEXT-01-NOT: {{.}}
; HEADERS-10: AddressOfEntryPoint: 0x1020 ; HEADERS-10: AddressOfEntryPoint: 0x1020
; TEXT-10: Disassembly of section .text: ; TEXT-10: Disassembly of section .text:
; TEXT-10-EMPTY: ; TEXT-10-EMPTY:
; TEXT-10-NEXT: .text: ; TEXT-10-NEXT: <.text>:
; TEXT-10-NEXT: subq $40, %rsp ; TEXT-10-NEXT: subq $40, %rsp
; TEXT-10-NEXT: callq 55 ; TEXT-10-NEXT: callq 55
; TEXT-10-NEXT: nop ; TEXT-10-NEXT: nop
; TEXT-10-NEXT: addq $40, %rsp ; TEXT-10-NEXT: addq $40, %rsp
; TEXT-10-NEXT: retq ; TEXT-10-NEXT: retq
; TEXT-10-NEXT: int3 ; TEXT-10-NEXT: int3
; TEXT-10-NEXT: subq $40, %rsp ; TEXT-10-NEXT: subq $40, %rsp
; TEXT-10-NEXT: callq 39 ; TEXT-10-NEXT: callq 39
Show All 32 Lines

lld/test/COFF/lto.ll

Show All 29 Lines
; RUN: llvm-readobj --file-headers %T/main.exe | FileCheck -check-prefix=HEADERS-10 %s ; RUN: llvm-readobj --file-headers %T/main.exe | FileCheck -check-prefix=HEADERS-10 %s
; RUN: llvm-objdump -d %T/main.exe | FileCheck -check-prefix=TEXT-10 %s ; RUN: llvm-objdump -d %T/main.exe | FileCheck -check-prefix=TEXT-10 %s
; VERBOSE: foo.lto.lib({{.*}}foo.lto.obj) ; VERBOSE: foo.lto.lib({{.*}}foo.lto.obj)
; HEADERS-11: AddressOfEntryPoint: 0x1000 ; HEADERS-11: AddressOfEntryPoint: 0x1000
; TEXT-11: Disassembly of section .text: ; TEXT-11: Disassembly of section .text:
; TEXT-11-EMPTY: ; TEXT-11-EMPTY:
; TEXT-11-NEXT: .text: ; TEXT-11-NEXT: <.text>:
; TEXT-11-NEXT: xorl %eax, %eax ; TEXT-11-NEXT: xorl %eax, %eax
; TEXT-11-NEXT: retq ; TEXT-11-NEXT: retq
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: int3 ; TEXT-11-NEXT: int3
; TEXT-11-NEXT: movl $2, %eax ; TEXT-11-NEXT: movl $2, %eax
; TEXT-11-NEXT: retq ; TEXT-11-NEXT: retq
; HEADERS-01: AddressOfEntryPoint: 0x1000 ; HEADERS-01: AddressOfEntryPoint: 0x1000
; TEXT-01: Disassembly of section .text: ; TEXT-01: Disassembly of section .text:
; TEXT-01-EMPTY: ; TEXT-01-EMPTY:
; TEXT-01-NEXT: .text: ; TEXT-01-NEXT: <.text>:
; TEXT-01-NEXT: subq $40, %rsp ; TEXT-01-NEXT: subq $40, %rsp
; TEXT-01-NEXT: callq 23 ; TEXT-01-NEXT: callq 23
; TEXT-01-NEXT: xorl %eax, %eax ; TEXT-01-NEXT: xorl %eax, %eax
; TEXT-01-NEXT: addq $40, %rsp ; TEXT-01-NEXT: addq $40, %rsp
; TEXT-01-NEXT: retq ; TEXT-01-NEXT: retq
; TEXT-01-NEXT: retq ; TEXT-01-NEXT: retq
; TEXT-01-NEXT: int3 ; TEXT-01-NEXT: int3
; TEXT-01-NEXT: int3 ; TEXT-01-NEXT: int3
Show All 10 Lines
; TEXT-01-NEXT: int3 ; TEXT-01-NEXT: int3
; TEXT-01-NEXT: int3 ; TEXT-01-NEXT: int3
; TEXT-01-NEXT: int3 ; TEXT-01-NEXT: int3
; TEXT-01-NEXT: retq ; TEXT-01-NEXT: retq
; HEADERS-10: AddressOfEntryPoint: 0x1020 ; HEADERS-10: AddressOfEntryPoint: 0x1020
; TEXT-10: Disassembly of section .text: ; TEXT-10: Disassembly of section .text:
; TEXT-10-EMPTY: ; TEXT-10-EMPTY:
; TEXT-10-NEXT: .text: ; TEXT-10-NEXT: <.text>:
; TEXT-10-NEXT: retq ; TEXT-10-NEXT: retq
; TEXT-10-NEXT: nop ; TEXT-10-NEXT: nop
; TEXT-10-NEXT: nop ; TEXT-10-NEXT: nop
; TEXT-10-NEXT: nop ; TEXT-10-NEXT: nop
; TEXT-10-NEXT: nop ; TEXT-10-NEXT: nop
; TEXT-10-NEXT: nop ; TEXT-10-NEXT: nop
; TEXT-10-NEXT: nop ; TEXT-10-NEXT: nop
; TEXT-10-NEXT: nop ; TEXT-10-NEXT: nop
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

lld/test/COFF/mixed-resource-obj.yaml

# REQUIRES: x86 # REQUIRES: x86
# RUN: yaml2obj < %s > %t.o # RUN: yaml2obj < %s > %t.o
# Test that we get both the resource and the code from a single object # Test that we get both the resource and the code from a single object
# file that contains both, while merging resources from another object # file that contains both, while merging resources from another object
# file. # file.
# RUN: lld-link -lldmingw -out:%t.exe %t.o %p/Inputs/id.res.o -entry:main # RUN: lld-link -lldmingw -out:%t.exe %t.o %p/Inputs/id.res.o -entry:main
# RUN: llvm-readobj --coff-resources %t.exe | FileCheck %s --check-prefix=CHECK-RESOURCES # RUN: llvm-readobj --coff-resources %t.exe | FileCheck %s --check-prefix=CHECK-RESOURCES
# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefix=CHECK-DISASM # RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefix=CHECK-DISASM
# CHECK-RESOURCES: Resources [ # CHECK-RESOURCES: Resources [
# CHECK-RESOURCES-NEXT: Total Number of Resources: 2 # CHECK-RESOURCES-NEXT: Total Number of Resources: 2
# CHECK-DISASM: Disassembly of section .text: # CHECK-DISASM: <.text>:
# CHECK-DISASM: .text:
# CHECK-DISASM-NEXT: movl $42, %eax # CHECK-DISASM-NEXT: movl $42, %eax
# CHECK-DISASM-NEXT: retq # CHECK-DISASM-NEXT: retq
--- !COFF --- !COFF
header: header:
Machine: IMAGE_FILE_MACHINE_AMD64 Machine: IMAGE_FILE_MACHINE_AMD64
Characteristics: [ IMAGE_FILE_LINE_NUMS_STRIPPED ] Characteristics: [ IMAGE_FILE_LINE_NUMS_STRIPPED ]
sections: sections:
Show All 38 Lines

lld/test/ELF/aarch64-call26-thunk.s

// REQUIRES: aarch64 // REQUIRES: aarch64
// RUN: llvm-mc -filetype=obj -triple=aarch64 %S/Inputs/abs.s -o %tabs.o // RUN: llvm-mc -filetype=obj -triple=aarch64 %S/Inputs/abs.s -o %tabs.o
// RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o
// RUN: ld.lld %t.o %tabs.o -o %t // RUN: ld.lld %t.o %tabs.o -o %t
// RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s // RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
.text .text
.globl _start .globl _start
_start: _start:
bl big bl big
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 210120: bl #4 // CHECK-NEXT: 210120: bl #4
// CHECK: __AArch64AbsLongThunk_big: // CHECK: <__AArch64AbsLongThunk_big>:
// CHECK-NEXT: 210124: ldr x16, #8 // CHECK-NEXT: 210124: ldr x16, #8
// CHECK-NEXT: 210128: br x16 // CHECK-NEXT: 210128: br x16
// CHECK: $d: // CHECK: <$d>:
// CHECK-NEXT: 21012c: 00 00 00 00 .word 0x00000000 // CHECK-NEXT: 21012c: 00 00 00 00 .word 0x00000000
// CHECK-NEXT: 210130: 10 00 00 00 .word 0x00000010 // CHECK-NEXT: 210130: 10 00 00 00 .word 0x00000010

lld/test/ELF/aarch64-condb-reloc.s

# REQUIRES: aarch64 # REQUIRES: aarch64
# RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %p/Inputs/aarch64-condb-reloc.s -o %t1.o # RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %p/Inputs/aarch64-condb-reloc.s -o %t1.o
# RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %s -o %t2.o # RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %s -o %t2.o
# RUN: ld.lld %t1.o %t2.o -o %t # RUN: ld.lld %t1.o %t2.o -o %t
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
# RUN: ld.lld -shared %t1.o %t2.o -o %t.so # RUN: ld.lld -shared %t1.o %t2.o -o %t.so
# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck -check-prefix=DSO %s # RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck -check-prefix=DSO %s
# RUN: llvm-readobj -S -r %t.so | FileCheck -check-prefix=DSOREL %s # RUN: llvm-readobj -S -r %t.so | FileCheck -check-prefix=DSOREL %s
# 0x11024 - 36 = 0x11000 # 0x11024 - 36 = 0x11000
# 0x11028 - 24 = 0x11010 # 0x11028 - 24 = 0x11010
# 0x1102c - 16 = 0x1101c # 0x1102c - 16 = 0x1101c
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: _foo: # CHECK-NEXT: <_foo>:
# CHECK-NEXT: 210120: nop # CHECK-NEXT: 210120: nop
# CHECK-NEXT: 210124: nop # CHECK-NEXT: 210124: nop
# CHECK-NEXT: 210128: nop # CHECK-NEXT: 210128: nop
# CHECK-NEXT: 21012c: nop # CHECK-NEXT: 21012c: nop
# CHECK: _bar: # CHECK: <_bar>:
# CHECK-NEXT: 210130: nop # CHECK-NEXT: 210130: nop
# CHECK-NEXT: 210134: nop # CHECK-NEXT: 210134: nop
# CHECK-NEXT: 210138: nop # CHECK-NEXT: 210138: nop
# CHECK: _dah: # CHECK: <_dah>:
# CHECK-NEXT: 21013c: nop # CHECK-NEXT: 21013c: nop
# CHECK-NEXT: 210140: nop # CHECK-NEXT: 210140: nop
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: 210144: b.eq #-36 <_foo> # CHECK-NEXT: 210144: b.eq #-36 <_foo>
# CHECK-NEXT: 210148: b.eq #-24 <_bar> # CHECK-NEXT: 210148: b.eq #-24 <_bar>
# CHECK-NEXT: 21014c: b.eq #-16 <_dah> # CHECK-NEXT: 21014c: b.eq #-16 <_dah>
#DSOREL: Section { #DSOREL: Section {
#DSOREL: Index: #DSOREL: Index:
#DSOREL: Name: .got.plt #DSOREL: Name: .got.plt
#DSOREL-NEXT: Type: SHT_PROGBITS #DSOREL-NEXT: Type: SHT_PROGBITS
Show All 14 Lines
#DSOREL-NEXT: 0x30488 R_AARCH64_JUMP_SLOT _foo #DSOREL-NEXT: 0x30488 R_AARCH64_JUMP_SLOT _foo
#DSOREL-NEXT: 0x30490 R_AARCH64_JUMP_SLOT _bar #DSOREL-NEXT: 0x30490 R_AARCH64_JUMP_SLOT _bar
#DSOREL-NEXT: 0x30498 R_AARCH64_JUMP_SLOT _dah #DSOREL-NEXT: 0x30498 R_AARCH64_JUMP_SLOT _dah
#DSOREL-NEXT: } #DSOREL-NEXT: }
#DSOREL-NEXT:] #DSOREL-NEXT:]
#DSO: Disassembly of section .text: #DSO: Disassembly of section .text:
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: _foo: #DSO-NEXT: <_foo>:
#DSO-NEXT: 10338: nop #DSO-NEXT: 10338: nop
#DSO-NEXT: 1033c: nop #DSO-NEXT: 1033c: nop
#DSO-NEXT: 10340: nop #DSO-NEXT: 10340: nop
#DSO-NEXT: 10344: nop #DSO-NEXT: 10344: nop
#DSO: _bar: #DSO: <_bar>:
#DSO-NEXT: 10348: nop #DSO-NEXT: 10348: nop
#DSO-NEXT: 1034c: nop #DSO-NEXT: 1034c: nop
#DSO-NEXT: 10350: nop #DSO-NEXT: 10350: nop
#DSO: _dah: #DSO: <_dah>:
#DSO-NEXT: 10354: nop #DSO-NEXT: 10354: nop
#DSO-NEXT: 10358: nop #DSO-NEXT: 10358: nop
#DSO: _start: #DSO: <_start>:
#DSO-NEXT: 1035c: b.eq #52 <_foo@plt> #DSO-NEXT: 1035c: b.eq #52 <_foo@plt>
#DSO-NEXT: 10360: b.eq #64 <_bar@plt> #DSO-NEXT: 10360: b.eq #64 <_bar@plt>
#DSO-NEXT: 10364: b.eq #76 <_dah@plt> #DSO-NEXT: 10364: b.eq #76 <_dah@plt>
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: Disassembly of section .plt: #DSO-NEXT: Disassembly of section .plt:
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: .plt: #DSO-NEXT: <.plt>:
#DSO-NEXT: 10370: stp x16, x30, [sp, #-16]! #DSO-NEXT: 10370: stp x16, x30, [sp, #-16]!
#DSO-NEXT: 10374: adrp x16, #131072 #DSO-NEXT: 10374: adrp x16, #131072
#DSO-NEXT: 10378: ldr x17, [x16, #1152] #DSO-NEXT: 10378: ldr x17, [x16, #1152]
#DSO-NEXT: 1037c: add x16, x16, #1152 #DSO-NEXT: 1037c: add x16, x16, #1152
#DSO-NEXT: 10380: br x17 #DSO-NEXT: 10380: br x17
#DSO-NEXT: 10384: nop #DSO-NEXT: 10384: nop
#DSO-NEXT: 10388: nop #DSO-NEXT: 10388: nop
#DSO-NEXT: 1038c: nop #DSO-NEXT: 1038c: nop
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: _foo@plt: #DSO-NEXT: <_foo@plt>:
#DSO-NEXT: 10390: adrp x16, #131072 #DSO-NEXT: 10390: adrp x16, #131072
#DSO-NEXT: 10394: ldr x17, [x16, #1160] #DSO-NEXT: 10394: ldr x17, [x16, #1160]
#DSO-NEXT: 10398: add x16, x16, #1160 #DSO-NEXT: 10398: add x16, x16, #1160
#DSO-NEXT: 1039c: br x17 #DSO-NEXT: 1039c: br x17
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: _bar@plt: #DSO-NEXT: <_bar@plt>:
#DSO-NEXT: 103a0: adrp x16, #131072 #DSO-NEXT: 103a0: adrp x16, #131072
#DSO-NEXT: 103a4: ldr x17, [x16, #1168] #DSO-NEXT: 103a4: ldr x17, [x16, #1168]
#DSO-NEXT: 103a8: add x16, x16, #1168 #DSO-NEXT: 103a8: add x16, x16, #1168
#DSO-NEXT: 103ac: br x17 #DSO-NEXT: 103ac: br x17
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: _dah@plt: #DSO-NEXT: <_dah@plt>:
#DSO-NEXT: 103b0: adrp x16, #131072 #DSO-NEXT: 103b0: adrp x16, #131072
#DSO-NEXT: 103b4: ldr x17, [x16, #1176] #DSO-NEXT: 103b4: ldr x17, [x16, #1176]
#DSO-NEXT: 103b8: add x16, x16, #1176 #DSO-NEXT: 103b8: add x16, x16, #1176
#DSO-NEXT: 103bc: br x17 #DSO-NEXT: 103bc: br x17
.globl _start .globl _start
_start: _start:
b.eq _foo b.eq _foo
b.eq _bar b.eq _bar
b.eq _dah b.eq _dah

lld/test/ELF/aarch64-copy.s

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
// CHECK-NEXT: Binding: Global // CHECK-NEXT: Binding: Global
// CHECK-NEXT: Type: Object // CHECK-NEXT: Type: Object
// CHECK-NEXT: Other: // CHECK-NEXT: Other:
// CHECK-NEXT: Section: .bss // CHECK-NEXT: Section: .bss
// CHECK: ] // CHECK: ]
// CODE: Disassembly of section .text: // CODE: Disassembly of section .text:
// CODE-EMPTY: // CODE-EMPTY:
// CODE-NEXT: _start: // CODE-NEXT: <_start>:
// S + A - P = 0x2303f0 + 0 - 0x21031c = 131284 // S + A - P = 0x2303f0 + 0 - 0x21031c = 131284
// CODE-NEXT: 21031c: adr x1, #131284 // CODE-NEXT: 21031c: adr x1, #131284
// Page(S + A) - Page(P) = Page(0x230400) - Page(0x210320) = 131072 // Page(S + A) - Page(P) = Page(0x230400) - Page(0x210320) = 131072
// CODE-NEXT: 210320: adrp x2, #131072 // CODE-NEXT: 210320: adrp x2, #131072
// (S + A) & 0xFFF = (0x230400 + 0) & 0xFFF = 1024 // (S + A) & 0xFFF = (0x230400 + 0) & 0xFFF = 1024
// CODE-NEXT: 210324: add x2, x2, #1024 // CODE-NEXT: 210324: add x2, x2, #1024
// RODATA: Contents of section .rodata: // RODATA: Contents of section .rodata:
// S(z) = 0x230404 // S(z) = 0x230404
// RODATA-NEXT: 200318 04042300 // RODATA-NEXT: 200318 04042300

lld/test/ELF/aarch64-cortex-a53-843419-address.s

Show All 31 Lines
// symbols). // symbols).
// - We can handle a patch in more than range of code, with literal data // - We can handle a patch in more than range of code, with literal data
// inbetween. // inbetween.
// - We can handle redundant mapping symbols (two or more consecutive mapping // - We can handle redundant mapping symbols (two or more consecutive mapping
// symbols with the same type). // symbols with the same type).
// - We can ignore erratum sequences in multiple literal data ranges. // - We can ignore erratum sequences in multiple literal data ranges.
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at FF8 in unpatched output.
// CHECK: t3_ff8_ldr: // CHECK: <t3_ff8_ldr>:
// CHECK-NEXT: ff8: 20 00 00 d0 adrp x0, #24576 // CHECK-NEXT: ff8: 20 00 00 d0 adrp x0, #24576
// CHECK-NEXT: ffc: 21 00 40 f9 ldr x1, [x1] // CHECK-NEXT: ffc: 21 00 40 f9 ldr x1, [x1]
// CHECK-NEXT: 1000: f9 0f 00 14 b #16356 // CHECK-NEXT: 1000: f9 0f 00 14 b #16356
// CHECK-NEXT: 1004: c0 03 5f d6 ret // CHECK-NEXT: 1004: c0 03 5f d6 ret
.section .text.01, "ax", %progbits .section .text.01, "ax", %progbits
.balign 4096 .balign 4096
.space 4096 - 8 .space 4096 - 8
.globl t3_ff8_ldr .globl t3_ff8_ldr
.type t3_ff8_ldr, %function .type t3_ff8_ldr, %function
t3_ff8_ldr: t3_ff8_ldr:
adrp x0, dat adrp x0, dat
ldr x1, [x1, #0] ldr x1, [x1, #0]
ldr x0, [x0, :got_lo12:dat] ldr x0, [x0, :got_lo12:dat]
ret ret
// create a redundant mapping symbol as we are already in a $x range // create a redundant mapping symbol as we are already in a $x range
// some object producers unconditionally generate a mapping symbol on // some object producers unconditionally generate a mapping symbol on
// every symbol so we need to handle the case of $x $x. // every symbol so we need to handle the case of $x $x.
.local $x.999 .local $x.999
$x.999: $x.999:
// CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 1FFC in unpatched output. // CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 1FFC in unpatched output.
// CHECK: t3_ffc_ldrsimd: // CHECK: <t3_ffc_ldrsimd>:
// CHECK-NEXT: 1ffc: 20 00 00 b0 adrp x0, #20480 // CHECK-NEXT: 1ffc: 20 00 00 b0 adrp x0, #20480
// CHECK-NEXT: 2000: 21 00 40 bd ldr s1, [x1] // CHECK-NEXT: 2000: 21 00 40 bd ldr s1, [x1]
// CHECK-NEXT: 2004: fa 0b 00 14 b #12264 // CHECK-NEXT: 2004: fa 0b 00 14 b #12264
// CHECK-NEXT: 2008: c0 03 5f d6 ret // CHECK-NEXT: 2008: c0 03 5f d6 ret
.globl t3_ffc_ldrsimd .globl t3_ffc_ldrsimd
.type t3_ffc_ldrsimd, %function .type t3_ffc_ldrsimd, %function
.space 4096 - 12 .space 4096 - 12
t3_ffc_ldrsimd: t3_ffc_ldrsimd:
Show All 20 Linest3_ff8_ldralldata:
// 0xf9400000 = ldr x0, [x0] // 0xf9400000 = ldr x0, [x0]
.byte 0x00 .byte 0x00
.byte 0x00 .byte 0x00
.byte 0x40 .byte 0x40
.byte 0xf9 .byte 0xf9
// Check that we can recognise the erratum sequence post literal data. // Check that we can recognise the erratum sequence post literal data.
// CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 3FF8 in unpatched output. // CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 3FF8 in unpatched output.
// CHECK: t3_ffc_ldr: // CHECK: <t3_ffc_ldr>:
// CHECK-NEXT: 3ff8: 00 00 00 f0 adrp x0, #12288 // CHECK-NEXT: 3ff8: 00 00 00 f0 adrp x0, #12288
// CHECK-NEXT: 3ffc: 21 00 40 f9 ldr x1, [x1] // CHECK-NEXT: 3ffc: 21 00 40 f9 ldr x1, [x1]
// CHECK-NEXT: 4000: fd 03 00 14 b #4084 // CHECK-NEXT: 4000: fd 03 00 14 b #4084
// CHECK-NEXT: 4004: c0 03 5f d6 ret // CHECK-NEXT: 4004: c0 03 5f d6 ret
.space 4096 - 12 .space 4096 - 12
.globl t3_ffc_ldr .globl t3_ffc_ldr
.type t3_ffc_ldr, %function .type t3_ffc_ldr, %function
t3_ffc_ldr: t3_ffc_ldr:
adrp x0, dat adrp x0, dat
ldr x1, [x1, #0] ldr x1, [x1, #0]
ldr x0, [x0, :got_lo12:dat] ldr x0, [x0, :got_lo12:dat]
ret ret
// CHECK: __CortexA53843419_1000: // CHECK: <__CortexA53843419_1000>:
// CHECK-NEXT: 4fe4: 00 0c 40 f9 ldr x0, [x0, #24] // CHECK-NEXT: 4fe4: 00 0c 40 f9 ldr x0, [x0, #24]
// CHECK-NEXT: 4fe8: 07 f0 ff 17 b #-16356 // CHECK-NEXT: 4fe8: 07 f0 ff 17 b #-16356
// CHECK: __CortexA53843419_2004: // CHECK: <__CortexA53843419_2004>:
// CHECK-NEXT: 4fec: 02 0c 40 f9 ldr x2, [x0, #24] // CHECK-NEXT: 4fec: 02 0c 40 f9 ldr x2, [x0, #24]
// CHECK-NEXT: 4ff0: 06 f4 ff 17 b #-12264 // CHECK-NEXT: 4ff0: 06 f4 ff 17 b #-12264
// CHECK: __CortexA53843419_4000: // CHECK: <__CortexA53843419_4000>:
// CHECK-NEXT: 4ff4: 00 0c 40 f9 ldr x0, [x0, #24] // CHECK-NEXT: 4ff4: 00 0c 40 f9 ldr x0, [x0, #24]
// CHECK-NEXT: 4ff8: 03 fc ff 17 b #-4084 // CHECK-NEXT: 4ff8: 03 fc ff 17 b #-4084
.section .text.02, "ax", %progbits .section .text.02, "ax", %progbits
.space 4096 - 36 .space 4096 - 36
// Start a new InputSectionDescription (see Linker Script) so the // Start a new InputSectionDescription (see Linker Script) so the
// start address will be affected by any patches added to previous // start address will be affected by any patches added to previous
// InputSectionDescription. // InputSectionDescription.
// CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 4FFC in unpatched output // CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 4FFC in unpatched output
// CHECK: t3_ffc_str: // CHECK: <t3_ffc_str>:
// CHECK-NEXT: 4ffc: 00 00 00 d0 adrp x0, #8192 // CHECK-NEXT: 4ffc: 00 00 00 d0 adrp x0, #8192
// CHECK-NEXT: 5000: 21 00 00 f9 str x1, [x1] // CHECK-NEXT: 5000: 21 00 00 f9 str x1, [x1]
// CHECK-NEXT: 5004: fb 03 00 14 b #4076 // CHECK-NEXT: 5004: fb 03 00 14 b #4076
// CHECK-NEXT: 5008: c0 03 5f d6 ret // CHECK-NEXT: 5008: c0 03 5f d6 ret
.section .newisd, "ax", %progbits .section .newisd, "ax", %progbits
.globl t3_ffc_str .globl t3_ffc_str
.type t3_ffc_str, %function .type t3_ffc_str, %function
t3_ffc_str: t3_ffc_str:
adrp x0, dat adrp x0, dat
str x1, [x1, #0] str x1, [x1, #0]
ldr x0, [x0, :got_lo12:dat] ldr x0, [x0, :got_lo12:dat]
ret ret
.space 4096 - 28 .space 4096 - 28
// CHECK: __CortexA53843419_5004: // CHECK: <__CortexA53843419_5004>:
// CHECK-NEXT: 5ff0: 00 0c 40 f9 ldr x0, [x0, #24] // CHECK-NEXT: 5ff0: 00 0c 40 f9 ldr x0, [x0, #24]
// CHECK-NEXT: 5ff4: 05 fc ff 17 b #-4076 // CHECK-NEXT: 5ff4: 05 fc ff 17 b #-4076
// Start a new OutputSection (see Linker Script) so the // Start a new OutputSection (see Linker Script) so the
// start address will be affected by any patches added to previous // start address will be affected by any patches added to previous
// InputSectionDescription. // InputSectionDescription.
//CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 5FF8 in unpatched output //CHECK-PRINT-NEXT: detected cortex-a53-843419 erratum sequence starting at 5FF8 in unpatched output
// CHECK: t3_ff8_str: // CHECK: <t3_ff8_str>:
// CHECK-NEXT: 5ff8: 00 00 00 b0 adrp x0, #4096 // CHECK-NEXT: 5ff8: 00 00 00 b0 adrp x0, #4096
// CHECK-NEXT: 5ffc: 21 00 00 f9 str x1, [x1] // CHECK-NEXT: 5ffc: 21 00 00 f9 str x1, [x1]
// CHECK-NEXT: 6000: 03 00 00 14 b #12 // CHECK-NEXT: 6000: 03 00 00 14 b #12
// CHECK-NEXT: 6004: c0 03 5f d6 ret // CHECK-NEXT: 6004: c0 03 5f d6 ret
.section .newos, "ax", %progbits .section .newos, "ax", %progbits
.globl t3_ff8_str .globl t3_ff8_str
.type t3_ff8_str, %function .type t3_ff8_str, %function
t3_ff8_str: t3_ff8_str:
adrp x0, dat adrp x0, dat
str x1, [x1, #0] str x1, [x1, #0]
ldr x0, [x0, :got_lo12:dat] ldr x0, [x0, :got_lo12:dat]
ret ret
.globl _start .globl _start
.type _start, %function .type _start, %function
_start: _start:
ret ret
// CHECK: __CortexA53843419_6000: // CHECK: <__CortexA53843419_6000>:
// CHECK-NEXT: 600c: 00 0c 40 f9 ldr x0, [x0, #24] // CHECK-NEXT: 600c: 00 0c 40 f9 ldr x0, [x0, #24]
// CHECK-NEXT: 6010: fd ff ff 17 b #-12 // CHECK-NEXT: 6010: fd ff ff 17 b #-12
.data .data
.globl dat .globl dat
dat: .word 0 dat: .word 0

lld/test/ELF/aarch64-cortex-a53-843419-large.s

// REQUIRES: aarch64 // REQUIRES: aarch64
// RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o
// RUN: ld.lld --fix-cortex-a53-843419 -z separate-code %t.o -o %t2 // RUN: ld.lld --fix-cortex-a53-843419 -z separate-code %t.o -o %t2
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2162688 -stop-address=2162700 | FileCheck --check-prefix=CHECK1 %s // RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2162688 -stop-address=2162700 | FileCheck --check-prefix=CHECK1 %s
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2166784 -stop-address=2166788 | FileCheck --check-prefix=CHECK2 %s // RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2166784 -stop-address=2166788 | FileCheck --check-prefix=CHECK2 %s
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2170872 -stop-address=2170888 | FileCheck --check-prefix=CHECK3 %s // RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2170872 -stop-address=2170888 | FileCheck --check-prefix=CHECK3 %s
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=69287928 -stop-address=69287944 | FileCheck --check-prefix=CHECK4 %s // RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=69287928 -stop-address=69287944 | FileCheck --check-prefix=CHECK4 %s
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=102842376 -stop-address=102842392 | FileCheck --check-prefix=CHECK5 %s // RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=102842376 -stop-address=102842392 | FileCheck --check-prefix=CHECK5 %s
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=136384524 -stop-address=136384528 | FileCheck --check-prefix=CHECK6 %s // RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=136384524 -stop-address=136384528 | FileCheck --check-prefix=CHECK6 %s
// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=136388604 -stop-address=136388628 | FileCheck --check-prefix=CHECK7 %s // RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=136388604 -stop-address=136388628 | FileCheck --check-prefix=CHECK7 %s
// Test case for Cortex-A53 Erratum 843419 in an OutputSection exceeding // Test case for Cortex-A53 Erratum 843419 in an OutputSection exceeding
// the maximum branch range. Both range extension thunks and patches are // the maximum branch range. Both range extension thunks and patches are
// required. // required.
// CHECK1: __AArch64AbsLongThunk_need_thunk_after_patch: // CHECK1: <__AArch64AbsLongThunk_need_thunk_after_patch>:
// CHECK1-NEXT: 210000: 50 00 00 58 ldr x16, #8 // CHECK1-NEXT: 210000: 50 00 00 58 ldr x16, #8
// CHECK1-NEXT: 210004: 00 02 1f d6 br x16 // CHECK1-NEXT: 210004: 00 02 1f d6 br x16
// CHECK1: $d: // CHECK1: <$d>:
// CHECK1-NEXT: 210008: 0c 10 21 08 .word 0x0821100c // CHECK1-NEXT: 210008: 0c 10 21 08 .word 0x0821100c
.section .text.01, "ax", %progbits .section .text.01, "ax", %progbits
.balign 4096 .balign 4096
.globl _start .globl _start
.type _start, %function .type _start, %function
_start: _start:
// Expect thunk on pass 2 // Expect thunk on pass 2
bl need_thunk_after_patch bl need_thunk_after_patch
.section .text.02, "ax", %progbits .section .text.02, "ax", %progbits
.space 4096 - 12 .space 4096 - 12
// CHECK2: _start: // CHECK2: <_start>:
// CHECK2-NEXT: 211000: 00 fc ff 97 bl #-4096 // CHECK2-NEXT: 211000: 00 fc ff 97 bl #-4096
// Expect patch on pass 1 // Expect patch on pass 1
.section .text.03, "ax", %progbits .section .text.03, "ax", %progbits
.globl t3_ff8_ldr .globl t3_ff8_ldr
.type t3_ff8_ldr, %function .type t3_ff8_ldr, %function
t3_ff8_ldr: t3_ff8_ldr:
adrp x0, dat adrp x0, dat
ldr x1, [x1, #0] ldr x1, [x1, #0]
ldr x0, [x0, :got_lo12:dat] ldr x0, [x0, :got_lo12:dat]
ret ret
// CHECK3: t3_ff8_ldr: // CHECK3: <t3_ff8_ldr>:
// CHECK3-NEXT: 211ff8: e0 00 04 f0 adrp x0, #134344704 // CHECK3-NEXT: 211ff8: e0 00 04 f0 adrp x0, #134344704
// CHECK3-NEXT: 211ffc: 21 00 40 f9 ldr x1, [x1] // CHECK3-NEXT: 211ffc: 21 00 40 f9 ldr x1, [x1]
// CHECK3-NEXT: 212000: 02 08 80 15 b #100671496 // CHECK3-NEXT: 212000: 02 08 80 15 b #100671496
// CHECK3-NEXT: 212004: c0 03 5f d6 ret // CHECK3-NEXT: 212004: c0 03 5f d6 ret
.section .text.04, "ax", %progbits .section .text.04, "ax", %progbits
.space 64 * 1024 * 1024 .space 64 * 1024 * 1024
// Expect patch on pass 1 // Expect patch on pass 1
.section .text.05, "ax", %progbits .section .text.05, "ax", %progbits
.balign 4096 .balign 4096
.space 4096 - 8 .space 4096 - 8
.globl t3_ff8_str .globl t3_ff8_str
.type t3_ff8_str, %function .type t3_ff8_str, %function
t3_ff8_str: t3_ff8_str:
adrp x0, dat adrp x0, dat
ldr x1, [x1, #0] ldr x1, [x1, #0]
str x0, [x0, :got_lo12:dat] str x0, [x0, :got_lo12:dat]
ret ret
// CHECK4: t3_ff8_str: // CHECK4: <t3_ff8_str>:
// CHECK4-NEXT: 4213ff8: e0 00 02 b0 adrp x0, #67227648 // CHECK4-NEXT: 4213ff8: e0 00 02 b0 adrp x0, #67227648
// CHECK4-NEXT: 4213ffc: 21 00 40 f9 ldr x1, [x1] // CHECK4-NEXT: 4213ffc: 21 00 40 f9 ldr x1, [x1]
// CHECK4-NEXT: 4214000: 04 00 80 14 b #33554448 // CHECK4-NEXT: 4214000: 04 00 80 14 b #33554448
// CHECK4-NEXT: 4214004: c0 03 5f d6 ret // CHECK4-NEXT: 4214004: c0 03 5f d6 ret
.section .text.06, "ax", %progbits .section .text.06, "ax", %progbits
.space 32 * 1024 * 1024 .space 32 * 1024 * 1024
// CHECK5: __CortexA53843419_211000: // CHECK5: <__CortexA53843419_211000>:
// CHECK5-NEXT: 6214008: 00 00 40 f9 ldr x0, [x0] // CHECK5-NEXT: 6214008: 00 00 40 f9 ldr x0, [x0]
// CHECK5-NEXT: 621400c: fe f7 7f 16 b #-100671496 // CHECK5-NEXT: 621400c: fe f7 7f 16 b #-100671496
// CHECK5: __CortexA53843419_4213000: // CHECK5: <__CortexA53843419_4213000>:
// CHECK5-NEXT: 6214010: 00 00 00 f9 str x0, [x0] // CHECK5-NEXT: 6214010: 00 00 00 f9 str x0, [x0]
// CHECK5-NEXT: 6214014: fc ff 7f 17 b #-33554448 // CHECK5-NEXT: 6214014: fc ff 7f 17 b #-33554448
.section .text.07, "ax", %progbits .section .text.07, "ax", %progbits
.space (32 * 1024 * 1024) - 12300 .space (32 * 1024 * 1024) - 12300
.section .text.08, "ax", %progbits .section .text.08, "ax", %progbits
.globl need_thunk_after_patch .globl need_thunk_after_patch
.type need_thunk_after_patch, %function .type need_thunk_after_patch, %function
need_thunk_after_patch: need_thunk_after_patch:
ret ret
// CHECK6: need_thunk_after_patch: // CHECK6: <need_thunk_after_patch>:
// CHECK6-NEXT: 821100c: c0 03 5f d6 ret // CHECK6-NEXT: 821100c: c0 03 5f d6 ret
// Will need a patch on pass 2 // Will need a patch on pass 2
.section .text.09, "ax", %progbits .section .text.09, "ax", %progbits
.space 4096 - 20 .space 4096 - 20
.globl t3_ffc_ldr .globl t3_ffc_ldr
.type t3_ffc_ldr, %function .type t3_ffc_ldr, %function
t3_ffc_ldr: t3_ffc_ldr:
adrp x0, dat adrp x0, dat
ldr x1, [x1, #0] ldr x1, [x1, #0]
ldr x0, [x0, :got_lo12:dat] ldr x0, [x0, :got_lo12:dat]
ret ret
// CHECK7: t3_ffc_ldr: // CHECK7: <t3_ffc_ldr>:
// CHECK7-NEXT: 8211ffc: e0 00 00 f0 adrp x0, #126976 // CHECK7-NEXT: 8211ffc: e0 00 00 f0 adrp x0, #126976
// CHECK7-NEXT: 8212000: 21 00 40 f9 ldr x1, [x1] // CHECK7-NEXT: 8212000: 21 00 40 f9 ldr x1, [x1]
// CHECK7-NEXT: 8212004: 02 00 00 14 b #8 // CHECK7-NEXT: 8212004: 02 00 00 14 b #8
// CHECK7-NEXT: 8212008: c0 03 5f d6 ret // CHECK7-NEXT: 8212008: c0 03 5f d6 ret
// CHECK7: __CortexA53843419_8212004: // CHECK7: <__CortexA53843419_8212004>:
// CHECK7-NEXT: 821200c: 00 00 40 f9 ldr x0, [x0] // CHECK7-NEXT: 821200c: 00 00 40 f9 ldr x0, [x0]
// CHECK7-NEXT: 8212010: fe ff ff 17 b #-8 // CHECK7-NEXT: 8212010: fe ff ff 17 b #-8
.section .data .section .data
.globl dat .globl dat
dat: .quad 0 dat: .quad 0

lld/test/ELF/aarch64-cortex-a53-843419-large2.s

// REQUIRES: aarch64 // REQUIRES: aarch64
// RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o
// RUN: ld.lld --fix-cortex-a53-843419 -Ttext=0x8000000 %t.o -o %t2 // RUN: ld.lld --fix-cortex-a53-843419 -Ttext=0x8000000 %t.o -o %t2
// RUN: llvm-objdump -d --start-address=0x8001000 --stop-address=0x8001004 %t2 | FileCheck %s // RUN: llvm-objdump -d --start-address=0x8001000 --stop-address=0x8001004 %t2 | FileCheck %s
.section .text.01, "ax", %progbits .section .text.01, "ax", %progbits
.balign 4096 .balign 4096
.space 4096 - 8 .space 4096 - 8
adrp x0, thunk adrp x0, thunk
ldr x1, [x1, #0] ldr x1, [x1, #0]
// CHECK: thunk: // CHECK: <thunk>:
// CHECK-NEXT: b #67108872 <__CortexA53843419_8001000> // CHECK-NEXT: b #67108872 <__CortexA53843419_8001000>
thunk: thunk:
ldr x0, [x0, :got_lo12:thunk] ldr x0, [x0, :got_lo12:thunk]
ret ret
.space 64 * 1024 * 1024 .space 64 * 1024 * 1024
.section .text.02, "ax", %progbits .section .text.02, "ax", %progbits
.space 64 * 1024 * 1024 .space 64 * 1024 * 1024

lld/test/ELF/aarch64-cortex-a53-843419-recognize.s

Show All 23 Lines
// Each section contains a sequence of instructions that should be recognized // Each section contains a sequence of instructions that should be recognized
// as erratum 843419. The test cases cover the major variations such as: // as erratum 843419. The test cases cover the major variations such as:
// - adrp starts at 0xfff8 or 0xfffc. // - adrp starts at 0xfff8 or 0xfffc.
// - Variations in instruction class for instruction 2. // - Variations in instruction class for instruction 2.
// - Optional instruction 3 present or not. // - Optional instruction 3 present or not.
// - Load or store for instruction 4. // - Load or store for instruction 4.
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 211FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 211FF8 in unpatched output.
// CHECK: t3_ff8_ldr: // CHECK: <t3_ff8_ldr>:
// CHECK-NEXT: 211ff8: 60 02 00 f0 adrp x0, #323584 // CHECK-NEXT: 211ff8: 60 02 00 f0 adrp x0, #323584
// CHECK-NEXT: 211ffc: 21 00 40 f9 ldr x1, [x1] // CHECK-NEXT: 211ffc: 21 00 40 f9 ldr x1, [x1]
// CHECK-FIX: 212000: 03 c8 00 14 b #204812 // CHECK-FIX: 212000: 03 c8 00 14 b #204812
// CHECK-NOFIX: 212000: 00 00 40 f9 ldr x0, [x0] // CHECK-NOFIX: 212000: 00 00 40 f9 ldr x0, [x0]
// CHECK-NEXT: 212004: c0 03 5f d6 ret // CHECK-NEXT: 212004: c0 03 5f d6 ret
// CHECK-RELOCATABLE: t3_ff8_ldr: // CHECK-RELOCATABLE: <t3_ff8_ldr>:
// CHECK-RELOCATABLE-NEXT: ff8: 00 00 00 90 adrp x0, #0 // CHECK-RELOCATABLE-NEXT: ff8: 00 00 00 90 adrp x0, #0
// CHECK-RELOCATABLE-NEXT: ffc: 21 00 40 f9 ldr x1, [x1] // CHECK-RELOCATABLE-NEXT: ffc: 21 00 40 f9 ldr x1, [x1]
// CHECK-RELOCATABLE-NEXT: 1000: 00 00 40 f9 ldr x0, [x0] // CHECK-RELOCATABLE-NEXT: 1000: 00 00 40 f9 ldr x0, [x0]
// CHECK-RELOCATABLE-NEXT: 1004: c0 03 5f d6 ret // CHECK-RELOCATABLE-NEXT: 1004: c0 03 5f d6 ret
.section .text.01, "ax", %progbits .section .text.01, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ff8_ldr .globl t3_ff8_ldr
.type t3_ff8_ldr, %function .type t3_ff8_ldr, %function
.space 4096 - 8 .space 4096 - 8
t3_ff8_ldr: t3_ff8_ldr:
adrp x0, dat1 adrp x0, dat1
ldr x1, [x1, #0] ldr x1, [x1, #0]
ldr x0, [x0, :got_lo12:dat1] ldr x0, [x0, :got_lo12:dat1]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 213FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 213FF8 in unpatched output.
// CHECK: t3_ff8_ldrsimd: // CHECK: <t3_ff8_ldrsimd>:
// CHECK-NEXT: 213ff8: 60 02 00 b0 adrp x0, #315392 // CHECK-NEXT: 213ff8: 60 02 00 b0 adrp x0, #315392
// CHECK-NEXT: 213ffc: 21 00 40 bd ldr s1, [x1] // CHECK-NEXT: 213ffc: 21 00 40 bd ldr s1, [x1]
// CHECK-FIX: 214000: 05 c0 00 14 b #196628 // CHECK-FIX: 214000: 05 c0 00 14 b #196628
// CHECK-NOFIX: 214000: 02 04 40 f9 ldr x2, [x0, #8] // CHECK-NOFIX: 214000: 02 04 40 f9 ldr x2, [x0, #8]
// CHECK-NEXT: 214004: c0 03 5f d6 ret // CHECK-NEXT: 214004: c0 03 5f d6 ret
.section .text.02, "ax", %progbits .section .text.02, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ff8_ldrsimd .globl t3_ff8_ldrsimd
.type t3_ff8_ldrsimd, %function .type t3_ff8_ldrsimd, %function
.space 4096 - 8 .space 4096 - 8
t3_ff8_ldrsimd: t3_ff8_ldrsimd:
adrp x0, dat2 adrp x0, dat2
ldr s1, [x1, #0] ldr s1, [x1, #0]
ldr x2, [x0, :got_lo12:dat2] ldr x2, [x0, :got_lo12:dat2]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 215FFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 215FFC in unpatched output.
// CHECK: t3_ffc_ldrpost: // CHECK: <t3_ffc_ldrpost>:
// CHECK-NEXT: 215ffc: 40 02 00 f0 adrp x0, #307200 // CHECK-NEXT: 215ffc: 40 02 00 f0 adrp x0, #307200
// CHECK-NEXT: 216000: 21 84 40 bc ldr s1, [x1], #8 // CHECK-NEXT: 216000: 21 84 40 bc ldr s1, [x1], #8
// CHECK-FIX: 216004: 06 b8 00 14 b #188440 // CHECK-FIX: 216004: 06 b8 00 14 b #188440
// CHECK-NOFIX: 216004: 03 08 40 f9 ldr x3, [x0, #16] // CHECK-NOFIX: 216004: 03 08 40 f9 ldr x3, [x0, #16]
// CHECK-NEXT: 216008: c0 03 5f d6 ret // CHECK-NEXT: 216008: c0 03 5f d6 ret
.section .text.03, "ax", %progbits .section .text.03, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ffc_ldrpost .globl t3_ffc_ldrpost
.type t3_ffc_ldrpost, %function .type t3_ffc_ldrpost, %function
.space 4096 - 4 .space 4096 - 4
t3_ffc_ldrpost: t3_ffc_ldrpost:
adrp x0, dat3 adrp x0, dat3
ldr s1, [x1], #8 ldr s1, [x1], #8
ldr x3, [x0, :got_lo12:dat3] ldr x3, [x0, :got_lo12:dat3]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 217FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 217FF8 in unpatched output.
// CHECK: t3_ff8_strpre: // CHECK: <t3_ff8_strpre>:
// CHECK-NEXT: 217ff8: 40 02 00 b0 adrp x0, #299008 // CHECK-NEXT: 217ff8: 40 02 00 b0 adrp x0, #299008
// CHECK-NEXT: 217ffc: 21 8c 00 bc str s1, [x1, #8]! // CHECK-NEXT: 217ffc: 21 8c 00 bc str s1, [x1, #8]!
// CHECK-FIX: 218000: 09 b0 00 14 b #180260 // CHECK-FIX: 218000: 09 b0 00 14 b #180260
// CHECK-NOFIX: 218000: 02 0c 40 f9 ldr x2, [x0, #24] // CHECK-NOFIX: 218000: 02 0c 40 f9 ldr x2, [x0, #24]
// CHECK-NEXT: 218004: c0 03 5f d6 ret // CHECK-NEXT: 218004: c0 03 5f d6 ret
.section .text.04, "ax", %progbits .section .text.04, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ff8_strpre .globl t3_ff8_strpre
.type t3_ff8_strpre, %function .type t3_ff8_strpre, %function
.space 4096 - 8 .space 4096 - 8
t3_ff8_strpre: t3_ff8_strpre:
adrp x0, dat1 adrp x0, dat1
str s1, [x1, #8]! str s1, [x1, #8]!
ldr x2, [x0, :lo12:dat1] ldr x2, [x0, :lo12:dat1]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 219FFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 219FFC in unpatched output.
// CHECK: t3_ffc_str: // CHECK: <t3_ffc_str>:
// CHECK-NEXT: 219ffc: 3c 02 00 f0 adrp x28, #290816 // CHECK-NEXT: 219ffc: 3c 02 00 f0 adrp x28, #290816
// CHECK-NEXT: 21a000: 42 00 00 f9 str x2, [x2] // CHECK-NEXT: 21a000: 42 00 00 f9 str x2, [x2]
// CHECK-FIX: 21a004: 0a a8 00 14 b #172072 // CHECK-FIX: 21a004: 0a a8 00 14 b #172072
// CHECK-NOFIX: 21a004: 9c 13 00 f9 str x28, [x28, #32] // CHECK-NOFIX: 21a004: 9c 13 00 f9 str x28, [x28, #32]
// CHECK-NEXT: 21a008: c0 03 5f d6 ret // CHECK-NEXT: 21a008: c0 03 5f d6 ret
.section .text.05, "ax", %progbits .section .text.05, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ffc_str .globl t3_ffc_str
.type t3_ffc_str, %function .type t3_ffc_str, %function
.space 4096 - 4 .space 4096 - 4
t3_ffc_str: t3_ffc_str:
adrp x28, dat2 adrp x28, dat2
str x2, [x2, #0] str x2, [x2, #0]
str x28, [x28, :lo12:dat2] str x28, [x28, :lo12:dat2]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 21BFFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 21BFFC in unpatched output.
// CHECK: t3_ffc_strsimd: // CHECK: <t3_ffc_strsimd>:
// CHECK-NEXT: 21bffc: 3c 02 00 b0 adrp x28, #282624 // CHECK-NEXT: 21bffc: 3c 02 00 b0 adrp x28, #282624
// CHECK-NEXT: 21c000: 44 00 00 b9 str w4, [x2] // CHECK-NEXT: 21c000: 44 00 00 b9 str w4, [x2]
// CHECK-FIX: 21c004: 0c a0 00 14 b #163888 // CHECK-FIX: 21c004: 0c a0 00 14 b #163888
// CHECK-NOFIX: 21c004: 84 17 00 f9 str x4, [x28, #40] // CHECK-NOFIX: 21c004: 84 17 00 f9 str x4, [x28, #40]
// CHECK-NEXT: 21c008: c0 03 5f d6 ret // CHECK-NEXT: 21c008: c0 03 5f d6 ret
.section .text.06, "ax", %progbits .section .text.06, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ffc_strsimd .globl t3_ffc_strsimd
.type t3_ffc_strsimd, %function .type t3_ffc_strsimd, %function
.space 4096 - 4 .space 4096 - 4
t3_ffc_strsimd: t3_ffc_strsimd:
adrp x28, dat3 adrp x28, dat3
str w4, [x2, #0] str w4, [x2, #0]
str x4, [x28, :lo12:dat3] str x4, [x28, :lo12:dat3]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 21DFF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 21DFF8 in unpatched output.
// CHECK: t3_ff8_ldrunpriv: // CHECK: <t3_ff8_ldrunpriv>:
// CHECK-NEXT: 21dff8: 1d 02 00 f0 adrp x29, #274432 // CHECK-NEXT: 21dff8: 1d 02 00 f0 adrp x29, #274432
// CHECK-NEXT: 21dffc: 41 08 40 38 ldtrb w1, [x2] // CHECK-NEXT: 21dffc: 41 08 40 38 ldtrb w1, [x2]
// CHECK-FIX: 21e000: 0f 98 00 14 b #155708 // CHECK-FIX: 21e000: 0f 98 00 14 b #155708
// CHECK-NOFIX: 21e000: bd 03 40 f9 ldr x29, [x29] // CHECK-NOFIX: 21e000: bd 03 40 f9 ldr x29, [x29]
// CHECK-NEXT: 21e004: c0 03 5f d6 ret // CHECK-NEXT: 21e004: c0 03 5f d6 ret
.section .text.07, "ax", %progbits .section .text.07, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ff8_ldrunpriv .globl t3_ff8_ldrunpriv
.type t3_ff8_ldrunpriv, %function .type t3_ff8_ldrunpriv, %function
.space 4096 - 8 .space 4096 - 8
t3_ff8_ldrunpriv: t3_ff8_ldrunpriv:
adrp x29, dat1 adrp x29, dat1
ldtrb w1, [x2, #0] ldtrb w1, [x2, #0]
ldr x29, [x29, :got_lo12:dat1] ldr x29, [x29, :got_lo12:dat1]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 21FFFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 21FFFC in unpatched output.
// CHECK: t3_ffc_ldur: // CHECK: <t3_ffc_ldur>:
// CHECK-NEXT: 21fffc: 1d 02 00 b0 adrp x29, #266240 // CHECK-NEXT: 21fffc: 1d 02 00 b0 adrp x29, #266240
// CHECK-NEXT: 220000: 42 40 40 b8 ldur w2, [x2, #4] // CHECK-NEXT: 220000: 42 40 40 b8 ldur w2, [x2, #4]
// CHECK-FIX: 220004: 10 90 00 14 b #147520 // CHECK-FIX: 220004: 10 90 00 14 b #147520
// CHECK-NOFIX: 220004: bd 07 40 f9 ldr x29, [x29, #8] // CHECK-NOFIX: 220004: bd 07 40 f9 ldr x29, [x29, #8]
// CHECK-NEXT: 220008: c0 03 5f d6 ret // CHECK-NEXT: 220008: c0 03 5f d6 ret
.balign 4096 .balign 4096
.globl t3_ffc_ldur .globl t3_ffc_ldur
.type t3_ffc_ldur, %function .type t3_ffc_ldur, %function
.space 4096 - 4 .space 4096 - 4
t3_ffc_ldur: t3_ffc_ldur:
adrp x29, dat2 adrp x29, dat2
ldur w2, [x2, #4] ldur w2, [x2, #4]
ldr x29, [x29, :got_lo12:dat2] ldr x29, [x29, :got_lo12:dat2]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 221FFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 221FFC in unpatched output.
// CHECK: t3_ffc_sturh: // CHECK: <t3_ffc_sturh>:
// CHECK-NEXT: 221ffc: f2 01 00 f0 adrp x18, #258048 // CHECK-NEXT: 221ffc: f2 01 00 f0 adrp x18, #258048
// CHECK-NEXT: 222000: 43 40 00 78 sturh w3, [x2, #4] // CHECK-NEXT: 222000: 43 40 00 78 sturh w3, [x2, #4]
// CHECK-FIX: 222004: 12 88 00 14 b #139336 // CHECK-FIX: 222004: 12 88 00 14 b #139336
// CHECK-NOFIX: 222004: 41 0a 40 f9 ldr x1, [x18, #16] // CHECK-NOFIX: 222004: 41 0a 40 f9 ldr x1, [x18, #16]
// CHECK-NEXT: 222008: c0 03 5f d6 ret // CHECK-NEXT: 222008: c0 03 5f d6 ret
.section .text.09, "ax", %progbits .section .text.09, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ffc_sturh .globl t3_ffc_sturh
.type t3_ffc_sturh, %function .type t3_ffc_sturh, %function
.space 4096 - 4 .space 4096 - 4
t3_ffc_sturh: t3_ffc_sturh:
adrp x18, dat3 adrp x18, dat3
sturh w3, [x2, #4] sturh w3, [x2, #4]
ldr x1, [x18, :got_lo12:dat3] ldr x1, [x18, :got_lo12:dat3]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 223FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 223FF8 in unpatched output.
// CHECK: t3_ff8_literal: // CHECK: <t3_ff8_literal>:
// CHECK-NEXT: 223ff8: f2 01 00 b0 adrp x18, #249856 // CHECK-NEXT: 223ff8: f2 01 00 b0 adrp x18, #249856
// CHECK-NEXT: 223ffc: e3 ff ff 58 ldr x3, #-4 // CHECK-NEXT: 223ffc: e3 ff ff 58 ldr x3, #-4
// CHECK-FIX: 224000: 15 80 00 14 b #131156 // CHECK-FIX: 224000: 15 80 00 14 b #131156
// CHECK-NOFIX: 224000: 52 0e 40 f9 ldr x18, [x18, #24] // CHECK-NOFIX: 224000: 52 0e 40 f9 ldr x18, [x18, #24]
// CHECK-NEXT: 224004: c0 03 5f d6 ret // CHECK-NEXT: 224004: c0 03 5f d6 ret
.section .text.10, "ax", %progbits .section .text.10, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ff8_literal .globl t3_ff8_literal
.type t3_ff8_literal, %function .type t3_ff8_literal, %function
.space 4096 - 8 .space 4096 - 8
t3_ff8_literal: t3_ff8_literal:
adrp x18, dat1 adrp x18, dat1
ldr x3, t3_ff8_literal ldr x3, t3_ff8_literal
ldr x18, [x18, :lo12:dat1] ldr x18, [x18, :lo12:dat1]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 225FFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 225FFC in unpatched output.
// CHECK: t3_ffc_register: // CHECK: <t3_ffc_register>:
// CHECK-NEXT: 225ffc: cf 01 00 f0 adrp x15, #241664 // CHECK-NEXT: 225ffc: cf 01 00 f0 adrp x15, #241664
// CHECK-NEXT: 226000: 43 68 61 f8 ldr x3, [x2, x1] // CHECK-NEXT: 226000: 43 68 61 f8 ldr x3, [x2, x1]
// CHECK-FIX: 226004: 16 78 00 14 b #122968 // CHECK-FIX: 226004: 16 78 00 14 b #122968
// CHECK-NOFIX: 226004: ea 11 40 f9 ldr x10, [x15, #32] // CHECK-NOFIX: 226004: ea 11 40 f9 ldr x10, [x15, #32]
// CHECK-NEXT: 226008: c0 03 5f d6 ret // CHECK-NEXT: 226008: c0 03 5f d6 ret
.section .text.11, "ax", %progbits .section .text.11, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ffc_register .globl t3_ffc_register
.type t3_ffc_register, %function .type t3_ffc_register, %function
.space 4096 - 4 .space 4096 - 4
t3_ffc_register: t3_ffc_register:
adrp x15, dat2 adrp x15, dat2
ldr x3, [x2, x1] ldr x3, [x2, x1]
ldr x10, [x15, :lo12:dat2] ldr x10, [x15, :lo12:dat2]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 227FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 227FF8 in unpatched output.
// CHECK: t3_ff8_stp: // CHECK: <t3_ff8_stp>:
// CHECK-NEXT: 227ff8: d0 01 00 b0 adrp x16, #233472 // CHECK-NEXT: 227ff8: d0 01 00 b0 adrp x16, #233472
// CHECK-NEXT: 227ffc: 61 08 00 a9 stp x1, x2, [x3] // CHECK-NEXT: 227ffc: 61 08 00 a9 stp x1, x2, [x3]
// CHECK-FIX: 228000: 19 70 00 14 b #114788 // CHECK-FIX: 228000: 19 70 00 14 b #114788
// CHECK-NOFIX: 228000: 0d 16 40 f9 ldr x13, [x16, #40] // CHECK-NOFIX: 228000: 0d 16 40 f9 ldr x13, [x16, #40]
// CHECK-NEXT: 228004: c0 03 5f d6 ret // CHECK-NEXT: 228004: c0 03 5f d6 ret
.section .text.12, "ax", %progbits .section .text.12, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ff8_stp .globl t3_ff8_stp
.type t3_ff8_stp, %function .type t3_ff8_stp, %function
.space 4096 - 8 .space 4096 - 8
t3_ff8_stp: t3_ff8_stp:
adrp x16, dat3 adrp x16, dat3
stp x1,x2, [x3, #0] stp x1,x2, [x3, #0]
ldr x13, [x16, :lo12:dat3] ldr x13, [x16, :lo12:dat3]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 229FFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 229FFC in unpatched output.
// CHECK: t3_ffc_stnp: // CHECK: <t3_ffc_stnp>:
// CHECK-NEXT: 229ffc: a7 01 00 f0 adrp x7, #225280 // CHECK-NEXT: 229ffc: a7 01 00 f0 adrp x7, #225280
// CHECK-NEXT: 22a000: 61 08 00 a8 stnp x1, x2, [x3] // CHECK-NEXT: 22a000: 61 08 00 a8 stnp x1, x2, [x3]
// CHECK-FIX: 22a004: 1a 68 00 14 b #106600 // CHECK-FIX: 22a004: 1a 68 00 14 b #106600
// CHECK-NOFIX: 22a004: e9 0c 40 f9 ldr x9, [x7, #24] // CHECK-NOFIX: 22a004: e9 0c 40 f9 ldr x9, [x7, #24]
// CHECK-NEXT: 22a008: c0 03 5f d6 ret // CHECK-NEXT: 22a008: c0 03 5f d6 ret
.section .text.13, "ax", %progbits .section .text.13, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ffc_stnp .globl t3_ffc_stnp
.type t3_ffc_stnp, %function .type t3_ffc_stnp, %function
.space 4096 - 4 .space 4096 - 4
t3_ffc_stnp: t3_ffc_stnp:
adrp x7, dat1 adrp x7, dat1
stnp x1,x2, [x3, #0] stnp x1,x2, [x3, #0]
ldr x9, [x7, :lo12:dat1] ldr x9, [x7, :lo12:dat1]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 22BFFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 22BFFC in unpatched output.
// CHECK: t3_ffc_st1singlepost: // CHECK: <t3_ffc_st1singlepost>:
// CHECK-NEXT: 22bffc: b7 01 00 b0 adrp x23, #217088 // CHECK-NEXT: 22bffc: b7 01 00 b0 adrp x23, #217088
// CHECK-NEXT: 22c000: 20 04 82 0d st1 { v0.b }[1], [x1], x2 // CHECK-NEXT: 22c000: 20 04 82 0d st1 { v0.b }[1], [x1], x2
// CHECK-FIX: 22c004: 1c 60 00 14 b #98416 // CHECK-FIX: 22c004: 1c 60 00 14 b #98416
// CHECK-NOFIX: 22c004: f6 12 40 f9 ldr x22, [x23, #32] // CHECK-NOFIX: 22c004: f6 12 40 f9 ldr x22, [x23, #32]
// CHECK-NEXT: 22c008: c0 03 5f d6 ret // CHECK-NEXT: 22c008: c0 03 5f d6 ret
.section .text.14, "ax", %progbits .section .text.14, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ffc_st1singlepost .globl t3_ffc_st1singlepost
.type t3_ffc_st1singlepost, %function .type t3_ffc_st1singlepost, %function
.space 4096 - 4 .space 4096 - 4
t3_ffc_st1singlepost: t3_ffc_st1singlepost:
adrp x23, dat2 adrp x23, dat2
st1 { v0.b }[1], [x1], x2 st1 { v0.b }[1], [x1], x2
ldr x22, [x23, :lo12:dat2] ldr x22, [x23, :lo12:dat2]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 22DFF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 22DFF8 in unpatched output.
// CHECK: t3_ff8_st1multiple: // CHECK: <t3_ff8_st1multiple>:
// CHECK-NEXT: 22dff8: 97 01 00 f0 adrp x23, #208896 // CHECK-NEXT: 22dff8: 97 01 00 f0 adrp x23, #208896
// CHECK-NEXT: 22dffc: 20 a0 00 4c st1 { v0.16b, v1.16b }, [x1] // CHECK-NEXT: 22dffc: 20 a0 00 4c st1 { v0.16b, v1.16b }, [x1]
// CHECK-FIX: 22e000: 1f 58 00 14 b #90236 // CHECK-FIX: 22e000: 1f 58 00 14 b #90236
// CHECK-NOFIX: 22e000: f8 16 40 f9 ldr x24, [x23, #40] // CHECK-NOFIX: 22e000: f8 16 40 f9 ldr x24, [x23, #40]
// CHECK-NEXT: 22e004: c0 03 5f d6 ret // CHECK-NEXT: 22e004: c0 03 5f d6 ret
.section .text.15, "ax", %progbits .section .text.15, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ff8_st1multiple .globl t3_ff8_st1multiple
.type t3_ff8_st1muliple, %function .type t3_ff8_st1muliple, %function
.space 4096 - 8 .space 4096 - 8
t3_ff8_st1multiple: t3_ff8_st1multiple:
adrp x23, dat3 adrp x23, dat3
st1 { v0.16b, v1.16b }, [x1] st1 { v0.16b, v1.16b }, [x1]
ldr x24, [x23, :lo12:dat3] ldr x24, [x23, :lo12:dat3]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 22FFF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 22FFF8 in unpatched output.
// CHECK: t4_ff8_ldr: // CHECK: <t4_ff8_ldr>:
// CHECK-NEXT: 22fff8: 80 01 00 b0 adrp x0, #200704 // CHECK-NEXT: 22fff8: 80 01 00 b0 adrp x0, #200704
// CHECK-NEXT: 22fffc: 21 00 40 f9 ldr x1, [x1] // CHECK-NEXT: 22fffc: 21 00 40 f9 ldr x1, [x1]
// CHECK-NEXT: 230000: 42 00 00 8b add x2, x2, x0 // CHECK-NEXT: 230000: 42 00 00 8b add x2, x2, x0
// CHECK-FIX: 230004: 20 50 00 14 b #82048 // CHECK-FIX: 230004: 20 50 00 14 b #82048
// CHECK-NOFIX: 230004: 02 00 40 f9 ldr x2, [x0] // CHECK-NOFIX: 230004: 02 00 40 f9 ldr x2, [x0]
// CHECK-NEXT: 230008: c0 03 5f d6 ret // CHECK-NEXT: 230008: c0 03 5f d6 ret
.section .text.16, "ax", %progbits .section .text.16, "ax", %progbits
.balign 4096 .balign 4096
.globl t4_ff8_ldr .globl t4_ff8_ldr
.type t4_ff8_ldr, %function .type t4_ff8_ldr, %function
.space 4096 - 8 .space 4096 - 8
t4_ff8_ldr: t4_ff8_ldr:
adrp x0, dat1 adrp x0, dat1
ldr x1, [x1, #0] ldr x1, [x1, #0]
add x2, x2, x0 add x2, x2, x0
ldr x2, [x0, :got_lo12:dat1] ldr x2, [x0, :got_lo12:dat1]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 231FFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 231FFC in unpatched output.
// CHECK: t4_ffc_str: // CHECK: <t4_ffc_str>:
// CHECK-NEXT: 231ffc: 7c 01 00 f0 adrp x28, #192512 // CHECK-NEXT: 231ffc: 7c 01 00 f0 adrp x28, #192512
// CHECK-NEXT: 232000: 42 00 00 f9 str x2, [x2] // CHECK-NEXT: 232000: 42 00 00 f9 str x2, [x2]
// CHECK-NEXT: 232004: 20 00 02 cb sub x0, x1, x2 // CHECK-NEXT: 232004: 20 00 02 cb sub x0, x1, x2
// CHECK-FIX: 232008: 21 48 00 14 b #73860 // CHECK-FIX: 232008: 21 48 00 14 b #73860
// CHECK-NOFIX: 232008: 9b 07 00 f9 str x27, [x28, #8] // CHECK-NOFIX: 232008: 9b 07 00 f9 str x27, [x28, #8]
// CHECK-NEXT: 23200c: c0 03 5f d6 ret // CHECK-NEXT: 23200c: c0 03 5f d6 ret
.section .text.17, "ax", %progbits .section .text.17, "ax", %progbits
.balign 4096 .balign 4096
.globl t4_ffc_str .globl t4_ffc_str
.type t4_ffc_str, %function .type t4_ffc_str, %function
.space 4096 - 4 .space 4096 - 4
t4_ffc_str: t4_ffc_str:
adrp x28, dat2 adrp x28, dat2
str x2, [x2, #0] str x2, [x2, #0]
sub x0, x1, x2 sub x0, x1, x2
str x27, [x28, :got_lo12:dat2] str x27, [x28, :got_lo12:dat2]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 233FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 233FF8 in unpatched output.
// CHECK: t4_ff8_stp: // CHECK: <t4_ff8_stp>:
// CHECK-NEXT: 233ff8: 70 01 00 b0 adrp x16, #184320 // CHECK-NEXT: 233ff8: 70 01 00 b0 adrp x16, #184320
// CHECK-NEXT: 233ffc: 61 08 00 a9 stp x1, x2, [x3] // CHECK-NEXT: 233ffc: 61 08 00 a9 stp x1, x2, [x3]
// CHECK-NEXT: 234000: 03 7e 10 9b mul x3, x16, x16 // CHECK-NEXT: 234000: 03 7e 10 9b mul x3, x16, x16
// CHECK-FIX: 234004: 24 40 00 14 b #65680 // CHECK-FIX: 234004: 24 40 00 14 b #65680
// CHECK-NOFIX: 234004: 0e 0a 40 f9 ldr x14, [x16, #16] // CHECK-NOFIX: 234004: 0e 0a 40 f9 ldr x14, [x16, #16]
// CHECK-NEXT: 234008: c0 03 5f d6 ret // CHECK-NEXT: 234008: c0 03 5f d6 ret
.section .text.18, "ax", %progbits .section .text.18, "ax", %progbits
.balign 4096 .balign 4096
.globl t4_ff8_stp .globl t4_ff8_stp
.type t4_ff8_stp, %function .type t4_ff8_stp, %function
.space 4096 - 8 .space 4096 - 8
t4_ff8_stp: t4_ff8_stp:
adrp x16, dat3 adrp x16, dat3
stp x1,x2, [x3, #0] stp x1,x2, [x3, #0]
mul x3, x16, x16 mul x3, x16, x16
ldr x14, [x16, :got_lo12:dat3] ldr x14, [x16, :got_lo12:dat3]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 235FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 235FF8 in unpatched output.
// CHECK: t4_ff8_stppre: // CHECK: <t4_ff8_stppre>:
// CHECK-NEXT: 235ff8: 50 01 00 f0 adrp x16, #176128 // CHECK-NEXT: 235ff8: 50 01 00 f0 adrp x16, #176128
// CHECK-NEXT: 235ffc: 61 08 81 a9 stp x1, x2, [x3, #16]! // CHECK-NEXT: 235ffc: 61 08 81 a9 stp x1, x2, [x3, #16]!
// CHECK-NEXT: 236000: 03 7e 10 9b mul x3, x16, x16 // CHECK-NEXT: 236000: 03 7e 10 9b mul x3, x16, x16
// CHECK-FIX: 236004: 26 38 00 14 b #57496 // CHECK-FIX: 236004: 26 38 00 14 b #57496
// CHECK-NOFIX: 236004: 0e 06 40 f9 ldr x14, [x16, #8] // CHECK-NOFIX: 236004: 0e 06 40 f9 ldr x14, [x16, #8]
// CHECK-NEXT: 236008: c0 03 5f d6 ret // CHECK-NEXT: 236008: c0 03 5f d6 ret
.section .text.19, "ax", %progbits .section .text.19, "ax", %progbits
.balign 4096 .balign 4096
.globl t4_ff8_stppre .globl t4_ff8_stppre
.type t4_ff8_stppre, %function .type t4_ff8_stppre, %function
.space 4096 - 8 .space 4096 - 8
t4_ff8_stppre: t4_ff8_stppre:
adrp x16, dat1 adrp x16, dat1
stp x1,x2, [x3, #16]! stp x1,x2, [x3, #16]!
mul x3, x16, x16 mul x3, x16, x16
ldr x14, [x16, #8] ldr x14, [x16, #8]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 237FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 237FF8 in unpatched output.
// CHECK: t4_ff8_stppost: // CHECK: <t4_ff8_stppost>:
// CHECK-NEXT: 237ff8: 50 01 00 b0 adrp x16, #167936 // CHECK-NEXT: 237ff8: 50 01 00 b0 adrp x16, #167936
// CHECK-NEXT: 237ffc: 61 08 81 a8 stp x1, x2, [x3], #16 // CHECK-NEXT: 237ffc: 61 08 81 a8 stp x1, x2, [x3], #16
// CHECK-NEXT: 238000: 03 7e 10 9b mul x3, x16, x16 // CHECK-NEXT: 238000: 03 7e 10 9b mul x3, x16, x16
// CHECK-FIX: 238004: 28 30 00 14 b #49312 // CHECK-FIX: 238004: 28 30 00 14 b #49312
// CHECK-NOFIX: 238004: 0e 06 40 f9 ldr x14, [x16, #8] // CHECK-NOFIX: 238004: 0e 06 40 f9 ldr x14, [x16, #8]
// CHECK-NEXT: 238008: c0 03 5f d6 ret // CHECK-NEXT: 238008: c0 03 5f d6 ret
.section .text.20, "ax", %progbits .section .text.20, "ax", %progbits
.balign 4096 .balign 4096
.globl t4_ff8_stppost .globl t4_ff8_stppost
.type t4_ff8_stppost, %function .type t4_ff8_stppost, %function
.space 4096 - 8 .space 4096 - 8
t4_ff8_stppost: t4_ff8_stppost:
adrp x16, dat2 adrp x16, dat2
stp x1,x2, [x3], #16 stp x1,x2, [x3], #16
mul x3, x16, x16 mul x3, x16, x16
ldr x14, [x16, #8] ldr x14, [x16, #8]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 239FFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 239FFC in unpatched output.
// CHECK: t4_ffc_stpsimd: // CHECK: <t4_ffc_stpsimd>:
// CHECK-NEXT: 239ffc: 30 01 00 f0 adrp x16, #159744 // CHECK-NEXT: 239ffc: 30 01 00 f0 adrp x16, #159744
// CHECK-NEXT: 23a000: 61 08 00 ad stp q1, q2, [x3] // CHECK-NEXT: 23a000: 61 08 00 ad stp q1, q2, [x3]
// CHECK-NEXT: 23a004: 03 7e 10 9b mul x3, x16, x16 // CHECK-NEXT: 23a004: 03 7e 10 9b mul x3, x16, x16
// CHECK-FIX: 23a008: 29 28 00 14 b #41124 // CHECK-FIX: 23a008: 29 28 00 14 b #41124
// CHECK-NOFIX: 23a008: 0e 06 40 f9 ldr x14, [x16, #8] // CHECK-NOFIX: 23a008: 0e 06 40 f9 ldr x14, [x16, #8]
// CHECK-NEXT: 23a00c: c0 03 5f d6 ret // CHECK-NEXT: 23a00c: c0 03 5f d6 ret
.section .text.21, "ax", %progbits .section .text.21, "ax", %progbits
.balign 4096 .balign 4096
.globl t4_ffc_stpsimd .globl t4_ffc_stpsimd
.type t4_ffc_stpsimd, %function .type t4_ffc_stpsimd, %function
.space 4096 - 4 .space 4096 - 4
t4_ffc_stpsimd: t4_ffc_stpsimd:
adrp x16, dat3 adrp x16, dat3
stp q1,q2, [x3, #0] stp q1,q2, [x3, #0]
mul x3, x16, x16 mul x3, x16, x16
ldr x14, [x16, #8] ldr x14, [x16, #8]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 23BFFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 23BFFC in unpatched output.
// CHECK: t4_ffc_stnp: // CHECK: <t4_ffc_stnp>:
// CHECK-NEXT: 23bffc: 27 01 00 b0 adrp x7, #151552 // CHECK-NEXT: 23bffc: 27 01 00 b0 adrp x7, #151552
// CHECK-NEXT: 23c000: 61 08 00 a8 stnp x1, x2, [x3] // CHECK-NEXT: 23c000: 61 08 00 a8 stnp x1, x2, [x3]
// CHECK-NEXT: 23c004: 1f 20 03 d5 nop // CHECK-NEXT: 23c004: 1f 20 03 d5 nop
// CHECK-FIX: 23c008: 2b 20 00 14 b #32940 // CHECK-FIX: 23c008: 2b 20 00 14 b #32940
// CHECK-NOFIX: 23c008: ea 00 40 f9 ldr x10, [x7] // CHECK-NOFIX: 23c008: ea 00 40 f9 ldr x10, [x7]
// CHECK-NEXT: 23c00c: c0 03 5f d6 ret // CHECK-NEXT: 23c00c: c0 03 5f d6 ret
.section .text.22, "ax", %progbits .section .text.22, "ax", %progbits
.balign 4096 .balign 4096
.globl t4_ffc_stnp .globl t4_ffc_stnp
.type t4_ffc_stnp, %function .type t4_ffc_stnp, %function
.space 4096 - 4 .space 4096 - 4
t4_ffc_stnp: t4_ffc_stnp:
adrp x7, dat1 adrp x7, dat1
stnp x1,x2, [x3, #0] stnp x1,x2, [x3, #0]
nop nop
ldr x10, [x7, :got_lo12:dat1] ldr x10, [x7, :got_lo12:dat1]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 23DFFC in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 23DFFC in unpatched output.
// CHECK: t4_ffc_st1: // CHECK: <t4_ffc_st1>:
// CHECK-NEXT: 23dffc: 18 01 00 f0 adrp x24, #143360 // CHECK-NEXT: 23dffc: 18 01 00 f0 adrp x24, #143360
// CHECK-NEXT: 23e000: 20 80 00 4d st1 { v0.s }[2], [x1] // CHECK-NEXT: 23e000: 20 80 00 4d st1 { v0.s }[2], [x1]
// CHECK-NEXT: 23e004: f6 06 40 f9 ldr x22, [x23, #8] // CHECK-NEXT: 23e004: f6 06 40 f9 ldr x22, [x23, #8]
// CHECK-FIX: 23e008: 2d 18 00 14 b #24756 // CHECK-FIX: 23e008: 2d 18 00 14 b #24756
// CHECK-NOFIX: 23e008: 18 ff 3f f9 str x24, [x24, #32760] // CHECK-NOFIX: 23e008: 18 ff 3f f9 str x24, [x24, #32760]
// CHECK-NEXT: 23e00c: c0 03 5f d6 ret // CHECK-NEXT: 23e00c: c0 03 5f d6 ret
.section .text.23, "ax", %progbits .section .text.23, "ax", %progbits
.balign 4096 .balign 4096
.globl t4_ffc_st1 .globl t4_ffc_st1
.type t4_ffc_st1, %function .type t4_ffc_st1, %function
.space 4096 - 4 .space 4096 - 4
t4_ffc_st1: t4_ffc_st1:
adrp x24, dat2 adrp x24, dat2
st1 { v0.s }[2], [x1] st1 { v0.s }[2], [x1]
ldr x22, [x23, :got_lo12:dat2] ldr x22, [x23, :got_lo12:dat2]
str x24, [x24, #32760] str x24, [x24, #32760]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 23FFF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 23FFF8 in unpatched output.
// CHECK: t3_ff8_ldr_once: // CHECK: <t3_ff8_ldr_once>:
// CHECK-NEXT: 23fff8: 00 01 00 b0 adrp x0, #135168 // CHECK-NEXT: 23fff8: 00 01 00 b0 adrp x0, #135168
// CHECK-NEXT: 23fffc: 20 70 82 4c st1 { v0.16b }, [x1], x2 // CHECK-NEXT: 23fffc: 20 70 82 4c st1 { v0.16b }, [x1], x2
// CHECK-FIX: 240000: 31 10 00 14 b #16580 // CHECK-FIX: 240000: 31 10 00 14 b #16580
// CHECK-NOFIX: 240000: 01 08 40 f9 ldr x1, [x0, #16] // CHECK-NOFIX: 240000: 01 08 40 f9 ldr x1, [x0, #16]
// CHECK-NEXT: 240004: 02 08 40 f9 ldr x2, [x0, #16] // CHECK-NEXT: 240004: 02 08 40 f9 ldr x2, [x0, #16]
// CHECK-NEXT: 240008: c0 03 5f d6 ret // CHECK-NEXT: 240008: c0 03 5f d6 ret
.section .text.24, "ax", %progbits .section .text.24, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ff8_ldr_once .globl t3_ff8_ldr_once
.type t3_ff8_ldr_once, %function .type t3_ff8_ldr_once, %function
.space 4096 - 8 .space 4096 - 8
t3_ff8_ldr_once: t3_ff8_ldr_once:
adrp x0, dat3 adrp x0, dat3
st1 { v0.16b }, [x1], x2 st1 { v0.16b }, [x1], x2
ldr x1, [x0, #16] ldr x1, [x0, #16]
ldr x2, [x0, #16] ldr x2, [x0, #16]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 241FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 241FF8 in unpatched output.
// CHECK: t3_ff8_ldxr: // CHECK: <t3_ff8_ldxr>:
// CHECK-NEXT: 241ff8: e0 00 00 f0 adrp x0, #126976 // CHECK-NEXT: 241ff8: e0 00 00 f0 adrp x0, #126976
// CHECK-NEXT: 241ffc: 03 7c 5f c8 ldxr x3, [x0] // CHECK-NEXT: 241ffc: 03 7c 5f c8 ldxr x3, [x0]
// CHECK-FIX: 242000: 33 08 00 14 b #8396 // CHECK-FIX: 242000: 33 08 00 14 b #8396
// CHECK-NOFIX: 242000: 01 08 40 f9 ldr x1, [x0, #16] // CHECK-NOFIX: 242000: 01 08 40 f9 ldr x1, [x0, #16]
// CHECK: 242004: 02 08 40 f9 ldr x2, [x0, #16] // CHECK: 242004: 02 08 40 f9 ldr x2, [x0, #16]
// CHECK-NEXT: 242008: c0 03 5f d6 ret // CHECK-NEXT: 242008: c0 03 5f d6 ret
.section .text.25, "ax", %progbits .section .text.25, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ff8_ldxr .globl t3_ff8_ldxr
.type t3_ff8_ldxr, %function .type t3_ff8_ldxr, %function
.space 4096 - 8 .space 4096 - 8
t3_ff8_ldxr: t3_ff8_ldxr:
adrp x0, dat3 adrp x0, dat3
ldxr x3, [x0] ldxr x3, [x0]
ldr x1, [x0, #16] ldr x1, [x0, #16]
ldr x2, [x0, #16] ldr x2, [x0, #16]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 243FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 243FF8 in unpatched output.
// CHECK: t3_ff8_stxr: // CHECK: <t3_ff8_stxr>:
// CHECK-NEXT: 243ff8: e0 00 00 b0 adrp x0, #118784 // CHECK-NEXT: 243ff8: e0 00 00 b0 adrp x0, #118784
// CHECK-NEXT: 243ffc: 03 7c 04 c8 stxr w4, x3, [x0] // CHECK-NEXT: 243ffc: 03 7c 04 c8 stxr w4, x3, [x0]
// CHECK-FIX: 244000: 35 00 00 14 b #212 // CHECK-FIX: 244000: 35 00 00 14 b #212
// CHECK-NOFIX: 244000: 01 08 40 f9 ldr x1, [x0, #16] // CHECK-NOFIX: 244000: 01 08 40 f9 ldr x1, [x0, #16]
// CHECK: 244004: 02 08 40 f9 ldr x2, [x0, #16] // CHECK: 244004: 02 08 40 f9 ldr x2, [x0, #16]
// CHECK-NEXT: 244008: c0 03 5f d6 ret // CHECK-NEXT: 244008: c0 03 5f d6 ret
.section .text.26, "ax", %progbits .section .text.26, "ax", %progbits
.balign 4096 .balign 4096
.globl t3_ff8_stxr .globl t3_ff8_stxr
.type t3_ff8_stxr, %function .type t3_ff8_stxr, %function
.space 4096 - 8 .space 4096 - 8
t3_ff8_stxr: t3_ff8_stxr:
adrp x0, dat3 adrp x0, dat3
stxr w4, x3, [x0] stxr w4, x3, [x0]
ldr x1, [x0, #16] ldr x1, [x0, #16]
ldr x2, [x0, #16] ldr x2, [x0, #16]
ret ret
.text .text
.globl _start .globl _start
.type _start, %function .type _start, %function
_start: _start:
ret ret
// CHECK-FIX: __CortexA53843419_212000: // CHECK-FIX: <__CortexA53843419_212000>:
// CHECK-FIX-NEXT: 24400c: 00 00 40 f9 ldr x0, [x0] // CHECK-FIX-NEXT: 24400c: 00 00 40 f9 ldr x0, [x0]
// CHECK-FIX-NEXT: 244010: fd 37 ff 17 b #-204812 // CHECK-FIX-NEXT: 244010: fd 37 ff 17 b #-204812
// CHECK-FIX: __CortexA53843419_214000: // CHECK-FIX: <__CortexA53843419_214000>:
// CHECK-FIX-NEXT: 244014: 02 04 40 f9 ldr x2, [x0, #8] // CHECK-FIX-NEXT: 244014: 02 04 40 f9 ldr x2, [x0, #8]
// CHECK-FIX-NEXT: 244018: fb 3f ff 17 b #-196628 // CHECK-FIX-NEXT: 244018: fb 3f ff 17 b #-196628
// CHECK-FIX: __CortexA53843419_216004: // CHECK-FIX: <__CortexA53843419_216004>:
// CHECK-FIX-NEXT: 24401c: 03 08 40 f9 ldr x3, [x0, #16] // CHECK-FIX-NEXT: 24401c: 03 08 40 f9 ldr x3, [x0, #16]
// CHECK-FIX-NEXT: 244020: fa 47 ff 17 b #-188440 // CHECK-FIX-NEXT: 244020: fa 47 ff 17 b #-188440
// CHECK-FIX: __CortexA53843419_218000: // CHECK-FIX: <__CortexA53843419_218000>:
// CHECK-FIX-NEXT: 244024: 02 0c 40 f9 ldr x2, [x0, #24] // CHECK-FIX-NEXT: 244024: 02 0c 40 f9 ldr x2, [x0, #24]
// CHECK-FIX-NEXT: 244028: f7 4f ff 17 b #-180260 // CHECK-FIX-NEXT: 244028: f7 4f ff 17 b #-180260
// CHECK-FIX: __CortexA53843419_21A004: // CHECK-FIX: <__CortexA53843419_21A004>:
// CHECK-FIX-NEXT: 24402c: 9c 13 00 f9 str x28, [x28, #32] // CHECK-FIX-NEXT: 24402c: 9c 13 00 f9 str x28, [x28, #32]
// CHECK-FIX-NEXT: 244030: f6 57 ff 17 b #-172072 // CHECK-FIX-NEXT: 244030: f6 57 ff 17 b #-172072
// CHECK-FIX: __CortexA53843419_21C004: // CHECK-FIX: <__CortexA53843419_21C004>:
// CHECK-FIX-NEXT: 244034: 84 17 00 f9 str x4, [x28, #40] // CHECK-FIX-NEXT: 244034: 84 17 00 f9 str x4, [x28, #40]
// CHECK-FIX-NEXT: 244038: f4 5f ff 17 b #-163888 // CHECK-FIX-NEXT: 244038: f4 5f ff 17 b #-163888
// CHECK-FIX: __CortexA53843419_21E000: // CHECK-FIX: <__CortexA53843419_21E000>:
// CHECK-FIX-NEXT: 24403c: bd 03 40 f9 ldr x29, [x29] // CHECK-FIX-NEXT: 24403c: bd 03 40 f9 ldr x29, [x29]
// CHECK-FIX-NEXT: 244040: f1 67 ff 17 b #-155708 // CHECK-FIX-NEXT: 244040: f1 67 ff 17 b #-155708
// CHECK-FIX: __CortexA53843419_220004: // CHECK-FIX: <__CortexA53843419_220004>:
// CHECK-FIX-NEXT: 244044: bd 07 40 f9 ldr x29, [x29, #8] // CHECK-FIX-NEXT: 244044: bd 07 40 f9 ldr x29, [x29, #8]
// CHECK-FIX-NEXT: 244048: f0 6f ff 17 b #-147520 // CHECK-FIX-NEXT: 244048: f0 6f ff 17 b #-147520
// CHECK-FIX: __CortexA53843419_222004: // CHECK-FIX: <__CortexA53843419_222004>:
// CHECK-FIX-NEXT: 24404c: 41 0a 40 f9 ldr x1, [x18, #16] // CHECK-FIX-NEXT: 24404c: 41 0a 40 f9 ldr x1, [x18, #16]
// CHECK-FIX-NEXT: 244050: ee 77 ff 17 b #-139336 // CHECK-FIX-NEXT: 244050: ee 77 ff 17 b #-139336
// CHECK-FIX: __CortexA53843419_224000: // CHECK-FIX: <__CortexA53843419_224000>:
// CHECK-FIX-NEXT: 244054: 52 0e 40 f9 ldr x18, [x18, #24] // CHECK-FIX-NEXT: 244054: 52 0e 40 f9 ldr x18, [x18, #24]
// CHECK-FIX-NEXT: 244058: eb 7f ff 17 b #-131156 // CHECK-FIX-NEXT: 244058: eb 7f ff 17 b #-131156
// CHECK-FIX: __CortexA53843419_226004: // CHECK-FIX: <__CortexA53843419_226004>:
// CHECK-FIX-NEXT: 24405c: ea 11 40 f9 ldr x10, [x15, #32] // CHECK-FIX-NEXT: 24405c: ea 11 40 f9 ldr x10, [x15, #32]
// CHECK-FIX-NEXT: 244060: ea 87 ff 17 b #-122968 // CHECK-FIX-NEXT: 244060: ea 87 ff 17 b #-122968
// CHECK-FIX: __CortexA53843419_228000: // CHECK-FIX: <__CortexA53843419_228000>:
// CHECK-FIX-NEXT: 244064: 0d 16 40 f9 ldr x13, [x16, #40] // CHECK-FIX-NEXT: 244064: 0d 16 40 f9 ldr x13, [x16, #40]
// CHECK-FIX-NEXT: 244068: e7 8f ff 17 b #-114788 // CHECK-FIX-NEXT: 244068: e7 8f ff 17 b #-114788
// CHECK-FIX: __CortexA53843419_22A004: // CHECK-FIX: <__CortexA53843419_22A004>:
// CHECK-FIX-NEXT: 24406c: e9 0c 40 f9 ldr x9, [x7, #24] // CHECK-FIX-NEXT: 24406c: e9 0c 40 f9 ldr x9, [x7, #24]
// CHECK-FIX-NEXT: 244070: e6 97 ff 17 b #-106600 // CHECK-FIX-NEXT: 244070: e6 97 ff 17 b #-106600
// CHECK-FIX: __CortexA53843419_22C004: // CHECK-FIX: <__CortexA53843419_22C004>:
// CHECK-FIX-NEXT: 244074: f6 12 40 f9 ldr x22, [x23, #32] // CHECK-FIX-NEXT: 244074: f6 12 40 f9 ldr x22, [x23, #32]
// CHECK-FIX-NEXT: 244078: e4 9f ff 17 b #-98416 // CHECK-FIX-NEXT: 244078: e4 9f ff 17 b #-98416
// CHECK-FIX: __CortexA53843419_22E000: // CHECK-FIX: <__CortexA53843419_22E000>:
// CHECK-FIX-NEXT: 24407c: f8 16 40 f9 ldr x24, [x23, #40] // CHECK-FIX-NEXT: 24407c: f8 16 40 f9 ldr x24, [x23, #40]
// CHECK-FIX-NEXT: 244080: e1 a7 ff 17 b #-90236 // CHECK-FIX-NEXT: 244080: e1 a7 ff 17 b #-90236
// CHECK-FIX: __CortexA53843419_230004: // CHECK-FIX: <__CortexA53843419_230004>:
// CHECK-FIX-NEXT: 244084: 02 00 40 f9 ldr x2, [x0] // CHECK-FIX-NEXT: 244084: 02 00 40 f9 ldr x2, [x0]
// CHECK-FIX-NEXT: 244088: e0 af ff 17 b #-82048 // CHECK-FIX-NEXT: 244088: e0 af ff 17 b #-82048
// CHECK-FIX: __CortexA53843419_232008: // CHECK-FIX: <__CortexA53843419_232008>:
// CHECK-FIX-NEXT: 24408c: 9b 07 00 f9 str x27, [x28, #8] // CHECK-FIX-NEXT: 24408c: 9b 07 00 f9 str x27, [x28, #8]
// CHECK-FIX-NEXT: 244090: df b7 ff 17 b #-73860 // CHECK-FIX-NEXT: 244090: df b7 ff 17 b #-73860
// CHECK-FIX: __CortexA53843419_234004: // CHECK-FIX: <__CortexA53843419_234004>:
// CHECK-FIX-NEXT: 244094: 0e 0a 40 f9 ldr x14, [x16, #16] // CHECK-FIX-NEXT: 244094: 0e 0a 40 f9 ldr x14, [x16, #16]
// CHECK-FIX-NEXT: 244098: dc bf ff 17 b #-65680 // CHECK-FIX-NEXT: 244098: dc bf ff 17 b #-65680
// CHECK-FIX: __CortexA53843419_236004: // CHECK-FIX: <__CortexA53843419_236004>:
// CHECK-FIX-NEXT: 24409c: 0e 06 40 f9 ldr x14, [x16, #8] // CHECK-FIX-NEXT: 24409c: 0e 06 40 f9 ldr x14, [x16, #8]
// CHECK-FIX-NEXT: 2440a0: da c7 ff 17 b #-57496 // CHECK-FIX-NEXT: 2440a0: da c7 ff 17 b #-57496
// CHECK-FIX: __CortexA53843419_238004: // CHECK-FIX: <__CortexA53843419_238004>:
// CHECK-FIX-NEXT: 2440a4: 0e 06 40 f9 ldr x14, [x16, #8] // CHECK-FIX-NEXT: 2440a4: 0e 06 40 f9 ldr x14, [x16, #8]
// CHECK-FIX-NEXT: 2440a8: d8 cf ff 17 b #-49312 // CHECK-FIX-NEXT: 2440a8: d8 cf ff 17 b #-49312
// CHECK-FIX: __CortexA53843419_23A008: // CHECK-FIX: <__CortexA53843419_23A008>:
// CHECK-FIX-NEXT: 2440ac: 0e 06 40 f9 ldr x14, [x16, #8] // CHECK-FIX-NEXT: 2440ac: 0e 06 40 f9 ldr x14, [x16, #8]
// CHECK-FIX-NEXT: 2440b0: d7 d7 ff 17 b #-41124 // CHECK-FIX-NEXT: 2440b0: d7 d7 ff 17 b #-41124
// CHECK-FIX: __CortexA53843419_23C008: // CHECK-FIX: <__CortexA53843419_23C008>:
// CHECK-FIX-NEXT: 2440b4: ea 00 40 f9 ldr x10, [x7] // CHECK-FIX-NEXT: 2440b4: ea 00 40 f9 ldr x10, [x7]
// CHECK-FIX-NEXT: 2440b8: d5 df ff 17 b #-32940 // CHECK-FIX-NEXT: 2440b8: d5 df ff 17 b #-32940
// CHECK-FIX: __CortexA53843419_23E008: // CHECK-FIX: <__CortexA53843419_23E008>:
// CHECK-FIX-NEXT: 2440bc: 18 ff 3f f9 str x24, [x24, #32760] // CHECK-FIX-NEXT: 2440bc: 18 ff 3f f9 str x24, [x24, #32760]
// CHECK-FIX-NEXT: 2440c0: d3 e7 ff 17 b #-24756 // CHECK-FIX-NEXT: 2440c0: d3 e7 ff 17 b #-24756
// CHECK-FIX: __CortexA53843419_240000: // CHECK-FIX: <__CortexA53843419_240000>:
// CHECK-FIX-NEXT: 2440c4: 01 08 40 f9 ldr x1, [x0, #16] // CHECK-FIX-NEXT: 2440c4: 01 08 40 f9 ldr x1, [x0, #16]
// CHECK-FIX-NEXT: 2440c8: cf ef ff 17 b #-16580 // CHECK-FIX-NEXT: 2440c8: cf ef ff 17 b #-16580
// CHECK-FIX: __CortexA53843419_242000: // CHECK-FIX: <__CortexA53843419_242000>:
// CHECK-FIX-NEXT: 2440cc: 01 08 40 f9 ldr x1, [x0, #16] // CHECK-FIX-NEXT: 2440cc: 01 08 40 f9 ldr x1, [x0, #16]
// CHECK-FIX-NEXT: 2440d0: cd f7 ff 17 b #-8396 // CHECK-FIX-NEXT: 2440d0: cd f7 ff 17 b #-8396
// CHECK-FIX: __CortexA53843419_244000: // CHECK-FIX: <__CortexA53843419_244000>:
// CHECK-FIX-NEXT: 2440d4: 01 08 40 f9 ldr x1, [x0, #16] // CHECK-FIX-NEXT: 2440d4: 01 08 40 f9 ldr x1, [x0, #16]
// CHECK-FIX-NEXT: 2440d8: cb ff ff 17 b #-212 // CHECK-FIX-NEXT: 2440d8: cb ff ff 17 b #-212
.data .data
.globl dat .globl dat
.globl dat2 .globl dat2
.globl dat3 .globl dat3
dat1: .quad 1 dat1: .quad 1
dat2: .quad 2 dat2: .quad 2
dat3: .quad 3 dat3: .quad 3

lld/test/ELF/aarch64-cortex-a53-843419-thunk.s

Show All 32 Lines_start:
.type t3_ff8_ldr, %function .type t3_ff8_ldr, %function
t3_ff8_ldr: t3_ff8_ldr:
adrp x0, dat adrp x0, dat
ldr x1, [x1, #0] ldr x1, [x1, #0]
ldr x0, [x0, :got_lo12:dat] ldr x0, [x0, :got_lo12:dat]
ret ret
// CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 10FF8 in unpatched output. // CHECK-PRINT: detected cortex-a53-843419 erratum sequence starting at 10FF8 in unpatched output.
// CHECK: 0000000000010ff8 t3_ff8_ldr: // CHECK: 0000000000010ff8 <t3_ff8_ldr>:
// CHECK-NEXT: adrp x0, #134217728 // CHECK-NEXT: adrp x0, #134217728
// CHECK-NEXT: ldr x1, [x1] // CHECK-NEXT: ldr x1, [x1]
// CHECK-NEXT: b #8 // CHECK-NEXT: b #8
// CHECK-NEXT: ret // CHECK-NEXT: ret
// CHECK: 0000000000011008 __CortexA53843419_11000: // CHECK: 0000000000011008 <__CortexA53843419_11000>:
// CHECK-NEXT: ldr x0, [x0, #8] // CHECK-NEXT: ldr x0, [x0, #8]
// CHECK-NEXT: b #-8 // CHECK-NEXT: b #-8
.section .text.04, "ax", %progbits .section .text.04, "ax", %progbits
.globl far_away .globl far_away
.type far_away, function .type far_away, function
far_away: far_away:
ret ret
.section .data .section .data
.globl dat .globl dat
dat: .quad 0 dat: .quad 0

lld/test/ELF/aarch64-cortex-a53-843419-tlsrelax.s

Show All 17 Lines
_start: _start:
mrs x1, tpidr_el0 mrs x1, tpidr_el0
adrp x0, :gottprel:v adrp x0, :gottprel:v
ldr x1, [x0, #:gottprel_lo12:v] ldr x1, [x0, #:gottprel_lo12:v]
adrp x0, :gottprel:v adrp x0, :gottprel:v
ldr x1, [x0, #:gottprel_lo12:v] ldr x1, [x0, #:gottprel_lo12:v]
ret ret
// CHECK: _start: // CHECK: <_start>:
// CHECK-NEXT: 211ff8: 41 d0 3b d5 mrs x1, TPIDR_EL0 // CHECK-NEXT: 211ff8: 41 d0 3b d5 mrs x1, TPIDR_EL0
// CHECK-NEXT: 211ffc: 00 00 a0 d2 movz x0, #0, lsl #16 // CHECK-NEXT: 211ffc: 00 00 a0 d2 movz x0, #0, lsl #16
// CHECK-NEXT: 212000: 01 02 80 f2 movk x1, #16 // CHECK-NEXT: 212000: 01 02 80 f2 movk x1, #16
// CHECK-NEXT: 212004: 00 00 a0 d2 movz x0, #0, lsl #16 // CHECK-NEXT: 212004: 00 00 a0 d2 movz x0, #0, lsl #16
// CHECK-NEXT: 212008: 01 02 80 f2 movk x1, #16 // CHECK-NEXT: 212008: 01 02 80 f2 movk x1, #16
// CHECK-NEXT: 21200c: c0 03 5f d6 ret // CHECK-NEXT: 21200c: c0 03 5f d6 ret
.type v,@object .type v,@object
.section .tbss,"awT",@nobits .section .tbss,"awT",@nobits
.globl v .globl v
v: v:
.word 0 .word 0

lld/test/ELF/aarch64-feature-bti.s

Show All 10 Lines
# RUN: ld.lld %tno.o %t3.o --shared -o %tno.so # RUN: ld.lld %tno.o %t3.o --shared -o %tno.so
# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tno.so | FileCheck --check-prefix=NOBTI %s # RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tno.so | FileCheck --check-prefix=NOBTI %s
# RUN: llvm-readelf -x .got.plt %tno.so | FileCheck --check-prefix SOGOTPLT %s # RUN: llvm-readelf -x .got.plt %tno.so | FileCheck --check-prefix SOGOTPLT %s
# RUN: llvm-readelf --dynamic-table %tno.so | FileCheck --check-prefix NOBTIDYN %s # RUN: llvm-readelf --dynamic-table %tno.so | FileCheck --check-prefix NOBTIDYN %s
# NOBTIDYN-NOT: 0x0000000070000001 (AARCH64_BTI_PLT) # NOBTIDYN-NOT: 0x0000000070000001 (AARCH64_BTI_PLT)
# NOBTIDYN-NOT: 0x0000000070000003 (AARCH64_PAC_PLT) # NOBTIDYN-NOT: 0x0000000070000003 (AARCH64_PAC_PLT)
# NOBTI: 00000000000102b8 func2: # NOBTI: 00000000000102b8 <func2>:
# NOBTI-NEXT: 102b8: bl #56 <func3@plt> # NOBTI-NEXT: 102b8: bl #56 <func3@plt>
# NOBTI-NEXT: 102bc: ret # NOBTI-NEXT: 102bc: ret
# NOBTI: Disassembly of section .plt: # NOBTI: Disassembly of section .plt:
# NOBTI: 00000000000102d0 .plt: # NOBTI: 00000000000102d0 <.plt>:
# NOBTI-NEXT: 102d0: stp x16, x30, [sp, #-16]! # NOBTI-NEXT: 102d0: stp x16, x30, [sp, #-16]!
# NOBTI-NEXT: 102d4: adrp x16, #131072 # NOBTI-NEXT: 102d4: adrp x16, #131072
# NOBTI-NEXT: 102d8: ldr x17, [x16, #960] # NOBTI-NEXT: 102d8: ldr x17, [x16, #960]
# NOBTI-NEXT: 102dc: add x16, x16, #960 # NOBTI-NEXT: 102dc: add x16, x16, #960
# NOBTI-NEXT: 102e0: br x17 # NOBTI-NEXT: 102e0: br x17
# NOBTI-NEXT: 102e4: nop # NOBTI-NEXT: 102e4: nop
# NOBTI-NEXT: 102e8: nop # NOBTI-NEXT: 102e8: nop
# NOBTI-NEXT: 102ec: nop # NOBTI-NEXT: 102ec: nop
# NOBTI: 00000000000102f0 func3@plt: # NOBTI: 00000000000102f0 <func3@plt>:
# NOBTI-NEXT: 102f0: adrp x16, #131072 # NOBTI-NEXT: 102f0: adrp x16, #131072
# NOBTI-NEXT: 102f4: ldr x17, [x16, #968] # NOBTI-NEXT: 102f4: ldr x17, [x16, #968]
# NOBTI-NEXT: 102f8: add x16, x16, #968 # NOBTI-NEXT: 102f8: add x16, x16, #968
# NOBTI-NEXT: 102fc: br x17 # NOBTI-NEXT: 102fc: br x17
## The .got.plt should be identical between the BTI and no BTI DSO PLT. ## The .got.plt should be identical between the BTI and no BTI DSO PLT.
# SOGOTPLT: Hex dump of section '.got.plt' # SOGOTPLT: Hex dump of section '.got.plt'
# SOGOTPLT-NEXT: 0x000303b0 00000000 00000000 00000000 00000000 # SOGOTPLT-NEXT: 0x000303b0 00000000 00000000 00000000 00000000
Show All 9 Lines
# RUN: llvm-readelf -x .got.plt %t.so | FileCheck --check-prefix SOGOTPLT2 %s # RUN: llvm-readelf -x .got.plt %t.so | FileCheck --check-prefix SOGOTPLT2 %s
# RUN: llvm-readelf --dynamic-table %t.so | FileCheck --check-prefix BTIDYN %s # RUN: llvm-readelf --dynamic-table %t.so | FileCheck --check-prefix BTIDYN %s
# BTIPROP: Properties: aarch64 feature: BTI # BTIPROP: Properties: aarch64 feature: BTI
# BTIDYN: 0x0000000070000001 (AARCH64_BTI_PLT) # BTIDYN: 0x0000000070000001 (AARCH64_BTI_PLT)
# BTIDYN-NOT: 0x0000000070000003 (AARCH64_PAC_PLT) # BTIDYN-NOT: 0x0000000070000003 (AARCH64_PAC_PLT)
# BTISO: 0000000000010348 func2: # BTISO: 0000000000010348 <func2>:
# BTISO-NEXT: 10348: bl #56 <func3@plt> # BTISO-NEXT: 10348: bl #56 <func3@plt>
# BTISO-NEXT: ret # BTISO-NEXT: ret
# BTISO: 0000000000010350 func3: # BTISO: 0000000000010350 <func3>:
# BTISO-NEXT: 10350: ret # BTISO-NEXT: 10350: ret
# BTISO: Disassembly of section .plt: # BTISO: Disassembly of section .plt:
# BTISO: 0000000000010360 .plt: # BTISO: 0000000000010360 <.plt>:
# BTISO-NEXT: 10360: bti c # BTISO-NEXT: 10360: bti c
# BTISO-NEXT: stp x16, x30, [sp, #-16]! # BTISO-NEXT: stp x16, x30, [sp, #-16]!
# BTISO-NEXT: adrp x16, #131072 # BTISO-NEXT: adrp x16, #131072
# BTISO-NEXT: ldr x17, [x16, #1136] # BTISO-NEXT: ldr x17, [x16, #1136]
# BTISO-NEXT: add x16, x16, #1136 # BTISO-NEXT: add x16, x16, #1136
# BTISO-NEXT: br x17 # BTISO-NEXT: br x17
# BTISO-NEXT: nop # BTISO-NEXT: nop
# BTISO-NEXT: nop # BTISO-NEXT: nop
# BTISO: 0000000000010380 func3@plt: # BTISO: 0000000000010380 <func3@plt>:
# BTISO-NEXT: 10380: adrp x16, #131072 # BTISO-NEXT: 10380: adrp x16, #131072
# BTISO-NEXT: ldr x17, [x16, #1144] # BTISO-NEXT: ldr x17, [x16, #1144]
# BTISO-NEXT: add x16, x16, #1144 # BTISO-NEXT: add x16, x16, #1144
# BTISO-NEXT: br x17 # BTISO-NEXT: br x17
# SOGOTPLT2: Hex dump of section '.got.plt' # SOGOTPLT2: Hex dump of section '.got.plt'
# SOGOTPLT2-NEXT: 0x00030460 00000000 00000000 00000000 00000000 # SOGOTPLT2-NEXT: 0x00030460 00000000 00000000 00000000 00000000
# SOGOTPLT2-NEXT: 0x00030470 00000000 00000000 60030100 00000000 # SOGOTPLT2-NEXT: 0x00030470 00000000 00000000 60030100 00000000
## Build an executable with all relocatable inputs having the BTI ## Build an executable with all relocatable inputs having the BTI
## .note.gnu.property. We expect a bti c in front of all PLT entries as the ## .note.gnu.property. We expect a bti c in front of all PLT entries as the
## address of a PLT entry can escape an executable. ## address of a PLT entry can escape an executable.
# RUN: ld.lld %t2.o --shared --soname=t2.so -o %t2.so # RUN: ld.lld %t2.o --shared --soname=t2.so -o %t2.so
# RUN: ld.lld %t.o %t.so %t2.so -o %t.exe # RUN: ld.lld %t.o %t.so %t2.so -o %t.exe
# RUN: llvm-readelf --dynamic-table -n %t.exe | FileCheck --check-prefix=BTIPROP %s # RUN: llvm-readelf --dynamic-table -n %t.exe | FileCheck --check-prefix=BTIPROP %s
# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %t.exe | FileCheck --check-prefix=EXECBTI %s # RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %t.exe | FileCheck --check-prefix=EXECBTI %s
# EXECBTI: Disassembly of section .text: # EXECBTI: Disassembly of section .text:
# EXECBTI: 0000000000210348 func1: # EXECBTI: 0000000000210348 <func1>:
# EXECBTI-NEXT: 210348: bl #40 <func2@plt> # EXECBTI-NEXT: 210348: bl #40 <func2@plt>
# EXECBTI-NEXT: ret # EXECBTI-NEXT: ret
# EXECBTI: Disassembly of section .plt: # EXECBTI: Disassembly of section .plt:
# EXECBTI: 0000000000210350 .plt: # EXECBTI: 0000000000210350 <.plt>:
# EXECBTI-NEXT: 210350: bti c # EXECBTI-NEXT: 210350: bti c
# EXECBTI-NEXT: stp x16, x30, [sp, #-16]! # EXECBTI-NEXT: stp x16, x30, [sp, #-16]!
# EXECBTI-NEXT: adrp x16, #131072 # EXECBTI-NEXT: adrp x16, #131072
# EXECBTI-NEXT: ldr x17, [x16, #1160] # EXECBTI-NEXT: ldr x17, [x16, #1160]
# EXECBTI-NEXT: add x16, x16, #1160 # EXECBTI-NEXT: add x16, x16, #1160
# EXECBTI-NEXT: br x17 # EXECBTI-NEXT: br x17
# EXECBTI-NEXT: nop # EXECBTI-NEXT: nop
# EXECBTI-NEXT: nop # EXECBTI-NEXT: nop
# EXECBTI: 0000000000210370 func2@plt: # EXECBTI: 0000000000210370 <func2@plt>:
# EXECBTI-NEXT: 210370: bti c # EXECBTI-NEXT: 210370: bti c
# EXECBTI-NEXT: adrp x16, #131072 # EXECBTI-NEXT: adrp x16, #131072
# EXECBTI-NEXT: ldr x17, [x16, #1168] # EXECBTI-NEXT: ldr x17, [x16, #1168]
# EXECBTI-NEXT: add x16, x16, #1168 # EXECBTI-NEXT: add x16, x16, #1168
# EXECBTI-NEXT: br x17 # EXECBTI-NEXT: br x17
# EXECBTI-NEXT: nop # EXECBTI-NEXT: nop
## We expect the same for PIE, as the address of an ifunc can escape ## We expect the same for PIE, as the address of an ifunc can escape
# RUN: ld.lld --pie %t.o %t.so %t2.so -o %tpie.exe # RUN: ld.lld --pie %t.o %t.so %t2.so -o %tpie.exe
# RUN: llvm-readelf -n %tpie.exe | FileCheck --check-prefix=BTIPROP %s # RUN: llvm-readelf -n %tpie.exe | FileCheck --check-prefix=BTIPROP %s
# RUN: llvm-readelf --dynamic-table -n %tpie.exe | FileCheck --check-prefix=BTIPROP %s # RUN: llvm-readelf --dynamic-table -n %tpie.exe | FileCheck --check-prefix=BTIPROP %s
# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tpie.exe | FileCheck --check-prefix=PIE %s # RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tpie.exe | FileCheck --check-prefix=PIE %s
# PIE: Disassembly of section .text: # PIE: Disassembly of section .text:
# PIE: 0000000000010348 func1: # PIE: 0000000000010348 <func1>:
# PIE-NEXT: 10348: bl #40 <func2@plt> # PIE-NEXT: 10348: bl #40 <func2@plt>
# PIE-NEXT: ret # PIE-NEXT: ret
# PIE: Disassembly of section .plt: # PIE: Disassembly of section .plt:
# PIE: 0000000000010350 .plt: # PIE: 0000000000010350 <.plt>:
# PIE-NEXT: 10350: bti c # PIE-NEXT: 10350: bti c
# PIE-NEXT: stp x16, x30, [sp, #-16]! # PIE-NEXT: stp x16, x30, [sp, #-16]!
# PIE-NEXT: adrp x16, #131072 # PIE-NEXT: adrp x16, #131072
# PIE-NEXT: ldr x17, [x16, #1160] # PIE-NEXT: ldr x17, [x16, #1160]
# PIE-NEXT: add x16, x16, #1160 # PIE-NEXT: add x16, x16, #1160
# PIE-NEXT: br x17 # PIE-NEXT: br x17
# PIE-NEXT: nop # PIE-NEXT: nop
# PIE-NEXT: nop # PIE-NEXT: nop
# PIE: 0000000000010370 func2@plt: # PIE: 0000000000010370 <func2@plt>:
# PIE-NEXT: 10370: bti c # PIE-NEXT: 10370: bti c
# PIE-NEXT: adrp x16, #131072 # PIE-NEXT: adrp x16, #131072
# PIE-NEXT: ldr x17, [x16, #1168] # PIE-NEXT: ldr x17, [x16, #1168]
# PIE-NEXT: add x16, x16, #1168 # PIE-NEXT: add x16, x16, #1168
# PIE-NEXT: br x17 # PIE-NEXT: br x17
# PIE-NEXT: nop # PIE-NEXT: nop
## Build and executable with not all relocatable inputs having the BTI ## Build and executable with not all relocatable inputs having the BTI
## .note.property, expect no bti c and no .note.gnu.property entry ## .note.property, expect no bti c and no .note.gnu.property entry
# RUN: ld.lld %t.o %t2.o %t.so -o %tnobti.exe # RUN: ld.lld %t.o %t2.o %t.so -o %tnobti.exe
# RUN: llvm-readelf --dynamic-table %tnobti.exe | FileCheck --check-prefix NOBTIDYN %s # RUN: llvm-readelf --dynamic-table %tnobti.exe | FileCheck --check-prefix NOBTIDYN %s
# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tnobti.exe | FileCheck --check-prefix=NOEX %s # RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tnobti.exe | FileCheck --check-prefix=NOEX %s
# NOEX: Disassembly of section .text: # NOEX: Disassembly of section .text:
# NOEX: 00000000002102e0 func1: # NOEX: 00000000002102e0 <func1>:
# NOEX-NEXT: 2102e0: bl #48 <func2@plt> # NOEX-NEXT: 2102e0: bl #48 <func2@plt>
# NOEX-NEXT: ret # NOEX-NEXT: ret
# NOEX: 00000000002102e8 func3: # NOEX: 00000000002102e8 <func3>:
# NOEX-NEXT: 2102e8: ret # NOEX-NEXT: 2102e8: ret
# NOEX: Disassembly of section .plt: # NOEX: Disassembly of section .plt:
# NOEX: 00000000002102f0 .plt: # NOEX: 00000000002102f0 <.plt>:
# NOEX-NEXT: 2102f0: stp x16, x30, [sp, #-16]! # NOEX-NEXT: 2102f0: stp x16, x30, [sp, #-16]!
# NOEX-NEXT: adrp x16, #131072 # NOEX-NEXT: adrp x16, #131072
# NOEX-NEXT: ldr x17, [x16, #1024] # NOEX-NEXT: ldr x17, [x16, #1024]
# NOEX-NEXT: add x16, x16, #1024 # NOEX-NEXT: add x16, x16, #1024
# NOEX-NEXT: br x17 # NOEX-NEXT: br x17
# NOEX-NEXT: nop # NOEX-NEXT: nop
# NOEX-NEXT: nop # NOEX-NEXT: nop
# NOEX-NEXT: nop # NOEX-NEXT: nop
# NOEX: 0000000000210310 func2@plt: # NOEX: 0000000000210310 <func2@plt>:
# NOEX-NEXT: 210310: adrp x16, #131072 # NOEX-NEXT: 210310: adrp x16, #131072
# NOEX-NEXT: ldr x17, [x16, #1032] # NOEX-NEXT: ldr x17, [x16, #1032]
# NOEX-NEXT: add x16, x16, #1032 # NOEX-NEXT: add x16, x16, #1032
# NOEX-NEXT: br x17 # NOEX-NEXT: br x17
## Force BTI entries with the -z force-bti command line option. Expect a warning ## Force BTI entries with the -z force-bti command line option. Expect a warning
## from the file without the .note.gnu.property. ## from the file without the .note.gnu.property.
# RUN: ld.lld %t.o %t2.o -z force-bti %t.so -o %tforcebti.exe 2>&1 | FileCheck --check-prefix=FORCE-WARN %s # RUN: ld.lld %t.o %t2.o -z force-bti %t.so -o %tforcebti.exe 2>&1 | FileCheck --check-prefix=FORCE-WARN %s
# FORCE-WARN: aarch64-feature-bti.s.tmp2.o: -z force-bti: file does not have GNU_PROPERTY_AARCH64_FEATURE_1_BTI property # FORCE-WARN: aarch64-feature-bti.s.tmp2.o: -z force-bti: file does not have GNU_PROPERTY_AARCH64_FEATURE_1_BTI property
# RUN: llvm-readelf -n %tforcebti.exe | FileCheck --check-prefix=BTIPROP %s # RUN: llvm-readelf -n %tforcebti.exe | FileCheck --check-prefix=BTIPROP %s
# RUN: llvm-readelf --dynamic-table %tforcebti.exe | FileCheck --check-prefix BTIDYN %s # RUN: llvm-readelf --dynamic-table %tforcebti.exe | FileCheck --check-prefix BTIDYN %s
# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tforcebti.exe | FileCheck --check-prefix=FORCE %s # RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tforcebti.exe | FileCheck --check-prefix=FORCE %s
# FORCE: Disassembly of section .text: # FORCE: Disassembly of section .text:
# FORCE: 0000000000210370 func1: # FORCE: 0000000000210370 <func1>:
# FORCE-NEXT: 210370: bl #48 <func2@plt> # FORCE-NEXT: 210370: bl #48 <func2@plt>
# FORCE-NEXT: ret # FORCE-NEXT: ret
# FORCE: 0000000000210378 func3: # FORCE: 0000000000210378 <func3>:
# FORCE-NEXT: 210378: ret # FORCE-NEXT: 210378: ret
# FORCE: Disassembly of section .plt: # FORCE: Disassembly of section .plt:
# FORCE: 0000000000210380 .plt: # FORCE: 0000000000210380 <.plt>:
# FORCE-NEXT: 210380: bti c # FORCE-NEXT: 210380: bti c
# FORCE-NEXT: stp x16, x30, [sp, #-16]! # FORCE-NEXT: stp x16, x30, [sp, #-16]!
# FORCE-NEXT: adrp x16, #131072 # FORCE-NEXT: adrp x16, #131072
# FORCE-NEXT: ldr x17, [x16, #1192] # FORCE-NEXT: ldr x17, [x16, #1192]
# FORCE-NEXT: add x16, x16, #1192 # FORCE-NEXT: add x16, x16, #1192
# FORCE-NEXT: br x17 # FORCE-NEXT: br x17
# FORCE-NEXT: nop # FORCE-NEXT: nop
# FORCE-NEXT: nop # FORCE-NEXT: nop
# FORCE: 00000000002103a0 func2@plt: # FORCE: 00000000002103a0 <func2@plt>:
# FORCE-NEXT: 2103a0: bti c # FORCE-NEXT: 2103a0: bti c
# FORCE-NEXT: adrp x16, #131072 # FORCE-NEXT: adrp x16, #131072
# FORCE-NEXT: ldr x17, [x16, #1200] # FORCE-NEXT: ldr x17, [x16, #1200]
# FORCE-NEXT: add x16, x16, #1200 # FORCE-NEXT: add x16, x16, #1200
# FORCE-NEXT: br x17 # FORCE-NEXT: br x17
# FORCE-NEXT: nop # FORCE-NEXT: nop
.section ".note.gnu.property", "a" .section ".note.gnu.property", "a"
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lld/test/ELF/aarch64-feature-btipac.s

Show All 9 Lines
## PLT[n] has autia1716 before br x17 ## PLT[n] has autia1716 before br x17
# RUN: ld.lld %t1.o %t3btipac.o --shared --soname=t.so -o %t.so # RUN: ld.lld %t1.o %t3btipac.o --shared --soname=t.so -o %t.so
# RUN: llvm-readelf -n %t.so | FileCheck --check-prefix BTIPACPROP %s # RUN: llvm-readelf -n %t.so | FileCheck --check-prefix BTIPACPROP %s
# RUN: llvm-objdump -d -mattr=+v8.5a --no-show-raw-insn %t.so | FileCheck --check-prefix BTIPACSO %s # RUN: llvm-objdump -d -mattr=+v8.5a --no-show-raw-insn %t.so | FileCheck --check-prefix BTIPACSO %s
# RUN: llvm-readelf --dynamic-table %t.so | FileCheck --check-prefix BTIPACDYN %s # RUN: llvm-readelf --dynamic-table %t.so | FileCheck --check-prefix BTIPACDYN %s
# BTIPACSO: Disassembly of section .text: # BTIPACSO: Disassembly of section .text:
# BTIPACSO: 0000000000010348 func2: # BTIPACSO: 0000000000010348 <func2>:
# BTIPACSO-NEXT: 10348: bl #56 <func3@plt> # BTIPACSO-NEXT: 10348: bl #56 <func3@plt>
# BTIPACSO-NEXT: ret # BTIPACSO-NEXT: ret
# BTIPACSO: 0000000000010350 func3: # BTIPACSO: 0000000000010350 <func3>:
# BTIPACSO-NEXT: 10350: ret # BTIPACSO-NEXT: 10350: ret
# BTIPACSO: Disassembly of section .plt: # BTIPACSO: Disassembly of section .plt:
# BTIPACSO: 0000000000010360 .plt: # BTIPACSO: 0000000000010360 <.plt>:
# BTIPACSO-NEXT: 10360: bti c # BTIPACSO-NEXT: 10360: bti c
# BTIPACSO-NEXT: stp x16, x30, [sp, #-16]! # BTIPACSO-NEXT: stp x16, x30, [sp, #-16]!
# BTIPACSO-NEXT: adrp x16, #131072 # BTIPACSO-NEXT: adrp x16, #131072
# BTIPACSO-NEXT: ldr x17, [x16, #1136] # BTIPACSO-NEXT: ldr x17, [x16, #1136]
# BTIPACSO-NEXT: add x16, x16, #1136 # BTIPACSO-NEXT: add x16, x16, #1136
# BTIPACSO-NEXT: br x17 # BTIPACSO-NEXT: br x17
# BTIPACSO-NEXT: nop # BTIPACSO-NEXT: nop
# BTIPACSO-NEXT: nop # BTIPACSO-NEXT: nop
# BTIPACSO: 0000000000010380 func3@plt: # BTIPACSO: 0000000000010380 <func3@plt>:
# BTIPACSO-NEXT: 10380: adrp x16, #131072 # BTIPACSO-NEXT: 10380: adrp x16, #131072
# BTIPACSO-NEXT: ldr x17, [x16, #1144] # BTIPACSO-NEXT: ldr x17, [x16, #1144]
# BTIPACSO-NEXT: add x16, x16, #1144 # BTIPACSO-NEXT: add x16, x16, #1144
# BTIPACSO-NEXT: br x17 # BTIPACSO-NEXT: br x17
# BTIPACPROP: Properties: aarch64 feature: BTI, PAC # BTIPACPROP: Properties: aarch64 feature: BTI, PAC
# BTIPACDYN: 0x0000000070000001 (AARCH64_BTI_PLT) # BTIPACDYN: 0x0000000070000001 (AARCH64_BTI_PLT)
# BTIPACDYN-NOT: 0x0000000070000003 (AARCH64_PAC_PLT) # BTIPACDYN-NOT: 0x0000000070000003 (AARCH64_PAC_PLT)
## Make an executable with both BTI and PAC properties. Expect: ## Make an executable with both BTI and PAC properties. Expect:
## PLT[0] bti c as first instruction ## PLT[0] bti c as first instruction
## PLT[n] bti n as first instruction ## PLT[n] bti n as first instruction
# RUN: ld.lld %t.o %t3btipac.o %t.so -o %t.exe # RUN: ld.lld %t.o %t3btipac.o %t.so -o %t.exe
# RUN: llvm-readelf -n %t.exe | FileCheck --check-prefix=BTIPACPROP %s # RUN: llvm-readelf -n %t.exe | FileCheck --check-prefix=BTIPACPROP %s
# RUN: llvm-objdump -d -mattr=+v8.5a --no-show-raw-insn %t.exe | FileCheck --check-prefix BTIPACEX %s # RUN: llvm-objdump -d -mattr=+v8.5a --no-show-raw-insn %t.exe | FileCheck --check-prefix BTIPACEX %s
# RUN: llvm-readelf --dynamic-table %t.exe | FileCheck --check-prefix BTIPACDYNEX %s # RUN: llvm-readelf --dynamic-table %t.exe | FileCheck --check-prefix BTIPACDYNEX %s
# BTIPACEX: Disassembly of section .text: # BTIPACEX: Disassembly of section .text:
# BTIPACEX: 0000000000210370 func1: # BTIPACEX: 0000000000210370 <func1>:
# BTIPACEX-NEXT: 210370: bl #48 <func2@plt> # BTIPACEX-NEXT: 210370: bl #48 <func2@plt>
# BTIPACEX-NEXT: ret # BTIPACEX-NEXT: ret
# BTIPACEX-NEXT: ret # BTIPACEX-NEXT: ret
# BTIPACEX: 000000000021037c func3: # BTIPACEX: 000000000021037c <func3>:
# BTIPACEX-NEXT: 21037c: ret # BTIPACEX-NEXT: 21037c: ret
# BTIPACEX: Disassembly of section .plt: # BTIPACEX: Disassembly of section .plt:
# BTIPACEX: 0000000000210380 .plt: # BTIPACEX: 0000000000210380 <.plt>:
# BTIPACEX-NEXT: 210380: bti c # BTIPACEX-NEXT: 210380: bti c
# BTIPACEX-NEXT: stp x16, x30, [sp, #-16]! # BTIPACEX-NEXT: stp x16, x30, [sp, #-16]!
# BTIPACEX-NEXT: adrp x16, #131072 # BTIPACEX-NEXT: adrp x16, #131072
# BTIPACEX-NEXT: ldr x17, [x16, #1192] # BTIPACEX-NEXT: ldr x17, [x16, #1192]
# BTIPACEX-NEXT: add x16, x16, #1192 # BTIPACEX-NEXT: add x16, x16, #1192
# BTIPACEX-NEXT: br x17 # BTIPACEX-NEXT: br x17
# BTIPACEX-NEXT: nop # BTIPACEX-NEXT: nop
# BTIPACEX-NEXT: nop # BTIPACEX-NEXT: nop
# BTIPACEX: 00000000002103a0 func2@plt: # BTIPACEX: 00000000002103a0 <func2@plt>:
# BTIPACEX-NEXT: 2103a0: bti c # BTIPACEX-NEXT: 2103a0: bti c
# BTIPACEX-NEXT: adrp x16, #131072 # BTIPACEX-NEXT: adrp x16, #131072
# BTIPACEX-NEXT: ldr x17, [x16, #1200] # BTIPACEX-NEXT: ldr x17, [x16, #1200]
# BTIPACEX-NEXT: add x16, x16, #1200 # BTIPACEX-NEXT: add x16, x16, #1200
# BTIPACEX-NEXT: br x17 # BTIPACEX-NEXT: br x17
# BTIPACDYNEX: 0x0000000070000001 (AARCH64_BTI_PLT) # BTIPACDYNEX: 0x0000000070000001 (AARCH64_BTI_PLT)
# BTIPACDYNEX-NOT: 0x0000000070000003 (AARCH64_PAC_PLT) # BTIPACDYNEX-NOT: 0x0000000070000003 (AARCH64_PAC_PLT)
## Check that combinations of BTI+PAC with 0 properties results in standard PLT ## Check that combinations of BTI+PAC with 0 properties results in standard PLT
# RUN: ld.lld %t.o %t3.o %t.so -o %t.exe # RUN: ld.lld %t.o %t3.o %t.so -o %t.exe
# RUN: llvm-objdump -d -mattr=+v8.5a --no-show-raw-insn %t.exe | FileCheck --check-prefix EX %s # RUN: llvm-objdump -d -mattr=+v8.5a --no-show-raw-insn %t.exe | FileCheck --check-prefix EX %s
# RUN: llvm-readelf --dynamic-table %t.exe | FileCheck --check-prefix=NODYN %s # RUN: llvm-readelf --dynamic-table %t.exe | FileCheck --check-prefix=NODYN %s
# EX: Disassembly of section .text: # EX: Disassembly of section .text:
# EX: 00000000002102e0 func1: # EX: 00000000002102e0 <func1>:
# EX-NEXT: 2102e0: bl #48 <func2@plt> # EX-NEXT: 2102e0: bl #48 <func2@plt>
# EX-NEXT: ret # EX-NEXT: ret
# EX-NEXT: ret # EX-NEXT: ret
# EX: 00000000002102ec func3: # EX: 00000000002102ec <func3>:
# EX-NEXT: 2102ec: ret # EX-NEXT: 2102ec: ret
# EX: Disassembly of section .plt: # EX: Disassembly of section .plt:
# EX: 00000000002102f0 .plt: # EX: 00000000002102f0 <.plt>:
# EX-NEXT: 2102f0: stp x16, x30, [sp, #-16]! # EX-NEXT: 2102f0: stp x16, x30, [sp, #-16]!
# EX-NEXT: adrp x16, #131072 # EX-NEXT: adrp x16, #131072
# EX-NEXT: ldr x17, [x16, #1024] # EX-NEXT: ldr x17, [x16, #1024]
# EX-NEXT: add x16, x16, #1024 # EX-NEXT: add x16, x16, #1024
# EX-NEXT: br x17 # EX-NEXT: br x17
# EX-NEXT: nop # EX-NEXT: nop
# EX-NEXT: nop # EX-NEXT: nop
# EX-NEXT: nop # EX-NEXT: nop
# EX: 0000000000210310 func2@plt: # EX: 0000000000210310 <func2@plt>:
# EX: 210310: adrp x16, #131072 # EX: 210310: adrp x16, #131072
# EX-NEXT: ldr x17, [x16, #1032] # EX-NEXT: ldr x17, [x16, #1032]
# EX-NEXT: add x16, x16, #1032 # EX-NEXT: add x16, x16, #1032
# EX-NEXT: br x17 # EX-NEXT: br x17
# NODYN-NOT: 0x0000000070000001 (AARCH64_BTI_PLT) # NODYN-NOT: 0x0000000070000001 (AARCH64_BTI_PLT)
# NODYN-NOT: 0x0000000070000003 (AARCH64_PAC_PLT) # NODYN-NOT: 0x0000000070000003 (AARCH64_PAC_PLT)
Show All 28 Lines
func1: func1:
bl func2 bl func2
ret ret
.globl func3 .globl func3
.type func3,%function .type func3,%function
ret ret
# BTIPACEX2: Disassembly of section .text: # BTIPACEX2: Disassembly of section .text:
# BTIPACEX2: 0000000000210370 func1: # BTIPACEX2: 0000000000210370 <func1>:
# BTIPACEX2-NEXT: 210370: bl #48 <func2@plt> # BTIPACEX2-NEXT: 210370: bl #48 <func2@plt>
# BTIPACEX2-NEXT: ret # BTIPACEX2-NEXT: ret
# BTIPACEX2-NEXT: ret # BTIPACEX2-NEXT: ret
# BTIPACEX2: 000000000021037c func3: # BTIPACEX2: 000000000021037c <func3>:
# BTIPACEX2-NEXT: 21037c: ret # BTIPACEX2-NEXT: 21037c: ret
# BTIPACEX2: Disassembly of section .plt: # BTIPACEX2: Disassembly of section .plt:
# BTIPACEX2: 0000000000210380 .plt: # BTIPACEX2: 0000000000210380 <.plt>:
# BTIPACEX2-NEXT: 210380: bti c # BTIPACEX2-NEXT: 210380: bti c
# BTIPACEX2-NEXT: stp x16, x30, [sp, #-16]! # BTIPACEX2-NEXT: stp x16, x30, [sp, #-16]!
# BTIPACEX2-NEXT: adrp x16, #131072 # BTIPACEX2-NEXT: adrp x16, #131072
# BTIPACEX2-NEXT: ldr x17, [x16, #1208] # BTIPACEX2-NEXT: ldr x17, [x16, #1208]
# BTIPACEX2-NEXT: add x16, x16, #1208 # BTIPACEX2-NEXT: add x16, x16, #1208
# BTIPACEX2-NEXT: br x17 # BTIPACEX2-NEXT: br x17
# BTIPACEX2-NEXT: nop # BTIPACEX2-NEXT: nop
# BTIPACEX2-NEXT: nop # BTIPACEX2-NEXT: nop
# BTIPACEX2: 00000000002103a0 func2@plt: # BTIPACEX2: 00000000002103a0 <func2@plt>:
# BTIPACEX2-NEXT: 2103a0: bti c # BTIPACEX2-NEXT: 2103a0: bti c
# BTIPACEX2-NEXT: adrp x16, #131072 # BTIPACEX2-NEXT: adrp x16, #131072
# BTIPACEX2-NEXT: ldr x17, [x16, #1216] # BTIPACEX2-NEXT: ldr x17, [x16, #1216]
# BTIPACEX2-NEXT: add x16, x16, #1216 # BTIPACEX2-NEXT: add x16, x16, #1216
# BTIPACEX2-NEXT: autia1716 # BTIPACEX2-NEXT: autia1716
# BTIPACEX2-NEXT: br x17 # BTIPACEX2-NEXT: br x17
# BTIPACDYN2: 0x0000000070000001 (AARCH64_BTI_PLT) # BTIPACDYN2: 0x0000000070000001 (AARCH64_BTI_PLT)
# BTIPACDYN2-NEXT: 0x0000000070000003 (AARCH64_PAC_PLT) # BTIPACDYN2-NEXT: 0x0000000070000003 (AARCH64_PAC_PLT)
No newline at end of file No newline at end of file

lld/test/ELF/aarch64-feature-pac.s

# REQUIRES: aarch64 # REQUIRES: aarch64
# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %s -o %t.o
# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %p/Inputs/aarch64-pac1.s -o %t1.o # RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %p/Inputs/aarch64-pac1.s -o %t1.o
# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %p/Inputs/aarch64-func3.s -o %t2.o # RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %p/Inputs/aarch64-func3.s -o %t2.o
# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %p/Inputs/aarch64-func3-pac.s -o %t3.o # RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %p/Inputs/aarch64-func3-pac.s -o %t3.o
# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %p/Inputs/aarch64-func2.s -o %tno.o # RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %p/Inputs/aarch64-func2.s -o %tno.o
## We do not add PAC support when the inputs don't have the .note.gnu.property ## We do not add PAC support when the inputs don't have the .note.gnu.property
## field. ## field.
# RUN: ld.lld %tno.o %t3.o --shared -o %tno.so # RUN: ld.lld %tno.o %t3.o --shared -o %tno.so
# RUN: llvm-objdump -d -mattr=+v8.3a --no-show-raw-insn %tno.so | FileCheck --check-prefix=NOPAC %s # RUN: llvm-objdump -d -mattr=+v8.3a --no-show-raw-insn %tno.so | FileCheck --check-prefix=NOPAC %s
# RUN: llvm-readelf -x .got.plt %tno.so | FileCheck --check-prefix SOGOTPLT %s # RUN: llvm-readelf -x .got.plt %tno.so | FileCheck --check-prefix SOGOTPLT %s
# RUN: llvm-readelf --dynamic-table %tno.so | FileCheck --check-prefix NOPACDYN %s # RUN: llvm-readelf --dynamic-table %tno.so | FileCheck --check-prefix NOPACDYN %s
# NOPAC: 00000000000102b8 func2: # NOPAC: 00000000000102b8 <func2>:
# NOPAC-NEXT: 102b8: bl #56 <func3@plt> # NOPAC-NEXT: 102b8: bl #56 <func3@plt>
# NOPAC-NEXT: ret # NOPAC-NEXT: ret
# NOPAC: Disassembly of section .plt: # NOPAC: Disassembly of section .plt:
# NOPAC: 00000000000102d0 .plt: # NOPAC: 00000000000102d0 <.plt>:
# NOPAC-NEXT: 102d0: stp x16, x30, [sp, #-16]! # NOPAC-NEXT: 102d0: stp x16, x30, [sp, #-16]!
# NOPAC-NEXT: adrp x16, #131072 # NOPAC-NEXT: adrp x16, #131072
# NOPAC-NEXT: ldr x17, [x16, #960] # NOPAC-NEXT: ldr x17, [x16, #960]
# NOPAC-NEXT: add x16, x16, #960 # NOPAC-NEXT: add x16, x16, #960
# NOPAC-NEXT: br x17 # NOPAC-NEXT: br x17
# NOPAC-NEXT: nop # NOPAC-NEXT: nop
# NOPAC-NEXT: nop # NOPAC-NEXT: nop
# NOPAC-NEXT: nop # NOPAC-NEXT: nop
# NOPAC: 00000000000102f0 func3@plt: # NOPAC: 00000000000102f0 <func3@plt>:
# NOPAC-NEXT: 102f0: adrp x16, #131072 # NOPAC-NEXT: 102f0: adrp x16, #131072
# NOPAC-NEXT: ldr x17, [x16, #968] # NOPAC-NEXT: ldr x17, [x16, #968]
# NOPAC-NEXT: add x16, x16, #968 # NOPAC-NEXT: add x16, x16, #968
# NOPAC-NEXT: br x17 # NOPAC-NEXT: br x17
# SOGOTPLT: Hex dump of section '.got.plt': # SOGOTPLT: Hex dump of section '.got.plt':
# SOGOTPLT-NEXT: 0x000303b0 00000000 00000000 00000000 00000000 # SOGOTPLT-NEXT: 0x000303b0 00000000 00000000 00000000 00000000
# SOGOTPLT-NEXT: 0x000303c0 00000000 00000000 d0020100 00000000 # SOGOTPLT-NEXT: 0x000303c0 00000000 00000000 d0020100 00000000
# NOPACDYN-NOT: 0x0000000070000001 (AARCH64_BTI_PLT) # NOPACDYN-NOT: 0x0000000070000001 (AARCH64_BTI_PLT)
# NOPACDYN-NOT: 0x0000000070000003 (AARCH64_PAC_PLT) # NOPACDYN-NOT: 0x0000000070000003 (AARCH64_PAC_PLT)
# RUN: ld.lld %t1.o %t3.o --shared --soname=t.so -o %t.so # RUN: ld.lld %t1.o %t3.o --shared --soname=t.so -o %t.so
# RUN: llvm-readelf -n %t.so | FileCheck --check-prefix PACPROP %s # RUN: llvm-readelf -n %t.so | FileCheck --check-prefix PACPROP %s
# RUN: llvm-objdump -d -mattr=+v8.3a --no-show-raw-insn %t.so | FileCheck --check-prefix PACSO %s # RUN: llvm-objdump -d -mattr=+v8.3a --no-show-raw-insn %t.so | FileCheck --check-prefix PACSO %s
# RUN: llvm-readelf -x .got.plt %t.so | FileCheck --check-prefix SOGOTPLT2 %s # RUN: llvm-readelf -x .got.plt %t.so | FileCheck --check-prefix SOGOTPLT2 %s
# RUN: llvm-readelf --dynamic-table %t.so | FileCheck --check-prefix PACDYN %s # RUN: llvm-readelf --dynamic-table %t.so | FileCheck --check-prefix PACDYN %s
## PAC has no effect on PLT[0], for PLT[N]. ## PAC has no effect on PLT[0], for PLT[N].
# PACSO: 0000000000010348 func2: # PACSO: 0000000000010348 <func2>:
# PACSO-NEXT: 10348: bl #56 <func3@plt> # PACSO-NEXT: 10348: bl #56 <func3@plt>
# PACSO-NEXT: ret # PACSO-NEXT: ret
# PACSO: 0000000000010350 func3: # PACSO: 0000000000010350 <func3>:
# PACSO-NEXT: 10350: ret # PACSO-NEXT: 10350: ret
# PACSO: Disassembly of section .plt: # PACSO: Disassembly of section .plt:
# PACSO: 0000000000010360 .plt: # PACSO: 0000000000010360 <.plt>:
# PACSO-NEXT: 10360: stp x16, x30, [sp, #-16]! # PACSO-NEXT: 10360: stp x16, x30, [sp, #-16]!
# PACSO-NEXT: adrp x16, #131072 # PACSO-NEXT: adrp x16, #131072
# PACSO-NEXT: ldr x17, [x16, #1120] # PACSO-NEXT: ldr x17, [x16, #1120]
# PACSO-NEXT: add x16, x16, #1120 # PACSO-NEXT: add x16, x16, #1120
# PACSO-NEXT: br x17 # PACSO-NEXT: br x17
# PACSO-NEXT: nop # PACSO-NEXT: nop
# PACSO-NEXT: nop # PACSO-NEXT: nop
# PACSO-NEXT: nop # PACSO-NEXT: nop
# PACSO: 0000000000010380 func3@plt: # PACSO: 0000000000010380 <func3@plt>:
# PACSO-NEXT: 10380: adrp x16, #131072 # PACSO-NEXT: 10380: adrp x16, #131072
# PACSO-NEXT: ldr x17, [x16, #1128] # PACSO-NEXT: ldr x17, [x16, #1128]
# PACSO-NEXT: add x16, x16, #1128 # PACSO-NEXT: add x16, x16, #1128
# PACSO-NEXT: br x17 # PACSO-NEXT: br x17
# SOGOTPLT2: Hex dump of section '.got.plt': # SOGOTPLT2: Hex dump of section '.got.plt':
# SOGOTPLT2-NEXT: 0x00030450 00000000 00000000 00000000 00000000 # SOGOTPLT2-NEXT: 0x00030450 00000000 00000000 00000000 00000000
# SOGOTPLT2-NEXT: 0x00030460 00000000 00000000 60030100 00000000 # SOGOTPLT2-NEXT: 0x00030460 00000000 00000000 60030100 00000000
Show All 9 Lines
## .note.gnu.property is an indication of preference by the relocatable object. ## .note.gnu.property is an indication of preference by the relocatable object.
# RUN: ld.lld %t.o %t2.o -z pac-plt %t.so -o %tpacplt.exe # RUN: ld.lld %t.o %t2.o -z pac-plt %t.so -o %tpacplt.exe
# RUN: llvm-readelf -n %tpacplt.exe | FileCheck --check-prefix=PACPROP %s # RUN: llvm-readelf -n %tpacplt.exe | FileCheck --check-prefix=PACPROP %s
# RUN: llvm-readelf --dynamic-table %tpacplt.exe | FileCheck --check-prefix PACDYN2 %s # RUN: llvm-readelf --dynamic-table %tpacplt.exe | FileCheck --check-prefix PACDYN2 %s
# RUN: llvm-objdump -d -mattr=+v8.3a --no-show-raw-insn %tpacplt.exe | FileCheck --check-prefix PACPLT %s # RUN: llvm-objdump -d -mattr=+v8.3a --no-show-raw-insn %tpacplt.exe | FileCheck --check-prefix PACPLT %s
# PACPLT: Disassembly of section .text: # PACPLT: Disassembly of section .text:
# PACPLT: 0000000000210370 func1: # PACPLT: 0000000000210370 <func1>:
# PACPLT-NEXT: 210370: bl #48 <func2@plt> # PACPLT-NEXT: 210370: bl #48 <func2@plt>
# PACPLT-NEXT: ret # PACPLT-NEXT: ret
# PACPLT: 0000000000210378 func3: # PACPLT: 0000000000210378 <func3>:
# PACPLT-NEXT: 210378: ret # PACPLT-NEXT: 210378: ret
# PACPLT: Disassembly of section .plt: # PACPLT: Disassembly of section .plt:
# PACPLT: 0000000000210380 .plt: # PACPLT: 0000000000210380 <.plt>:
# PACPLT-NEXT: 210380: stp x16, x30, [sp, #-16]! # PACPLT-NEXT: 210380: stp x16, x30, [sp, #-16]!
# PACPLT-NEXT: adrp x16, #131072 # PACPLT-NEXT: adrp x16, #131072
# PACPLT-NEXT: ldr x17, [x16, #1192] # PACPLT-NEXT: ldr x17, [x16, #1192]
# PACPLT-NEXT: add x16, x16, #1192 # PACPLT-NEXT: add x16, x16, #1192
# PACPLT-NEXT: br x17 # PACPLT-NEXT: br x17
# PACPLT-NEXT: nop # PACPLT-NEXT: nop
# PACPLT-NEXT: nop # PACPLT-NEXT: nop
# PACPLT-NEXT: nop # PACPLT-NEXT: nop
# PACPLT: 00000000002103a0 func2@plt: # PACPLT: 00000000002103a0 <func2@plt>:
# PACPLT-NEXT: 2103a0: adrp x16, #131072 # PACPLT-NEXT: 2103a0: adrp x16, #131072
# PACPLT-NEXT: ldr x17, [x16, #1200] # PACPLT-NEXT: ldr x17, [x16, #1200]
# PACPLT-NEXT: add x16, x16, #1200 # PACPLT-NEXT: add x16, x16, #1200
# PACPLT-NEXT: autia1716 # PACPLT-NEXT: autia1716
# PACPLT-NEXT: br x17 # PACPLT-NEXT: br x17
# PACPLT-NEXT: nop # PACPLT-NEXT: nop
# PACDYN2-NOT: 0x0000000070000001 (AARCH64_BTI_PLT) # PACDYN2-NOT: 0x0000000070000001 (AARCH64_BTI_PLT)
Show All 19 Lines

lld/test/ELF/aarch64-fpic-got.s

Show All 10 Lines
## Checks if got access to dynamic objects is done through a got relative ## Checks if got access to dynamic objects is done through a got relative
## dynamic relocation and not using plt relative (R_AARCH64_JUMP_SLOT). ## dynamic relocation and not using plt relative (R_AARCH64_JUMP_SLOT).
# RELOC: .rela.dyn { # RELOC: .rela.dyn {
# RELOC-NEXT: 0x220320 R_AARCH64_GLOB_DAT bar 0x0 # RELOC-NEXT: 0x220320 R_AARCH64_GLOB_DAT bar 0x0
# RELOC-NEXT: } # RELOC-NEXT: }
## page(0x220320) - page(0x210000) = 65536 ## page(0x220320) - page(0x210000) = 65536
## page(0x220320) & 0xff8 = 800 ## page(0x220320) & 0xff8 = 800
# DIS: _start: # DIS: <_start>:
# DIS-NEXT: 210258: adrp x0, #65536 # DIS-NEXT: 210258: adrp x0, #65536
# DIS-NEXT: 21025c: ldr x0, [x0, #800] # DIS-NEXT: 21025c: ldr x0, [x0, #800]
.globl _start .globl _start
_start: _start:
adrp x0, :got:bar adrp x0, :got:bar
ldr x0, [x0, :got_lo12:bar] ldr x0, [x0, :got_lo12:bar]

lld/test/ELF/aarch64-gnu-ifunc-address.s

Show All 14 Lines
.text .text
.globl main .globl main
.type main,@function .type main,@function
main: main:
adrp x8, :got:myfunc adrp x8, :got:myfunc
ldr x8, [x8, :got_lo12:myfunc] ldr x8, [x8, :got_lo12:myfunc]
ret ret
# CHECK: 0000000000010284 main: # CHECK: 0000000000010284 <main>:
## myfunc's got entry = page(0x20330)-page(0x10284) + 0x330 = 65536 + 816 ## myfunc's got entry = page(0x20330)-page(0x10284) + 0x330 = 65536 + 816
# CHECK-NEXT: 10284: adrp x8, #65536 # CHECK-NEXT: 10284: adrp x8, #65536
# CHECK-NEXT: 10288: ldr x8, [x8, #816] # CHECK-NEXT: 10288: ldr x8, [x8, #816]
# CHECK-NEXT: 1028c: ret # CHECK-NEXT: 1028c: ret
# CHECK: Disassembly of section .got: # CHECK: Disassembly of section .got:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 0000000000020330 .got: # CHECK-NEXT: 0000000000020330 <.got>:
# CHECK-RELOCS: Relocations [ # CHECK-RELOCS: Relocations [
# CHECK-RELOCS-NEXT: Section {{.*}} .rela.dyn { # CHECK-RELOCS-NEXT: Section {{.*}} .rela.dyn {
# CHECK-RELOCS-NEXT: 0x20330 R_AARCH64_GLOB_DAT myfunc 0x0 # CHECK-RELOCS-NEXT: 0x20330 R_AARCH64_GLOB_DAT myfunc 0x0
# CHECK-RELOCS-NEXT: } # CHECK-RELOCS-NEXT: }
# CHECK-RELOCS-NEXT: ] # CHECK-RELOCS-NEXT: ]

lld/test/ELF/aarch64-gnu-ifunc-nonpreemptable.s

Show All 24 Lines
.globl main .globl main
.type main,@function .type main,@function
main: main:
adrp x8, myfunc adrp x8, myfunc
add x8, x8, :lo12: myfunc add x8, x8, :lo12: myfunc
ret ret
## The address of myfunc is the address of the PLT entry for myfunc. ## The address of myfunc is the address of the PLT entry for myfunc.
# PDE: myfunc_resolver: # PDE: <myfunc_resolver>:
# PDE-NEXT: 210170: ret # PDE-NEXT: 210170: ret
# PDE: main: # PDE: <main>:
# PDE-NEXT: 210174: adrp x8, #0 # PDE-NEXT: 210174: adrp x8, #0
# PDE-NEXT: 210178: add x8, x8, #384 # PDE-NEXT: 210178: add x8, x8, #384
# PDE-NEXT: 21017c: ret # PDE-NEXT: 21017c: ret
# PDE-EMPTY: # PDE-EMPTY:
# PDE-NEXT: Disassembly of section .iplt: # PDE-NEXT: Disassembly of section .iplt:
# PDE-EMPTY: # PDE-EMPTY:
# PDE-NEXT: myfunc: # PDE-NEXT: <myfunc>:
## page(.got.plt) - page(0x210010) = 65536 ## page(.got.plt) - page(0x210010) = 65536
# PDE-NEXT: 210180: adrp x16, #65536 # PDE-NEXT: 210180: adrp x16, #65536
# PDE-NEXT: 210184: ldr x17, [x16, #400] # PDE-NEXT: 210184: ldr x17, [x16, #400]
# PDE-NEXT: 210188: add x16, x16, #400 # PDE-NEXT: 210188: add x16, x16, #400
# PDE-NEXT: 21018c: br x17 # PDE-NEXT: 21018c: br x17
## The adrp to myfunc should generate a PLT entry and a GOT entry with an ## The adrp to myfunc should generate a PLT entry and a GOT entry with an
## irelative relocation. ## irelative relocation.
# PDE-RELOC: .rela.dyn { # PDE-RELOC: .rela.dyn {
# PDE-RELOC-NEXT: 0x220190 R_AARCH64_IRELATIVE - 0x210170 # PDE-RELOC-NEXT: 0x220190 R_AARCH64_IRELATIVE - 0x210170
# PDE-RELOC-NEXT: } # PDE-RELOC-NEXT: }
# PIE: myfunc_resolver: # PIE: <myfunc_resolver>:
# PIE-NEXT: 10260: ret # PIE-NEXT: 10260: ret
# PIE: main: # PIE: <main>:
# PIE-NEXT: 10264: adrp x8, #0 # PIE-NEXT: 10264: adrp x8, #0
# PIE-NEXT: 10268: add x8, x8, #624 # PIE-NEXT: 10268: add x8, x8, #624
# PIE-NEXT: 1026c: ret # PIE-NEXT: 1026c: ret
# PIE-EMPTY: # PIE-EMPTY:
# PIE-NEXT: Disassembly of section .iplt: # PIE-NEXT: Disassembly of section .iplt:
# PIE-EMPTY: # PIE-EMPTY:
# PIE-NEXT: myfunc: # PIE-NEXT: <myfunc>:
# PIE-NEXT: 10270: adrp x16, #131072 # PIE-NEXT: 10270: adrp x16, #131072
# PIE-NEXT: 10274: ldr x17, [x16, #880] # PIE-NEXT: 10274: ldr x17, [x16, #880]
# PIE-NEXT: 10278: add x16, x16, #880 # PIE-NEXT: 10278: add x16, x16, #880
# PIE-NEXT: 1027c: br x17 # PIE-NEXT: 1027c: br x17
# PIE-RELOC: .rela.dyn { # PIE-RELOC: .rela.dyn {
# PIE-RELOC-NEXT: 0x30370 R_AARCH64_IRELATIVE - 0x10260 # PIE-RELOC-NEXT: 0x30370 R_AARCH64_IRELATIVE - 0x10260
# PIE-RELOC-NEXT: } # PIE-RELOC-NEXT: }

lld/test/ELF/aarch64-gnu-ifunc-plt.s

Show All 28 Lines
// GOTPLT-NEXT: 230440 00000000 00000000 00000000 00000000 // GOTPLT-NEXT: 230440 00000000 00000000 00000000 00000000
// GOTPLT-NEXT: 230450 00000000 00000000 f0022100 00000000 // GOTPLT-NEXT: 230450 00000000 00000000 f0022100 00000000
// GOTPLT-NEXT: 230460 f0022100 00000000 00000000 00000000 // GOTPLT-NEXT: 230460 f0022100 00000000 00000000 00000000
// GOTPLT-NEXT: 230470 00000000 00000000 // GOTPLT-NEXT: 230470 00000000 00000000
// Check that a PLT header is written and the ifunc entries appear last // Check that a PLT header is written and the ifunc entries appear last
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: foo: // DISASM-NEXT: <foo>:
// DISASM-NEXT: 2102d8: ret // DISASM-NEXT: 2102d8: ret
// DISASM: bar: // DISASM: <bar>:
// DISASM-NEXT: 2102dc: ret // DISASM-NEXT: 2102dc: ret
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 2102e0: bl #80 <zed2+0x210330> // DISASM-NEXT: 2102e0: bl #80 <zed2+0x210330>
// DISASM-NEXT: 2102e4: bl #92 <zed2+0x210340> // DISASM-NEXT: 2102e4: bl #92 <zed2+0x210340>
// DISASM-NEXT: 2102e8: bl #40 <bar2@plt> // DISASM-NEXT: 2102e8: bl #40 <bar2@plt>
// DISASM-NEXT: 2102ec: bl #52 <zed2@plt> // DISASM-NEXT: 2102ec: bl #52 <zed2@plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .plt: // DISASM-NEXT: Disassembly of section .plt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .plt: // DISASM-NEXT: <.plt>:
// DISASM-NEXT: 2102f0: stp x16, x30, [sp, #-16]! // DISASM-NEXT: 2102f0: stp x16, x30, [sp, #-16]!
// DISASM-NEXT: 2102f4: adrp x16, #131072 // DISASM-NEXT: 2102f4: adrp x16, #131072
// DISASM-NEXT: 2102f8: ldr x17, [x16, #1104] // DISASM-NEXT: 2102f8: ldr x17, [x16, #1104]
// DISASM-NEXT: 2102fc: add x16, x16, #1104 // DISASM-NEXT: 2102fc: add x16, x16, #1104
// DISASM-NEXT: 210300: br x17 // DISASM-NEXT: 210300: br x17
// DISASM-NEXT: 210304: nop // DISASM-NEXT: 210304: nop
// DISASM-NEXT: 210308: nop // DISASM-NEXT: 210308: nop
// DISASM-NEXT: 21030c: nop // DISASM-NEXT: 21030c: nop
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: bar2@plt: // DISASM-NEXT: <bar2@plt>:
// DISASM-NEXT: 210310: adrp x16, #131072 // DISASM-NEXT: 210310: adrp x16, #131072
// DISASM-NEXT: 210314: ldr x17, [x16, #1112] // DISASM-NEXT: 210314: ldr x17, [x16, #1112]
// DISASM-NEXT: 210318: add x16, x16, #1112 // DISASM-NEXT: 210318: add x16, x16, #1112
// DISASM-NEXT: 21031c: br x17 // DISASM-NEXT: 21031c: br x17
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: zed2@plt: // DISASM-NEXT: <zed2@plt>:
// DISASM-NEXT: 210320: adrp x16, #131072 // DISASM-NEXT: 210320: adrp x16, #131072
// DISASM-NEXT: 210324: ldr x17, [x16, #1120] // DISASM-NEXT: 210324: ldr x17, [x16, #1120]
// DISASM-NEXT: 210328: add x16, x16, #1120 // DISASM-NEXT: 210328: add x16, x16, #1120
// DISASM-NEXT: 21032c: br x17 // DISASM-NEXT: 21032c: br x17
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .iplt: // DISASM-NEXT: Disassembly of section .iplt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .iplt: // DISASM-NEXT: <.iplt>:
// DISASM-NEXT: 210330: adrp x16, #131072 // DISASM-NEXT: 210330: adrp x16, #131072
// DISASM-NEXT: 210334: ldr x17, [x16, #1128] // DISASM-NEXT: 210334: ldr x17, [x16, #1128]
// DISASM-NEXT: 210338: add x16, x16, #1128 // DISASM-NEXT: 210338: add x16, x16, #1128
// DISASM-NEXT: 21033c: br x17 // DISASM-NEXT: 21033c: br x17
// DISASM-NEXT: 210340: adrp x16, #131072 // DISASM-NEXT: 210340: adrp x16, #131072
// DISASM-NEXT: 210344: ldr x17, [x16, #1136] // DISASM-NEXT: 210344: ldr x17, [x16, #1136]
// DISASM-NEXT: 210348: add x16, x16, #1136 // DISASM-NEXT: 210348: add x16, x16, #1136
// DISASM-NEXT: 21034c: br x17 // DISASM-NEXT: 21034c: br x17
Show All 18 Lines

lld/test/ELF/aarch64-gnu-ifunc.s

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: ] // CHECK-NEXT: ]
// 344 = 0x158 // 344 = 0x158
// 392 = 0x188 // 392 = 0x188
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: foo: // DISASM-NEXT: <foo>:
// DISASM-NEXT: 210188: ret // DISASM-NEXT: 210188: ret
// DISASM: bar: // DISASM: <bar>:
// DISASM-NEXT: 21018c: ret // DISASM-NEXT: 21018c: ret
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 210190: bl #16 // DISASM-NEXT: 210190: bl #16
// DISASM-NEXT: 210194: bl #28 // DISASM-NEXT: 210194: bl #28
// DISASM-NEXT: 210198: add x2, x2, #344 // DISASM-NEXT: 210198: add x2, x2, #344
// DISASM-NEXT: 21019c: add x2, x2, #392 // DISASM-NEXT: 21019c: add x2, x2, #392
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .iplt: // DISASM-NEXT: Disassembly of section .iplt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .iplt: // DISASM-NEXT: <.iplt>:
// DISASM-NEXT: 2101a0: adrp x16, #65536 // DISASM-NEXT: 2101a0: adrp x16, #65536
// DISASM-NEXT: 2101a4: ldr x17, [x16, #448] // DISASM-NEXT: 2101a4: ldr x17, [x16, #448]
// DISASM-NEXT: 2101a8: add x16, x16, #448 // DISASM-NEXT: 2101a8: add x16, x16, #448
// DISASM-NEXT: 2101ac: br x17 // DISASM-NEXT: 2101ac: br x17
// DISASM-NEXT: 2101b0: adrp x16, #65536 // DISASM-NEXT: 2101b0: adrp x16, #65536
// DISASM-NEXT: 2101b4: ldr x17, [x16, #456] // DISASM-NEXT: 2101b4: ldr x17, [x16, #456]
// DISASM-NEXT: 2101b8: add x16, x16, #456 // DISASM-NEXT: 2101b8: add x16, x16, #456
// DISASM-NEXT: 2101bc: br x17 // DISASM-NEXT: 2101bc: br x17
Show All 18 Lines

lld/test/ELF/aarch64-gnu-ifunc2.s

# REQUIRES: aarch64 # REQUIRES: aarch64
# RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux-gnu %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux-gnu %s -o %t.o
# RUN: ld.lld %t.o -o %t # RUN: ld.lld %t.o -o %t
# RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t | FileCheck %s
# RUN: llvm-readelf -S %t | FileCheck %s --check-prefix=SEC # RUN: llvm-readelf -S %t | FileCheck %s --check-prefix=SEC
# RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=RELOC # RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=RELOC
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: myfunc: # CHECK-NEXT: <myfunc>:
# CHECK-NEXT: 210170: # CHECK-NEXT: 210170:
# CHECK: main: # CHECK: <main>:
# .got.plt - page(0x210174) = 0x220190 - 0x210000 = 0x10190 # .got.plt - page(0x210174) = 0x220190 - 0x210000 = 0x10190
# CHECK-NEXT: 210174: adrp x8, #0x10000 # CHECK-NEXT: 210174: adrp x8, #0x10000
# CHECK-NEXT: 210178: ldr x8, [x8, #0x190] # CHECK-NEXT: 210178: ldr x8, [x8, #0x190]
# CHECK-NEXT: 21017c: ret # CHECK-NEXT: 21017c: ret
# CHECK: Disassembly of section .iplt: # CHECK: Disassembly of section .iplt:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: .iplt: # CHECK-NEXT: <.iplt>:
# .got.plt - page(0x210180) = 0x220190 - 0x210000 = 0x10190 # .got.plt - page(0x210180) = 0x220190 - 0x210000 = 0x10190
# CHECK-NEXT: 210180: adrp x16, #0x10000 # CHECK-NEXT: 210180: adrp x16, #0x10000
# CHECK-NEXT: 210184: ldr x17, [x16, #0x190] # CHECK-NEXT: 210184: ldr x17, [x16, #0x190]
# CHECK-NEXT: 210188: add x16, x16, #0x190 # CHECK-NEXT: 210188: add x16, x16, #0x190
# CHECK-NEXT: 21018c: br x17 # CHECK-NEXT: 21018c: br x17
# SEC: .got.plt PROGBITS 0000000000220190 000190 000008 00 WA 0 0 8 # SEC: .got.plt PROGBITS 0000000000220190 000190 000008 00 WA 0 0 8
Show All 19 Lines

lld/test/ELF/aarch64-ifunc-bti.s

# REQUIRES: aarch64 # REQUIRES: aarch64
# RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux-gnu %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux-gnu %s -o %t.o
# RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux-gnu %p/Inputs/aarch64-addrifunc.s -o %t1.o # RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux-gnu %p/Inputs/aarch64-addrifunc.s -o %t1.o
# RUN: ld.lld --shared --soname=t1.so %t1.o -o %t1.so # RUN: ld.lld --shared --soname=t1.so %t1.o -o %t1.so
# RUN: ld.lld --pie %t1.so %t.o -o %t # RUN: ld.lld --pie %t1.so %t.o -o %t
# RUN: llvm-objdump -d --no-show-raw-insn -mattr=+bti -triple=aarch64-linux-gnu %t | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn -mattr=+bti -triple=aarch64-linux-gnu %t | FileCheck %s
# When the address of an ifunc is taken using a non-got reference which clang # When the address of an ifunc is taken using a non-got reference which clang
# can do, LLD exports a canonical PLT entry that may have its address taken so # can do, LLD exports a canonical PLT entry that may have its address taken so
# we must use bti c. # we must use bti c.
# CHECK: Disassembly of section .plt: # CHECK: Disassembly of section .plt:
# CHECK: 0000000000010380 .plt: # CHECK: 0000000000010380 <.plt>:
# CHECK-NEXT: 10380: bti c # CHECK-NEXT: 10380: bti c
# CHECK-NEXT: stp x16, x30, [sp, #-16]! # CHECK-NEXT: stp x16, x30, [sp, #-16]!
# CHECK-NEXT: adrp x16, #131072 # CHECK-NEXT: adrp x16, #131072
# CHECK-NEXT: ldr x17, [x16, #1272] # CHECK-NEXT: ldr x17, [x16, #1272]
# CHECK-NEXT: add x16, x16, #1272 # CHECK-NEXT: add x16, x16, #1272
# CHECK-NEXT: br x17 # CHECK-NEXT: br x17
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK: 00000000000103a0 func1@plt: # CHECK: 00000000000103a0 <func1@plt>:
# CHECK-NEXT: 103a0: bti c # CHECK-NEXT: 103a0: bti c
# CHECK-NEXT: adrp x16, #131072 # CHECK-NEXT: adrp x16, #131072
# CHECK-NEXT: ldr x17, [x16, #1280] # CHECK-NEXT: ldr x17, [x16, #1280]
# CHECK-NEXT: add x16, x16, #1280 # CHECK-NEXT: add x16, x16, #1280
# CHECK-NEXT: br x17 # CHECK-NEXT: br x17
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK: Disassembly of section .iplt: # CHECK: Disassembly of section .iplt:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 00000000000103c0 myfunc: # CHECK-NEXT: 00000000000103c0 <myfunc>:
# CHECK-NEXT: 103c0: bti c # CHECK-NEXT: 103c0: bti c
# CHECK-NEXT: adrp x16, #131072 # CHECK-NEXT: adrp x16, #131072
# CHECK-NEXT: ldr x17, [x16, #1288] # CHECK-NEXT: ldr x17, [x16, #1288]
# CHECK-NEXT: add x16, x16, #1288 # CHECK-NEXT: add x16, x16, #1288
# CHECK-NEXT: br x17 # CHECK-NEXT: br x17
# CHECK-NEXT: nop # CHECK-NEXT: nop
.section ".note.gnu.property", "a" .section ".note.gnu.property", "a"
Show All 26 Lines

lld/test/ELF/aarch64-jump26-thunk.s

// REQUIRES: aarch64 // REQUIRES: aarch64
// RUN: llvm-mc -filetype=obj -triple=aarch64 %S/Inputs/abs.s -o %tabs.o // RUN: llvm-mc -filetype=obj -triple=aarch64 %S/Inputs/abs.s -o %tabs.o
// RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o
// RUN: ld.lld %t.o %tabs.o -o %t // RUN: ld.lld %t.o %tabs.o -o %t
// RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s // RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
.text .text
.globl _start .globl _start
_start: _start:
b big b big
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 210120: b #4 // CHECK-NEXT: 210120: b #4
// CHECK: __AArch64AbsLongThunk_big: // CHECK: <__AArch64AbsLongThunk_big>:
// CHECK-NEXT: 210124: ldr x16, #8 // CHECK-NEXT: 210124: ldr x16, #8
// CHECK-NEXT: 210128: br x16 // CHECK-NEXT: 210128: br x16
// CHECK: $d: // CHECK: <$d>:
// CHECK-NEXT: 21012c: 00 00 00 00 .word 0x00000000 // CHECK-NEXT: 21012c: 00 00 00 00 .word 0x00000000
// CHECK-NEXT: 210130: 10 00 00 00 .word 0x00000010 // CHECK-NEXT: 210130: 10 00 00 00 .word 0x00000010

lld/test/ELF/aarch64-plt.s

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
// DUMPDSO: Contents of section .got.plt: // DUMPDSO: Contents of section .got.plt:
// .got.plt[0..2] = 0 (reserved) // .got.plt[0..2] = 0 (reserved)
// .got.plt[3..5] = .plt = 0x10010 // .got.plt[3..5] = .plt = 0x10010
// DUMPDSO-NEXT: 30450 00000000 00000000 00000000 00000000 // DUMPDSO-NEXT: 30450 00000000 00000000 00000000 00000000
// DUMPDSO-NEXT: 30460 00000000 00000000 40030100 00000000 // DUMPDSO-NEXT: 30460 00000000 00000000 40030100 00000000
// DUMPDSO-NEXT: 30470 40030100 00000000 40030100 00000000 // DUMPDSO-NEXT: 30470 40030100 00000000 40030100 00000000
// DISASMDSO: _start: // DISASMDSO: <_start>:
// DISASMDSO-NEXT: 10330: b #0x30 <foo@plt> // DISASMDSO-NEXT: 10330: b #0x30 <foo@plt>
// DISASMDSO-NEXT: 10334: b #0x3c <bar@plt> // DISASMDSO-NEXT: 10334: b #0x3c <bar@plt>
// DISASMDSO-NEXT: 10338: b #0x48 <weak@plt> // DISASMDSO-NEXT: 10338: b #0x48 <weak@plt>
// DISASMDSO: foo: // DISASMDSO: <foo>:
// DISASMDSO-NEXT: 1033c: nop // DISASMDSO-NEXT: 1033c: nop
// DISASMDSO: Disassembly of section .plt: // DISASMDSO: Disassembly of section .plt:
// DISASMDSO-EMPTY: // DISASMDSO-EMPTY:
// DISASMDSO-NEXT: .plt: // DISASMDSO-NEXT: <.plt>:
// DISASMDSO-NEXT: 10340: stp x16, x30, [sp, #-0x10]! // DISASMDSO-NEXT: 10340: stp x16, x30, [sp, #-0x10]!
// &(.got.plt[2]) = 0x30450 + 2 * 8 = 0x30460 // &(.got.plt[2]) = 0x30450 + 2 * 8 = 0x30460
// DISASMDSO-NEXT: 10344: adrp x16, #0x20000 // DISASMDSO-NEXT: 10344: adrp x16, #0x20000
// DISASMDSO-NEXT: 10348: ldr x17, [x16, #0x460] // DISASMDSO-NEXT: 10348: ldr x17, [x16, #0x460]
// DISASMDSO-NEXT: 1034c: add x16, x16, #0x460 // DISASMDSO-NEXT: 1034c: add x16, x16, #0x460
// DISASMDSO-NEXT: 10350: br x17 // DISASMDSO-NEXT: 10350: br x17
// DISASMDSO-NEXT: 10354: nop // DISASMDSO-NEXT: 10354: nop
// DISASMDSO-NEXT: 10358: nop // DISASMDSO-NEXT: 10358: nop
// DISASMDSO-NEXT: 1035c: nop // DISASMDSO-NEXT: 1035c: nop
// foo@plt 0x30468 // foo@plt 0x30468
// &.got.plt[foo] = 0x30468 // &.got.plt[foo] = 0x30468
// DISASMDSO-EMPTY: // DISASMDSO-EMPTY:
// DISASMDSO-NEXT: foo@plt: // DISASMDSO-NEXT: <foo@plt>:
// DISASMDSO-NEXT: 10360: adrp x16, #0x20000 // DISASMDSO-NEXT: 10360: adrp x16, #0x20000
// DISASMDSO-NEXT: 10364: ldr x17, [x16, #0x468] // DISASMDSO-NEXT: 10364: ldr x17, [x16, #0x468]
// DISASMDSO-NEXT: 10368: add x16, x16, #0x468 // DISASMDSO-NEXT: 10368: add x16, x16, #0x468
// DISASMDSO-NEXT: 1036c: br x17 // DISASMDSO-NEXT: 1036c: br x17
// bar@plt // bar@plt
// &.got.plt[foo] = 0x30470 // &.got.plt[foo] = 0x30470
// DISASMDSO-EMPTY: // DISASMDSO-EMPTY:
// DISASMDSO-NEXT: bar@plt: // DISASMDSO-NEXT: <bar@plt>:
// DISASMDSO-NEXT: 10370: adrp x16, #0x20000 // DISASMDSO-NEXT: 10370: adrp x16, #0x20000
// DISASMDSO-NEXT: 10374: ldr x17, [x16, #0x470] // DISASMDSO-NEXT: 10374: ldr x17, [x16, #0x470]
// DISASMDSO-NEXT: 10378: add x16, x16, #0x470 // DISASMDSO-NEXT: 10378: add x16, x16, #0x470
// DISASMDSO-NEXT: 1037c: br x17 // DISASMDSO-NEXT: 1037c: br x17
// weak@plt // weak@plt
// 0x30468 = 0x10000 + 131072 + 1128 // 0x30468 = 0x10000 + 131072 + 1128
// DISASMDSO-EMPTY: // DISASMDSO-EMPTY:
// DISASMDSO-NEXT: weak@plt: // DISASMDSO-NEXT: <weak@plt>:
// DISASMDSO-NEXT: 10380: adrp x16, #0x20000 // DISASMDSO-NEXT: 10380: adrp x16, #0x20000
// DISASMDSO-NEXT: 10384: ldr x17, [x16, #0x478] // DISASMDSO-NEXT: 10384: ldr x17, [x16, #0x478]
// DISASMDSO-NEXT: 10388: add x16, x16, #0x478 // DISASMDSO-NEXT: 10388: add x16, x16, #0x478
// DISASMDSO-NEXT: 1038c: br x17 // DISASMDSO-NEXT: 1038c: br x17
// CHECKEXE: Name: .plt // CHECKEXE: Name: .plt
// CHECKEXE-NEXT: Type: SHT_PROGBITS // CHECKEXE-NEXT: Type: SHT_PROGBITS
// CHECKEXE-NEXT: Flags [ // CHECKEXE-NEXT: Flags [
Show All 33 Lines
// DUMPEXE: Contents of section .got.plt: // DUMPEXE: Contents of section .got.plt:
// .got.plt[0..2] = 0 (reserved) // .got.plt[0..2] = 0 (reserved)
// .got.plt[3..4] = .plt = 0x40010 // .got.plt[3..4] = .plt = 0x40010
// DUMPEXE-NEXT: 2303f0 00000000 00000000 00000000 00000000 // DUMPEXE-NEXT: 2303f0 00000000 00000000 00000000 00000000
// DUMPEXE-NEXT: 230400 00000000 00000000 e0022100 00000000 // DUMPEXE-NEXT: 230400 00000000 00000000 e0022100 00000000
// DUMPEXE-NEXT: 230410 e0022100 00000000 // DUMPEXE-NEXT: 230410 e0022100 00000000
// DISASMEXE: _start: // DISASMEXE: <_start>:
// DISASMEXE-NEXT: 2102c8: b #0xc <foo> // DISASMEXE-NEXT: 2102c8: b #0xc <foo>
// DISASMEXE-NEXT: 2102cc: b #0x34 <bar@plt> // DISASMEXE-NEXT: 2102cc: b #0x34 <bar@plt>
// DISASMEXE-NEXT: 2102d0: b #0x40 <weak@plt> // DISASMEXE-NEXT: 2102d0: b #0x40 <weak@plt>
// DISASMEXE: foo: // DISASMEXE: <foo>:
// DISASMEXE-NEXT: 2102d4: nop // DISASMEXE-NEXT: 2102d4: nop
// DISASMEXE: Disassembly of section .plt: // DISASMEXE: Disassembly of section .plt:
// DISASMEXE-EMPTY: // DISASMEXE-EMPTY:
// DISASMEXE-NEXT: .plt: // DISASMEXE-NEXT: <.plt>:
// DISASMEXE-NEXT: 2102e0: stp x16, x30, [sp, #-0x10]! // DISASMEXE-NEXT: 2102e0: stp x16, x30, [sp, #-0x10]!
// &(.got.plt[2]) = 0x2303f0 + 2 * 8 = 0x230400 // &(.got.plt[2]) = 0x2303f0 + 2 * 8 = 0x230400
// DISASMEXE-NEXT: 2102e4: adrp x16, #0x20000 // DISASMEXE-NEXT: 2102e4: adrp x16, #0x20000
// DISASMEXE-NEXT: 2102e8: ldr x17, [x16, #0x400] // DISASMEXE-NEXT: 2102e8: ldr x17, [x16, #0x400]
// DISASMEXE-NEXT: 2102ec: add x16, x16, #0x400 // DISASMEXE-NEXT: 2102ec: add x16, x16, #0x400
// DISASMEXE-NEXT: 2102f0: br x17 // DISASMEXE-NEXT: 2102f0: br x17
// DISASMEXE-NEXT: 2102f4: nop // DISASMEXE-NEXT: 2102f4: nop
// DISASMEXE-NEXT: 2102f8: nop // DISASMEXE-NEXT: 2102f8: nop
// DISASMEXE-NEXT: 2102fc: nop // DISASMEXE-NEXT: 2102fc: nop
// bar@plt // bar@plt
// DISASMEXE-EMPTY: // DISASMEXE-EMPTY:
// DISASMEXE-NEXT: bar@plt: // DISASMEXE-NEXT: <bar@plt>:
// DISASMEXE-NEXT: 210300: adrp x16, #0x20000 // DISASMEXE-NEXT: 210300: adrp x16, #0x20000
// DISASMEXE-NEXT: 210304: ldr x17, [x16, #0x408] // DISASMEXE-NEXT: 210304: ldr x17, [x16, #0x408]
// DISASMEXE-NEXT: 210308: add x16, x16, #0x408 // DISASMEXE-NEXT: 210308: add x16, x16, #0x408
// DISASMEXE-NEXT: 21030c: br x17 // DISASMEXE-NEXT: 21030c: br x17
// weak@plt // weak@plt
// DISASMEXE-EMPTY: // DISASMEXE-EMPTY:
// DISASMEXE-NEXT: weak@plt: // DISASMEXE-NEXT: <weak@plt>:
// DISASMEXE-NEXT: 210310: adrp x16, #0x20000 // DISASMEXE-NEXT: 210310: adrp x16, #0x20000
// DISASMEXE-NEXT: 210314: ldr x17, [x16, #0x410] // DISASMEXE-NEXT: 210314: ldr x17, [x16, #0x410]
// DISASMEXE-NEXT: 210318: add x16, x16, #0x410 // DISASMEXE-NEXT: 210318: add x16, x16, #0x410
// DISASMEXE-NEXT: 21031c: br x17 // DISASMEXE-NEXT: 21031c: br x17
.global _start,foo,bar .global _start,foo,bar
.weak weak .weak weak
_start: _start:
b foo b foo
b bar b bar
b weak b weak
.section .text2,"ax",@progbits .section .text2,"ax",@progbits
foo: foo:
nop nop

lld/test/ELF/aarch64-relocs.s

# REQUIRES: aarch64 # REQUIRES: aarch64
# RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %s -o %t # RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %s -o %t
# RUN: echo '.globl zero; zero = 0' | llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd -o %t2.o # RUN: echo '.globl zero; zero = 0' | llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd -o %t2.o
# RUN: ld.lld %t %t2.o -o %t2 # RUN: ld.lld %t %t2.o -o %t2
# RUN: llvm-objdump -d %t2 | FileCheck %s # RUN: llvm-objdump -d %t2 | FileCheck %s
.section .R_AARCH64_ADR_PREL_LO21,"ax",@progbits .section .R_AARCH64_ADR_PREL_LO21,"ax",@progbits
.globl _start .globl _start
_start: _start:
adr x1,msg adr x1,msg
msg: .asciz "Hello, world\n" msg: .asciz "Hello, world\n"
msgend: msgend:
# CHECK: Disassembly of section .R_AARCH64_ADR_PREL_LO21: # CHECK: Disassembly of section .R_AARCH64_ADR_PREL_LO21:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK: _start: # CHECK: <_start>:
# CHECK: 0: 21 00 00 10 adr x1, #4 # CHECK: 0: 21 00 00 10 adr x1, #4
# CHECK: msg: # CHECK: <msg>:
# CHECK: 4: # CHECK: 4:
# #4 is the adr immediate value. # #4 is the adr immediate value.
.section .R_AARCH64_ADR_PREL_PG_H121,"ax",@progbits .section .R_AARCH64_ADR_PREL_PG_H121,"ax",@progbits
adrp x1,mystr adrp x1,mystr
mystr: mystr:
.asciz "blah" .asciz "blah"
.size mystr, 4 .size mystr, 4
# PAGE(S + A) - PAGE(P) = PAGE(210136) - PAGE(0x210132) = 0 # PAGE(S + A) - PAGE(P) = PAGE(210136) - PAGE(0x210132) = 0
# #
# CHECK: Disassembly of section .R_AARCH64_ADR_PREL_PG_H121: # CHECK: Disassembly of section .R_AARCH64_ADR_PREL_PG_H121:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: $x.2: # CHECK-NEXT: <$x.2>:
# CHECK-NEXT: 210132: 01 00 00 90 adrp x1, #0 # CHECK-NEXT: 210132: 01 00 00 90 adrp x1, #0
.section .R_AARCH64_ADD_ABS_LO12_NC,"ax",@progbits .section .R_AARCH64_ADD_ABS_LO12_NC,"ax",@progbits
add x0, x0, :lo12:.L.str add x0, x0, :lo12:.L.str
.L.str: .L.str:
.asciz "blah" .asciz "blah"
.size mystr, 4 .size mystr, 4
# S = 0x21013b, A = 0x4 # S = 0x21013b, A = 0x4
# R = (S + A) & 0xFFF = 319 # R = (S + A) & 0xFFF = 319
# #
# CHECK: Disassembly of section .R_AARCH64_ADD_ABS_LO12_NC: # CHECK: Disassembly of section .R_AARCH64_ADD_ABS_LO12_NC:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: $x.4: # CHECK-NEXT: <$x.4>:
# CHECK-NEXT: 21013b: 00 fc 04 91 add x0, x0, #319 # CHECK-NEXT: 21013b: 00 fc 04 91 add x0, x0, #319
.section .R_AARCH64_LDST64_ABS_LO12_NC,"ax",@progbits .section .R_AARCH64_LDST64_ABS_LO12_NC,"ax",@progbits
ldr x28, [x27, :lo12:foo] ldr x28, [x27, :lo12:foo]
foo: foo:
.asciz "foo" .asciz "foo"
.size mystr, 3 .size mystr, 3
# S = 0x210144, A = 0x4 # S = 0x210144, A = 0x4
# R = ((S + A) & 0xFFF) << 7 = 0x0000a400 # R = ((S + A) & 0xFFF) << 7 = 0x0000a400
# 0x0000a400 | 0xf940177c = 0xf940a77c # 0x0000a400 | 0xf940177c = 0xf940a77c
# CHECK: Disassembly of section .R_AARCH64_LDST64_ABS_LO12_NC: # CHECK: Disassembly of section .R_AARCH64_LDST64_ABS_LO12_NC:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: $x.6: # CHECK-NEXT: <$x.6>:
# CHECK-NEXT: 210144: 7c a7 40 f9 ldr x28, [x27, #328] # CHECK-NEXT: 210144: 7c a7 40 f9 ldr x28, [x27, #328]
.section .SUB,"ax",@progbits .section .SUB,"ax",@progbits
nop nop
sub: sub:
nop nop
# CHECK: Disassembly of section .SUB: # CHECK: Disassembly of section .SUB:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: $x.8: # CHECK-NEXT: <$x.8>:
# CHECK-NEXT: 21014c: 1f 20 03 d5 nop # CHECK-NEXT: 21014c: 1f 20 03 d5 nop
# CHECK: sub: # CHECK: <sub>:
# CHECK-NEXT: 210150: 1f 20 03 d5 nop # CHECK-NEXT: 210150: 1f 20 03 d5 nop
.section .R_AARCH64_CALL26,"ax",@progbits .section .R_AARCH64_CALL26,"ax",@progbits
call26: call26:
bl sub bl sub
# S = 0x21014c, A = 0x4, P = 0x210154 # S = 0x21014c, A = 0x4, P = 0x210154
# R = S + A - P = -0x4 = 0xfffffffc # R = S + A - P = -0x4 = 0xfffffffc
# (R & 0x0ffffffc) >> 2 = 0x03ffffff # (R & 0x0ffffffc) >> 2 = 0x03ffffff
# 0x94000000 | 0x03ffffff = 0x97ffffff # 0x94000000 | 0x03ffffff = 0x97ffffff
# CHECK: Disassembly of section .R_AARCH64_CALL26: # CHECK: Disassembly of section .R_AARCH64_CALL26:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: call26: # CHECK-NEXT: <call26>:
# CHECK-NEXT: 210154: ff ff ff 97 bl #-4 # CHECK-NEXT: 210154: ff ff ff 97 bl #-4
.section .R_AARCH64_JUMP26,"ax",@progbits .section .R_AARCH64_JUMP26,"ax",@progbits
jump26: jump26:
b sub b sub
# S = 0x21014c, A = 0x4, P = 0x210158 # S = 0x21014c, A = 0x4, P = 0x210158
# R = S + A - P = -0x8 = 0xfffffff8 # R = S + A - P = -0x8 = 0xfffffff8
# (R & 0x0ffffffc) >> 2 = 0x03fffffe # (R & 0x0ffffffc) >> 2 = 0x03fffffe
# 0x14000000 | 0x03fffffe = 0x17fffffe # 0x14000000 | 0x03fffffe = 0x17fffffe
# CHECK: Disassembly of section .R_AARCH64_JUMP26: # CHECK: Disassembly of section .R_AARCH64_JUMP26:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: jump26: # CHECK-NEXT: <jump26>:
# CHECK-NEXT: 210158: fe ff ff 17 b #-8 # CHECK-NEXT: 210158: fe ff ff 17 b #-8
.section .R_AARCH64_LDST32_ABS_LO12_NC,"ax",@progbits .section .R_AARCH64_LDST32_ABS_LO12_NC,"ax",@progbits
ldst32: ldst32:
ldr s4, [x5, :lo12:foo32] ldr s4, [x5, :lo12:foo32]
foo32: foo32:
.asciz "foo" .asciz "foo"
.size mystr, 3 .size mystr, 3
# S = 0x21015c, A = 0x4 # S = 0x21015c, A = 0x4
# R = ((S + A) & 0xFFC) << 8 = 0x00016000 # R = ((S + A) & 0xFFC) << 8 = 0x00016000
# 0x00016000 | 0xbd4000a4 = 0xbd4160a4 # 0x00016000 | 0xbd4000a4 = 0xbd4160a4
# CHECK: Disassembly of section .R_AARCH64_LDST32_ABS_LO12_NC: # CHECK: Disassembly of section .R_AARCH64_LDST32_ABS_LO12_NC:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: ldst32: # CHECK-NEXT: <ldst32>:
# CHECK-NEXT: 21015c: a4 60 41 bd ldr s4, [x5, #352] # CHECK-NEXT: 21015c: a4 60 41 bd ldr s4, [x5, #352]
.section .R_AARCH64_LDST8_ABS_LO12_NC,"ax",@progbits .section .R_AARCH64_LDST8_ABS_LO12_NC,"ax",@progbits
ldst8: ldst8:
ldrsb x11, [x13, :lo12:foo8] ldrsb x11, [x13, :lo12:foo8]
foo8: foo8:
.asciz "foo" .asciz "foo"
.size mystr, 3 .size mystr, 3
# S = 0x210164, A = 0x4 # S = 0x210164, A = 0x4
# R = ((S + A) & 0xFFF) << 10 = 0x0005a000 # R = ((S + A) & 0xFFF) << 10 = 0x0005a000
# 0x0005a000 | 0x398001ab = 0x3985a1ab # 0x0005a000 | 0x398001ab = 0x3985a1ab
# CHECK: Disassembly of section .R_AARCH64_LDST8_ABS_LO12_NC: # CHECK: Disassembly of section .R_AARCH64_LDST8_ABS_LO12_NC:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: ldst8: # CHECK-NEXT: <ldst8>:
# CHECK-NEXT: 210164: ab a1 85 39 ldrsb x11, [x13, #360] # CHECK-NEXT: 210164: ab a1 85 39 ldrsb x11, [x13, #360]
.section .R_AARCH64_LDST128_ABS_LO12_NC,"ax",@progbits .section .R_AARCH64_LDST128_ABS_LO12_NC,"ax",@progbits
ldst128: ldst128:
ldr q20, [x19, #:lo12:foo128] ldr q20, [x19, #:lo12:foo128]
foo128: foo128:
.asciz "foo" .asciz "foo"
.size mystr, 3 .size mystr, 3
# S = 0x21016c, A = 0x4 # S = 0x21016c, A = 0x4
# R = ((S + A) & 0xFF8) << 6 = 0x00005c00 # R = ((S + A) & 0xFF8) << 6 = 0x00005c00
# 0x00005c00 | 0x3dc00274 = 0x3dc05e74 # 0x00005c00 | 0x3dc00274 = 0x3dc05e74
# CHECK: Disassembly of section .R_AARCH64_LDST128_ABS_LO12_NC: # CHECK: Disassembly of section .R_AARCH64_LDST128_ABS_LO12_NC:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK: ldst128: # CHECK: <ldst128>:
# CHECK: 21016c: 74 5e c0 3d ldr q20, [x19, #368] # CHECK: 21016c: 74 5e c0 3d ldr q20, [x19, #368]
#foo128: #foo128:
# 210170: 66 6f 6f 00 .word # 210170: 66 6f 6f 00 .word
.section .R_AARCH64_LDST16_ABS_LO12_NC,"ax",@progbits .section .R_AARCH64_LDST16_ABS_LO12_NC,"ax",@progbits
ldst16: ldst16:
ldr h17, [x19, :lo12:foo16] ldr h17, [x19, :lo12:foo16]
ldrh w1, [x19, :lo12:foo16] ldrh w1, [x19, :lo12:foo16]
ldrh w2, [x19, :lo12:foo16 + 2] ldrh w2, [x19, :lo12:foo16 + 2]
foo16: foo16:
.asciz "foo" .asciz "foo"
.size mystr, 4 .size mystr, 4
# S = 0x210174, A = 0x4 # S = 0x210174, A = 0x4
# R = ((S + A) & 0x0FFC) << 9 = 0x2f000 # R = ((S + A) & 0x0FFC) << 9 = 0x2f000
# 0x2f000 | 0x7d400271 = 0x7d430271 # 0x2f000 | 0x7d400271 = 0x7d430271
# CHECK: Disassembly of section .R_AARCH64_LDST16_ABS_LO12_NC: # CHECK: Disassembly of section .R_AARCH64_LDST16_ABS_LO12_NC:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: ldst16: # CHECK-NEXT: <ldst16>:
# CHECK-NEXT: 210174: 71 02 43 7d ldr h17, [x19, #384] # CHECK-NEXT: 210174: 71 02 43 7d ldr h17, [x19, #384]
# CHECK-NEXT: 210178: 61 02 43 79 ldrh w1, [x19, #384] # CHECK-NEXT: 210178: 61 02 43 79 ldrh w1, [x19, #384]
# CHECK-NEXT: 21017c: 62 06 43 79 ldrh w2, [x19, #386] # CHECK-NEXT: 21017c: 62 06 43 79 ldrh w2, [x19, #386]
.section .R_AARCH64_MOVW_UABS,"ax",@progbits .section .R_AARCH64_MOVW_UABS,"ax",@progbits
movz1: movz1:
movk x12, #:abs_g0:zero+0xC movk x12, #:abs_g0:zero+0xC
movk x12, #:abs_g0_nc:zero+0xF000E000D000C movk x12, #:abs_g0_nc:zero+0xF000E000D000C
movk x13, #:abs_g1:zero+0xD000C movk x13, #:abs_g1:zero+0xD000C
movk x13, #:abs_g1_nc:zero+0xF000E000D000C movk x13, #:abs_g1_nc:zero+0xF000E000D000C
movk x14, #:abs_g2:zero+0xE000D000C movk x14, #:abs_g2:zero+0xE000D000C
movk x14, #:abs_g2_nc:zero+0xF000E000D000C movk x14, #:abs_g2_nc:zero+0xF000E000D000C
movz x15, #:abs_g3:zero+0xF000E000D000C movz x15, #:abs_g3:zero+0xF000E000D000C
movk x16, #:abs_g3:zero+0xF000E000D000C movk x16, #:abs_g3:zero+0xF000E000D000C
## 4222124650659840 == (0xF << 48) ## 4222124650659840 == (0xF << 48)
# CHECK: Disassembly of section .R_AARCH64_MOVW_UABS: # CHECK: Disassembly of section .R_AARCH64_MOVW_UABS:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: movz1: # CHECK-NEXT: <movz1>:
# CHECK-NEXT: 8c 01 80 f2 movk x12, #12 # CHECK-NEXT: 8c 01 80 f2 movk x12, #12
# CHECK-NEXT: 8c 01 80 f2 movk x12, #12 # CHECK-NEXT: 8c 01 80 f2 movk x12, #12
# CHECK-NEXT: ad 01 a0 f2 movk x13, #13, lsl #16 # CHECK-NEXT: ad 01 a0 f2 movk x13, #13, lsl #16
# CHECK-NEXT: ad 01 a0 f2 movk x13, #13, lsl #16 # CHECK-NEXT: ad 01 a0 f2 movk x13, #13, lsl #16
# CHECK-NEXT: ce 01 c0 f2 movk x14, #14, lsl #32 # CHECK-NEXT: ce 01 c0 f2 movk x14, #14, lsl #32
# CHECK-NEXT: ce 01 c0 f2 movk x14, #14, lsl #32 # CHECK-NEXT: ce 01 c0 f2 movk x14, #14, lsl #32
# CHECK-NEXT: ef 01 e0 d2 mov x15, #4222124650659840 # CHECK-NEXT: ef 01 e0 d2 mov x15, #4222124650659840
# CHECK-NEXT: f0 01 e0 f2 movk x16, #15, lsl #48 # CHECK-NEXT: f0 01 e0 f2 movk x16, #15, lsl #48
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

lld/test/ELF/aarch64-thunk-pi.s

Show All 9 Lines
// Check that Position Independent thunks are generated for shared libraries. // Check that Position Independent thunks are generated for shared libraries.
.section .text_low, "ax", %progbits .section .text_low, "ax", %progbits
.globl low_target .globl low_target
.type low_target, %function .type low_target, %function
low_target: low_target:
// Need thunk to high_target@plt // Need thunk to high_target@plt
bl high_target bl high_target
ret ret
// CHECK: low_target: // CHECK: <low_target>:
// CHECK-NEXT: d8: bl #0x14 <__AArch64ADRPThunk_high_target> // CHECK-NEXT: d8: bl #0x14 <__AArch64ADRPThunk_high_target>
// CHECK-NEXT: ret // CHECK-NEXT: ret
.hidden low_target2 .hidden low_target2
.globl low_target2 .globl low_target2
.type low_target2, %function .type low_target2, %function
low_target2: low_target2:
// Need thunk to high_target2 // Need thunk to high_target2
bl high_target2 bl high_target2
// .text_high+8 = high_target2 // .text_high+8 = high_target2
bl .text_high+8 bl .text_high+8
ret ret
// CHECK: low_target2: // CHECK: <low_target2>:
// CHECK-NEXT: e0: bl #0x18 <__AArch64ADRPThunk_high_target2> // CHECK-NEXT: e0: bl #0x18 <__AArch64ADRPThunk_high_target2>
// CHECK-NEXT: e4: bl #0x20 <__AArch64ADRPThunk_> // CHECK-NEXT: e4: bl #0x20 <__AArch64ADRPThunk_>
// CHECK-NEXT: ret // CHECK-NEXT: ret
// Expect range extension thunks for .text_low // Expect range extension thunks for .text_low
// adrp calculation is (PC + signed immediate) & (!0xfff) // adrp calculation is (PC + signed immediate) & (!0xfff)
// CHECK: __AArch64ADRPThunk_high_target: // CHECK: <__AArch64ADRPThunk_high_target>:
// CHECK-NEXT: ec: adrp x16, #0x10000000 // CHECK-NEXT: ec: adrp x16, #0x10000000
// CHECK-NEXT: add x16, x16, #0x40 // CHECK-NEXT: add x16, x16, #0x40
// CHECK-NEXT: br x16 // CHECK-NEXT: br x16
// CHECK: __AArch64ADRPThunk_high_target2: // CHECK: <__AArch64ADRPThunk_high_target2>:
// CHECK-NEXT: f8: adrp x16, #0x10000000 // CHECK-NEXT: f8: adrp x16, #0x10000000
// CHECK-NEXT: add x16, x16, #0x8 // CHECK-NEXT: add x16, x16, #0x8
// CHECK-NEXT: br x16 // CHECK-NEXT: br x16
/// Identical to the previous one, but for the target .text_high+8. /// Identical to the previous one, but for the target .text_high+8.
// CHECK: __AArch64ADRPThunk_: // CHECK: <__AArch64ADRPThunk_>:
// CHECK-NEXT: 104: adrp x16, #0x10000000 // CHECK-NEXT: 104: adrp x16, #0x10000000
// CHECK-NEXT: add x16, x16, #0x8 // CHECK-NEXT: add x16, x16, #0x8
// CHECK-NEXT: br x16 // CHECK-NEXT: br x16
.section .text_high, "ax", %progbits .section .text_high, "ax", %progbits
.globl high_target .globl high_target
.type high_target, %function .type high_target, %function
high_target: high_target:
// No thunk needed as we can reach low_target@plt // No thunk needed as we can reach low_target@plt
bl low_target bl low_target
ret ret
// CHECK: high_target: // CHECK: <high_target>:
// CHECK-NEXT: 10000000: bl #0x50 <low_target@plt> // CHECK-NEXT: 10000000: bl #0x50 <low_target@plt>
// CHECK-NEXT: ret // CHECK-NEXT: ret
.hidden high_target2 .hidden high_target2
.globl high_target2 .globl high_target2
.type high_target2, %function .type high_target2, %function
high_target2: high_target2:
// Need thunk to low_target // Need thunk to low_target
bl low_target2 bl low_target2
ret ret
// CHECK: high_target2: // CHECK: <high_target2>:
// CHECK-NEXT: 10000008: bl #0x8 <__AArch64ADRPThunk_low_target2> // CHECK-NEXT: 10000008: bl #0x8 <__AArch64ADRPThunk_low_target2>
// CHECK-NEXT: ret // CHECK-NEXT: ret
// Expect Thunk for .text.high // Expect Thunk for .text.high
// CHECK: __AArch64ADRPThunk_low_target2: // CHECK: <__AArch64ADRPThunk_low_target2>:
// CHECK-NEXT: 10000010: adrp x16, #-0x10000000 // CHECK-NEXT: 10000010: adrp x16, #-0x10000000
// CHECK-NEXT: add x16, x16, #0xe0 // CHECK-NEXT: add x16, x16, #0xe0
// CHECK-NEXT: br x16 // CHECK-NEXT: br x16
// CHECK: Disassembly of section .plt: // CHECK: Disassembly of section .plt:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: .plt: // CHECK-NEXT: <.plt>:
// CHECK-NEXT: 10000020: stp x16, x30, [sp, #-0x10]! // CHECK-NEXT: 10000020: stp x16, x30, [sp, #-0x10]!
// CHECK-NEXT: adrp x16, #0 // CHECK-NEXT: adrp x16, #0
// CHECK-NEXT: ldr x17, [x16, #0x120] // CHECK-NEXT: ldr x17, [x16, #0x120]
// CHECK-NEXT: add x16, x16, #0x120 // CHECK-NEXT: add x16, x16, #0x120
// CHECK-NEXT: br x17 // CHECK-NEXT: br x17
// CHECK-NEXT: nop // CHECK-NEXT: nop
// CHECK-NEXT: nop // CHECK-NEXT: nop
// CHECK-NEXT: nop // CHECK-NEXT: nop
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: high_target@plt: // CHECK-NEXT: <high_target@plt>:
// CHECK-NEXT: 10000040: adrp x16, #0x0 // CHECK-NEXT: 10000040: adrp x16, #0x0
// CHECK-NEXT: ldr x17, [x16, #0x128] // CHECK-NEXT: ldr x17, [x16, #0x128]
// CHECK-NEXT: add x16, x16, #0x128 // CHECK-NEXT: add x16, x16, #0x128
// CHECK-NEXT: br x17 // CHECK-NEXT: br x17
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: low_target@plt: // CHECK-NEXT: <low_target@plt>:
// CHECK-NEXT: 10000050: adrp x16, #0x0 // CHECK-NEXT: 10000050: adrp x16, #0x0
// CHECK-NEXT: ldr x17, [x16, #0x130] // CHECK-NEXT: ldr x17, [x16, #0x130]
// CHECK-NEXT: add x16, x16, #0x130 // CHECK-NEXT: add x16, x16, #0x130
// CHECK-NEXT: br x17 // CHECK-NEXT: br x17

lld/test/ELF/aarch64-thunk-script.s

Show All 23 Lines
.type high_target, %function .type high_target, %function
high_target: high_target:
// No Thunk needed as we are within signed immediate range // No Thunk needed as we are within signed immediate range
bl _start bl _start
ret ret
// CHECK: Disassembly of section .text_low: // CHECK: Disassembly of section .text_low:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 2000: bl #0xc <__AArch64AbsLongThunk_high_target> // CHECK-NEXT: 2000: bl #0xc <__AArch64AbsLongThunk_high_target>
// CHECK-NEXT: 2004: bl #0x18 <__AArch64AbsLongThunk_> // CHECK-NEXT: 2004: bl #0x18 <__AArch64AbsLongThunk_>
// CHECK-NEXT: ret // CHECK-NEXT: ret
// CHECK: __AArch64AbsLongThunk_high_target: // CHECK: <__AArch64AbsLongThunk_high_target>:
// CHECK-NEXT: 200c: ldr x16, #0x8 // CHECK-NEXT: 200c: ldr x16, #0x8
// CHECK-NEXT: br x16 // CHECK-NEXT: br x16
// CHECK: $d: // CHECK: <$d>:
// CHECK-NEXT: 2014: 00 20 00 08 .word 0x08002000 // CHECK-NEXT: 2014: 00 20 00 08 .word 0x08002000
// CHECK-NEXT: 2018: 00 00 00 00 .word 0x00000000 // CHECK-NEXT: 2018: 00 00 00 00 .word 0x00000000
// CHECK: __AArch64AbsLongThunk_: // CHECK: <__AArch64AbsLongThunk_>:
// CHECK-NEXT: 201c: ldr x16, #0x8 // CHECK-NEXT: 201c: ldr x16, #0x8
// CHECK-NEXT: 2020: br x16 // CHECK-NEXT: 2020: br x16
// CHECK: $d: // CHECK: <$d>:
// CHECK-NEXT: 2024: 04 20 00 08 .word 0x08002004 // CHECK-NEXT: 2024: 04 20 00 08 .word 0x08002004
// CHECK-NEXT: 2028: 00 00 00 00 .word 0x00000000 // CHECK-NEXT: 2028: 00 00 00 00 .word 0x00000000
// CHECK: Disassembly of section .text_high: // CHECK: Disassembly of section .text_high:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: high_target: // CHECK-NEXT: <high_target>:
// CHECK-NEXT: 8002000: bl #-0x8000000 <_start> // CHECK-NEXT: 8002000: bl #-0x8000000 <_start>
// CHECK-NEXT: ret // CHECK-NEXT: ret

lld/test/ELF/aarch64-thunk-section-location.s

Show All 28 Lines
.section .text.6, "ax", %progbits .section .text.6, "ax", %progbits
.balign 0x1000 .balign 0x1000
.globl high_target .globl high_target
.type high_target, %function .type high_target, %function
high_target: high_target:
ret ret
// CHECK: __AArch64AbsLongThunk_high_target: // CHECK: <__AArch64AbsLongThunk_high_target>:
// CHECK-NEXT: 81d1008: ldr x16, #8 // CHECK-NEXT: 81d1008: ldr x16, #8
// CHECK-NEXT: 81d100c: br x16 // CHECK-NEXT: 81d100c: br x16
// CHECK: $d: // CHECK: <$d>:
// CHECK-NEXT: 81d1010: 00 20 21 08 .word 0x08212000 // CHECK-NEXT: 81d1010: 00 20 21 08 .word 0x08212000

lld/test/ELF/aarch64-tls-gdie.s

Show All 20 Lines
// SEC-NEXT: SHF_ALLOC // SEC-NEXT: SHF_ALLOC
// SEC-NEXT: SHF_WRITE // SEC-NEXT: SHF_WRITE
// SEC-NEXT: ] // SEC-NEXT: ]
// SEC-NEXT: Address: 0x220300 // SEC-NEXT: Address: 0x220300
// page(0x220300) - page(0x21023c) = 65536 // page(0x220300) - page(0x21023c) = 65536
// 0x23c = 768 // 0x23c = 768
// CHECK: _start: // CHECK: <_start>:
// CHECK-NEXT: 210238: nop // CHECK-NEXT: 210238: nop
// CHECK-NEXT: 21023c: adrp x0, #65536 // CHECK-NEXT: 21023c: adrp x0, #65536
// CHECK-NEXT: 210240: ldr x0, [x0, #768] // CHECK-NEXT: 210240: ldr x0, [x0, #768]
// CHECK-NEXT: 210244: nop // CHECK-NEXT: 210244: nop
// CHECK-NEXT: 210248: nop // CHECK-NEXT: 210248: nop

lld/test/ELF/aarch64-tls-gdle.s

# REQUIRES: aarch64 # REQUIRES: aarch64
# RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-linux %p/Inputs/aarch64-tls-ie.s -o %ttlsie.o # RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-linux %p/Inputs/aarch64-tls-ie.s -o %ttlsie.o
# RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-linux %s -o %tmain.o # RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-linux %s -o %tmain.o
# RUN: ld.lld %tmain.o %ttlsie.o -o %tout # RUN: ld.lld %tmain.o %ttlsie.o -o %tout
# RUN: llvm-objdump -d --no-show-raw-insn %tout | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %tout | FileCheck %s
# RUN: llvm-readobj -r %tout | FileCheck -check-prefix=RELOC %s # RUN: llvm-readobj -r %tout | FileCheck -check-prefix=RELOC %s
## Local-Dynamic to Local-Exec relax creates no dynamic relocations. ## Local-Dynamic to Local-Exec relax creates no dynamic relocations.
# RELOC: Relocations [ # RELOC: Relocations [
# RELOC-NEXT: ] # RELOC-NEXT: ]
# TCB size = 0x16 and foo is first element from TLS register. # TCB size = 0x16 and foo is first element from TLS register.
# CHECK-LABEL: _start: # CHECK-LABEL: <_start>:
# CHECK-NEXT: 2101c8: movz x0, #0, lsl #16 # CHECK-NEXT: 2101c8: movz x0, #0, lsl #16
# CHECK-NEXT: 2101cc: movk x0, #16 # CHECK-NEXT: 2101cc: movk x0, #16
# CHECK-NEXT: 2101d0: nop # CHECK-NEXT: 2101d0: nop
# CHECK-NEXT: 2101d4: nop # CHECK-NEXT: 2101d4: nop
.globl _start .globl _start
_start: _start:
adrp x0, :tlsdesc:foo adrp x0, :tlsdesc:foo
ldr x1, [x0, :tlsdesc_lo12:foo] ldr x1, [x0, :tlsdesc_lo12:foo]
add x0, x0, :tlsdesc_lo12:foo add x0, x0, :tlsdesc_lo12:foo
.tlsdesccall foo .tlsdesccall foo
blr x1 blr x1

lld/test/ELF/aarch64-tls-ie.s

Show All 27 Lines
# RELOC-NEXT: 0x220338 R_AARCH64_TLS_TPREL64 foo 0x0 # RELOC-NEXT: 0x220338 R_AARCH64_TLS_TPREL64 foo 0x0
# RELOC-NEXT: } # RELOC-NEXT: }
# RELOC-NEXT:] # RELOC-NEXT:]
## Page(0x2200B0) - Page(0x210000) = 0x10000 = 65536 ## Page(0x2200B0) - Page(0x210000) = 0x10000 = 65536
## 0x2200B0 & 0xff8 = 0xB0 = 176 ## 0x2200B0 & 0xff8 = 0xB0 = 176
## Page(0x2200B8) - Page(0x210000) = 0x10000 = 65536 ## Page(0x2200B8) - Page(0x210000) = 0x10000 = 65536
## 0x2200B8 & 0xff8 = 0xB8 = 184 ## 0x2200B8 & 0xff8 = 0xB8 = 184
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: 210278: adrp x0, #65536 # CHECK-NEXT: 210278: adrp x0, #65536
# CHECK-NEXT: 21027c: ldr x0, [x0, #824] # CHECK-NEXT: 21027c: ldr x0, [x0, #824]
# CHECK-NEXT: 210280: adrp x0, #65536 # CHECK-NEXT: 210280: adrp x0, #65536
# CHECK-NEXT: 210284: ldr x0, [x0, #832] # CHECK-NEXT: 210284: ldr x0, [x0, #832]
.globl _start .globl _start
_start: _start:
adrp x0, :gottprel:foo adrp x0, :gottprel:foo
ldr x0, [x0, #:gottprel_lo12:foo] ldr x0, [x0, #:gottprel_lo12:foo]
adrp x0, :gottprel:bar adrp x0, :gottprel:bar
ldr x0, [x0, #:gottprel_lo12:bar] ldr x0, [x0, #:gottprel_lo12:bar]

lld/test/ELF/aarch64-tls-iele.s

Show All 10 Lines
# Initial-Exec to Local-Exec relax creates no dynamic relocations. # Initial-Exec to Local-Exec relax creates no dynamic relocations.
# RELOC: Relocations [ # RELOC: Relocations [
# RELOC-NEXT: ] # RELOC-NEXT: ]
# TCB size = 0x16 and foo is first element from TLS register. # TCB size = 0x16 and foo is first element from TLS register.
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: movz x0, #0, lsl #16 # CHECK-NEXT: movz x0, #0, lsl #16
# CHECK-NEXT: movk x0, #20 # CHECK-NEXT: movk x0, #20
# CHECK-NEXT: movz x0, #0, lsl #16 # CHECK-NEXT: movz x0, #0, lsl #16
# CHECK-NEXT: movk x0, #16 # CHECK-NEXT: movk x0, #16
.section .tdata .section .tdata
.align 2 .align 2
.type foo_local, %object .type foo_local, %object
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lld/test/ELF/aarch64-tls-le.s

Show All 13 Lines
add x0, x0, :tprel_hi12:v1 add x0, x0, :tprel_hi12:v1
add x0, x0, :tprel_lo12_nc:v1 add x0, x0, :tprel_lo12_nc:v1
mrs x0, TPIDR_EL0 mrs x0, TPIDR_EL0
add x0, x0, :tprel_hi12:v2 add x0, x0, :tprel_hi12:v2
add x0, x0, :tprel_lo12_nc:v2 add x0, x0, :tprel_lo12_nc:v2
# TCB size = 0x16 and foo is first element from TLS register. # TCB size = 0x16 and foo is first element from TLS register.
#CHECK: Disassembly of section .text: #CHECK: Disassembly of section .text:
#CHECK: _start: #CHECK: <_start>:
#CHECK: 210158: 40 d0 3b d5 mrs x0, TPIDR_EL0 #CHECK: 210158: 40 d0 3b d5 mrs x0, TPIDR_EL0
#CHECK: 21015c: 00 00 40 91 add x0, x0, #0, lsl #12 #CHECK: 21015c: 00 00 40 91 add x0, x0, #0, lsl #12
#CHECK: 210160: 00 40 00 91 add x0, x0, #16 #CHECK: 210160: 00 40 00 91 add x0, x0, #16
#CHECK: 210164: 40 d0 3b d5 mrs x0, TPIDR_EL0 #CHECK: 210164: 40 d0 3b d5 mrs x0, TPIDR_EL0
#CHECK: 210168: 00 fc 7f 91 add x0, x0, #4095, lsl #12 #CHECK: 210168: 00 fc 7f 91 add x0, x0, #4095, lsl #12
#CHECK: 21016c: 00 e0 3f 91 add x0, x0, #4088 #CHECK: 21016c: 00 e0 3f 91 add x0, x0, #4088
.section .tbss,"awT",@nobits .section .tbss,"awT",@nobits
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lld/test/ELF/aarch64-tlsld-ldst.s

Show All 18 Lines_start: mrs x8, TPIDR_EL0
ldr w0, [x8, :tprel_lo12_nc:var2] ldr w0, [x8, :tprel_lo12_nc:var2]
add x8, x8, :tprel_hi12:var3 add x8, x8, :tprel_hi12:var3
ldrh w0, [x8, :tprel_lo12_nc:var3] ldrh w0, [x8, :tprel_lo12_nc:var3]
add x8, x8, :tprel_hi12:var4 add x8, x8, :tprel_hi12:var4
ldrb w0, [x8, :tprel_lo12_nc:var4] ldrb w0, [x8, :tprel_lo12_nc:var4]
// CHECK: _start: // CHECK: <_start>:
// CHECK-NEXT: 210158: mrs x8, TPIDR_EL0 // CHECK-NEXT: 210158: mrs x8, TPIDR_EL0
// 0x0 + c10 = 0xc10 = tcb (16-bytes) + var0 // 0x0 + c10 = 0xc10 = tcb (16-bytes) + var0
// CHECK-NEXT: 21015c: add x8, x8, #0, lsl #12 // CHECK-NEXT: 21015c: add x8, x8, #0, lsl #12
// CHECK-NEXT: 210160: ldr q20, [x8, #3088] // CHECK-NEXT: 210160: ldr q20, [x8, #3088]
// 0x1000 + 0x820 = 0x1820 = tcb + var1 // 0x1000 + 0x820 = 0x1820 = tcb + var1
// CHECK-NEXT: 210164: add x8, x8, #1, lsl #12 // CHECK-NEXT: 210164: add x8, x8, #1, lsl #12
// CHECK-NEXT: 210168: ldr x0, [x8, #2080] // CHECK-NEXT: 210168: ldr x0, [x8, #2080]
// 0x2000 + 0x428 = 0x2428 = tcb + var2 // 0x2000 + 0x428 = 0x2428 = tcb + var2
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

lld/test/ELF/aarch64-tstbr14-reloc.s

# REQUIRES: aarch64 # REQUIRES: aarch64
# RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %p/Inputs/aarch64-tstbr14-reloc.s -o %t1 # RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %p/Inputs/aarch64-tstbr14-reloc.s -o %t1
# RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %s -o %t2 # RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %s -o %t2
# RUN: ld.lld %t1 %t2 -o %t # RUN: ld.lld %t1 %t2 -o %t
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
# RUN: ld.lld -shared %t1 %t2 -o %t3 # RUN: ld.lld -shared %t1 %t2 -o %t3
# RUN: llvm-objdump -d --no-show-raw-insn %t3 | FileCheck -check-prefix=DSO %s # RUN: llvm-objdump -d --no-show-raw-insn %t3 | FileCheck -check-prefix=DSO %s
# RUN: llvm-readobj -S -r %t3 | FileCheck -check-prefix=DSOREL %s # RUN: llvm-readobj -S -r %t3 | FileCheck -check-prefix=DSOREL %s
# CHECK: _foo: # CHECK: <_foo>:
# CHECK-NEXT: 210120: nop # CHECK-NEXT: 210120: nop
# CHECK-NEXT: 210124: nop # CHECK-NEXT: 210124: nop
# CHECK-NEXT: 210128: nop # CHECK-NEXT: 210128: nop
# CHECK-NEXT: 21012c: nop # CHECK-NEXT: 21012c: nop
# CHECK: _bar: # CHECK: <_bar>:
# CHECK-NEXT: 210130: nop # CHECK-NEXT: 210130: nop
# CHECK-NEXT: 210134: nop # CHECK-NEXT: 210134: nop
# CHECK-NEXT: 210138: nop # CHECK-NEXT: 210138: nop
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: 21013c: tbnz w3, #15, #-28 <_foo> # CHECK-NEXT: 21013c: tbnz w3, #15, #-28 <_foo>
# CHECK-NEXT: 210140: tbnz w3, #15, #-16 <_bar> # CHECK-NEXT: 210140: tbnz w3, #15, #-16 <_bar>
# CHECK-NEXT: 210144: tbz x6, #45, #-36 <_foo> # CHECK-NEXT: 210144: tbz x6, #45, #-36 <_foo>
# CHECK-NEXT: 210148: tbz x6, #45, #-24 <_bar> # CHECK-NEXT: 210148: tbz x6, #45, #-24 <_bar>
#DSOREL: Section { #DSOREL: Section {
#DSOREL: Index: #DSOREL: Index:
#DSOREL: Name: .got.plt #DSOREL: Name: .got.plt
Show All 14 Lines
#DSOREL-NEXT: Section ({{.*}}) .rela.plt { #DSOREL-NEXT: Section ({{.*}}) .rela.plt {
#DSOREL-NEXT: 0x30438 R_AARCH64_JUMP_SLOT _foo #DSOREL-NEXT: 0x30438 R_AARCH64_JUMP_SLOT _foo
#DSOREL-NEXT: 0x30440 R_AARCH64_JUMP_SLOT _bar #DSOREL-NEXT: 0x30440 R_AARCH64_JUMP_SLOT _bar
#DSOREL-NEXT: } #DSOREL-NEXT: }
#DSOREL-NEXT:] #DSOREL-NEXT:]
#DSO: Disassembly of section .text: #DSO: Disassembly of section .text:
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: _foo: #DSO-NEXT: <_foo>:
#DSO-NEXT: 102f8: nop #DSO-NEXT: 102f8: nop
#DSO-NEXT: 102fc: nop #DSO-NEXT: 102fc: nop
#DSO-NEXT: 10300: nop #DSO-NEXT: 10300: nop
#DSO-NEXT: 10304: nop #DSO-NEXT: 10304: nop
#DSO: _bar: #DSO: <_bar>:
#DSO-NEXT: 10308: nop #DSO-NEXT: 10308: nop
#DSO-NEXT: 1030c: nop #DSO-NEXT: 1030c: nop
#DSO-NEXT: 10310: nop #DSO-NEXT: 10310: nop
#DSO: _start: #DSO: <_start>:
#DSO-NEXT: 10314: tbnz w3, #15, #60 <_foo@plt> #DSO-NEXT: 10314: tbnz w3, #15, #60 <_foo@plt>
#DSO-NEXT: 10318: tbnz w3, #15, #72 <_bar@plt> #DSO-NEXT: 10318: tbnz w3, #15, #72 <_bar@plt>
#DSO-NEXT: 1031c: tbz x6, #45, #52 <_foo@plt> #DSO-NEXT: 1031c: tbz x6, #45, #52 <_foo@plt>
#DSO-NEXT: 10320: tbz x6, #45, #64 <_bar@plt> #DSO-NEXT: 10320: tbz x6, #45, #64 <_bar@plt>
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: Disassembly of section .plt: #DSO-NEXT: Disassembly of section .plt:
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: .plt: #DSO-NEXT: <.plt>:
#DSO-NEXT: 10330: stp x16, x30, [sp, #-16]! #DSO-NEXT: 10330: stp x16, x30, [sp, #-16]!
#DSO-NEXT: 10334: adrp x16, #131072 #DSO-NEXT: 10334: adrp x16, #131072
#DSO-NEXT: 10338: ldr x17, [x16, #1072] #DSO-NEXT: 10338: ldr x17, [x16, #1072]
#DSO-NEXT: 1033c: add x16, x16, #1072 #DSO-NEXT: 1033c: add x16, x16, #1072
#DSO-NEXT: 10340: br x17 #DSO-NEXT: 10340: br x17
#DSO-NEXT: 10344: nop #DSO-NEXT: 10344: nop
#DSO-NEXT: 10348: nop #DSO-NEXT: 10348: nop
#DSO-NEXT: 1034c: nop #DSO-NEXT: 1034c: nop
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: _foo@plt: #DSO-NEXT: <_foo@plt>:
#DSO-NEXT: 10350: adrp x16, #131072 #DSO-NEXT: 10350: adrp x16, #131072
#DSO-NEXT: 10354: ldr x17, [x16, #1080] #DSO-NEXT: 10354: ldr x17, [x16, #1080]
#DSO-NEXT: 10358: add x16, x16, #1080 #DSO-NEXT: 10358: add x16, x16, #1080
#DSO-NEXT: 1035c: br x17 #DSO-NEXT: 1035c: br x17
#DSO-EMPTY: #DSO-EMPTY:
#DSO-NEXT: _bar@plt: #DSO-NEXT: <_bar@plt>:
#DSO-NEXT: 10360: adrp x16, #131072 #DSO-NEXT: 10360: adrp x16, #131072
#DSO-NEXT: 10364: ldr x17, [x16, #1088] #DSO-NEXT: 10364: ldr x17, [x16, #1088]
#DSO-NEXT: 10368: add x16, x16, #1088 #DSO-NEXT: 10368: add x16, x16, #1088
#DSO-NEXT: 1036c: br x17 #DSO-NEXT: 1036c: br x17
.globl _start .globl _start
_start: _start:
tbnz w3, #15, _foo tbnz w3, #15, _foo
tbnz w3, #15, _bar tbnz w3, #15, _bar
tbz x6, #45, _foo tbz x6, #45, _foo
tbz x6, #45, _bar tbz x6, #45, _bar

lld/test/ELF/aarch64-undefined-weak.s

Show All 30 Lines
.word target - . .word target - .
// R_AARCH64_PREL64 // R_AARCH64_PREL64
.xword target - . .xword target - .
// R_AARCH64_PREL16 // R_AARCH64_PREL16
.hword target - . .hword target - .
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: 0000000010010120 _start: // CHECK-NEXT: 0000000010010120 <_start>:
// CHECK-NEXT: 10010120: b #4 // CHECK-NEXT: 10010120: b #4
// CHECK-NEXT: 10010124: bl #4 // CHECK-NEXT: 10010124: bl #4
// CHECK-NEXT: 10010128: b.eq #4 // CHECK-NEXT: 10010128: b.eq #4
// CHECK-NEXT: 1001012c: cbz x1, #4 // CHECK-NEXT: 1001012c: cbz x1, #4
// CHECK-NEXT: 10010130: adr x0, #0 // CHECK-NEXT: 10010130: adr x0, #0
// CHECK-NEXT: 10010134: adrp x0, #0 // CHECK-NEXT: 10010134: adrp x0, #0
// CHECK-NEXT: 10010138: ldr x8, #0 // CHECK-NEXT: 10010138: ldr x8, #0
// CHECK: 1001013c: 00 00 00 00 .word 0x00000000 // CHECK: 1001013c: 00 00 00 00 .word 0x00000000
// CHECK-NEXT: 10010140: 00 00 00 00 .word 0x00000000 // CHECK-NEXT: 10010140: 00 00 00 00 .word 0x00000000
// CHECK-NEXT: 10010144: 00 00 00 00 .word 0x00000000 // CHECK-NEXT: 10010144: 00 00 00 00 .word 0x00000000
// CHECK-NEXT: 10010148: 00 00 .short 0x0000 // CHECK-NEXT: 10010148: 00 00 .short 0x0000

lld/test/ELF/allow-multiple-definition.s

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# RUN: llvm-objdump -d %t4 | FileCheck -check-prefix=REVERT %s # RUN: llvm-objdump -d %t4 | FileCheck -check-prefix=REVERT %s
# inputs contain different constants for instuction movl. # inputs contain different constants for instuction movl.
# Tests below checks that order of files in command line # Tests below checks that order of files in command line
# affects on what symbol will be used. # affects on what symbol will be used.
# If flag allow-multiple-definition is enabled the first # If flag allow-multiple-definition is enabled the first
# meet symbol should be used. # meet symbol should be used.
# CHECK: _bar: # CHECK: <_bar>:
# CHECK-NEXT: movl $1, %eax # CHECK-NEXT: movl $1, %eax
# REVERT: _bar: # REVERT: <_bar>:
# REVERT-NEXT: movl $2, %eax # REVERT-NEXT: movl $2, %eax
.globl _bar .globl _bar
.type _bar, @function .type _bar, @function
_bar: _bar:
mov $1, %eax mov $1, %eax
.globl _start .globl _start
_start: _start:

lld/test/ELF/arm-bl-v6-inrange.s

Show All 22 Lines_start:
.section .callee_low, "ax", %progbits .section .callee_low, "ax", %progbits
.globl thumbfunc .globl thumbfunc
.type thumbfunc, %function .type thumbfunc, %function
thumbfunc: thumbfunc:
bx lr bx lr
// CHECK: Disassembly of section .callee1: // CHECK: Disassembly of section .callee1:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: thumbfunc: // CHECK-NEXT: <thumbfunc>:
// CHECK-NEXT: 100004: 70 47 bx lr // CHECK-NEXT: 100004: 70 47 bx lr
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: Disassembly of section .caller: // CHECK-NEXT: Disassembly of section .caller:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 500000: 00 f4 00 f8 bl #-4194304 // CHECK-NEXT: 500000: 00 f4 00 f8 bl #-4194304
// CHECK-NEXT: 500004: ff f3 fe ef blx #4194300 // CHECK-NEXT: 500004: ff f3 fe ef blx #4194300
// CHECK-NEXT: 500008: 70 47 bx lr // CHECK-NEXT: 500008: 70 47 bx lr
.arm .arm
.section .callee_high, "ax", %progbits .section .callee_high, "ax", %progbits
.globl armfunc .globl armfunc
.type armfunc, %function .type armfunc, %function
armfunc: armfunc:
bx lr bx lr
// CHECK: Disassembly of section .callee2: // CHECK: Disassembly of section .callee2:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: armfunc: // CHECK-NEXT: <armfunc>:
// CHECK-NEXT: 900004: 1e ff 2f e1 bx lr // CHECK-NEXT: 900004: 1e ff 2f e1 bx lr

lld/test/ELF/arm-bl-v6.s

Show All 21 Lines
.type _start,%function .type _start,%function
.balign 0x1000 .balign 0x1000
_start: _start:
bl thumbfunc bl thumbfunc
bx lr bx lr
// CHECK-ARM1: Disassembly of section .text: // CHECK-ARM1: Disassembly of section .text:
// CHECK-ARM1-EMPTY: // CHECK-ARM1-EMPTY:
// CHECK-ARM1-NEXT: _start: // CHECK-ARM1-NEXT: <_start>:
// CHECK-ARM1-NEXT: 12000: 00 00 00 fa blx #0 <thumbfunc> // CHECK-ARM1-NEXT: 12000: 00 00 00 fa blx #0 <thumbfunc>
// CHECK-ARM1-NEXT: 12004: 1e ff 2f e1 bx lr // CHECK-ARM1-NEXT: 12004: 1e ff 2f e1 bx lr
.thumb .thumb
.section .text.2, "ax", %progbits .section .text.2, "ax", %progbits
.globl thumbfunc .globl thumbfunc
.type thumbfunc,%function .type thumbfunc,%function
thumbfunc: thumbfunc:
bl farthumbfunc bl farthumbfunc
// CHECK-THUMB1: thumbfunc: // CHECK-THUMB1: <thumbfunc>:
// CHECK-THUMB1-NEXT: 12008: 00 f2 00 e8 blx #2097152 // CHECK-THUMB1-NEXT: 12008: 00 f2 00 e8 blx #2097152
// 6 Megabytes, enough to make farthumbfunc out of range of caller // 6 Megabytes, enough to make farthumbfunc out of range of caller
// on a v6 Arm, but not on a v7 Arm. // on a v6 Arm, but not on a v7 Arm.
.section .text.3, "ax", %progbits .section .text.3, "ax", %progbits
.space 0x200000 .space 0x200000
// CHECK-ARM2: __ARMv5ABSLongThunk_farthumbfunc: // CHECK-ARM2: <__ARMv5ABSLongThunk_farthumbfunc>:
// CHECK-ARM2-NEXT: 21200c: 04 f0 1f e5 ldr pc, [pc, #-4] // CHECK-ARM2-NEXT: 21200c: 04 f0 1f e5 ldr pc, [pc, #-4]
// CHECK-ARM2: $d: // CHECK-ARM2: <$d>:
// CHECK-ARM2-NEXT: 212010: 01 30 61 00 .word 0x00613001 // CHECK-ARM2-NEXT: 212010: 01 30 61 00 .word 0x00613001
.section .text.4, "ax", %progbits .section .text.4, "ax", %progbits
.space 0x200000 .space 0x200000
.section .text.5, "ax", %progbits .section .text.5, "ax", %progbits
.space 0x200000 .space 0x200000
.thumb .thumb
.section .text.6, "ax", %progbits .section .text.6, "ax", %progbits
.balign 0x1000 .balign 0x1000
.globl farthumbfunc .globl farthumbfunc
.type farthumbfunc,%function .type farthumbfunc,%function
farthumbfunc: farthumbfunc:
bx lr bx lr
// CHECK-THUMB2: farthumbfunc: // CHECK-THUMB2: <farthumbfunc>:
// CHECK-THUMB2-NEXT: 613000: 70 47 bx lr // CHECK-THUMB2-NEXT: 613000: 70 47 bx lr

lld/test/ELF/arm-blx.s

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
.arm .arm
.balign 0x100 .balign 0x100
.type callee_arm_high,%function .type callee_arm_high,%function
callee_arm_high: callee_arm_high:
bx lr bx lr
// CHECK: Disassembly of section .callee1: // CHECK: Disassembly of section .callee1:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: callee_low: // CHECK-NEXT: <callee_low>:
// CHECK-NEXT: b4: 70 47 bx lr // CHECK-NEXT: b4: 70 47 bx lr
// CHECK: callee_low2: // CHECK: <callee_low2>:
// CHECK-NEXT: b6: 70 47 bx lr // CHECK-NEXT: b6: 70 47 bx lr
// CHECK: Disassembly of section .callee2: // CHECK: Disassembly of section .callee2:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: callee_arm_low: // CHECK-NEXT: <callee_arm_low>:
// CHECK-NEXT: 100: 1e ff 2f e1 bx lr // CHECK-NEXT: 100: 1e ff 2f e1 bx lr
// CHECK: Disassembly of section .caller: // CHECK: Disassembly of section .caller:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 10000: 2b c0 ff fa blx #-65364 <callee_low> // CHECK-NEXT: 10000: 2b c0 ff fa blx #-65364 <callee_low>
// CHECK-NEXT: 10004: 2a c0 ff fa blx #-65368 <callee_low> // CHECK-NEXT: 10004: 2a c0 ff fa blx #-65368 <callee_low>
// CHECK-NEXT: 10008: 29 c0 ff fb blx #-65370 <callee_low2> // CHECK-NEXT: 10008: 29 c0 ff fb blx #-65370 <callee_low2>
// CHECK-NEXT: 1000c: 28 c0 ff fb blx #-65374 <callee_low2> // CHECK-NEXT: 1000c: 28 c0 ff fb blx #-65374 <callee_low2>
// CHECK-NEXT: 10010: 3a 00 00 fa blx #232 <callee_high> // CHECK-NEXT: 10010: 3a 00 00 fa blx #232 <callee_high>
// CHECK-NEXT: 10014: 39 00 00 fa blx #228 <callee_high> // CHECK-NEXT: 10014: 39 00 00 fa blx #228 <callee_high>
// CHECK-NEXT: 10018: 38 00 00 fb blx #226 <callee_high2> // CHECK-NEXT: 10018: 38 00 00 fb blx #226 <callee_high2>
// CHECK-NEXT: 1001c: 37 00 00 fb blx #222 <callee_high2> // CHECK-NEXT: 1001c: 37 00 00 fb blx #222 <callee_high2>
// 10020 + 1FFFFFC + 8 = 0x2010024 = blx_far // 10020 + 1FFFFFC + 8 = 0x2010024 = blx_far
// CHECK-NEXT: 10020: ff ff 7f fa blx #33554428 // CHECK-NEXT: 10020: ff ff 7f fa blx #33554428
// 10024 + 1FFFFFC + 8 = 0x2010028 = blx_far2 // 10024 + 1FFFFFC + 8 = 0x2010028 = blx_far2
// CHECK-NEXT: 10024: ff ff 7f fa blx #33554428 // CHECK-NEXT: 10024: ff ff 7f fa blx #33554428
// CHECK-NEXT: 10028: 34 c0 ff eb bl #-65328 <callee_arm_low> // CHECK-NEXT: 10028: 34 c0 ff eb bl #-65328 <callee_arm_low>
// CHECK-NEXT: 1002c: 33 c0 ff eb bl #-65332 <callee_arm_low> // CHECK-NEXT: 1002c: 33 c0 ff eb bl #-65332 <callee_arm_low>
// CHECK-NEXT: 10030: 72 00 00 eb bl #456 <callee_arm_high> // CHECK-NEXT: 10030: 72 00 00 eb bl #456 <callee_arm_high>
// CHECK-NEXT: 10034: 71 00 00 eb bl #452 <callee_arm_high> // CHECK-NEXT: 10034: 71 00 00 eb bl #452 <callee_arm_high>
// CHECK-NEXT: 10038: 1e ff 2f e1 bx lr // CHECK-NEXT: 10038: 1e ff 2f e1 bx lr
// CHECK: Disassembly of section .callee3: // CHECK: Disassembly of section .callee3:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK: callee_high: // CHECK: <callee_high>:
// CHECK-NEXT: 10100: 70 47 bx lr // CHECK-NEXT: 10100: 70 47 bx lr
// CHECK: callee_high2: // CHECK: <callee_high2>:
// CHECK-NEXT: 10102: 70 47 bx lr // CHECK-NEXT: 10102: 70 47 bx lr
// CHECK: Disassembly of section .callee4: // CHECK: Disassembly of section .callee4:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: callee_arm_high: // CHECK-NEXT: <callee_arm_high>:
// CHECK-NEXT: 10200: 1e ff 2f e1 bx lr // CHECK-NEXT: 10200: 1e ff 2f e1 bx lr

lld/test/ELF/arm-branch-rangethunk.s

Show All 14 Lines
// address of too_far symbols are just out of range of ARM branch with // address of too_far symbols are just out of range of ARM branch with
// 26-bit immediate field and an addend of -8 // 26-bit immediate field and an addend of -8
bl too_far1 bl too_far1
b too_far2 b too_far2
beq too_far3 beq too_far3
// SHORT: Disassembly of section .text: // SHORT: Disassembly of section .text:
// SHORT-EMPTY: // SHORT-EMPTY:
// SHORT-NEXT: _start: // SHORT-NEXT: <_start>:
// SHORT-NEXT: 20000: 01 00 00 eb bl #4 <__ARMv7ABSLongThunk_too_far1> // SHORT-NEXT: 20000: 01 00 00 eb bl #4 <__ARMv7ABSLongThunk_too_far1>
// SHORT-NEXT: 20004: 01 00 00 ea b #4 <__ARMv7ABSLongThunk_too_far2> // SHORT-NEXT: 20004: 01 00 00 ea b #4 <__ARMv7ABSLongThunk_too_far2>
// SHORT-NEXT: 20008: 01 00 00 0a beq #4 <__ARMv7ABSLongThunk_too_far3> // SHORT-NEXT: 20008: 01 00 00 0a beq #4 <__ARMv7ABSLongThunk_too_far3>
// SHORT: __ARMv7ABSLongThunk_too_far1: // SHORT: <__ARMv7ABSLongThunk_too_far1>:
// SHORT-NEXT: 2000c: fd ff 7f ea b #33554420 <__ARMv7ABSLongThunk_too_far3+0x1fffff4> // SHORT-NEXT: 2000c: fd ff 7f ea b #33554420 <__ARMv7ABSLongThunk_too_far3+0x1fffff4>
// SHORT: __ARMv7ABSLongThunk_too_far2: // SHORT: <__ARMv7ABSLongThunk_too_far2>:
// SHORT-NEXT: 20010: fd ff 7f ea b #33554420 <__ARMv7ABSLongThunk_too_far3+0x1fffff8> // SHORT-NEXT: 20010: fd ff 7f ea b #33554420 <__ARMv7ABSLongThunk_too_far3+0x1fffff8>
// SHORT: __ARMv7ABSLongThunk_too_far3: // SHORT: <__ARMv7ABSLongThunk_too_far3>:
// SHORT-NEXT: 20014: fd ff 7f ea b #33554420 <__ARMv7ABSLongThunk_too_far3+0x1fffffc> // SHORT-NEXT: 20014: fd ff 7f ea b #33554420 <__ARMv7ABSLongThunk_too_far3+0x1fffffc>
// LONG: Disassembly of section .text: // LONG: Disassembly of section .text:
// LONG-EMPTY: // LONG-EMPTY:
// LONG-NEXT: _start: // LONG-NEXT: <_start>:
// LONG-NEXT: 20000: 01 00 00 eb bl #4 <__ARMv7ABSLongThunk_too_far1> // LONG-NEXT: 20000: 01 00 00 eb bl #4 <__ARMv7ABSLongThunk_too_far1>
// LONG-NEXT: 20004: 03 00 00 ea b #12 <__ARMv7ABSLongThunk_too_far2> // LONG-NEXT: 20004: 03 00 00 ea b #12 <__ARMv7ABSLongThunk_too_far2>
// LONG-NEXT: 20008: 05 00 00 0a beq #20 <__ARMv7ABSLongThunk_too_far3> // LONG-NEXT: 20008: 05 00 00 0a beq #20 <__ARMv7ABSLongThunk_too_far3>
// LONG: __ARMv7ABSLongThunk_too_far1: // LONG: <__ARMv7ABSLongThunk_too_far1>:
// LONG-NEXT: 2000c: 14 c0 00 e3 movw r12, #20 // LONG-NEXT: 2000c: 14 c0 00 e3 movw r12, #20
// LONG-NEXT: 20010: 02 c2 40 e3 movt r12, #514 // LONG-NEXT: 20010: 02 c2 40 e3 movt r12, #514
// LONG-NEXT: 20014: 1c ff 2f e1 bx r12 // LONG-NEXT: 20014: 1c ff 2f e1 bx r12
// LONG: __ARMv7ABSLongThunk_too_far2: // LONG: <__ARMv7ABSLongThunk_too_far2>:
// LONG-NEXT: 20018: 20 c0 00 e3 movw r12, #32 // LONG-NEXT: 20018: 20 c0 00 e3 movw r12, #32
// LONG-NEXT: 2001c: 02 c2 40 e3 movt r12, #514 // LONG-NEXT: 2001c: 02 c2 40 e3 movt r12, #514
// LONG-NEXT: 20020: 1c ff 2f e1 bx r12 // LONG-NEXT: 20020: 1c ff 2f e1 bx r12
// LONG: __ARMv7ABSLongThunk_too_far3: // LONG: <__ARMv7ABSLongThunk_too_far3>:
// LONG-NEXT: 20024: 2c c0 00 e3 movw r12, #44 // LONG-NEXT: 20024: 2c c0 00 e3 movw r12, #44
// LONG-NEXT: 20028: 02 c2 40 e3 movt r12, #514 // LONG-NEXT: 20028: 02 c2 40 e3 movt r12, #514
// LONG-NEXT: 2002c: 1c ff 2f e1 bx r12 // LONG-NEXT: 2002c: 1c ff 2f e1 bx r12

lld/test/ELF/arm-branch-undef-weak-plt-thunk.s

Show All 17 Lines
bl bar2 bl bar2
// Create 32 Mb gap between the call to the weak reference and the PLT so that // Create 32 Mb gap between the call to the weak reference and the PLT so that
// the b and bl need a range-extension thunk. // the b and bl need a range-extension thunk.
.section .text.1, "ax", %progbits .section .text.1, "ax", %progbits
.space 32 * 1024 * 1024 .space 32 * 1024 * 1024
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 111e4: 00 00 00 ea b #0 <__ARMv7ABSLongThunk_undefined_weak_we_expect_a_plt_entry_for> // CHECK-NEXT: 111e4: 00 00 00 ea b #0 <__ARMv7ABSLongThunk_undefined_weak_we_expect_a_plt_entry_for>
// CHECK-NEXT: 111e8: 02 00 00 eb bl #8 <__ARMv7ABSLongThunk_bar2> // CHECK-NEXT: 111e8: 02 00 00 eb bl #8 <__ARMv7ABSLongThunk_bar2>
// CHECK: __ARMv7ABSLongThunk_undefined_weak_we_expect_a_plt_entry_for: // CHECK: <__ARMv7ABSLongThunk_undefined_weak_we_expect_a_plt_entry_for>:
// CHECK-NEXT: 111ec: 30 c2 01 e3 movw r12, #4656 // CHECK-NEXT: 111ec: 30 c2 01 e3 movw r12, #4656
// CHECK-NEXT: 111f0: 01 c2 40 e3 movt r12, #513 // CHECK-NEXT: 111f0: 01 c2 40 e3 movt r12, #513
// CHECK-NEXT: 111f4: 1c ff 2f e1 bx r12 // CHECK-NEXT: 111f4: 1c ff 2f e1 bx r12
// CHECK: __ARMv7ABSLongThunk_bar2: // CHECK: <__ARMv7ABSLongThunk_bar2>:
// CHECK-NEXT: 111f8: 40 c2 01 e3 movw r12, #4672 // CHECK-NEXT: 111f8: 40 c2 01 e3 movw r12, #4672
// CHECK-NEXT: 111fc: 01 c2 40 e3 movt r12, #513 // CHECK-NEXT: 111fc: 01 c2 40 e3 movt r12, #513
// CHECK-NEXT: 11200: 1c ff 2f e1 bx r12 // CHECK-NEXT: 11200: 1c ff 2f e1 bx r12

lld/test/ELF/arm-branch.s

Show All 33 Lines
.section .callee_high, "ax",%progbits .section .callee_high, "ax",%progbits
.align 2 .align 2
.type callee_high,%function .type callee_high,%function
callee_high: callee_high:
bx lr bx lr
// CHECK: Disassembly of section .caller: // CHECK: Disassembly of section .caller:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// S(callee_low) = 0xb4 P = 0x10000 A = -8 = -0xff54 = -65364 // S(callee_low) = 0xb4 P = 0x10000 A = -8 = -0xff54 = -65364
// CHECK-NEXT: 10000: 2b c0 ff eb bl #-65364 <callee_low> // CHECK-NEXT: 10000: 2b c0 ff eb bl #-65364 <callee_low>
// S(callee_low) = 0xb4 P = 0x10004 A = -8 = -0xff58 = -65368 // S(callee_low) = 0xb4 P = 0x10004 A = -8 = -0xff58 = -65368
// CHECK-NEXT: 10004: 2a c0 ff ea b #-65368 <callee_low> // CHECK-NEXT: 10004: 2a c0 ff ea b #-65368 <callee_low>
// S(callee_low) = 0xb4 P = 0x10008 A = -8 = -0xff5c -65372 // S(callee_low) = 0xb4 P = 0x10008 A = -8 = -0xff5c -65372
// CHECK-NEXT: 10008: 29 c0 ff 0a beq #-65372 <callee_low> // CHECK-NEXT: 10008: 29 c0 ff 0a beq #-65372 <callee_low>
// S(callee_high) = 0x10028 P = 0x1000c A = -8 = 0x14 = 20 // S(callee_high) = 0x10028 P = 0x1000c A = -8 = 0x14 = 20
// CHECK-NEXT: 1000c: 05 00 00 eb bl #20 <callee_high> // CHECK-NEXT: 1000c: 05 00 00 eb bl #20 <callee_high>
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lld/test/ELF/arm-copy.s

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
// CHECK-NEXT: Size: 4 // CHECK-NEXT: Size: 4
// CHECK-NEXT: Binding: Global // CHECK-NEXT: Binding: Global
// CHECK-NEXT: Type: Object // CHECK-NEXT: Type: Object
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .bss // CHECK-NEXT: Section: .bss
// CODE: Disassembly of section .text: // CODE: Disassembly of section .text:
// CODE-EMPTY: // CODE-EMPTY:
// CODE-NEXT: _start: // CODE-NEXT: <_start>:
// S + A = 0x13220 + 0 = 65536 * 1 + 12832 // S + A = 0x13220 + 0 = 65536 * 1 + 12832
// CODE-NEXT: 111b4: movw r2, #12832 // CODE-NEXT: 111b4: movw r2, #12832
// CODE-NEXT: 111b8: movt r2, #1 // CODE-NEXT: 111b8: movt r2, #1
// CODE-NEXT: 111bc: ldr r3, [pc, #4] // CODE-NEXT: 111bc: ldr r3, [pc, #4]
// CODE-NEXT: 111c0: ldr r3, [r3] // CODE-NEXT: 111c0: ldr r3, [r3]
// RODATA: Contents of section .rodata: // RODATA: Contents of section .rodata:
// S(z) = 0x13004 // S(z) = 0x13004
// RODATA-NEXT: 101b0 24320100 // RODATA-NEXT: 101b0 24320100

lld/test/ELF/arm-exidx-canunwind.s

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
.global _start .global _start
_start: _start:
bl func1 bl func1
bl func2 bl func2
bx lr bx lr
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 11108: bl #4 <func1> // CHECK-NEXT: 11108: bl #4 <func1>
// CHECK-NEXT: bl #4 <func2> // CHECK-NEXT: bl #4 <func2>
// CHECK-NEXT: bx lr // CHECK-NEXT: bx lr
// CHECK: func1: // CHECK: <func1>:
// CHECK-NEXT: 11114: bx lr // CHECK-NEXT: 11114: bx lr
// CHECK: func2: // CHECK: <func2>:
// CHECK-NEXT: 11118: bx lr // CHECK-NEXT: 11118: bx lr
// CHECK: __gxx_personality_v0: // CHECK: <__gxx_personality_v0>:
// CHECK-NEXT: 1111c: bx lr // CHECK-NEXT: 1111c: bx lr
// CHECK: __aeabi_unwind_cpp_pr0: // CHECK: <__aeabi_unwind_cpp_pr0>:
// CHECK-NEXT: 11120: bx lr // CHECK-NEXT: 11120: bx lr
// 100d4 + 0x1034 = 0x11108 = main (linker generated cantunwind) // 100d4 + 0x1034 = 0x11108 = main (linker generated cantunwind)
// 100dc + 0x1038 = 0x11114 = func1 (inline unwinding data) // 100dc + 0x1038 = 0x11114 = func1 (inline unwinding data)
// CHECK-EXIDX: 100d4 34100000 01000000 38100000 08849780 // CHECK-EXIDX: 100d4 34100000 01000000 38100000 08849780
// 100e4 + 0x1034 = 0x11118 = func2 (100e8 + 14 = 100fc = .ARM.extab entry) // 100e4 + 0x1034 = 0x11118 = func2 (100e8 + 14 = 100fc = .ARM.extab entry)
// 100ec + 0x1030 = 0x1111c = __gxx_personality_v0 (linker generated cantunwind) // 100ec + 0x1030 = 0x1111c = __gxx_personality_v0 (linker generated cantunwind)
// CHECK-EXIDX-NEXT: 100e4 34100000 14000000 30100000 01000000 // CHECK-EXIDX-NEXT: 100e4 34100000 14000000 30100000 01000000
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lld/test/ELF/arm-exidx-gc.s

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
bl func2 bl func2
bx lr bx lr
// GC should have only removed unusedfunc1 and unusedfunc2 the personality // GC should have only removed unusedfunc1 and unusedfunc2 the personality
// routines are kept alive by references from live .ARM.exidx and .ARM.extab // routines are kept alive by references from live .ARM.exidx and .ARM.extab
// sections // sections
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 1110c: bl #4 <func1> // CHECK-NEXT: 1110c: bl #4 <func1>
// CHECK-NEXT: 11110: bl #4 <func2> // CHECK-NEXT: 11110: bl #4 <func2>
// CHECK-NEXT: 11114: bx lr // CHECK-NEXT: 11114: bx lr
// CHECK: func1: // CHECK: <func1>:
// CHECK-NEXT: 11118: bx lr // CHECK-NEXT: 11118: bx lr
// CHECK: func2: // CHECK: <func2>:
// CHECK-NEXT: 1111c: bx lr // CHECK-NEXT: 1111c: bx lr
// CHECK: __gxx_personality_v0: // CHECK: <__gxx_personality_v0>:
// CHECK-NEXT: 11120: bx lr // CHECK-NEXT: 11120: bx lr
// CHECK: __aeabi_unwind_cpp_pr0: // CHECK: <__aeabi_unwind_cpp_pr0>:
// CHECK-NEXT: 11124: bx lr // CHECK-NEXT: 11124: bx lr
// GC should have removed table entries for unusedfunc1, unusedfunc2 // GC should have removed table entries for unusedfunc1, unusedfunc2
// and __gxx_personality_v1 // and __gxx_personality_v1
// CHECK-NOT: unusedfunc1 // CHECK-NOT: unusedfunc1
// CHECK-NOT: unusedfunc2 // CHECK-NOT: unusedfunc2
// CHECK-NOT: __gxx_personality_v1 // CHECK-NOT: __gxx_personality_v1
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lld/test/ELF/arm-exidx-order.s

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
bx lr bx lr
.cantunwind .cantunwind
.fnend .fnend
// Check default no linker script order. // Check default no linker script order.
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK: _start: // CHECK: <_start>:
// CHECK-NEXT: 11124: bx lr // CHECK-NEXT: 11124: bx lr
// CHECK: f1: // CHECK: <f1>:
// CHECK-NEXT: 11128: bx lr // CHECK-NEXT: 11128: bx lr
// CHECK: f2: // CHECK: <f2>:
// CHECK-NEXT: 1112c: bx lr // CHECK-NEXT: 1112c: bx lr
// CHECK: f3: // CHECK: <f3>:
// CHECK-NEXT: 11130: bx lr // CHECK-NEXT: 11130: bx lr
// CHECK: func4: // CHECK: <func4>:
// CHECK-NEXT: 11134: bx lr // CHECK-NEXT: 11134: bx lr
// CHECK: func5: // CHECK: <func5>:
// CHECK-NEXT: 11138: bx lr // CHECK-NEXT: 11138: bx lr
// CHECK: Disassembly of section .func1: // CHECK: Disassembly of section .func1:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: func1: // CHECK-NEXT: <func1>:
// CHECK-NEXT: 1113c: bx lr // CHECK-NEXT: 1113c: bx lr
// CHECK: Disassembly of section .func2: // CHECK: Disassembly of section .func2:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: func2: // CHECK-NEXT: <func2>:
// CHECK-NEXT: 11140: bx lr // CHECK-NEXT: 11140: bx lr
// CHECK: Disassembly of section .func3: // CHECK: Disassembly of section .func3:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: func3: // CHECK-NEXT: <func3>:
// CHECK-NEXT: 11144: bx lr // CHECK-NEXT: 11144: bx lr
// Each .ARM.exidx section has two 4 byte fields // Each .ARM.exidx section has two 4 byte fields
// Field 1 is the 31-bit offset to the function. The top bit is used to // Field 1 is the 31-bit offset to the function. The top bit is used to
// indicate whether Field 2 is a pointer or an inline table entry. // indicate whether Field 2 is a pointer or an inline table entry.
// Field 2 is either a pointer to a .ARM.extab section or an inline table // Field 2 is either a pointer to a .ARM.extab section or an inline table
// In this example all Field 2 entries are inline can't unwind (0x1) // In this example all Field 2 entries are inline can't unwind (0x1)
// We expect to see the entries in the same order as the functions // We expect to see the entries in the same order as the functions
Show All 39 Lines
// CHECK-PT-NEXT: } // CHECK-PT-NEXT: }
// Check linker script order. The .ARM.exidx section will be inserted after // Check linker script order. The .ARM.exidx section will be inserted after
// the .text section but before the orphan sections // the .text section but before the orphan sections
// CHECK-SCRIPT: Disassembly of section .text: // CHECK-SCRIPT: Disassembly of section .text:
// CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-EMPTY:
// CHECK-SCRIPT-NEXT: func4: // CHECK-SCRIPT-NEXT: <func4>:
// CHECK-SCRIPT-NEXT: 11000: 1e ff 2f e1 bx lr // CHECK-SCRIPT-NEXT: 11000: 1e ff 2f e1 bx lr
// CHECK-SCRIPT: func5: // CHECK-SCRIPT: <func5>:
// CHECK-SCRIPT-NEXT: 11004: 1e ff 2f e1 bx lr // CHECK-SCRIPT-NEXT: 11004: 1e ff 2f e1 bx lr
// CHECK-SCRIPT: _start: // CHECK-SCRIPT: <_start>:
// CHECK-SCRIPT-NEXT: 11008: 1e ff 2f e1 bx lr // CHECK-SCRIPT-NEXT: 11008: 1e ff 2f e1 bx lr
// CHECK-SCRIPT: f1: // CHECK-SCRIPT: <f1>:
// CHECK-SCRIPT-NEXT: 1100c: 1e ff 2f e1 bx lr // CHECK-SCRIPT-NEXT: 1100c: 1e ff 2f e1 bx lr
// CHECK-SCRIPT: f2: // CHECK-SCRIPT: <f2>:
// CHECK-SCRIPT-NEXT: 11010: 1e ff 2f e1 bx lr // CHECK-SCRIPT-NEXT: 11010: 1e ff 2f e1 bx lr
// CHECK-SCRIPT: f3: // CHECK-SCRIPT: <f3>:
// CHECK-SCRIPT-NEXT: 11014: 1e ff 2f e1 bx lr // CHECK-SCRIPT-NEXT: 11014: 1e ff 2f e1 bx lr
// CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-EMPTY:
// CHECK-SCRIPT-NEXT: Disassembly of section .func1: // CHECK-SCRIPT-NEXT: Disassembly of section .func1:
// CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-EMPTY:
// CHECK-SCRIPT-NEXT: func1: // CHECK-SCRIPT-NEXT: <func1>:
// CHECK-SCRIPT-NEXT: 11018: 1e ff 2f e1 bx lr // CHECK-SCRIPT-NEXT: 11018: 1e ff 2f e1 bx lr
// CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-EMPTY:
// CHECK-SCRIPT-NEXT: Disassembly of section .func2: // CHECK-SCRIPT-NEXT: Disassembly of section .func2:
// CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-EMPTY:
// CHECK-SCRIPT-NEXT: func2: // CHECK-SCRIPT-NEXT: <func2>:
// CHECK-SCRIPT-NEXT: 1101c: 1e ff 2f e1 bx lr // CHECK-SCRIPT-NEXT: 1101c: 1e ff 2f e1 bx lr
// CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-EMPTY:
// CHECK-SCRIPT-NEXT: Disassembly of section .func3: // CHECK-SCRIPT-NEXT: Disassembly of section .func3:
// CHECK-SCRIPT-EMPTY: // CHECK-SCRIPT-EMPTY:
// CHECK-SCRIPT-NEXT: func3: // CHECK-SCRIPT-NEXT: <func3>:
// CHECK-SCRIPT-NEXT: 11020: 1e ff 2f e1 bx lr // CHECK-SCRIPT-NEXT: 11020: 1e ff 2f e1 bx lr
// Check that the .ARM.exidx section is sorted in order as the functions // Check that the .ARM.exidx section is sorted in order as the functions
// The offset in field 1, is 32-bit so in the binary the most significant bit // The offset in field 1, is 32-bit so in the binary the most significant bit
// 11024 - 24 = 11000 func4 // 11024 - 24 = 11000 func4
// 1102c - 28 = 11004 func5 // 1102c - 28 = 11004 func5
// CHECK-SCRIPT-EXIDX: 11024 dcffff7f 01000000 d8ffff7f 01000000 // CHECK-SCRIPT-EXIDX: 11024 dcffff7f 01000000 d8ffff7f 01000000
// 11034 - 2c = 11008 _start // 11034 - 2c = 11008 _start
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lld/test/ELF/arm-extreme-range-pi-thunk.s

Show All 27 Lines
high: high:
bl _start bl _start
bx lr bx lr
// ARMv7a instructions and relocations. // ARMv7a instructions and relocations.
// CHECK: Disassembly of section .text_low: // CHECK: Disassembly of section .text_low:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 130: bl #0 <__ARMV7PILongThunk_high> // CHECK-NEXT: 130: bl #0 <__ARMV7PILongThunk_high>
// CHECK-NEXT: 134: bx lr // CHECK-NEXT: 134: bx lr
// CHECK: __ARMV7PILongThunk_high: // CHECK: <__ARMV7PILongThunk_high>:
// CHECK-NEXT: 138: movw r12, #65208 // CHECK-NEXT: 138: movw r12, #65208
// CHECK-NEXT: 13c: movt r12, #61439 // CHECK-NEXT: 13c: movt r12, #61439
// 0x140 + 0xEFFF0000 + 0x0000FEB8 + 8 = 0xf0000000 = high // 0x140 + 0xEFFF0000 + 0x0000FEB8 + 8 = 0xf0000000 = high
// CHECK-NEXT: 140: add r12, r12, pc // CHECK-NEXT: 140: add r12, r12, pc
// CHECK-NEXT: 144: bx r12 // CHECK-NEXT: 144: bx r12
// CHECK: Disassembly of section .text_high: // CHECK: Disassembly of section .text_high:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: high: // CHECK-NEXT: <high>:
// CHECK-NEXT: f0000000: bl #0 <__ARMV7PILongThunk__start> // CHECK-NEXT: f0000000: bl #0 <__ARMV7PILongThunk__start>
// CHECK-NEXT: f0000004: bx lr // CHECK-NEXT: f0000004: bx lr
// CHECK: __ARMV7PILongThunk__start: // CHECK: <__ARMV7PILongThunk__start>:
// CHECK-NEXT: f0000008: movw r12, #280 // CHECK-NEXT: f0000008: movw r12, #280
// CHECK-NEXT: f000000c: movt r12, #4096 // CHECK-NEXT: f000000c: movt r12, #4096
// 0xf0000010 + 0x10000000 + 0x0000118 + 8 = bits32(0x100000130),0x130 = _start // 0xf0000010 + 0x10000000 + 0x0000118 + 8 = bits32(0x100000130),0x130 = _start
// CHECK-NEXT: f0000010: add r12, r12, pc // CHECK-NEXT: f0000010: add r12, r12, pc
// CHECK-NEXT: f0000014: bx r12 // CHECK-NEXT: f0000014: bx r12
// Thumbv7a instructions and relocations // Thumbv7a instructions and relocations
// CHECK-THUMB: Disassembly of section .text_low: // CHECK-THUMB: Disassembly of section .text_low:
// CHECK-THUMB-EMPTY: // CHECK-THUMB-EMPTY:
// CHECK-THUMB-NEXT: _start: // CHECK-THUMB-NEXT: <_start>:
// CHECK-THUMB-NEXT: 130: bl #4 // CHECK-THUMB-NEXT: 130: bl #4
// CHECK-THUMB-NEXT: 134: bx lr // CHECK-THUMB-NEXT: 134: bx lr
// CHECK-THUMB-NEXT: 136: bmi #-88 // CHECK-THUMB-NEXT: 136: bmi #-88
// CHECK-THUMB: __ThumbV7PILongThunk_high: // CHECK-THUMB: <__ThumbV7PILongThunk_high>:
// CHECK-THUMB-NEXT: 138: movw r12, #65213 // CHECK-THUMB-NEXT: 138: movw r12, #65213
// CHECK-THUMB-NEXT: 13c: movt r12, #61439 // CHECK-THUMB-NEXT: 13c: movt r12, #61439
// 0x140 + 0xEFFF0000 + 0x0000FEBD + 4 = 0xf0000001 = high // 0x140 + 0xEFFF0000 + 0x0000FEBD + 4 = 0xf0000001 = high
// CHECK-THUMB-NEXT: 140: add r12, pc // CHECK-THUMB-NEXT: 140: add r12, pc
// CHECK-THUMB-NEXT: 142: bx r12 // CHECK-THUMB-NEXT: 142: bx r12
// CHECK-THUMB: Disassembly of section .text_high: // CHECK-THUMB: Disassembly of section .text_high:
// CHECK-THUMB-EMPTY: // CHECK-THUMB-EMPTY:
// CHECK-THUMB-NEXT: high: // CHECK-THUMB-NEXT: <high>:
// CHECK-THUMB-NEXT: f0000000: bl #4 // CHECK-THUMB-NEXT: f0000000: bl #4
// CHECK-THUMB-NEXT: f0000004: bx lr // CHECK-THUMB-NEXT: f0000004: bx lr
// CHECK-THUMB: __ThumbV7PILongThunk__start: // CHECK-THUMB: <__ThumbV7PILongThunk__start>:
// CHECK-THUMB-NEXT: f0000008: movw r12, #285 // CHECK-THUMB-NEXT: f0000008: movw r12, #285
// CHECK-THUMB-NEXT: f000000c: movt r12, #4096 // CHECK-THUMB-NEXT: f000000c: movt r12, #4096
// 0xf0000010 + 0x10000000 + 0x000011d +4 = bits32(0x100000131),0x131 = _start // 0xf0000010 + 0x10000000 + 0x000011d +4 = bits32(0x100000131),0x131 = _start
// CHECK-THUMB-NEXT: f0000010: add r12, pc // CHECK-THUMB-NEXT: f0000010: add r12, pc
// CHECK-THUMB-NEXT: f0000012: bx r12 // CHECK-THUMB-NEXT: f0000012: bx r12

lld/test/ELF/arm-fix-cortex-a8-blx.s

Show All 23 Lines
/// 32-bit non branch instruction. Expect a patch. /// 32-bit non branch instruction. Expect a patch.
nop.w nop.w
/// Encoding for blx _start. Use .inst.n directives to avoid a relocation. /// Encoding for blx _start. Use .inst.n directives to avoid a relocation.
.inst.n 0xf7ff .inst.n 0xf7ff
.inst.n 0xe800 .inst.n 0xe800
// CHECK-PATCH: 12ffa: nop.w // CHECK-PATCH: 12ffa: nop.w
// CHECK-PATCH-NEXT: 12ffe: blx #4 // CHECK-PATCH-NEXT: 12ffe: blx #4
// CHECK-PATCH: 00013004 __CortexA8657417_12FFE: // CHECK-PATCH: 00013004 <__CortexA8657417_12FFE>:
// CHECK-PATCH-NEXT: 13004: b #-4104 // CHECK-PATCH-NEXT: 13004: b #-4104

lld/test/ELF/arm-fix-cortex-a8-nopatch.s

Show All 21 Lines
.space 4086 .space 4086
.thumb_func .thumb_func
target: target:
/// 32-bit branch spans 2 4KiB regions, preceded by a 32-bit branch so no patch /// 32-bit branch spans 2 4KiB regions, preceded by a 32-bit branch so no patch
/// expected. /// expected.
b.w target b.w target
b.w target b.w target
// CALLSITE1: 00012ffa target: // CALLSITE1: 00012ffa <target>:
// CALLSITE1-NEXT: 12ffa: b.w #-4 // CALLSITE1-NEXT: 12ffa: b.w #-4
// CALLSITE1-NEXT: 12ffe: b.w #-8 // CALLSITE1-NEXT: 12ffe: b.w #-8
.space 4088 .space 4088
.type target2, %function .type target2, %function
target2: target2:
/// 32-bit Branch and link spans 2 4KiB regions, preceded by a 16-bit /// 32-bit Branch and link spans 2 4KiB regions, preceded by a 16-bit
/// instruction so no patch expected. /// instruction so no patch expected.
nop nop
nop nop
bl target2 bl target2
// CALLSITE2: 00013ffa target2: // CALLSITE2: 00013ffa <target2>:
// CALLSITE2-NEXT: 13ffa: nop // CALLSITE2-NEXT: 13ffa: nop
// CALLSITE2-NEXT: 13ffc: nop // CALLSITE2-NEXT: 13ffc: nop
// CALLSITE2-NEXT: 13ffe: bl #-8 // CALLSITE2-NEXT: 13ffe: bl #-8
.space 4088 .space 4088
.type target3, %function .type target3, %function
target3: target3:
/// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit /// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
/// non branch instruction, branch is backwards but outside 4KiB region. So /// non branch instruction, branch is backwards but outside 4KiB region. So
/// expect no patch. /// expect no patch.
nop.w nop.w
beq.w target2 beq.w target2
// CALLSITE3: 00014ffa target3: // CALLSITE3: 00014ffa <target3>:
// CALLSITE3-NEXT: 14ffa: nop.w // CALLSITE3-NEXT: 14ffa: nop.w
// CALLSITE3-NEXT: 14ffe: beq.w #-4104 // CALLSITE3-NEXT: 14ffe: beq.w #-4104
.space 4088 .space 4088
.type source4, %function .type source4, %function
source4: source4:
/// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit /// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
/// non branch instruction, branch is forwards to 2nd region so expect no patch. /// non branch instruction, branch is forwards to 2nd region so expect no patch.
nop.w nop.w
beq.w target4 beq.w target4
.thumb_func .thumb_func
target4: target4:
nop.w nop.w
// CALLSITE4: 00015ffa source4: // CALLSITE4: 00015ffa <source4>:
// CALLSITE4-NEXT: 15ffa: nop.w // CALLSITE4-NEXT: 15ffa: nop.w
// CALLSITE4-NEXT: 15ffe: beq.w #0 // CALLSITE4-NEXT: 15ffe: beq.w #0
// CALLSITE4: 00016002 target4: // CALLSITE4: 00016002 <target4>:
// CALLSITE4-NEXT: 16002: nop.w // CALLSITE4-NEXT: 16002: nop.w
.space 4084 .space 4084
.type target5, %function .type target5, %function
target5: target5:
/// 32-bit conditional branch spans 2 4KiB regions, preceded by the encoding of /// 32-bit conditional branch spans 2 4KiB regions, preceded by the encoding of
/// a 32-bit thumb instruction, but in ARM state (illegal instruction), we /// a 32-bit thumb instruction, but in ARM state (illegal instruction), we
/// should not decode and match it as Thumb, expect no patch. /// should not decode and match it as Thumb, expect no patch.
.arm .arm
.inst 0x800f3af /// nop.w encoding in Thumb .inst 0x800f3af /// nop.w encoding in Thumb
.thumb .thumb
.thumb_func .thumb_func
source5: source5:
beq.w target5 beq.w target5
// CALLSITE5: 00016ffe source5: // CALLSITE5: 00016ffe <source5>:
// CALLSITE5-NEXT: 16ffe: beq.w #-8 // CALLSITE5-NEXT: 16ffe: beq.w #-8
/// Edge case where two word sequence starts at offset 0xffc, check that /// Edge case where two word sequence starts at offset 0xffc, check that
/// we don't match. In this case the branch will be completely in the 2nd /// we don't match. In this case the branch will be completely in the 2nd
/// region and the branch will target the second region. This will pass a /// region and the branch will target the second region. This will pass a
/// branch destination in the same region test, but not the branch must have /// branch destination in the same region test, but not the branch must have
/// and address of the form xxxxxffe. /// and address of the form xxxxxffe.
.space 4090 .space 4090
.type target6, %function .type target6, %function
nop.w nop.w
/// Make sure target of branch is in the same 4KiB region as the branch. /// Make sure target of branch is in the same 4KiB region as the branch.
target6: target6:
bl target6 bl target6
// CALLSITE6: 00018000 target6: // CALLSITE6: 00018000 <target6>:
// CALLSITE6-NEXT: 18000: bl #-4 // CALLSITE6-NEXT: 18000: bl #-4
/// Edge case where two word sequence starts at offset 0xffe, check that /// Edge case where two word sequence starts at offset 0xffe, check that
/// we don't match. In this case the branch will be completely in the 2nd /// we don't match. In this case the branch will be completely in the 2nd
/// region and the branch will target the second region. This will pass a /// region and the branch will target the second region. This will pass a
/// branch destination in the same region test, but not the branch must have /// branch destination in the same region test, but not the branch must have
/// and address of the form xxxxxffe. /// and address of the form xxxxxffe.
.space 4090 .space 4090
.type target7, %function .type target7, %function
nop.w nop.w
/// Make sure target of branch is in the same 4KiB region as the branch. /// Make sure target of branch is in the same 4KiB region as the branch.
target7: target7:
bl target7 bl target7
// CALLSITE7: 00019002 target7: // CALLSITE7: 00019002 <target7>:
// CALLSITE7: 19002: bl #-4 // CALLSITE7: 19002: bl #-4

lld/test/ELF/arm-fix-cortex-a8-plt.s

Show All 26 Lines
.space 2042 .space 2042
.global source .global source
.thumb_func .thumb_func
source: source:
nop.w nop.w
bl external bl external
// CHECK: 00002ffa source: // CHECK: 00002ffa <source>:
// CHECK-NEXT: 2ffa: nop.w // CHECK-NEXT: 2ffa: nop.w
// CHECK-NEXT: 2ffe: blx #4 // CHECK-NEXT: 2ffe: blx #4
// CHECK: 00003004 __CortexA8657417_2FFE: // CHECK: 00003004 <__CortexA8657417_2FFE>:
// CHECK-NEXT: 3004: b #-4076 // CHECK-NEXT: 3004: b #-4076

lld/test/ELF/arm-fix-cortex-a8-recognize.s

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
.global target .global target
.type target, %function .type target, %function
target: target:
/// 32-bit Branch spans 2 4KiB regions, preceded by a 32-bit non branch /// 32-bit Branch spans 2 4KiB regions, preceded by a 32-bit non branch
/// instruction, expect a patch. /// instruction, expect a patch.
nop.w nop.w
b.w target b.w target
// CALLSITE1: 00012ffa target: // CALLSITE1: 00012ffa <target>:
// CALLSITE1-NEXT: 12ffa: nop.w // CALLSITE1-NEXT: 12ffa: nop.w
// CALLSITE1-NEXT: 12ffe: b.w #28674 // CALLSITE1-NEXT: 12ffe: b.w #28674
/// Expect no patch when doing a relocatable link ld -r. /// Expect no patch when doing a relocatable link ld -r.
// CHECK-RELOCATABLE: 00000ffa target: // CHECK-RELOCATABLE: 00000ffa <target>:
// CHECK-RELOCATABLE-NEXT: ffa: nop.w // CHECK-RELOCATABLE-NEXT: ffa: nop.w
// CHECK-RELOCATABLE-NEXT: ffe: b.w #-4 // CHECK-RELOCATABLE-NEXT: ffe: b.w #-4
.space 4088 .space 4088
.type target2, %function .type target2, %function
.local target2 .local target2
target2: target2:
/// 32-bit Branch and link spans 2 4KiB regions, preceded by a 32-bit /// 32-bit Branch and link spans 2 4KiB regions, preceded by a 32-bit
/// non branch instruction, expect a patch. /// non branch instruction, expect a patch.
nop.w nop.w
bl target2 bl target2
// CALLSITE2: 00013ffa target2: // CALLSITE2: 00013ffa <target2>:
// CALLSITE2-NEXT: 13ffa: nop.w // CALLSITE2-NEXT: 13ffa: nop.w
// CALLSITE2-NEXT: 13ffe: bl #24582 // CALLSITE2-NEXT: 13ffe: bl #24582
.space 4088 .space 4088
.type target3, %function .type target3, %function
.local target3 .local target3
target3: target3:
/// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit /// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
/// non branch instruction, expect a patch. /// non branch instruction, expect a patch.
nop.w nop.w
beq.w target3 beq.w target3
// CALLSITE3: 00014ffa target3: // CALLSITE3: 00014ffa <target3>:
// CALLSITE3-NEXT: 14ffa: nop.w // CALLSITE3-NEXT: 14ffa: nop.w
// CALLSITE3-NEXT: 14ffe: beq.w #20490 // CALLSITE3-NEXT: 14ffe: beq.w #20490
.space 4082 .space 4082
.type target4, %function .type target4, %function
.local target4 .local target4
.arm .arm
target4: target4:
bx lr bx lr
.space 2 .space 2
.thumb .thumb
/// 32-bit Branch link and exchange spans 2 4KiB regions, preceded by a /// 32-bit Branch link and exchange spans 2 4KiB regions, preceded by a
/// 32-bit non branch instruction, blx always goes via relocation. Expect /// 32-bit non branch instruction, blx always goes via relocation. Expect
/// a patch. /// a patch.
nop.w nop.w
blx target4 blx target4
/// Target = 0x19010 __CortexA8657417_15FFE /// Target = 0x19010 __CortexA8657417_15FFE
// CALLSITE4: 00015ff4 target4: // CALLSITE4: 00015ff4 <target4>:
// CALLSITE4-NEXT: 15ff4: bx lr // CALLSITE4-NEXT: 15ff4: bx lr
// CALLSITE4: 15ff8: 00 00 .short 0x0000 // CALLSITE4: 15ff8: 00 00 .short 0x0000
// CALLSITE4: 15ffa: nop.w // CALLSITE4: 15ffa: nop.w
// CALLSITE4-NEXT: 15ffe: blx #16400 // CALLSITE4-NEXT: 15ffe: blx #16400
/// Separate sections for source and destination of branches to force /// Separate sections for source and destination of branches to force
/// a relocation. /// a relocation.
.section .text.0, "ax", %progbits .section .text.0, "ax", %progbits
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
.thumb .thumb
/// 32-bit Branch link spans 2 4KiB regions, preceded by a 32-bit non branch /// 32-bit Branch link spans 2 4KiB regions, preceded by a 32-bit non branch
/// instruction, expect a patch. The target of the BL is in ARM state so we /// instruction, expect a patch. The target of the BL is in ARM state so we
/// expect it to be turned into a BLX. The patch must be in ARM state to /// expect it to be turned into a BLX. The patch must be in ARM state to
/// avoid a state change thunk. /// avoid a state change thunk.
nop.w nop.w
bl target8 bl target8
// CALLSITE8: 00019ff4 target8: // CALLSITE8: 00019ff4 <target8>:
// CALLSITE8-NEXT: 19ff4: bx lr // CALLSITE8-NEXT: 19ff4: bx lr
// CALLSITE8: 19ff8: 00 00 .short 0x0000 // CALLSITE8: 19ff8: 00 00 .short 0x0000
// CALLSITE8: 19ffa: nop.w // CALLSITE8: 19ffa: nop.w
// CALLSITE8-NEXT: 19ffe: blx #32 // CALLSITE8-NEXT: 19ffe: blx #32
// CHECK-PATCHES: 0001a004 __CortexA8657417_12FFE: // CHECK-PATCHES: 0001a004 <__CortexA8657417_12FFE>:
// CHECK-PATCHES-NEXT: 1a004: b.w #-28686 // CHECK-PATCHES-NEXT: 1a004: b.w #-28686
// CHECK-PATCHES: 0001a008 __CortexA8657417_13FFE: // CHECK-PATCHES: 0001a008 <__CortexA8657417_13FFE>:
// CHECK-PATCHES-NEXT: 1a008: b.w #-24594 // CHECK-PATCHES-NEXT: 1a008: b.w #-24594
// CHECK-PATCHES: 0001a00c __CortexA8657417_14FFE: // CHECK-PATCHES: 0001a00c <__CortexA8657417_14FFE>:
// CHECK-PATCHES-NEXT: 1a00c: b.w #-20502 // CHECK-PATCHES-NEXT: 1a00c: b.w #-20502
// CHECK-PATCHES: 0001a010 __CortexA8657417_15FFE: // CHECK-PATCHES: 0001a010 <__CortexA8657417_15FFE>:
// CHECK-PATCHES-NEXT: 1a010: b #-16420 // CHECK-PATCHES-NEXT: 1a010: b #-16420
// CHECK-PATCHES: 0001a014 __CortexA8657417_16FFE: // CHECK-PATCHES: 0001a014 <__CortexA8657417_16FFE>:
// CHECK-PATCHES-NEXT: 1a014: b.w #-16406 // CHECK-PATCHES-NEXT: 1a014: b.w #-16406
// CHECK-PATCHES: 0001a018 __CortexA8657417_17FFE: // CHECK-PATCHES: 0001a018 <__CortexA8657417_17FFE>:
// CHECK-PATCHES-NEXT: 1a018: b.w #-12314 // CHECK-PATCHES-NEXT: 1a018: b.w #-12314
// CHECK-PATCHES: 0001a01c __CortexA8657417_18FFE: // CHECK-PATCHES: 0001a01c <__CortexA8657417_18FFE>:
// CHECK-PATCHES-NEXT: 1a01c: b.w #-8222 // CHECK-PATCHES-NEXT: 1a01c: b.w #-8222
// CHECK-PATCHES: 0001a020 __CortexA8657417_19FFE: // CHECK-PATCHES: 0001a020 <__CortexA8657417_19FFE>:
// CHECK-PATCHES-NEXT: 1a020: b #-52 // CHECK-PATCHES-NEXT: 1a020: b #-52

lld/test/ELF/arm-fix-cortex-a8-thunk-align.s

Show All 16 Lines_start:
b.w arm_func b.w arm_func
thumb_target: thumb_target:
.space 4096 - 10 .space 4096 - 10
/// erratum patch needed /// erratum patch needed
nop.w nop.w
b.w thumb_target b.w thumb_target
/// Expect thunk and patch to be inserted here /// Expect thunk and patch to be inserted here
// CHECK: 00003004 __ThumbV7PILongThunk_arm_func: // CHECK: 00003004 <__ThumbV7PILongThunk_arm_func>:
// CHECK-NEXT: 3004: movw r12, #4088 // CHECK-NEXT: 3004: movw r12, #4088
// CHECK-NEXT: movt r12, #256 // CHECK-NEXT: movt r12, #256
// CHECK-NEXT: add r12, pc // CHECK-NEXT: add r12, pc
// CHECK-NEXT: bx r12 // CHECK-NEXT: bx r12
// CHECK: 00004004 __CortexA8657417_2FFE: // CHECK: 00004004 <__CortexA8657417_2FFE>:
// CHECK-NEXT: 4004: b.w #-8196 // CHECK-NEXT: 4004: b.w #-8196
.section .text.02 .section .text.02
/// Take us over thunk section spacing /// Take us over thunk section spacing
.space 16 * 1024 * 1024 .space 16 * 1024 * 1024
.section .text.03, "ax", %progbits .section .text.03, "ax", %progbits
.arm .arm
.balign 4 .balign 4
.type arm_func, %function .type arm_func, %function
arm_func: arm_func:
bx lr bx lr

lld/test/ELF/arm-fix-cortex-a8-thunk.s

Show All 19 Lines
.section .text.01, "ax", %progbits .section .text.01, "ax", %progbits
.balign 4096 .balign 4096
.globl _start .globl _start
.type _start, %function .type _start, %function
_start: _start:
beq.w far_away beq.w far_away
/// Thunk to far_away and state change needed, size 12-bytes goes here. /// Thunk to far_away and state change needed, size 12-bytes goes here.
// CHECK: 00110004 __ThumbV7PILongThunk_far_away: // CHECK: 00110004 <__ThumbV7PILongThunk_far_away>:
// CHECK-NEXT: 110004: movw r12, #65524 // CHECK-NEXT: 110004: movw r12, #65524
// CHECK-NEXT: movt r12, #15 // CHECK-NEXT: movt r12, #15
// CHECK-NEXT: add r12, pc // CHECK-NEXT: add r12, pc
// CHECK-NEXT: bx r12 // CHECK-NEXT: bx r12
.section .text.02, "ax", %progbits .section .text.02, "ax", %progbits
.space 4096 - 22 .space 4096 - 22
.section .text.03, "ax", %progbits .section .text.03, "ax", %progbits
.thumb_func .thumb_func
target: target:
/// After thunk is added this branch will line up across 2 4 KiB regions /// After thunk is added this branch will line up across 2 4 KiB regions
/// and will trigger a patch. /// and will trigger a patch.
nop.w nop.w
bl target bl target
/// Expect erratum patch inserted here /// Expect erratum patch inserted here
// CHECK: 00110ffa target: // CHECK: 00110ffa <target>:
// CHECK-NEXT: 110ffa: nop.w // CHECK-NEXT: 110ffa: nop.w
// CHECK-NEXT: bl #2 // CHECK-NEXT: bl #2
// CHECK: 00111004 __CortexA8657417_110FFE: // CHECK: 00111004 <__CortexA8657417_110FFE>:
// CHECK-NEXT: 111004: b.w #-14 // CHECK-NEXT: 111004: b.w #-14
/// Expect range extension thunk here. /// Expect range extension thunk here.
// CHECK: 00111008 __ThumbV7PILongThunk_early: // CHECK: 00111008 <__ThumbV7PILongThunk_early>:
// CHECK-NEXT: 111008: b.w #-1048582 // CHECK-NEXT: 111008: b.w #-1048582
.section .text.04, "ax", %progbits .section .text.04, "ax", %progbits
/// The erratum patch will push this branch out of range, so another /// The erratum patch will push this branch out of range, so another
/// range extension thunk will be needed. /// range extension thunk will be needed.
beq.w early beq.w early
// CHECK: 11100c: beq.w #-8 // CHECK: 11100c: beq.w #-8
.section .text.05, "ax", %progbits .section .text.05, "ax", %progbits
.arm .arm
nop nop
.type far_away, %function .type far_away, %function
far_away: far_away:
bx lr bx lr

lld/test/ELF/arm-force-pi-thunk.s

Show All 26 Lines
.globl low_target2 .globl low_target2
.type low_target2, %function .type low_target2, %function
low_target2: low_target2:
bl high_target bl high_target
bl high_target2 bl high_target2
// CHECK: Disassembly of section .text_low: // CHECK: Disassembly of section .text_low:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 94: 70 47 bx lr // CHECK-NEXT: 94: 70 47 bx lr
// CHECK: low_target: // CHECK: <low_target>:
// CHECK-NEXT: 96: 00 f0 03 f8 bl #6 // CHECK-NEXT: 96: 00 f0 03 f8 bl #6
// CHECK-NEXT: 9a: 00 f0 07 f8 bl #14 // CHECK-NEXT: 9a: 00 f0 07 f8 bl #14
// CHECK-NEXT: 9e: d4 d4 bmi #-88 // CHECK-NEXT: 9e: d4 d4 bmi #-88
// CHECK: __ThumbV7PILongThunk_high_target: // CHECK: <__ThumbV7PILongThunk_high_target>:
// CHECK-NEXT: a0: 4f f6 55 7c movw r12, #65365 // CHECK-NEXT: a0: 4f f6 55 7c movw r12, #65365
// CHECK-NEXT: a4: c0 f2 ff 1c movt r12, #511 // CHECK-NEXT: a4: c0 f2 ff 1c movt r12, #511
// CHECK-NEXT: a8: fc 44 add r12, pc // CHECK-NEXT: a8: fc 44 add r12, pc
// CHECK-NEXT: aa: 60 47 bx r12 // CHECK-NEXT: aa: 60 47 bx r12
// CHECK: __ThumbV7PILongThunk_high_target2: // CHECK: <__ThumbV7PILongThunk_high_target2>:
// CHECK-NEXT: ac: 4f f6 69 7c movw r12, #65385 // CHECK-NEXT: ac: 4f f6 69 7c movw r12, #65385
// CHECK-NEXT: b0: c0 f2 ff 1c movt r12, #511 // CHECK-NEXT: b0: c0 f2 ff 1c movt r12, #511
// CHECK-NEXT: b4: fc 44 add r12, pc // CHECK-NEXT: b4: fc 44 add r12, pc
// CHECK-NEXT: b6: 60 47 bx r12 // CHECK-NEXT: b6: 60 47 bx r12
// CHECK: low_target2: // CHECK: <low_target2>:
// CHECK-NEXT: b8: ff f7 f2 ff bl #-28 // CHECK-NEXT: b8: ff f7 f2 ff bl #-28
// CHECK-NEXT: bc: ff f7 f6 ff bl #-20 // CHECK-NEXT: bc: ff f7 f6 ff bl #-20
.section .text_high, "ax", %progbits .section .text_high, "ax", %progbits
.thumb .thumb
.globl high_target .globl high_target
.type high_target, %function .type high_target, %function
high_target: high_target:
bl low_target bl low_target
bl low_target2 bl low_target2
.section .text_high2, "ax", %progbits .section .text_high2, "ax", %progbits
.thumb .thumb
.globl high_target2 .globl high_target2
.type high_target2, %function .type high_target2, %function
high_target2: high_target2:
bl low_target bl low_target
bl low_target2 bl low_target2
// CHECK: Disassembly of section .text_high: // CHECK: Disassembly of section .text_high:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: high_target: // CHECK-NEXT: <high_target>:
// CHECK-NEXT: 2000000: 00 f0 02 f8 bl #4 // CHECK-NEXT: 2000000: 00 f0 02 f8 bl #4
// CHECK-NEXT: 2000004: 00 f0 06 f8 bl #12 // CHECK-NEXT: 2000004: 00 f0 06 f8 bl #12
// CHECK: __ThumbV7PILongThunk_low_target: // CHECK: <__ThumbV7PILongThunk_low_target>:
// CHECK-NEXT: 2000008: 40 f2 83 0c movw r12, #131 // CHECK-NEXT: 2000008: 40 f2 83 0c movw r12, #131
// CHECK-NEXT: 200000c: cf f6 00 6c movt r12, #65024 // CHECK-NEXT: 200000c: cf f6 00 6c movt r12, #65024
// CHECK-NEXT: 2000010: fc 44 add r12, pc // CHECK-NEXT: 2000010: fc 44 add r12, pc
// CHECK-NEXT: 2000012: 60 47 bx r12 // CHECK-NEXT: 2000012: 60 47 bx r12
// CHECK: __ThumbV7PILongThunk_low_target2: // CHECK: <__ThumbV7PILongThunk_low_target2>:
// CHECK-NEXT: 2000014: 40 f2 99 0c movw r12, #153 // CHECK-NEXT: 2000014: 40 f2 99 0c movw r12, #153
// CHECK-NEXT: 2000018: cf f6 00 6c movt r12, #65024 // CHECK-NEXT: 2000018: cf f6 00 6c movt r12, #65024
// CHECK-NEXT: 200001c: fc 44 add r12, pc // CHECK-NEXT: 200001c: fc 44 add r12, pc
// CHECK-NEXT: 200001e: 60 47 bx r12 // CHECK-NEXT: 200001e: 60 47 bx r12
// CHECK: high_target2: // CHECK: <high_target2>:
// CHECK-NEXT: 2000020: ff f7 f2 ff bl #-28 // CHECK-NEXT: 2000020: ff f7 f2 ff bl #-28
// CHECK-NEXT: 2000024: ff f7 f6 ff bl #-20 // CHECK-NEXT: 2000024: ff f7 f6 ff bl #-20

lld/test/ELF/arm-fpic-got.s

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
// SYMBOLS-NEXT: Size: 4 // SYMBOLS-NEXT: Size: 4
// SYMBOLS-NEXT: Binding: Global // SYMBOLS-NEXT: Binding: Global
// SYMBOLS-NEXT: Type: Object // SYMBOLS-NEXT: Type: Object
// SYMBOLS-NEXT: Other: // SYMBOLS-NEXT: Other:
// SYMBOLS-NEXT: Section: .data // SYMBOLS-NEXT: Section: .data
// CODE: Disassembly of section .text: // CODE: Disassembly of section .text:
// CODE-EMPTY: // CODE-EMPTY:
// CODE-NEXT: _start: // CODE-NEXT: <_start>:
// CODE-NEXT: 11114: ldr r0, [pc, #8] // CODE-NEXT: 11114: ldr r0, [pc, #8]
// CODE-NEXT: 11118: ldr r0, [pc, r0] // CODE-NEXT: 11118: ldr r0, [pc, r0]
// CODE-NEXT: 1111c: ldr r0, [r0] // CODE-NEXT: 1111c: ldr r0, [r0]
// CODE-NEXT: 11120: bx lr // CODE-NEXT: 11120: bx lr
// CODE: $d.1: // CODE: <$d.1>:
// 0x11124 + 0x1008 + 8 = 0x12128 = .got // 0x11124 + 0x1008 + 8 = 0x12128 = .got
// CODE-NEXT: 11124: 08 10 00 00 // CODE-NEXT: 11124: 08 10 00 00

lld/test/ELF/arm-gnu-ifunc-plt.s

Show All 24 Lines
// GOTPLT: Contents of section .got: // GOTPLT: Contents of section .got:
// GOTPLT-NEXT: 122e0 00000000 00000000 dc110100 e0110100 // GOTPLT-NEXT: 122e0 00000000 00000000 dc110100 e0110100
// GOTPLT: Contents of section .got.plt: // GOTPLT: Contents of section .got.plt:
// GOTPLT-NEXT: 132f0 00000000 00000000 00000000 00120100 // GOTPLT-NEXT: 132f0 00000000 00000000 00000000 00120100
// GOTPLT-NEXT: 13300 00120100 // GOTPLT-NEXT: 13300 00120100
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: foo: // DISASM-NEXT: <foo>:
// DISASM-NEXT: 111dc: bx lr // DISASM-NEXT: 111dc: bx lr
// DISASM: bar: // DISASM: <bar>:
// DISASM-NEXT: 111e0: bx lr // DISASM-NEXT: 111e0: bx lr
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 111e4: bl #84 // DISASM-NEXT: 111e4: bl #84
// DISASM-NEXT: 111e8: bl #96 // DISASM-NEXT: 111e8: bl #96
// DISASM: $d.1: // DISASM: <$d.1>:
// DISASM-NEXT: 111ec: 00 00 00 00 .word 0x00000000 // DISASM-NEXT: 111ec: 00 00 00 00 .word 0x00000000
// DISASM-NEXT: 111f0: 04 00 00 00 .word 0x00000004 // DISASM-NEXT: 111f0: 04 00 00 00 .word 0x00000004
// DISASM: 111f4: bl #36 // DISASM: 111f4: bl #36
// DISASM-NEXT: 111f8: bl #48 // DISASM-NEXT: 111f8: bl #48
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .plt: // DISASM-NEXT: Disassembly of section .plt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: $a: // DISASM-NEXT: <$a>:
// DISASM-NEXT: 11200: str lr, [sp, #-4]! // DISASM-NEXT: 11200: str lr, [sp, #-4]!
// DISASM-NEXT: 11204: add lr, pc, #0, #12 // DISASM-NEXT: 11204: add lr, pc, #0, #12
// DISASM-NEXT: 11208: add lr, lr, #8192 // DISASM-NEXT: 11208: add lr, lr, #8192
// DISASM-NEXT: 1120c: ldr pc, [lr, #236]! // DISASM-NEXT: 1120c: ldr pc, [lr, #236]!
// DISASM: $d: // DISASM: <$d>:
// DISASM-NEXT: 11210: d4 d4 d4 d4 .word 0xd4d4d4d4 // DISASM-NEXT: 11210: d4 d4 d4 d4 .word 0xd4d4d4d4
// DISASM-NEXT: 11214: d4 d4 d4 d4 .word 0xd4d4d4d4 // DISASM-NEXT: 11214: d4 d4 d4 d4 .word 0xd4d4d4d4
// DISASM-NEXT: 11218: d4 d4 d4 d4 .word 0xd4d4d4d4 // DISASM-NEXT: 11218: d4 d4 d4 d4 .word 0xd4d4d4d4
// DISASM-NEXT: 1121c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DISASM-NEXT: 1121c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DISASM: $a: // DISASM: <$a>:
// DISASM-NEXT: 11220: add r12, pc, #0, #12 // DISASM-NEXT: 11220: add r12, pc, #0, #12
// DISASM-NEXT: 11224: add r12, r12, #8192 // DISASM-NEXT: 11224: add r12, r12, #8192
// DISASM-NEXT: 11228: ldr pc, [r12, #212]! // DISASM-NEXT: 11228: ldr pc, [r12, #212]!
// DISASM: $d: // DISASM: <$d>:
// DISASM-NEXT: 1122c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DISASM-NEXT: 1122c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DISASM: $a: // DISASM: <$a>:
// DISASM-NEXT: 11230: add r12, pc, #0, #12 // DISASM-NEXT: 11230: add r12, pc, #0, #12
// DISASM-NEXT: 11234: add r12, r12, #8192 // DISASM-NEXT: 11234: add r12, r12, #8192
// DISASM-NEXT: 11238: ldr pc, [r12, #200]! // DISASM-NEXT: 11238: ldr pc, [r12, #200]!
// DISASM: $d: // DISASM: <$d>:
// DISASM-NEXT: 1123c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DISASM-NEXT: 1123c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DISASM: $a: // DISASM: <$a>:
// DISASM-NEXT: 11240: add r12, pc, #0, #12 // DISASM-NEXT: 11240: add r12, pc, #0, #12
// DISASM-NEXT: 11244: add r12, r12, #4096 // DISASM-NEXT: 11244: add r12, r12, #4096
// DISASM-NEXT: 11248: ldr pc, [r12, #160]! // DISASM-NEXT: 11248: ldr pc, [r12, #160]!
// DISASM: $d: // DISASM: <$d>:
// DISASM-NEXT: 1124c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DISASM-NEXT: 1124c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DISASM: $a: // DISASM: <$a>:
// DISASM-NEXT: 11250: add r12, pc, #0, #12 // DISASM-NEXT: 11250: add r12, pc, #0, #12
// DISASM-NEXT: 11254: add r12, r12, #4096 // DISASM-NEXT: 11254: add r12, r12, #4096
// DISASM-NEXT: 11258: ldr pc, [r12, #148]! // DISASM-NEXT: 11258: ldr pc, [r12, #148]!
// DISASM: $d: // DISASM: <$d>:
// DISASM-NEXT: 1125c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DISASM-NEXT: 1125c: d4 d4 d4 d4 .word 0xd4d4d4d4
.syntax unified .syntax unified
.text .text
.type foo STT_GNU_IFUNC .type foo STT_GNU_IFUNC
.globl foo .globl foo
foo: foo:
bx lr bx lr
Show All 16 Lines

lld/test/ELF/arm-gnu-ifunc.s

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
// CHECK-NEXT: Binding: Global // CHECK-NEXT: Binding: Global
// CHECK-NEXT: Type: GNU_IFunc // CHECK-NEXT: Type: GNU_IFunc
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .text // CHECK-NEXT: Section: .text
// CHECK-NEXT: } // CHECK-NEXT: }
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: foo: // DISASM-NEXT: <foo>:
// DISASM-NEXT: 11104: bx lr // DISASM-NEXT: 11104: bx lr
// DISASM: bar: // DISASM: <bar>:
// DISASM-NEXT: 11108: bx lr // DISASM-NEXT: 11108: bx lr
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 1110c: bl #28 // DISASM-NEXT: 1110c: bl #28
// DISASM-NEXT: 11110: bl #40 // DISASM-NEXT: 11110: bl #40
// 1 * 65536 + 244 = 0x100f4 __rel_iplt_start // 1 * 65536 + 244 = 0x100f4 __rel_iplt_start
// DISASM-NEXT: 11114: movw r0, #244 // DISASM-NEXT: 11114: movw r0, #244
// DISASM-NEXT: 11118: movt r0, #1 // DISASM-NEXT: 11118: movt r0, #1
// 1 * 65536 + 260 = 0x10104 __rel_iplt_end // 1 * 65536 + 260 = 0x10104 __rel_iplt_end
// DISASM-NEXT: 1111c: movw r0, #260 // DISASM-NEXT: 1111c: movw r0, #260
// DISASM-NEXT: 11120: movt r0, #1 // DISASM-NEXT: 11120: movt r0, #1
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .iplt: // DISASM-NEXT: Disassembly of section .iplt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: $a: // DISASM-NEXT: <$a>:
// DISASM-NEXT: 11130: add r12, pc, #0, #12 // DISASM-NEXT: 11130: add r12, pc, #0, #12
// DISASM-NEXT: 11134: add r12, r12, #4096 // DISASM-NEXT: 11134: add r12, r12, #4096
// DISASM-NEXT: 11138: ldr pc, [r12, #24]! // DISASM-NEXT: 11138: ldr pc, [r12, #24]!
// DISASM: $d: // DISASM: <$d>:
// DISASM-NEXT: 1113c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DISASM-NEXT: 1113c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DISASM: $a: // DISASM: <$a>:
// DISASM-NEXT: 11140: add r12, pc, #0, #12 // DISASM-NEXT: 11140: add r12, pc, #0, #12
// DISASM-NEXT: 11144: add r12, r12, #4096 // DISASM-NEXT: 11144: add r12, r12, #4096
// DISASM-NEXT: 11148: ldr pc, [r12, #12]! // DISASM-NEXT: 11148: ldr pc, [r12, #12]!
// DISASM: $d: // DISASM: <$d>:
// DISASM-NEXT: 1114c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DISASM-NEXT: 1114c: d4 d4 d4 d4 .word 0xd4d4d4d4

lld/test/ELF/arm-got-relative.s

Show All 36 Lines
// CHECK-NEXT: Type: None // CHECK-NEXT: Type: None
// CHECK-NEXT: Other [ // CHECK-NEXT: Other [
// CHECK-NEXT: STV_HIDDEN // CHECK-NEXT: STV_HIDDEN
// CHECK-NEXT: ] // CHECK-NEXT: ]
// CHECK-NEXT: Section: .got // CHECK-NEXT: Section: .got
// CODE: Disassembly of section .text: // CODE: Disassembly of section .text:
// CODE-EMPTY: // CODE-EMPTY:
// CODE-NEXT: _start: // CODE-NEXT: <_start>:
// CODE-NEXT: 11a0: 08 30 9f e5 ldr r3, [pc, #8] // CODE-NEXT: 11a0: 08 30 9f e5 ldr r3, [pc, #8]
// CODE-NEXT: 11a4: 08 20 9f e5 ldr r2, [pc, #8] // CODE-NEXT: 11a4: 08 20 9f e5 ldr r2, [pc, #8]
// CODE-NEXT: 11a8: 03 00 8f e0 add r0, pc, r3 // CODE-NEXT: 11a8: 03 00 8f e0 add r0, pc, r3
// CODE-NEXT: 11ac: 1e ff 2f e1 bx lr // CODE-NEXT: 11ac: 1e ff 2f e1 bx lr
// CODE:$d.1: // CODE: <$d.1>:
// (_GLOBAL_OFFSET_TABLE_ = 0x220c) - (0x11a8 + 8) = 0x105c // (_GLOBAL_OFFSET_TABLE_ = 0x220c) - (0x11a8 + 8) = 0x105c
// CODE-NEXT: 11b0: 5c 10 00 00 // CODE-NEXT: 11b0: 5c 10 00 00
// (Got(function) - GotBase = 0x0 // (Got(function) - GotBase = 0x0
// CODE-NEXT: 11b4: 00 00 00 00 // CODE-NEXT: 11b4: 00 00 00 00

lld/test/ELF/arm-icf-exidx.s

Show All 21 Lines
nop nop
bx lr bx lr
// CHECK: Contents of section .ARM.exidx: // CHECK: Contents of section .ARM.exidx:
// CHECK-NEXT: 100d4 18100000 b0b0b080 14100000 01000000 // CHECK-NEXT: 100d4 18100000 b0b0b080 14100000 01000000
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: g: // CHECK-NEXT: <g>:
// CHECK-NEXT: 110ec: 1e ff 2f e1 bx lr // CHECK-NEXT: 110ec: 1e ff 2f e1 bx lr
// CHECK: __aeabi_unwind_cpp_pr0: // CHECK: <__aeabi_unwind_cpp_pr0>:
// CHECK-NEXT: 110f0: 00 f0 20 e3 nop // CHECK-NEXT: 110f0: 00 f0 20 e3 nop
// CHECK-NEXT: 110f4: 1e ff 2f e1 bx lr // CHECK-NEXT: 110f4: 1e ff 2f e1 bx lr

lld/test/ELF/arm-long-thunk-converge.s

// REQUIRES: arm // REQUIRES: arm
// RUN: llvm-mc -triple armv7-unknown-gnu -arm-add-build-attributes -filetype=obj -o %t %s // RUN: llvm-mc -triple armv7-unknown-gnu -arm-add-build-attributes -filetype=obj -o %t %s
// RUN: ld.lld %t %S/Inputs/arm-long-thunk-converge.lds -o %t2 // RUN: ld.lld %t %S/Inputs/arm-long-thunk-converge.lds -o %t2
// RUN: llvm-objdump -d -start-address=0x00000000 -stop-address=0x00000010 -triple=armv7a-linux-gnueabihf %t2 | FileCheck --check-prefix=CHECK1 %s // RUN: llvm-objdump -d -start-address=0x00000000 -stop-address=0x00000010 -triple=armv7a-linux-gnueabihf %t2 | FileCheck --check-prefix=CHECK1 %s
// RUN: llvm-objdump -d -start-address=0x02000000 -stop-address=0x02000010 -triple=armv7a-linux-gnueabihf %t2 | FileCheck --check-prefix=CHECK2 %s // RUN: llvm-objdump -d -start-address=0x02000000 -stop-address=0x02000010 -triple=armv7a-linux-gnueabihf %t2 | FileCheck --check-prefix=CHECK2 %s
// RUN: rm -f %t2 // RUN: rm -f %t2
// CHECK1: __ARMv7ABSLongThunk_bar: // CHECK1: <__ARMv7ABSLongThunk_bar>:
// CHECK1-NEXT: 0: 0c c0 00 e3 movw r12, #12 // CHECK1-NEXT: 0: 0c c0 00 e3 movw r12, #12
// CHECK1-NEXT: 4: 00 c2 40 e3 movt r12, #512 // CHECK1-NEXT: 4: 00 c2 40 e3 movt r12, #512
// CHECK1-NEXT: 8: 1c ff 2f e1 bx r12 // CHECK1-NEXT: 8: 1c ff 2f e1 bx r12
// CHECK1: foo: // CHECK1: <foo>:
// CHECK1-NEXT: c: fb ff ff eb bl #-20 // CHECK1-NEXT: c: fb ff ff eb bl #-20
.section .foo,"ax",%progbits,unique,1 .section .foo,"ax",%progbits,unique,1
foo: foo:
bl bar bl bar
// CHECK2: __ARMv7ABSLongThunk_foo: // CHECK2: <__ARMv7ABSLongThunk_foo>:
// CHECK2-NEXT: 2000000: 0c c0 00 e3 movw r12, #12 // CHECK2-NEXT: 2000000: 0c c0 00 e3 movw r12, #12
// CHECK2-NEXT: 2000004: 00 c0 40 e3 movt r12, #0 // CHECK2-NEXT: 2000004: 00 c0 40 e3 movt r12, #0
// CHECK2-NEXT: 2000008: 1c ff 2f e1 bx r12 // CHECK2-NEXT: 2000008: 1c ff 2f e1 bx r12
// CHECK2: bar: // CHECK2: <bar>:
// CHECK2-NEXT: 200000c: fb ff ff eb bl #-20 <__ARMv7ABSLongThunk_foo> // CHECK2-NEXT: 200000c: fb ff ff eb bl #-20 <__ARMv7ABSLongThunk_foo>
.section .bar,"ax",%progbits,unique,1 .section .bar,"ax",%progbits,unique,1
bar: bar:
bl foo bl foo
.zero 0x1000000 .zero 0x1000000

lld/test/ELF/arm-plt-reloc.s

Show All 15 Lines
_start: _start:
b func1 b func1
bl func2 bl func2
beq func3 beq func3
// Executable, expect no PLT // Executable, expect no PLT
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: func1: // CHECK-NEXT: <func1>:
// CHECK-NEXT: 110b4: bx lr // CHECK-NEXT: 110b4: bx lr
// CHECK: func2: // CHECK: <func2>:
// CHECK-NEXT: 110b8: bx lr // CHECK-NEXT: 110b8: bx lr
// CHECK: func3: // CHECK: <func3>:
// CHECK-NEXT: 110bc: bx lr // CHECK-NEXT: 110bc: bx lr
// CHECK: _start: // CHECK: <_start>:
// CHECK-NEXT: 110c0: b #-20 <func1> // CHECK-NEXT: 110c0: b #-20 <func1>
// CHECK-NEXT: 110c4: bl #-20 <func2> // CHECK-NEXT: 110c4: bl #-20 <func2>
// CHECK-NEXT: 110c8: beq #-20 <func3> // CHECK-NEXT: 110c8: beq #-20 <func3>
// Expect PLT entries as symbols can be preempted // Expect PLT entries as symbols can be preempted
// The .got.plt and .plt displacement is small so we can use small PLT entries. // The .got.plt and .plt displacement is small so we can use small PLT entries.
// DSO: Disassembly of section .text: // DSO: Disassembly of section .text:
// DSO-EMPTY: // DSO-EMPTY:
// DSO-NEXT: func1: // DSO-NEXT: <func1>:
// DSO-NEXT: 1214: bx lr // DSO-NEXT: 1214: bx lr
// DSO: func2: // DSO: <func2>:
// DSO-NEXT: 1218: bx lr // DSO-NEXT: 1218: bx lr
// DSO: func3: // DSO: <func3>:
// DSO-NEXT: 121c: bx lr // DSO-NEXT: 121c: bx lr
// DSO: _start: // DSO: <_start>:
// S(0x1214) - P(0x1220) + A(-8) = 0x2c = 32 // S(0x1214) - P(0x1220) + A(-8) = 0x2c = 32
// DSO-NEXT: 1220: b #40 // DSO-NEXT: 1220: b #40
// S(0x1218) - P(0x1224) + A(-8) = 0x38 = 56 // S(0x1218) - P(0x1224) + A(-8) = 0x38 = 56
// DSO-NEXT: 1224: bl #52 // DSO-NEXT: 1224: bl #52
// S(0x121c) - P(0x1228) + A(-8) = 0x44 = 68 // S(0x121c) - P(0x1228) + A(-8) = 0x44 = 68
// DSO-NEXT: 1228: beq #64 // DSO-NEXT: 1228: beq #64
// DSO-EMPTY: // DSO-EMPTY:
// DSO-NEXT: Disassembly of section .plt: // DSO-NEXT: Disassembly of section .plt:
// DSO-EMPTY: // DSO-EMPTY:
// DSO-NEXT: $a: // DSO-NEXT: <$a>:
// DSO-NEXT: 1230: str lr, [sp, #-4]! // DSO-NEXT: 1230: str lr, [sp, #-4]!
// (0x1234 + 8) + (0 RoR 12) + 8192 + 164 = 0x32e0 = .got.plt[2] // (0x1234 + 8) + (0 RoR 12) + 8192 + 164 = 0x32e0 = .got.plt[2]
// DSO-NEXT: 1234: add lr, pc, #0, #12 // DSO-NEXT: 1234: add lr, pc, #0, #12
// DSO-NEXT: 1238: add lr, lr, #8192 // DSO-NEXT: 1238: add lr, lr, #8192
// DSO-NEXT: 123c: ldr pc, [lr, #164]! // DSO-NEXT: 123c: ldr pc, [lr, #164]!
// DSO: $d: // DSO: <$d>:
// DSO-NEXT: 1240: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 1240: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO-NEXT: 1244: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 1244: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO-NEXT: 1248: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 1248: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO-NEXT: 124c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 124c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO: $a: // DSO: <$a>:
// (0x1250 + 8) + (0 RoR 12) + 8192 + 140 = 0x32e4 // (0x1250 + 8) + (0 RoR 12) + 8192 + 140 = 0x32e4
// DSO-NEXT: 1250: add r12, pc, #0, #12 // DSO-NEXT: 1250: add r12, pc, #0, #12
// DSO-NEXT: 1254: add r12, r12, #8192 // DSO-NEXT: 1254: add r12, r12, #8192
// DSO-NEXT: 1258: ldr pc, [r12, #140]! // DSO-NEXT: 1258: ldr pc, [r12, #140]!
// DSO: $d: // DSO: <$d>:
// DSO-NEXT: 125c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 125c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO: $a: // DSO: <$a>:
// (0x1260 + 8) + (0 RoR 12) + 8192 + 128 = 0x32e8 // (0x1260 + 8) + (0 RoR 12) + 8192 + 128 = 0x32e8
// DSO-NEXT: 1260: add r12, pc, #0, #12 // DSO-NEXT: 1260: add r12, pc, #0, #12
// DSO-NEXT: 1264: add r12, r12, #8192 // DSO-NEXT: 1264: add r12, r12, #8192
// DSO-NEXT: 1268: ldr pc, [r12, #128]! // DSO-NEXT: 1268: ldr pc, [r12, #128]!
// DSO: $d: // DSO: <$d>:
// DSO-NEXT: 126c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 126c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO: $a: // DSO: <$a>:
// (0x1270 + 8) + (0 RoR 12) + 8192 + 116 = 0x32ec // (0x1270 + 8) + (0 RoR 12) + 8192 + 116 = 0x32ec
// DSO-NEXT: 1270: add r12, pc, #0, #12 // DSO-NEXT: 1270: add r12, pc, #0, #12
// DSO-NEXT: 1274: add r12, r12, #8192 // DSO-NEXT: 1274: add r12, r12, #8192
// DSO-NEXT: 1278: ldr pc, [r12, #116]! // DSO-NEXT: 1278: ldr pc, [r12, #116]!
// DSO: $d: // DSO: <$d>:
// DSO-NEXT: 127c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 127c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSOREL: Name: .got.plt // DSOREL: Name: .got.plt
// DSOREL-NEXT: Type: SHT_PROGBITS // DSOREL-NEXT: Type: SHT_PROGBITS
// DSOREL-NEXT: Flags [ // DSOREL-NEXT: Flags [
// DSOREL-NEXT: SHF_ALLOC // DSOREL-NEXT: SHF_ALLOC
// DSOREL-NEXT: SHF_WRITE // DSOREL-NEXT: SHF_WRITE
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// RUN: .got.plt 0x1100000 : { *(.got.plt) } \ // RUN: .got.plt 0x1100000 : { *(.got.plt) } \
// RUN: }" > %t.script // RUN: }" > %t.script
// RUN: ld.lld --hash-style=sysv --script %t.script -shared %t1 %t2 -o %t4 // RUN: ld.lld --hash-style=sysv --script %t.script -shared %t1 %t2 -o %t4
// RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t4 | FileCheck --check-prefix=CHECKHIGH %s // RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t4 | FileCheck --check-prefix=CHECKHIGH %s
// RUN: llvm-readobj -S -r %t4 | FileCheck --check-prefix=DSORELHIGH %s // RUN: llvm-readobj -S -r %t4 | FileCheck --check-prefix=DSORELHIGH %s
// CHECKHIGH: Disassembly of section .text: // CHECKHIGH: Disassembly of section .text:
// CHECKHIGH-EMPTY: // CHECKHIGH-EMPTY:
// CHECKHIGH-NEXT: func1: // CHECKHIGH-NEXT: <func1>:
// CHECKHIGH-NEXT: 1000: bx lr // CHECKHIGH-NEXT: 1000: bx lr
// CHECKHIGH: func2: // CHECKHIGH: <func2>:
// CHECKHIGH-NEXT: 1004: bx lr // CHECKHIGH-NEXT: 1004: bx lr
// CHECKHIGH: func3: // CHECKHIGH: <func3>:
// CHECKHIGH-NEXT: 1008: bx lr // CHECKHIGH-NEXT: 1008: bx lr
// CHECKHIGH: _start: // CHECKHIGH: <_start>:
// CHECKHIGH-NEXT: 100c: b #4108 <$a> // CHECKHIGH-NEXT: 100c: b #4108 <$a>
// CHECKHIGH-NEXT: 1010: bl #4120 <$a> // CHECKHIGH-NEXT: 1010: bl #4120 <$a>
// CHECKHIGH-NEXT: 1014: beq #4132 <$a> // CHECKHIGH-NEXT: 1014: beq #4132 <$a>
// CHECKHIGH-EMPTY: // CHECKHIGH-EMPTY:
// CHECKHIGH-NEXT: Disassembly of section .plt: // CHECKHIGH-NEXT: Disassembly of section .plt:
// CHECKHIGH-EMPTY: // CHECKHIGH-EMPTY:
// CHECKHIGH-NEXT: $a: // CHECKHIGH-NEXT: <$a>:
// CHECKHIGH-NEXT: 2000: str lr, [sp, #-4]! // CHECKHIGH-NEXT: 2000: str lr, [sp, #-4]!
// CHECKHIGH-NEXT: 2004: add lr, pc, #16, #12 // CHECKHIGH-NEXT: 2004: add lr, pc, #16, #12
// CHECKHIGH-NEXT: 2008: add lr, lr, #1036288 // CHECKHIGH-NEXT: 2008: add lr, lr, #1036288
// CHECKHIGH-NEXT: 200c: ldr pc, [lr, #4092]! // CHECKHIGH-NEXT: 200c: ldr pc, [lr, #4092]!
// CHECKHIGH: $d: // CHECKHIGH: <$d>:
// CHECKHIGH-NEXT: 2010: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKHIGH-NEXT: 2010: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKHIGH-NEXT: 2014: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKHIGH-NEXT: 2014: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKHIGH-NEXT: 2018: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKHIGH-NEXT: 2018: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKHIGH-NEXT: 201c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKHIGH-NEXT: 201c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKHIGH: $a: // CHECKHIGH: <$a>:
// CHECKHIGH-NEXT: 2020: add r12, pc, #16, #12 // CHECKHIGH-NEXT: 2020: add r12, pc, #16, #12
// CHECKHIGH-NEXT: 2024: add r12, r12, #1036288 // CHECKHIGH-NEXT: 2024: add r12, r12, #1036288
// CHECKHIGH-NEXT: 2028: ldr pc, [r12, #4068]! // CHECKHIGH-NEXT: 2028: ldr pc, [r12, #4068]!
// CHECKHIGH: $d: // CHECKHIGH: <$d>:
// CHECKHIGH-NEXT: 202c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKHIGH-NEXT: 202c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKHIGH: $a: // CHECKHIGH: <$a>:
// CHECKHIGH-NEXT: 2030: add r12, pc, #16, #12 // CHECKHIGH-NEXT: 2030: add r12, pc, #16, #12
// CHECKHIGH-NEXT: 2034: add r12, r12, #1036288 // CHECKHIGH-NEXT: 2034: add r12, r12, #1036288
// CHECKHIGH-NEXT: 2038: ldr pc, [r12, #4056]! // CHECKHIGH-NEXT: 2038: ldr pc, [r12, #4056]!
// CHECKHIGH: $d: // CHECKHIGH: <$d>:
// CHECKHIGH-NEXT: 203c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKHIGH-NEXT: 203c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKHIGH: $a: // CHECKHIGH: <$a>:
// CHECKHIGH-NEXT: 2040: add r12, pc, #16, #12 // CHECKHIGH-NEXT: 2040: add r12, pc, #16, #12
// CHECKHIGH-NEXT: 2044: add r12, r12, #1036288 // CHECKHIGH-NEXT: 2044: add r12, r12, #1036288
// CHECKHIGH-NEXT: 2048: ldr pc, [r12, #4044]! // CHECKHIGH-NEXT: 2048: ldr pc, [r12, #4044]!
// CHECKHIGH: $d: // CHECKHIGH: <$d>:
// CHECKHIGH-NEXT: 204c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKHIGH-NEXT: 204c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSORELHIGH: Name: .got.plt // DSORELHIGH: Name: .got.plt
// DSORELHIGH-NEXT: Type: SHT_PROGBITS // DSORELHIGH-NEXT: Type: SHT_PROGBITS
// DSORELHIGH-NEXT: Flags [ // DSORELHIGH-NEXT: Flags [
// DSORELHIGH-NEXT: SHF_ALLOC // DSORELHIGH-NEXT: SHF_ALLOC
// DSORELHIGH-NEXT: SHF_WRITE // DSORELHIGH-NEXT: SHF_WRITE
// DSORELHIGH-NEXT: ] // DSORELHIGH-NEXT: ]
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// RUN: .got.plt 0x11111100 : { *(.got.plt) } \ // RUN: .got.plt 0x11111100 : { *(.got.plt) } \
// RUN: }" > %t2.script // RUN: }" > %t2.script
// RUN: ld.lld --hash-style=sysv --script %t2.script -shared %t1 %t2 -o %t5 // RUN: ld.lld --hash-style=sysv --script %t2.script -shared %t1 %t2 -o %t5
// RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t5 | FileCheck --check-prefix=CHECKLONG %s // RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t5 | FileCheck --check-prefix=CHECKLONG %s
// RUN: llvm-readobj -S -r %t5 | FileCheck --check-prefix=DSORELLONG %s // RUN: llvm-readobj -S -r %t5 | FileCheck --check-prefix=DSORELLONG %s
// CHECKLONG: Disassembly of section .text: // CHECKLONG: Disassembly of section .text:
// CHECKLONG-EMPTY: // CHECKLONG-EMPTY:
// CHECKLONG-NEXT: func1: // CHECKLONG-NEXT: <func1>:
// CHECKLONG-NEXT: 1000: bx lr // CHECKLONG-NEXT: 1000: bx lr
// CHECKLONG: func2: // CHECKLONG: <func2>:
// CHECKLONG-NEXT: 1004: bx lr // CHECKLONG-NEXT: 1004: bx lr
// CHECKLONG: func3: // CHECKLONG: <func3>:
// CHECKLONG-NEXT: 1008: bx lr // CHECKLONG-NEXT: 1008: bx lr
// CHECKLONG: _start: // CHECKLONG: <_start>:
// CHECKLONG-NEXT: 100c: b #4108 <$a> // CHECKLONG-NEXT: 100c: b #4108 <$a>
// CHECKLONG-NEXT: 1010: bl #4120 <$a> // CHECKLONG-NEXT: 1010: bl #4120 <$a>
// CHECKLONG-NEXT: 1014: beq #4132 <$a> // CHECKLONG-NEXT: 1014: beq #4132 <$a>
// CHECKLONG-EMPTY: // CHECKLONG-EMPTY:
// CHECKLONG-NEXT: Disassembly of section .plt: // CHECKLONG-NEXT: Disassembly of section .plt:
// CHECKLONG-EMPTY: // CHECKLONG-EMPTY:
// CHECKLONG-NEXT: $a: // CHECKLONG-NEXT: <$a>:
// CHECKLONG-NEXT: 2000: str lr, [sp, #-4]! // CHECKLONG-NEXT: 2000: str lr, [sp, #-4]!
// CHECKLONG-NEXT: 2004: ldr lr, [pc, #4] // CHECKLONG-NEXT: 2004: ldr lr, [pc, #4]
// CHECKLONG-NEXT: 2008: add lr, pc, lr // CHECKLONG-NEXT: 2008: add lr, pc, lr
// CHECKLONG-NEXT: 200c: ldr pc, [lr, #8]! // CHECKLONG-NEXT: 200c: ldr pc, [lr, #8]!
// CHECKLONG: $d: // CHECKLONG: <$d>:
// CHECKLONG-NEXT: 2010: f0 f0 10 11 .word 0x1110f0f0 // CHECKLONG-NEXT: 2010: f0 f0 10 11 .word 0x1110f0f0
// CHECKLONG-NEXT: 2014: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKLONG-NEXT: 2014: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKLONG-NEXT: 2018: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKLONG-NEXT: 2018: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKLONG-NEXT: 201c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKLONG-NEXT: 201c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKLONG: $a: // CHECKLONG: <$a>:
// CHECKLONG-NEXT: 2020: ldr r12, [pc, #4] // CHECKLONG-NEXT: 2020: ldr r12, [pc, #4]
// CHECKLONG-NEXT: 2024: add r12, r12, pc // CHECKLONG-NEXT: 2024: add r12, r12, pc
// CHECKLONG-NEXT: 2028: ldr pc, [r12] // CHECKLONG-NEXT: 2028: ldr pc, [r12]
// CHECKLONG: $d: // CHECKLONG: <$d>:
// CHECKLONG-NEXT: 202c: e0 f0 10 11 .word 0x1110f0e0 // CHECKLONG-NEXT: 202c: e0 f0 10 11 .word 0x1110f0e0
// CHECKLONG: $a: // CHECKLONG: <$a>:
// CHECKLONG-NEXT: 2030: ldr r12, [pc, #4] // CHECKLONG-NEXT: 2030: ldr r12, [pc, #4]
// CHECKLONG-NEXT: 2034: add r12, r12, pc // CHECKLONG-NEXT: 2034: add r12, r12, pc
// CHECKLONG-NEXT: 2038: ldr pc, [r12] // CHECKLONG-NEXT: 2038: ldr pc, [r12]
// CHECKLONG: $d: // CHECKLONG: <$d>:
// CHECKLONG-NEXT: 203c: d4 f0 10 11 .word 0x1110f0d4 // CHECKLONG-NEXT: 203c: d4 f0 10 11 .word 0x1110f0d4
// CHECKLONG: $a: // CHECKLONG: <$a>:
// CHECKLONG-NEXT: 2040: ldr r12, [pc, #4] // CHECKLONG-NEXT: 2040: ldr r12, [pc, #4]
// CHECKLONG-NEXT: 2044: add r12, r12, pc // CHECKLONG-NEXT: 2044: add r12, r12, pc
// CHECKLONG-NEXT: 2048: ldr pc, [r12] // CHECKLONG-NEXT: 2048: ldr pc, [r12]
// CHECKLONG: $d: // CHECKLONG: <$d>:
// CHECKLONG-NEXT: 204c: c8 f0 10 11 .word 0x1110f0c8 // CHECKLONG-NEXT: 204c: c8 f0 10 11 .word 0x1110f0c8
// DSORELLONG: Name: .got.plt // DSORELLONG: Name: .got.plt
// DSORELLONG-NEXT: Type: SHT_PROGBITS // DSORELLONG-NEXT: Type: SHT_PROGBITS
// DSORELLONG-NEXT: Flags [ // DSORELLONG-NEXT: Flags [
// DSORELLONG-NEXT: SHF_ALLOC // DSORELLONG-NEXT: SHF_ALLOC
// DSORELLONG-NEXT: SHF_WRITE // DSORELLONG-NEXT: SHF_WRITE
// DSORELLONG-NEXT: ] // DSORELLONG-NEXT: ]
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// RUN: .got.plt 0x8002020 : { *(.got.plt) } \ // RUN: .got.plt 0x8002020 : { *(.got.plt) } \
// RUN: }" > %t3.script // RUN: }" > %t3.script
// RUN: ld.lld --hash-style=sysv --script %t3.script -shared %t1 %t2 -o %t6 // RUN: ld.lld --hash-style=sysv --script %t3.script -shared %t1 %t2 -o %t6
// RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t6 | FileCheck --check-prefix=CHECKMIX %s // RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t6 | FileCheck --check-prefix=CHECKMIX %s
// RUN: llvm-readobj -S -r %t6 | FileCheck --check-prefix=DSORELMIX %s // RUN: llvm-readobj -S -r %t6 | FileCheck --check-prefix=DSORELMIX %s
// CHECKMIX: Disassembly of section .text: // CHECKMIX: Disassembly of section .text:
// CHECKMIX-EMPTY: // CHECKMIX-EMPTY:
// CHECKMIX-NEXT: func1: // CHECKMIX-NEXT: <func1>:
// CHECKMIX-NEXT: 1000: bx lr // CHECKMIX-NEXT: 1000: bx lr
// CHECKMIX: func2: // CHECKMIX: <func2>:
// CHECKMIX-NEXT: 1004: bx lr // CHECKMIX-NEXT: 1004: bx lr
// CHECKMIX: func3: // CHECKMIX: <func3>:
// CHECKMIX-NEXT: 1008: bx lr // CHECKMIX-NEXT: 1008: bx lr
// CHECKMIX: _start: // CHECKMIX: <_start>:
// CHECKMIX-NEXT: 100c: b #4108 <$a> // CHECKMIX-NEXT: 100c: b #4108 <$a>
// CHECKMIX-NEXT: 1010: bl #4120 <$a> // CHECKMIX-NEXT: 1010: bl #4120 <$a>
// CHECKMIX-NEXT: 1014: beq #4132 <$a> // CHECKMIX-NEXT: 1014: beq #4132 <$a>
// CHECKMIX-EMPTY: // CHECKMIX-EMPTY:
// CHECKMIX-NEXT: Disassembly of section .plt: // CHECKMIX-NEXT: Disassembly of section .plt:
// CHECKMIX-EMPTY: // CHECKMIX-EMPTY:
// CHECKMIX-NEXT: $a: // CHECKMIX-NEXT: <$a>:
// CHECKMIX-NEXT: 2000: str lr, [sp, #-4]! // CHECKMIX-NEXT: 2000: str lr, [sp, #-4]!
// CHECKMIX-NEXT: 2004: ldr lr, [pc, #4] // CHECKMIX-NEXT: 2004: ldr lr, [pc, #4]
// CHECKMIX-NEXT: 2008: add lr, pc, lr // CHECKMIX-NEXT: 2008: add lr, pc, lr
// CHECKMIX-NEXT: 200c: ldr pc, [lr, #8]! // CHECKMIX-NEXT: 200c: ldr pc, [lr, #8]!
// CHECKMIX: $d: // CHECKMIX: <$d>:
// CHECKMIX-NEXT: 2010: 10 00 00 08 .word 0x08000010 // CHECKMIX-NEXT: 2010: 10 00 00 08 .word 0x08000010
// CHECKMIX-NEXT: 2014: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKMIX-NEXT: 2014: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKMIX-NEXT: 2018: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKMIX-NEXT: 2018: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKMIX-NEXT: 201c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKMIX-NEXT: 201c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKMIX: $a: // CHECKMIX: <$a>:
// CHECKMIX-NEXT: 2020: ldr r12, [pc, #4] // CHECKMIX-NEXT: 2020: ldr r12, [pc, #4]
// CHECKMIX-NEXT: 2024: add r12, r12, pc // CHECKMIX-NEXT: 2024: add r12, r12, pc
// CHECKMIX-NEXT: 2028: ldr pc, [r12] // CHECKMIX-NEXT: 2028: ldr pc, [r12]
// CHECKMIX: $d: // CHECKMIX: <$d>:
// CHECKMIX-NEXT: 202c: 00 00 00 08 .word 0x08000000 // CHECKMIX-NEXT: 202c: 00 00 00 08 .word 0x08000000
// CHECKMIX: $a: // CHECKMIX: <$a>:
// CHECKMIX-NEXT: 2030: add r12, pc, #133169152 // CHECKMIX-NEXT: 2030: add r12, pc, #133169152
// CHECKMIX-NEXT: 2034: add r12, r12, #1044480 // CHECKMIX-NEXT: 2034: add r12, r12, #1044480
// CHECKMIX-NEXT: 2038: ldr pc, [r12, #4088]! // CHECKMIX-NEXT: 2038: ldr pc, [r12, #4088]!
// CHECKMIX: $d: // CHECKMIX: <$d>:
// CHECKMIX-NEXT: 203c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKMIX-NEXT: 203c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECKMIX: $a: // CHECKMIX: <$a>:
// CHECKMIX-NEXT: 2040: add r12, pc, #133169152 // CHECKMIX-NEXT: 2040: add r12, pc, #133169152
// CHECKMIX-NEXT: 2044: add r12, r12, #1044480 // CHECKMIX-NEXT: 2044: add r12, r12, #1044480
// CHECKMIX-NEXT: 2048: ldr pc, [r12, #4076]! // CHECKMIX-NEXT: 2048: ldr pc, [r12, #4076]!
// CHECKMIX: $d: // CHECKMIX: <$d>:
// CHECKMIX-NEXT: 204c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECKMIX-NEXT: 204c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSORELMIX: Name: .got.plt // DSORELMIX: Name: .got.plt
// DSORELMIX-NEXT: Type: SHT_PROGBITS // DSORELMIX-NEXT: Type: SHT_PROGBITS
// DSORELMIX-NEXT: Flags [ // DSORELMIX-NEXT: Flags [
// DSORELMIX-NEXT: SHF_ALLOC // DSORELMIX-NEXT: SHF_ALLOC
// DSORELMIX-NEXT: SHF_WRITE // DSORELMIX-NEXT: SHF_WRITE
// DSORELMIX-NEXT: ] // DSORELMIX-NEXT: ]
// DSORELMIX-NEXT: Address: 0x8002020 // DSORELMIX-NEXT: Address: 0x8002020
// DSORELMIX: Section {{.*}} .rel.plt { // DSORELMIX: Section {{.*}} .rel.plt {
// DSORELMIX-NEXT: 0x800202C R_ARM_JUMP_SLOT func1 0x0 // DSORELMIX-NEXT: 0x800202C R_ARM_JUMP_SLOT func1 0x0
// DSORELMIX-NEXT: 0x8002030 R_ARM_JUMP_SLOT func2 0x0 // DSORELMIX-NEXT: 0x8002030 R_ARM_JUMP_SLOT func2 0x0
// DSORELMIX-NEXT: 0x8002034 R_ARM_JUMP_SLOT func3 0x0 // DSORELMIX-NEXT: 0x8002034 R_ARM_JUMP_SLOT func3 0x0

lld/test/ELF/arm-sbrel32.s

Show All 26 Lines
foo2: .word 20 foo2: .word 20
.bss .bss
foo3: .space 4 foo3: .space 4
foo4: .space 4 foo4: .space 4
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 110d4: 1e ff 2f e1 bx lr // CHECK-NEXT: 110d4: 1e ff 2f e1 bx lr
// CHECK: 110d8: 00 00 00 00 .word 0x00000000 // CHECK: 110d8: 00 00 00 00 .word 0x00000000
// CHECK-NEXT: 110dc: 04 00 00 00 .word 0x00000004 // CHECK-NEXT: 110dc: 04 00 00 00 .word 0x00000004
// CHECK-NEXT: 110e0: 08 00 00 00 .word 0x00000008 // CHECK-NEXT: 110e0: 08 00 00 00 .word 0x00000008
// CHECK-NEXT: 110e4: 0c 00 00 00 .word 0x0000000c // CHECK-NEXT: 110e4: 0c 00 00 00 .word 0x0000000c

lld/test/ELF/arm-target1.s

Show All 23 Lines.text
patatino: patatino:
.word 32 .word 32
// Force generation of $d.0 as section is not all data // Force generation of $d.0 as section is not all data
nop nop
// RELATIVE: SYMBOL TABLE: // RELATIVE: SYMBOL TABLE:
// RELATIVE: 00001154 l .text 00000000 patatino // RELATIVE: 00001154 l .text 00000000 patatino
// RELATIVE: Disassembly of section .text: // RELATIVE: Disassembly of section .text:
// RELATIVE-EMPTY: // RELATIVE-EMPTY:
// RELATIVE: $d.0: // RELATIVE: <$d.0>:
// RELATIVE: 1150: 04 00 00 00 .word 0x00000004 // RELATIVE: 1150: 04 00 00 00 .word 0x00000004
// ABS: can't create dynamic relocation R_ARM_TARGET1 against symbol: patatino in readonly segment; recompile object files with -fPIC or pass '-Wl,-z,notext' to allow text relocations in the output // ABS: can't create dynamic relocation R_ARM_TARGET1 against symbol: patatino in readonly segment; recompile object files with -fPIC or pass '-Wl,-z,notext' to allow text relocations in the output
// ABS: >>> defined in {{.*}}.o // ABS: >>> defined in {{.*}}.o
// ABS: >>> referenced by {{.*}}.o:(.text+0x0) // ABS: >>> referenced by {{.*}}.o:(.text+0x0)

lld/test/ELF/arm-thumb-adr.s

Show All 22 Lines
.section .text.03, "ax", %progbits .section .text.03, "ax", %progbits
.balign 4 .balign 4
.space 1016 .space 1016
.type target2, %function .type target2, %function
target2: target2:
nop nop
bx lr bx lr
// CHECK: 000110b4 _start: // CHECK: 000110b4 <_start>:
// CHECK-NEXT: 110b4: adr r0, #0 // CHECK-NEXT: 110b4: adr r0, #0
// CHECK-NEXT: 110b6: adr r1, #1020 // CHECK-NEXT: 110b6: adr r1, #1020
// CHECK: 000110b8 target1: // CHECK: 000110b8 <target1>:
// CHECK-NEXT: 110b8: nop // CHECK-NEXT: 110b8: nop
// CHECK-NEXT: 110ba: bx lr // CHECK-NEXT: 110ba: bx lr
// CHECK: 000114b4 target2: // CHECK: 000114b4 <target2>:
// CHECK-NEXT: 114b4: nop // CHECK-NEXT: 114b4: nop
// CHECK-NEXT: 114b6: bx lr // CHECK-NEXT: 114b6: bx lr

lld/test/ELF/arm-thumb-blx.s

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
// CHECK: Disassembly of section .R_ARM_CALL24_callee2: // CHECK: Disassembly of section .R_ARM_CALL24_callee2:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT-THUMB: callee_thumb_low: // CHECK-NEXT-THUMB: callee_thumb_low:
// CHECK-NEXT-THUMB: 100: 70 47 bx lr // CHECK-NEXT-THUMB: 100: 70 47 bx lr
// CHECK: Disassembly of section .caller: // CHECK: Disassembly of section .caller:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK: _start: // CHECK: <_start>:
// Align(0x10000,4) - 0xff50 (65360) + 4 = 0xb4 = callee_low // Align(0x10000,4) - 0xff50 (65360) + 4 = 0xb4 = callee_low
// CHECK-NEXT-THUMB: 10000: f0 f7 58 e8 blx #-65360 // CHECK-NEXT-THUMB: 10000: f0 f7 58 e8 blx #-65360
// CHECK-NEXT-THUMB: 10004: 00 bf nop // CHECK-NEXT-THUMB: 10004: 00 bf nop
// Align(0x10006,4) - 0xff54 (65364) + 4 = 0xb4 = callee_low // Align(0x10006,4) - 0xff54 (65364) + 4 = 0xb4 = callee_low
// CHECK-NEXT-THUMB: 10006: f0 f7 56 e8 blx #-65364 // CHECK-NEXT-THUMB: 10006: f0 f7 56 e8 blx #-65364
// CHECK-NEXT-THUMB: 1000a: 00 bf nop // CHECK-NEXT-THUMB: 1000a: 00 bf nop
// Align(0x1000c,4) + 0xf0 (240) + 4 = 0x10100 = callee_high // Align(0x1000c,4) + 0xf0 (240) + 4 = 0x10100 = callee_high
// CHECK-NEXT-THUMB: 1000c: 00 f0 78 e8 blx #240 // CHECK-NEXT-THUMB: 1000c: 00 f0 78 e8 blx #240
Show All 27 Lines

lld/test/ELF/arm-thumb-branch.s

Show All 35 Lines
.section .callee_high, "ax",%progbits .section .callee_high, "ax",%progbits
.align 2 .align 2
.type callee_high,%function .type callee_high,%function
callee_high: callee_high:
bx lr bx lr
// CHECK: Disassembly of section .callee1: // CHECK: Disassembly of section .callee1:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: callee_low: // CHECK-NEXT: <callee_low>:
// CHECK-NEXT: b4: 70 47 bx lr // CHECK-NEXT: b4: 70 47 bx lr
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: Disassembly of section .caller: // CHECK-NEXT: Disassembly of section .caller:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 10000: f0 f7 58 f8 bl #-65360 // CHECK-NEXT: 10000: f0 f7 58 f8 bl #-65360
// CHECK-NEXT: 10004: f0 f7 56 b8 b.w #-65364 // CHECK-NEXT: 10004: f0 f7 56 b8 b.w #-65364
// CHECK-NEXT: 10008: 30 f4 54 a8 beq.w #-65368 // CHECK-NEXT: 10008: 30 f4 54 a8 beq.w #-65368
// CHECK-NEXT: 1000c: 00 f0 0c f8 bl #24 // CHECK-NEXT: 1000c: 00 f0 0c f8 bl #24
// CHECK-NEXT: 10010: 00 f0 0a b8 b.w #20 // CHECK-NEXT: 10010: 00 f0 0a b8 b.w #20
// CHECK-NEXT: 10014: 40 f0 08 80 bne.w #16 // CHECK-NEXT: 10014: 40 f0 08 80 bne.w #16
// CHECK-NEXT: 10018: ff f3 ff d7 bl #16777214 // CHECK-NEXT: 10018: ff f3 ff d7 bl #16777214
// CHECK-NEXT: 1001c: ff f3 fd 97 b.w #16777210 // CHECK-NEXT: 1001c: ff f3 fd 97 b.w #16777210
// CHECK-NEXT: 10020: 3f f3 ff af bgt.w #1048574 // CHECK-NEXT: 10020: 3f f3 ff af bgt.w #1048574
// CHECK-NEXT: 10024: 70 47 bx lr // CHECK-NEXT: 10024: 70 47 bx lr
// CHECK-NEXT: 10026: // CHECK-NEXT: 10026:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: Disassembly of section .callee2: // CHECK-NEXT: Disassembly of section .callee2:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: callee_high: // CHECK-NEXT: <callee_high>:
// CHECK-NEXT: 10028: 70 47 bx lr // CHECK-NEXT: 10028: 70 47 bx lr

lld/test/ELF/arm-thumb-condbranch-thunk.s

Show All 29 Lines
.globl _start .globl _start
_start: _start:
FUNCTION 00 FUNCTION 00
// Long Range Thunk needed for 16Mb range branch, can reach pre-created Thunk // Long Range Thunk needed for 16Mb range branch, can reach pre-created Thunk
// Section // Section
bl tfunc33 bl tfunc33
// CHECK1: Disassembly of section .text: // CHECK1: Disassembly of section .text:
// CHECK1-EMPTY: // CHECK1-EMPTY:
// CHECK1-NEXT: tfunc00: // CHECK1-NEXT: <tfunc00>:
// CHECK1-NEXT: 80000: 70 47 bx lr // CHECK1-NEXT: 80000: 70 47 bx lr
// CHECK1-NEXT: 80002: 7f f3 ff d7 bl #0xf7fffe // CHECK1-NEXT: 80002: 7f f3 ff d7 bl #0xf7fffe
// CHECK1: __Thumbv7ABSLongThunk_tfunc05: // CHECK1: <__Thumbv7ABSLongThunk_tfunc05>:
// CHECK1-NEXT: 80008: 7f f2 fa bf b.w #0x27fff4 <tfunc05> // CHECK1-NEXT: 80008: 7f f2 fa bf b.w #0x27fff4 <tfunc05>
// CHECK1: __Thumbv7ABSLongThunk_tfunc00: // CHECK1: <__Thumbv7ABSLongThunk_tfunc00>:
// CHECK1-NEXT: 8000c: ff f7 f8 bf b.w #-0x10 <tfunc00> // CHECK1-NEXT: 8000c: ff f7 f8 bf b.w #-0x10 <tfunc00>
FUNCTION 01 FUNCTION 01
// tfunc02 is within range of tfunc02 // tfunc02 is within range of tfunc02
beq.w tfunc02 beq.w tfunc02
// tfunc05 is out of range, and we can't reach the pre-created Thunk Section // tfunc05 is out of range, and we can't reach the pre-created Thunk Section
// create a new one. // create a new one.
bne.w tfunc05 bne.w tfunc05
// CHECK2: tfunc01: // CHECK2: <tfunc01>:
// CHECK2-NEXT: 100000: 70 47 bx lr // CHECK2-NEXT: 100000: 70 47 bx lr
// CHECK2-NEXT: 100002: 3f f0 fd a7 beq.w #0x7fffa <tfunc02> // CHECK2-NEXT: 100002: 3f f0 fd a7 beq.w #0x7fffa <tfunc02>
// CHECK2-NEXT: 100006: 7f f4 ff a7 bne.w #-0x80002 <__Thumbv7ABSLongThunk_tfunc05> // CHECK2-NEXT: 100006: 7f f4 ff a7 bne.w #-0x80002 <__Thumbv7ABSLongThunk_tfunc05>
FUNCTION 02 FUNCTION 02
// We can reach the Thunk Section created for bne.w tfunc05 // We can reach the Thunk Section created for bne.w tfunc05
bne.w tfunc05 bne.w tfunc05
beq.w tfunc00 beq.w tfunc00
// CHECK3: 180000: 70 47 bx lr // CHECK3: 180000: 70 47 bx lr
// CHECK3-NEXT: 180002: 40 f4 01 80 bne.w #-0xffffe <__Thumbv7ABSLongThunk_tfunc05> // CHECK3-NEXT: 180002: 40 f4 01 80 bne.w #-0xffffe <__Thumbv7ABSLongThunk_tfunc05>
// CHECK3-NEXT: 180006: 00 f4 01 80 beq.w #-0xffffe <__Thumbv7ABSLongThunk_tfunc00> // CHECK3-NEXT: 180006: 00 f4 01 80 beq.w #-0xffffe <__Thumbv7ABSLongThunk_tfunc00>
FUNCTION 03 FUNCTION 03
FUNCTION 04 FUNCTION 04
FUNCTION 05 FUNCTION 05
FUNCTION 06 FUNCTION 06
FUNCTION 07 FUNCTION 07
FUNCTION 08 FUNCTION 08
FUNCTION 09 FUNCTION 09
// CHECK4: __Thumbv7ABSLongThunk_tfunc03: // CHECK4: <__Thumbv7ABSLongThunk_tfunc03>:
// CHECK4-NEXT: 500004: ff f4 fc bf b.w #-0x300008 <tfunc03> // CHECK4-NEXT: 500004: ff f4 fc bf b.w #-0x300008 <tfunc03>
FUNCTION 10 FUNCTION 10
// We can't reach any Thunk Section, create a new one // We can't reach any Thunk Section, create a new one
beq.w tfunc03 beq.w tfunc03
// CHECK5: tfunc10: // CHECK5: <tfunc10>:
// CHECK5-NEXT: 580000: 70 47 bx lr // CHECK5-NEXT: 580000: 70 47 bx lr
// CHECK5-NEXT: 580002: 3f f4 ff a7 beq.w #-0x80002 <__Thumbv7ABSLongThunk_tfunc03> // CHECK5-NEXT: 580002: 3f f4 ff a7 beq.w #-0x80002 <__Thumbv7ABSLongThunk_tfunc03>
FUNCTION 11 FUNCTION 11
FUNCTION 12 FUNCTION 12
FUNCTION 13 FUNCTION 13
FUNCTION 14 FUNCTION 14
FUNCTION 15 FUNCTION 15
FUNCTION 16 FUNCTION 16
FUNCTION 17 FUNCTION 17
FUNCTION 18 FUNCTION 18
FUNCTION 19 FUNCTION 19
FUNCTION 20 FUNCTION 20
FUNCTION 21 FUNCTION 21
FUNCTION 22 FUNCTION 22
FUNCTION 23 FUNCTION 23
FUNCTION 24 FUNCTION 24
FUNCTION 25 FUNCTION 25
FUNCTION 26 FUNCTION 26
FUNCTION 27 FUNCTION 27
FUNCTION 28 FUNCTION 28
FUNCTION 29 FUNCTION 29
FUNCTION 30 FUNCTION 30
FUNCTION 31 FUNCTION 31
// CHECK6: __Thumbv7ABSLongThunk_tfunc33: // CHECK6: <__Thumbv7ABSLongThunk_tfunc33>:
// CHECK6-NEXT: 1000004: ff f0 fc bf b.w #0xffff8 <tfunc33> // CHECK6-NEXT: 1000004: ff f0 fc bf b.w #0xffff8 <tfunc33>
// CHECK6: __Thumbv7ABSLongThunk_tfunc00: // CHECK6: <__Thumbv7ABSLongThunk_tfunc00>:
// CHECK6-NEXT: 1000008: 7f f4 fa 97 b.w #-0xf8000c <tfunc00> // CHECK6-NEXT: 1000008: 7f f4 fa 97 b.w #-0xf8000c <tfunc00>
FUNCTION 32 FUNCTION 32
FUNCTION 33 FUNCTION 33
// We should be able to reach an existing ThunkSection. // We should be able to reach an existing ThunkSection.
b.w tfunc00 b.w tfunc00
// CHECK7: tfunc33: // CHECK7: <tfunc33>:
// CHECK7-NEXT: 1100000: 70 47 bx lr // CHECK7-NEXT: 1100000: 70 47 bx lr
// CHECK7-NEXT: 1100002: 00 f7 01 b8 b.w #-0xffffe <__Thumbv7ABSLongThunk_tfunc00> // CHECK7-NEXT: 1100002: 00 f7 01 b8 b.w #-0xffffe <__Thumbv7ABSLongThunk_tfunc00>

lld/test/ELF/arm-thumb-interwork-abs.s

Show All 21 Lines// WARN: branch and link relocation: R_ARM_CALL to non STT_FUNC symbol: sym interworking not performed; consider using directive '.type sym, %function' to give symbol type STT_FUNC if interworking between ARM and Thumb is required
blx sym blx sym
.thumb .thumb
thumb_caller: thumb_caller:
b sym b sym
bl sym bl sym
blx sym blx sym
// WARN: branch and link relocation: R_ARM_THM_CALL to non STT_FUNC symbol: sym interworking not performed; consider using directive '.type sym, %function' to give symbol type STT_FUNC if interworking between ARM and Thumb is required // WARN: branch and link relocation: R_ARM_THM_CALL to non STT_FUNC symbol: sym interworking not performed; consider using directive '.type sym, %function' to give symbol type STT_FUNC if interworking between ARM and Thumb is required
// CHECK: 00012000 arm_caller: // CHECK: 00012000 <arm_caller>:
// CHECK-NEXT: 12000: b #4088 // CHECK-NEXT: 12000: b #4088
// CHECK-NEXT: 12004: bl #4084 // CHECK-NEXT: 12004: bl #4084
// CHECK-NEXT: 12008: blx #4080 // CHECK-NEXT: 12008: blx #4080
// CHECK: 0001200c thumb_caller: // CHECK: 0001200c <thumb_caller>:
// CHECK-NEXT: 1200c: b.w #4080 // CHECK-NEXT: 1200c: b.w #4080
// CHECK-NEXT: 12010: bl #4076 // CHECK-NEXT: 12010: bl #4076
// CHECK-NEXT: 12014: blx #4076 // CHECK-NEXT: 12014: blx #4076

lld/test/ELF/arm-thumb-interwork-notfunc.s

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
bl thumb_func_with_explicit_notype bl thumb_func_with_explicit_notype
blx .arm_target blx .arm_target
blx arm_func_with_notype blx arm_func_with_notype
blx arm_func_with_explicit_notype blx arm_func_with_explicit_notype
blx .thumb_target blx .thumb_target
blx thumb_func_with_notype blx thumb_func_with_notype
blx thumb_func_with_explicit_notype blx thumb_func_with_explicit_notype
// CHECK: 00012008 _start: // CHECK: 00012008 <_start>:
// CHECK-NEXT: 12008: b #-16 // CHECK-NEXT: 12008: b #-16
// CHECK-NEXT: 1200c: b #-20 // CHECK-NEXT: 1200c: b #-20
// CHECK-NEXT: 12010: b #-24 // CHECK-NEXT: 12010: b #-24
// CHECK-NEXT: 12014: b #-24 // CHECK-NEXT: 12014: b #-24
// CHECK-NEXT: 12018: b #-28 // CHECK-NEXT: 12018: b #-28
// CHECK-NEXT: 1201c: b #-32 // CHECK-NEXT: 1201c: b #-32
// CHECK-NEXT: 12020: bl #-40 // CHECK-NEXT: 12020: bl #-40
// CHECK-NEXT: 12024: bl #-44 // CHECK-NEXT: 12024: bl #-44
// CHECK-NEXT: 12028: bl #-48 // CHECK-NEXT: 12028: bl #-48
// CHECK-NEXT: 1202c: bl #-48 // CHECK-NEXT: 1202c: bl #-48
// CHECK-NEXT: 12030: bl #-52 // CHECK-NEXT: 12030: bl #-52
// CHECK-NEXT: 12034: bl #-56 // CHECK-NEXT: 12034: bl #-56
// CHECK-NEXT: 12038: blx #-64 // CHECK-NEXT: 12038: blx #-64
// CHECK-NEXT: 1203c: blx #-68 // CHECK-NEXT: 1203c: blx #-68
// CHECK-NEXT: 12040: blx #-72 // CHECK-NEXT: 12040: blx #-72
// CHECK-NEXT: 12044: blx #-72 // CHECK-NEXT: 12044: blx #-72
// CHECK-NEXT: 12048: blx #-76 // CHECK-NEXT: 12048: blx #-76
// CHECK-NEXT: 1204c: blx #-80 // CHECK-NEXT: 1204c: blx #-80
// CHECK: 00012050 thumb_caller: // CHECK: 00012050 <thumb_caller>:
// CHECK-NEXT: 12050: b.w #-84 // CHECK-NEXT: 12050: b.w #-84
// CHECK-NEXT: 12054: b.w #-88 // CHECK-NEXT: 12054: b.w #-88
// CHECK-NEXT: 12058: b.w #-92 // CHECK-NEXT: 12058: b.w #-92
// CHECK-NEXT: 1205c: b.w #-92 // CHECK-NEXT: 1205c: b.w #-92
// CHECK-NEXT: 12060: b.w #-96 // CHECK-NEXT: 12060: b.w #-96
// CHECK-NEXT: 12064: b.w #-100 // CHECK-NEXT: 12064: b.w #-100
// CHECK-NEXT: 12068: beq.w #-108 // CHECK-NEXT: 12068: beq.w #-108
// CHECK-NEXT: 1206c: beq.w #-112 // CHECK-NEXT: 1206c: beq.w #-112
Show All 16 Lines

lld/test/ELF/arm-thumb-interwork-shared.s

Show All 12 Lines
bl elsewhere bl elsewhere
bl weakref bl weakref
// Check that we generate a thunk for an undefined symbol called via a plt // Check that we generate a thunk for an undefined symbol called via a plt
// entry. // entry.
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: sym1: // CHECK-NEXT: <sym1>:
// CHECK-NEXT: 11e0: b.w #12 <__ThumbV7PILongThunk_elsewhere> // CHECK-NEXT: 11e0: b.w #12 <__ThumbV7PILongThunk_elsewhere>
// CHECK-NEXT: b.w #20 <__ThumbV7PILongThunk_weakref> // CHECK-NEXT: b.w #20 <__ThumbV7PILongThunk_weakref>
// CHECK-NEXT: blx #68 // CHECK-NEXT: blx #68
// CHECK-NEXT: blx #80 // CHECK-NEXT: blx #80
// CHECK: __ThumbV7PILongThunk_elsewhere: // CHECK: <__ThumbV7PILongThunk_elsewhere>:
// CHECK-NEXT: 11f0: movw r12, #52 // CHECK-NEXT: 11f0: movw r12, #52
// CHECK-NEXT: movt r12, #0 // CHECK-NEXT: movt r12, #0
// CHECK-NEXT: add r12, pc // CHECK-NEXT: add r12, pc
// CHECK-NEXT: bx r12 // CHECK-NEXT: bx r12
// CHECK: __ThumbV7PILongThunk_weakref: // CHECK: <__ThumbV7PILongThunk_weakref>:
// CHECK-NEXT: 11fc: movw r12, #56 // CHECK-NEXT: 11fc: movw r12, #56
// CHECK-NEXT: movt r12, #0 // CHECK-NEXT: movt r12, #0
// CHECK-NEXT: add r12, pc // CHECK-NEXT: add r12, pc
// CHECK-NEXT: bx r12 // CHECK-NEXT: bx r12
// CHECK: Disassembly of section .plt: // CHECK: Disassembly of section .plt:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: $a: // CHECK-NEXT: <$a>:
// CHECK-NEXT: 1210: str lr, [sp, #-4]! // CHECK-NEXT: 1210: str lr, [sp, #-4]!
// CHECK-NEXT: add lr, pc, #0, #12 // CHECK-NEXT: add lr, pc, #0, #12
// CHECK-NEXT: add lr, lr, #8192 // CHECK-NEXT: add lr, lr, #8192
// CHECK-NEXT: ldr pc, [lr, #148]! // CHECK-NEXT: ldr pc, [lr, #148]!
// CHECK: $d: // CHECK: <$d>:
// CHECK-NEXT: 1220: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK-NEXT: 1220: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK-NEXT: .word 0xd4d4d4d4 // CHECK-NEXT: .word 0xd4d4d4d4
// CHECK-NEXT: .word 0xd4d4d4d4 // CHECK-NEXT: .word 0xd4d4d4d4
// CHECK-NEXT: .word 0xd4d4d4d4 // CHECK-NEXT: .word 0xd4d4d4d4
// CHECK: $a: // CHECK: <$a>:
// CHECK-NEXT: 1230: add r12, pc, #0, #12 // CHECK-NEXT: 1230: add r12, pc, #0, #12
// CHECK-NEXT: add r12, r12, #8192 // CHECK-NEXT: add r12, r12, #8192
// CHECK-NEXT: ldr pc, [r12, #124]! // CHECK-NEXT: ldr pc, [r12, #124]!
// CHECK: $d: // CHECK: <$d>:
// CHECK-NEXT: 123c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK-NEXT: 123c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK: $a: // CHECK: <$a>:
// CHECK-NEXT: 1240: add r12, pc, #0, #12 // CHECK-NEXT: 1240: add r12, pc, #0, #12
// CHECK-NEXT: add r12, r12, #8192 // CHECK-NEXT: add r12, r12, #8192
// CHECK-NEXT: ldr pc, [r12, #112]! // CHECK-NEXT: ldr pc, [r12, #112]!
// CHECK: $d: // CHECK: <$d>:
// CHECK-NEXT: 124c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK-NEXT: 124c: d4 d4 d4 d4 .word 0xd4d4d4d4

lld/test/ELF/arm-thumb-interwork-thunk-v5.s

Show All 20 Lines// support for the blx instruction for Thumb BL and BLX to an Arm symbol.
.type _start, %function .type _start, %function
.balign 0x1000 .balign 0x1000
_start: _start:
b thumb_func b thumb_func
bl thumb_func bl thumb_func
blx thumb_func blx thumb_func
bx lr bx lr
// CHECK: _start: // CHECK: <_start>:
// CHECK-NEXT: 12000: 03 00 00 ea b #12 <__ARMv5ABSLongThunk_thumb_func> // CHECK-NEXT: 12000: 03 00 00 ea b #12 <__ARMv5ABSLongThunk_thumb_func>
// CHECK-NEXT: 12004: 01 00 00 fa blx #4 <thumb_func> // CHECK-NEXT: 12004: 01 00 00 fa blx #4 <thumb_func>
// CHECK-NEXT: 12008: 00 00 00 fa blx #0 <thumb_func> // CHECK-NEXT: 12008: 00 00 00 fa blx #0 <thumb_func>
// CHECK-NEXT: 1200c: 1e ff 2f e1 bx lr // CHECK-NEXT: 1200c: 1e ff 2f e1 bx lr
// CHECK: thumb_func: // CHECK: <thumb_func>:
// CHECK-NEXT: 12010: 70 47 bx lr // CHECK-NEXT: 12010: 70 47 bx lr
// CHECK: __ARMv5ABSLongThunk_thumb_func: // CHECK: <__ARMv5ABSLongThunk_thumb_func>:
// CHECK-NEXT: 12014: 04 f0 1f e5 ldr pc, [pc, #-4] // CHECK-NEXT: 12014: 04 f0 1f e5 ldr pc, [pc, #-4]
// CHECK: $d: // CHECK: <$d>:
// CHECK-NEXT: 12018: 11 20 01 00 .word 0x00012011 // CHECK-NEXT: 12018: 11 20 01 00 .word 0x00012011
// CHECK-PI: _start: // CHECK-PI: <_start>:
// CHECK-PI-NEXT: 2000: 03 00 00 ea b #12 <__ARMV5PILongThunk_thumb_func> // CHECK-PI-NEXT: 2000: 03 00 00 ea b #12 <__ARMV5PILongThunk_thumb_func>
// CHECK-PI-NEXT: 2004: 01 00 00 fa blx #4 <thumb_func> // CHECK-PI-NEXT: 2004: 01 00 00 fa blx #4 <thumb_func>
// CHECK-PI-NEXT: 2008: 00 00 00 fa blx #0 <thumb_func> // CHECK-PI-NEXT: 2008: 00 00 00 fa blx #0 <thumb_func>
// CHECK-PI-NEXT: 200c: 1e ff 2f e1 bx lr // CHECK-PI-NEXT: 200c: 1e ff 2f e1 bx lr
// CHECK-PI: thumb_func: // CHECK-PI: <thumb_func>:
// CHECK-PI-NEXT: 2010: 70 47 bx lr // CHECK-PI-NEXT: 2010: 70 47 bx lr
// CHECK-PI: __ARMV5PILongThunk_thumb_func: // CHECK-PI: <__ARMV5PILongThunk_thumb_func>:
// CHECK-PI-NEXT: 2014: 04 c0 9f e5 ldr r12, [pc, #4] // CHECK-PI-NEXT: 2014: 04 c0 9f e5 ldr r12, [pc, #4]
// CHECK-PI-NEXT: 2018: 0c c0 8f e0 add r12, pc, r12 // CHECK-PI-NEXT: 2018: 0c c0 8f e0 add r12, pc, r12
// CHECK-PI-NEXT: 201c: 1c ff 2f e1 bx r12 // CHECK-PI-NEXT: 201c: 1c ff 2f e1 bx r12
// CHECK-PI: $d: // CHECK-PI: <$d>:
// CHECK-PI-NEXT: 2020: f1 ff ff ff .word 0xfffffff1 // CHECK-PI-NEXT: 2020: f1 ff ff ff .word 0xfffffff1
.section .text.1, "ax", %progbits .section .text.1, "ax", %progbits
.thumb .thumb
.hidden thumb_func .hidden thumb_func
.type thumb_func, %function .type thumb_func, %function
thumb_func: thumb_func:
bx lr bx lr

lld/test/ELF/arm-thumb-interwork-thunk.s

Show All 34 Lines
.balign 0x1000 .balign 0x1000
.globl thumb_callee1 .globl thumb_callee1
.type thumb_callee1, %function .type thumb_callee1, %function
thumb_callee1: thumb_callee1:
bx lr bx lr
// CHECK-THUMB: Disassembly of section .R_ARM_JUMP24_callee_1: // CHECK-THUMB: Disassembly of section .R_ARM_JUMP24_callee_1:
// CHECK-THUMB-EMPTY: // CHECK-THUMB-EMPTY:
// CHECK-THUMB: thumb_callee1: // CHECK-THUMB: <thumb_callee1>:
// CHECK-THUMB: 1000: 70 47 bx // CHECK-THUMB: 1000: 70 47 bx
.section .R_ARM_THM_JUMP_callee_low, "ax", %progbits .section .R_ARM_THM_JUMP_callee_low, "ax", %progbits
.arm .arm
.balign 0x100 .balign 0x100
.globl arm_callee1 .globl arm_callee1
.type arm_callee1, %function .type arm_callee1, %function
arm_callee1: arm_callee1:
bx lr bx lr
// Disassembly of section .R_ARM_THM_JUMP_callee_1: // Disassembly of section .R_ARM_THM_JUMP_callee_1:
// CHECK-ARM: arm_callee1: // CHECK-ARM: <arm_callee1>:
// CHECK-ARM-NEXT: 1100: 1e ff 2f e1 bx lr // CHECK-ARM-NEXT: 1100: 1e ff 2f e1 bx lr
// Calling sections // Calling sections
// At present ARM and Thumb interworking thunks are always added to the calling // At present ARM and Thumb interworking thunks are always added to the calling
// section. // section.
.section .arm_caller, "ax", %progbits .section .arm_caller, "ax", %progbits
.arm .arm
.balign 0x100 .balign 0x100
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
// 0x1503 = thumb_callee3 // 0x1503 = thumb_callee3
// CHECK-ARM-ABS-ARM: __ARMv7ABSLongThunk_thumb_callee3: // CHECK-ARM-ABS-ARM: __ARMv7ABSLongThunk_thumb_callee3:
// CHECK-ARM-ABS-ARM-NEXT: 1340: 03 c5 01 e3 movw r12, #5379 // CHECK-ARM-ABS-ARM-NEXT: 1340: 03 c5 01 e3 movw r12, #5379
// CHECK-ARM-ABS-ARM-NEXT: 1344: 00 c0 40 e3 movt r12, #0 // CHECK-ARM-ABS-ARM-NEXT: 1344: 00 c0 40 e3 movt r12, #0
// CHECK-ARM-ABS-ARM-NEXT: 1348: 1c ff 2f e1 bx r12 // CHECK-ARM-ABS-ARM-NEXT: 1348: 1c ff 2f e1 bx r12
// CHECK-PI-ARM: Disassembly of section .arm_caller: // CHECK-PI-ARM: Disassembly of section .arm_caller:
// CHECK-PI-ARM-EMPTY: // CHECK-PI-ARM-EMPTY:
// CHECK-PI-ARM-NEXT: arm_caller: // CHECK-PI-ARM-NEXT: <arm_caller>:
// CHECK-PI-ARM-NEXT: 1300: 3e ff ff fa blx #-776 <thumb_callee1> // CHECK-PI-ARM-NEXT: 1300: 3e ff ff fa blx #-776 <thumb_callee1>
// CHECK-PI-ARM-NEXT: 1304: 3d ff ff fa blx #-780 <thumb_callee1> // CHECK-PI-ARM-NEXT: 1304: 3d ff ff fa blx #-780 <thumb_callee1>
// CHECK-PI-ARM-NEXT: 1308: 06 00 00 ea b #24 <__ARMV7PILongThunk_thumb_callee1> // CHECK-PI-ARM-NEXT: 1308: 06 00 00 ea b #24 <__ARMV7PILongThunk_thumb_callee1>
// CHECK-PI-ARM-NEXT: 130c: 05 00 00 ea b #20 <__ARMV7PILongThunk_thumb_callee1> // CHECK-PI-ARM-NEXT: 130c: 05 00 00 ea b #20 <__ARMV7PILongThunk_thumb_callee1>
// CHECK-PI-ARM-NEXT: 1310: 08 00 00 ea b #32 <__ARMV7PILongThunk_thumb_callee2> // CHECK-PI-ARM-NEXT: 1310: 08 00 00 ea b #32 <__ARMV7PILongThunk_thumb_callee2>
// CHECK-PI-ARM-NEXT: 1314: 0b 00 00 ea b #44 <__ARMV7PILongThunk_thumb_callee3> // CHECK-PI-ARM-NEXT: 1314: 0b 00 00 ea b #44 <__ARMV7PILongThunk_thumb_callee3>
// CHECK-PI-ARM-NEXT: 1318: 78 ff ff ea b #-544 <arm_callee1> // CHECK-PI-ARM-NEXT: 1318: 78 ff ff ea b #-544 <arm_callee1>
// CHECK-PI-ARM-NEXT: 131c: b7 00 00 0a beq #732 <arm_callee2> // CHECK-PI-ARM-NEXT: 131c: b7 00 00 0a beq #732 <arm_callee2>
// CHECK-PI-ARM-NEXT: 1320: b7 00 00 1a bne #732 <arm_callee3> // CHECK-PI-ARM-NEXT: 1320: b7 00 00 1a bne #732 <arm_callee3>
// CHECK-PI-ARM-NEXT: 1324: 1e ff 2f e1 bx lr // CHECK-PI-ARM-NEXT: 1324: 1e ff 2f e1 bx lr
// CHECK-PI-ARM: __ARMV7PILongThunk_thumb_callee1: // CHECK-PI-ARM: <__ARMV7PILongThunk_thumb_callee1>:
// 0x1330 + 8 - 0x337 = 0x1001 = thumb_callee1 // 0x1330 + 8 - 0x337 = 0x1001 = thumb_callee1
// CHECK-PI-ARM-NEXT: 1328: c9 cc 0f e3 movw r12, #64713 // CHECK-PI-ARM-NEXT: 1328: c9 cc 0f e3 movw r12, #64713
// CHECK-PI-ARM-NEXT: 132c: ff cf 4f e3 movt r12, #65535 // CHECK-PI-ARM-NEXT: 132c: ff cf 4f e3 movt r12, #65535
// CHECK-PI-ARM-NEXT: 1330: 0f c0 8c e0 add r12, r12, pc // CHECK-PI-ARM-NEXT: 1330: 0f c0 8c e0 add r12, r12, pc
// CHECK-PI-ARM-NEXT: 1334: 1c ff 2f e1 bx r12 // CHECK-PI-ARM-NEXT: 1334: 1c ff 2f e1 bx r12
// CHECK-PI-ARM: __ARMV7PILongThunk_thumb_callee2: // CHECK-PI-ARM: <__ARMV7PILongThunk_thumb_callee2>:
// CHECK-PI-ARM-NEXT: 1338: b9 c1 00 e3 movw r12, #441 // CHECK-PI-ARM-NEXT: 1338: b9 c1 00 e3 movw r12, #441
// CHECK-PI-ARM-NEXT: 133c: 00 c0 40 e3 movt r12, #0 // CHECK-PI-ARM-NEXT: 133c: 00 c0 40 e3 movt r12, #0
// CHECK-PI-ARM-NEXT: 1340: 0f c0 8c e0 add r12, r12, pc // CHECK-PI-ARM-NEXT: 1340: 0f c0 8c e0 add r12, r12, pc
// CHECK-PI-ARM-NEXT: 1344: 1c ff 2f e1 bx r12 // CHECK-PI-ARM-NEXT: 1344: 1c ff 2f e1 bx r12
// CHECK-PI-ARM: __ARMV7PILongThunk_thumb_callee3: // CHECK-PI-ARM: <__ARMV7PILongThunk_thumb_callee3>:
// 0x1340 + 8 + 0x1b9 = 0x1501 // 0x1340 + 8 + 0x1b9 = 0x1501
// CHECK-PI-ARM-NEXT: 1348: ab c1 00 e3 movw r12, #427 // CHECK-PI-ARM-NEXT: 1348: ab c1 00 e3 movw r12, #427
// CHECK-PI-ARM-NEXT: 134c: 00 c0 40 e3 movt r12, #0 // CHECK-PI-ARM-NEXT: 134c: 00 c0 40 e3 movt r12, #0
// CHECK-PI-ARM-NEXT: 1350: 0f c0 8c e0 add r12, r12, pc // CHECK-PI-ARM-NEXT: 1350: 0f c0 8c e0 add r12, r12, pc
// CHECK-PI-ARM-NEXT: 1354: 1c ff 2f e1 bx r12 // CHECK-PI-ARM-NEXT: 1354: 1c ff 2f e1 bx r12
// 1350 + 8 + 0x1ab = 0x1503 // 1350 + 8 + 0x1ab = 0x1503
// All PLT entries are ARM, no need for interworking thunks // All PLT entries are ARM, no need for interworking thunks
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b.w arm_callee3 b.w arm_callee3
// Conditional branches also require interworking thunks, they can use the // Conditional branches also require interworking thunks, they can use the
// same interworking thunks. // same interworking thunks.
beq.w arm_callee1 beq.w arm_callee1
beq.w arm_callee2 beq.w arm_callee2
bne.w arm_callee3 bne.w arm_callee3
// CHECK-ABS-THUMB: Disassembly of section .thumb_caller: // CHECK-ABS-THUMB: Disassembly of section .thumb_caller:
// CHECK-ABS-THUMB-EMPTY: // CHECK-ABS-THUMB-EMPTY:
// CHECK-ABS-THUMB-NEXT: thumb_caller: // CHECK-ABS-THUMB-NEXT: <thumb_caller>:
// CHECK-ABS-THUMB-NEXT: 1400: ff f7 7e ee blx #-772 // CHECK-ABS-THUMB-NEXT: 1400: ff f7 7e ee blx #-772
// CHECK-ABS-THUMB-NEXT: 1404: ff f7 7c ee blx #-776 // CHECK-ABS-THUMB-NEXT: 1404: ff f7 7c ee blx #-776
// CHECK-ABS-THUMB-NEXT: 1408: 00 f0 0a b8 b.w #20 <__Thumbv7ABSLongThunk_arm_callee1> // CHECK-ABS-THUMB-NEXT: 1408: 00 f0 0a b8 b.w #20 <__Thumbv7ABSLongThunk_arm_callee1>
// CHECK-ABS-THUMB-NEXT: 140c: 00 f0 0d b8 b.w #26 <__Thumbv7ABSLongThunk_arm_callee2> // CHECK-ABS-THUMB-NEXT: 140c: 00 f0 0d b8 b.w #26 <__Thumbv7ABSLongThunk_arm_callee2>
// CHECK-ABS-THUMB-NEXT: 1410: 00 f0 10 b8 b.w #32 <__Thumbv7ABSLongThunk_arm_callee3> // CHECK-ABS-THUMB-NEXT: 1410: 00 f0 10 b8 b.w #32 <__Thumbv7ABSLongThunk_arm_callee3>
// CHECK-ABS-THUMB-NEXT: 1414: 00 f0 04 80 beq.w #8 <__Thumbv7ABSLongThunk_arm_callee1> // CHECK-ABS-THUMB-NEXT: 1414: 00 f0 04 80 beq.w #8 <__Thumbv7ABSLongThunk_arm_callee1>
// CHECK-ABS-THUMB-NEXT: 1418: 00 f0 07 80 beq.w #14 <__Thumbv7ABSLongThunk_arm_callee2> // CHECK-ABS-THUMB-NEXT: 1418: 00 f0 07 80 beq.w #14 <__Thumbv7ABSLongThunk_arm_callee2>
// CHECK-ABS-THUMB-NEXT: 141c: 40 f0 0a 80 bne.w #20 <__Thumbv7ABSLongThunk_arm_callee3> // CHECK-ABS-THUMB-NEXT: 141c: 40 f0 0a 80 bne.w #20 <__Thumbv7ABSLongThunk_arm_callee3>
// CHECK-ABS-THUMB: __Thumbv7ABSLongThunk_arm_callee1: // CHECK-ABS-THUMB: <__Thumbv7ABSLongThunk_arm_callee1>:
// 0x1100 = arm_callee1 // 0x1100 = arm_callee1
// CHECK-ABS-THUMB-NEXT: 1420: 41 f2 00 1c movw r12, #4352 // CHECK-ABS-THUMB-NEXT: 1420: 41 f2 00 1c movw r12, #4352
// CHECK-ABS-THUMB-NEXT: 1424: c0 f2 00 0c movt r12, #0 // CHECK-ABS-THUMB-NEXT: 1424: c0 f2 00 0c movt r12, #0
// CHECK-ABS-THUMB-NEXT: 1428: 60 47 bx r12 // CHECK-ABS-THUMB-NEXT: 1428: 60 47 bx r12
// CHECK-ABS-THUMB: __Thumbv7ABSLongThunk_arm_callee2: // CHECK-ABS-THUMB: <__Thumbv7ABSLongThunk_arm_callee2>:
// 0x1600 = arm_callee2 // 0x1600 = arm_callee2
// CHECK-ABS-THUMB-NEXT: 142a: 41 f2 00 6c movw r12, #5632 // CHECK-ABS-THUMB-NEXT: 142a: 41 f2 00 6c movw r12, #5632
// CHECK-ABS-THUMB-NEXT: 142e: c0 f2 00 0c movt r12, #0 // CHECK-ABS-THUMB-NEXT: 142e: c0 f2 00 0c movt r12, #0
// CHECK-ABS-THUMB-NEXT: 1432: 60 47 bx r12 // CHECK-ABS-THUMB-NEXT: 1432: 60 47 bx r12
// 0x1604 = arm_callee3 // 0x1604 = arm_callee3
// CHECK-ABS-THUMB: __Thumbv7ABSLongThunk_arm_callee3: // CHECK-ABS-THUMB: <__Thumbv7ABSLongThunk_arm_callee3>:
// CHECK-ABS-THUMB-NEXT: 1434: 41 f2 04 6c movw r12, #5636 // CHECK-ABS-THUMB-NEXT: 1434: 41 f2 04 6c movw r12, #5636
// CHECK-ABS-THUMB-NEXT: 1438: c0 f2 00 0c movt r12, #0 // CHECK-ABS-THUMB-NEXT: 1438: c0 f2 00 0c movt r12, #0
// CHECK-ABS-THUMB-NEXT: 143c: 60 47 bx r12 // CHECK-ABS-THUMB-NEXT: 143c: 60 47 bx r12
// CHECK-PI-THUMB: Disassembly of section .thumb_caller: // CHECK-PI-THUMB: Disassembly of section .thumb_caller:
// CHECK-PI-THUMB-EMPTY: // CHECK-PI-THUMB-EMPTY:
// CHECK-PI-THUMB-NEXT: thumb_caller: // CHECK-PI-THUMB-NEXT: <thumb_caller>:
// CHECK-PI-THUMB-NEXT: 1400: ff f7 7e ee blx #-772 // CHECK-PI-THUMB-NEXT: 1400: ff f7 7e ee blx #-772
// CHECK-PI-THUMB-NEXT: 1404: ff f7 7c ee blx #-776 // CHECK-PI-THUMB-NEXT: 1404: ff f7 7c ee blx #-776
// CHECK-PI-THUMB-NEXT: 1408: 00 f0 0a b8 b.w #20 <__ThumbV7PILongThunk_arm_callee1> // CHECK-PI-THUMB-NEXT: 1408: 00 f0 0a b8 b.w #20 <__ThumbV7PILongThunk_arm_callee1>
// CHECK-PI-THUMB-NEXT: 140c: 00 f0 0e b8 b.w #28 <__ThumbV7PILongThunk_arm_callee2> // CHECK-PI-THUMB-NEXT: 140c: 00 f0 0e b8 b.w #28 <__ThumbV7PILongThunk_arm_callee2>
// CHECK-PI-THUMB-NEXT: 1410: 00 f0 12 b8 b.w #36 <__ThumbV7PILongThunk_arm_callee3> // CHECK-PI-THUMB-NEXT: 1410: 00 f0 12 b8 b.w #36 <__ThumbV7PILongThunk_arm_callee3>
// CHECK-PI-THUMB-NEXT: 1414: 00 f0 04 80 beq.w #8 <__ThumbV7PILongThunk_arm_callee1> // CHECK-PI-THUMB-NEXT: 1414: 00 f0 04 80 beq.w #8 <__ThumbV7PILongThunk_arm_callee1>
// CHECK-PI-THUMB-NEXT: 1418: 00 f0 08 80 beq.w #16 <__ThumbV7PILongThunk_arm_callee2> // CHECK-PI-THUMB-NEXT: 1418: 00 f0 08 80 beq.w #16 <__ThumbV7PILongThunk_arm_callee2>
// CHECK-PI-THUMB-NEXT: 141c: 40 f0 0c 80 bne.w #24 <__ThumbV7PILongThunk_arm_callee3> // CHECK-PI-THUMB-NEXT: 141c: 40 f0 0c 80 bne.w #24 <__ThumbV7PILongThunk_arm_callee3>
// CHECK-PI-THUMB: __ThumbV7PILongThunk_arm_callee1: // CHECK-PI-THUMB: <__ThumbV7PILongThunk_arm_callee1>:
// 0x1428 + 4 - 0x32c = 0x1100 = arm_callee1 // 0x1428 + 4 - 0x32c = 0x1100 = arm_callee1
// CHECK-PI-THUMB-NEXT: 1420: 4f f6 d4 4c movw r12, #64724 // CHECK-PI-THUMB-NEXT: 1420: 4f f6 d4 4c movw r12, #64724
// CHECK-PI-THUMB-NEXT: 1424: cf f6 ff 7c movt r12, #65535 // CHECK-PI-THUMB-NEXT: 1424: cf f6 ff 7c movt r12, #65535
// CHECK-PI-THUMB-NEXT: 1428: fc 44 add r12, pc // CHECK-PI-THUMB-NEXT: 1428: fc 44 add r12, pc
// CHECK-PI-THUMB-NEXT: 142a: 60 47 bx r12 // CHECK-PI-THUMB-NEXT: 142a: 60 47 bx r12
// CHECK-PI-THUMB: __ThumbV7PILongThunk_arm_callee2: // CHECK-PI-THUMB: <__ThumbV7PILongThunk_arm_callee2>:
// 0x1434 + 4 + 0x1c8 = 0x1600 = arm_callee2 // 0x1434 + 4 + 0x1c8 = 0x1600 = arm_callee2
// CHECK-PI-THUMB-NEXT: 142c: 40 f2 c8 1c movw r12, #456 // CHECK-PI-THUMB-NEXT: 142c: 40 f2 c8 1c movw r12, #456
// CHECK-PI-THUMB-NEXT: 1430: c0 f2 00 0c movt r12, #0 // CHECK-PI-THUMB-NEXT: 1430: c0 f2 00 0c movt r12, #0
// CHECK-PI-THUMB-NEXT: 1434: fc 44 add r12, pc // CHECK-PI-THUMB-NEXT: 1434: fc 44 add r12, pc
// CHECK-PI-THUMB-NEXT: 1436: 60 47 bx r12 // CHECK-PI-THUMB-NEXT: 1436: 60 47 bx r12
// CHECK-PI-THUMB: __ThumbV7PILongThunk_arm_callee3: // CHECK-PI-THUMB: <__ThumbV7PILongThunk_arm_callee3>:
// 0x1440 + 4 + 0x1c0 = 0x1604 = arm_callee3 // 0x1440 + 4 + 0x1c0 = 0x1604 = arm_callee3
// CHECK-PI-THUMB-NEXT: 1438: 40 f2 c0 1c movw r12, #448 // CHECK-PI-THUMB-NEXT: 1438: 40 f2 c0 1c movw r12, #448
// CHECK-PI-THUMB-NEXT: 143c: c0 f2 00 0c movt r12, #0 // CHECK-PI-THUMB-NEXT: 143c: c0 f2 00 0c movt r12, #0
// CHECK-PI-THUMB-NEXT: 1440: fc 44 add r12, pc // CHECK-PI-THUMB-NEXT: 1440: fc 44 add r12, pc
// CHECK-PI-THUMB-NEXT: 1442: 60 47 bx r12 // CHECK-PI-THUMB-NEXT: 1442: 60 47 bx r12
// CHECK-PI-THUMB-PLT: Disassembly of section .arm_caller: // CHECK-PI-THUMB-PLT: Disassembly of section .arm_caller:
// CHECK-PI-THUMB-PLT-EMPTY: // CHECK-PI-THUMB-PLT-EMPTY:
Show All 40 Lines
bx lr bx lr
.globl thumb_callee3 .globl thumb_callee3
.type thumb_callee3, %function .type thumb_callee3, %function
thumb_callee3: thumb_callee3:
bx lr bx lr
// CHECK-THUMB: Disassembly of section .R_ARM_JUMP24_callee_2: // CHECK-THUMB: Disassembly of section .R_ARM_JUMP24_callee_2:
// CHECK-THUMB-EMPTY: // CHECK-THUMB-EMPTY:
// CHECK-THUMB-NEXT: thumb_callee2: // CHECK-THUMB-NEXT: <thumb_callee2>:
// CHECK-THUMB-NEXT: 1500: 70 47 bx lr // CHECK-THUMB-NEXT: 1500: 70 47 bx lr
// CHECK-THUMB: thumb_callee3: // CHECK-THUMB: <thumb_callee3>:
// CHECK-THUMB-NEXT: 1502: 70 47 bx lr // CHECK-THUMB-NEXT: 1502: 70 47 bx lr
.section .R_ARM_THM_JUMP_callee_high, "ax", %progbits .section .R_ARM_THM_JUMP_callee_high, "ax", %progbits
.arm .arm
.balign 0x100 .balign 0x100
.globl arm_callee2 .globl arm_callee2
.type arm_callee2, %function .type arm_callee2, %function
arm_callee2: arm_callee2:
bx lr bx lr
.globl arm_callee3 .globl arm_callee3
.type arm_callee3, %function .type arm_callee3, %function
arm_callee3: arm_callee3:
bx lr bx lr
// CHECK-ARM: Disassembly of section .R_ARM_THM_JUMP_callee_2: // CHECK-ARM: Disassembly of section .R_ARM_THM_JUMP_callee_2:
// CHECK-ARM-EMPTY: // CHECK-ARM-EMPTY:
// CHECK-ARM-NEXT: arm_callee2: // CHECK-ARM-NEXT: <arm_callee2>:
// CHECK-ARM-NEXT: 1600: 1e ff 2f e1 bx lr // CHECK-ARM-NEXT: 1600: 1e ff 2f e1 bx lr
// CHECK-ARM: arm_callee3: // CHECK-ARM: <arm_callee3>:
// CHECK-ARM-NEXT: 1604: 1e ff 2f e1 bx lr // CHECK-ARM-NEXT: 1604: 1e ff 2f e1 bx lr
// _start section just calls the arm and thumb calling sections // _start section just calls the arm and thumb calling sections
.text .text
.arm .arm
.globl _start .globl _start
.balign 0x100 .balign 0x100
.type _start, %function .type _start, %function
▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines

lld/test/ELF/arm-thumb-ldrlit.s

Show All 22 Lines
.section .text.03, "ax", %progbits .section .text.03, "ax", %progbits
.balign 4 .balign 4
.space 1016 .space 1016
.type target2, %function .type target2, %function
target2: target2:
nop nop
bx lr bx lr
// CHECK: 000110b4 _start: // CHECK: 000110b4 <_start>:
// CHECK-NEXT: 110b4: ldr r0, [pc, #0] // CHECK-NEXT: 110b4: ldr r0, [pc, #0]
// CHECK-NEXT: 110b6: ldr r1, [pc, #1020] // CHECK-NEXT: 110b6: ldr r1, [pc, #1020]
// CHECK: 000110b8 target1: // CHECK: 000110b8 <target1>:
// CHECK-NEXT: 110b8: nop // CHECK-NEXT: 110b8: nop
// CHECK-NEXT: 110ba: bx lr // CHECK-NEXT: 110ba: bx lr
// CHECK: 000114b4 target2: // CHECK: 000114b4 <target2>:
// CHECK-NEXT: 114b4: nop // CHECK-NEXT: 114b4: nop
// CHECK-NEXT: 114b6: bx lr // CHECK-NEXT: 114b6: bx lr

lld/test/ELF/arm-thumb-mix-range-thunk-os.s

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
bl tfunc31 bl tfunc31
// ARM b and beq are in range but need Thunk to change state to Thumb // ARM b and beq are in range but need Thunk to change state to Thumb
b tfunc31 b tfunc31
beq tfunc31 beq tfunc31
// afunc32 is out of range of ARM branch and branch and link // afunc32 is out of range of ARM branch and branch and link
bl afunc32 bl afunc32
b afunc32 b afunc32
bne afunc32 bne afunc32
// CHECK1: afunc00: // CHECK1: <afunc00>:
// CHECK1-NEXT: 100000: 1e ff 2f e1 bx lr // CHECK1-NEXT: 100000: 1e ff 2f e1 bx lr
// CHECK1-NEXT: 100004: fd ff 7b fa blx #32505844 // CHECK1-NEXT: 100004: fd ff 7b fa blx #32505844
// CHECK1-NEXT: 100008: fd ff 3b ea b #15728628 // CHECK1-NEXT: 100008: fd ff 3b ea b #15728628
// CHECK1-NEXT: 10000c: fc ff 3b 0a beq #15728624 // CHECK1-NEXT: 10000c: fc ff 3b 0a beq #15728624
// CHECK1-NEXT: 100010: fa ff 7f eb bl #33554408 // CHECK1-NEXT: 100010: fa ff 7f eb bl #33554408
// CHECK1-NEXT: 100014: f9 ff 7f ea b #33554404 // CHECK1-NEXT: 100014: f9 ff 7f ea b #33554404
// CHECK1-NEXT: 100018: f8 ff 7f 1a bne #33554400 // CHECK1-NEXT: 100018: f8 ff 7f 1a bne #33554400
THUMBFUNCTION 01 THUMBFUNCTION 01
// Expect Thumb bl to be in range (can use blx to change state) // Expect Thumb bl to be in range (can use blx to change state)
bl afunc14 bl afunc14
// In range but need thunk to change state to Thumb // In range but need thunk to change state to Thumb
b.w afunc14 b.w afunc14
// CHECK2: tfunc01: // CHECK2: <tfunc01>:
// CHECK2-NEXT: 200000: 70 47 bx lr // CHECK2-NEXT: 200000: 70 47 bx lr
// CHECK2-NEXT: 200002: ff f0 fe c7 blx #13631484 // CHECK2-NEXT: 200002: ff f0 fe c7 blx #13631484
// CHECK2-NEXT: 200006: 00 f2 03 90 b.w #14680070 <__Thumbv7ABSLongThunk_afunc14> // CHECK2-NEXT: 200006: 00 f2 03 90 b.w #14680070 <__Thumbv7ABSLongThunk_afunc14>
ARMFUNCTION 02 ARMFUNCTION 02
THUMBFUNCTION 03 THUMBFUNCTION 03
ARMFUNCTION 04 ARMFUNCTION 04
THUMBFUNCTION 05 THUMBFUNCTION 05
ARMFUNCTION 06 ARMFUNCTION 06
THUMBFUNCTION 07 THUMBFUNCTION 07
ARMFUNCTION 08 ARMFUNCTION 08
THUMBFUNCTION 09 THUMBFUNCTION 09
ARMFUNCTION 10 ARMFUNCTION 10
THUMBFUNCTION 11 THUMBFUNCTION 11
ARMFUNCTION 12 ARMFUNCTION 12
THUMBFUNCTION 13 THUMBFUNCTION 13
ARMFUNCTION 14 ARMFUNCTION 14
// CHECK3: __ARMv7ABSLongThunk_tfunc31: // CHECK3: <__ARMv7ABSLongThunk_tfunc31>:
// CHECK3-NEXT: 1000004: 01 c0 00 e3 movw r12, #1 // CHECK3-NEXT: 1000004: 01 c0 00 e3 movw r12, #1
// CHECK3-NEXT: 1000008: 00 c2 40 e3 movt r12, #512 // CHECK3-NEXT: 1000008: 00 c2 40 e3 movt r12, #512
// CHECK3-NEXT: 100000c: 1c ff 2f e1 bx r12 // CHECK3-NEXT: 100000c: 1c ff 2f e1 bx r12
// CHECK4: __Thumbv7ABSLongThunk_afunc14: // CHECK4: <__Thumbv7ABSLongThunk_afunc14>:
// CHECK4-NEXT: 1000010: 40 f2 00 0c movw r12, #0 // CHECK4-NEXT: 1000010: 40 f2 00 0c movw r12, #0
// CHECK4-NEXT: 1000014: c0 f2 f0 0c movt r12, #240 // CHECK4-NEXT: 1000014: c0 f2 f0 0c movt r12, #240
// CHECK4-NEXT: 1000018: 60 47 bx r12 // CHECK4-NEXT: 1000018: 60 47 bx r12
THUMBFUNCTION 15 THUMBFUNCTION 15
ARMFUNCTION 16 ARMFUNCTION 16
THUMBFUNCTION 17 THUMBFUNCTION 17
ARMFUNCTION 18 ARMFUNCTION 18
THUMBFUNCTION 19 THUMBFUNCTION 19
ARMFUNCTION 20 ARMFUNCTION 20
THUMBFUNCTION 21 THUMBFUNCTION 21
ARMFUNCTION 22 ARMFUNCTION 22
THUMBFUNCTION 23 THUMBFUNCTION 23
ARMFUNCTION 24 ARMFUNCTION 24
THUMBFUNCTION 25 THUMBFUNCTION 25
ARMFUNCTION 26 ARMFUNCTION 26
THUMBFUNCTION 27 THUMBFUNCTION 27
ARMFUNCTION 28 ARMFUNCTION 28
THUMBFUNCTION 29 THUMBFUNCTION 29
ARMFUNCTION 30 ARMFUNCTION 30
// Expect precreated Thunk Section here // Expect precreated Thunk Section here
// CHECK5: __Thumbv7ABSLongThunk_afunc00: // CHECK5: <__Thumbv7ABSLongThunk_afunc00>:
// CHECK5-NEXT: 1f00004: 40 f2 00 0c movw r12, #0 // CHECK5-NEXT: 1f00004: 40 f2 00 0c movw r12, #0
// CHECK5-NEXT: 1f00008: c0 f2 10 0c movt r12, #16 // CHECK5-NEXT: 1f00008: c0 f2 10 0c movt r12, #16
// CHECK5-NEXT: 1f0000c: 60 47 bx r12 // CHECK5-NEXT: 1f0000c: 60 47 bx r12
THUMBFUNCTION 31 THUMBFUNCTION 31
ARMFUNCTION 32 ARMFUNCTION 32
THUMBFUNCTION 33 THUMBFUNCTION 33
// Out of range, can only reach closest Thunk Section // Out of range, can only reach closest Thunk Section
bl afunc00 bl afunc00
// CHECK6: tfunc33: // CHECK6: <tfunc33>:
// CHECK6-NEXT: 2200000: 70 47 bx lr // CHECK6-NEXT: 2200000: 70 47 bx lr
// CHECK6-NEXT: 2200002: ff f4 ff ff bl #-3145730 // CHECK6-NEXT: 2200002: ff f4 ff ff bl #-3145730
ARMFUNCTION 34 ARMFUNCTION 34
// Out of range, can reach earlier Thunk Section // Out of range, can reach earlier Thunk Section
// CHECK7: afunc34: // CHECK7: <afunc34>:
// CHECK7-NEXT: 2300000: 1e ff 2f e1 bx lr // CHECK7-NEXT: 2300000: 1e ff 2f e1 bx lr
// CHECK7-NEXT: 2300004: fe ff ef fa blx #-4194312 <__Thumbv7ABSLongThunk_afunc00 // CHECK7-NEXT: 2300004: fe ff ef fa blx #-4194312 <__Thumbv7ABSLongThunk_afunc00
bl afunc00 bl afunc00
THUMBFUNCTION 35 THUMBFUNCTION 35
ARMFUNCTION 36 ARMFUNCTION 36
THUMBFUNCTION 37 THUMBFUNCTION 37
ARMFUNCTION 38 ARMFUNCTION 38
THUMBFUNCTION 39 THUMBFUNCTION 39
ARMFUNCTION 40 ARMFUNCTION 40
THUMBFUNCTION 41 THUMBFUNCTION 41
ARMFUNCTION 42 ARMFUNCTION 42
THUMBFUNCTION 43 THUMBFUNCTION 43
ARMFUNCTION 44 ARMFUNCTION 44
THUMBFUNCTION 45 THUMBFUNCTION 45
// Expect precreated Thunk Section here // Expect precreated Thunk Section here
// CHECK8: __ARMv7ABSLongThunk_tfunc35: // CHECK8: <__ARMv7ABSLongThunk_tfunc35>:
// CHECK8-NEXT: 2e00004: 01 c0 00 e3 movw r12, #1 // CHECK8-NEXT: 2e00004: 01 c0 00 e3 movw r12, #1
// CHECK8-NEXT: 2e00008: 40 c2 40 e3 movt r12, #576 // CHECK8-NEXT: 2e00008: 40 c2 40 e3 movt r12, #576
// CHECK8-NEXT: 2e0000c: 1c ff 2f e1 bx r12 // CHECK8-NEXT: 2e0000c: 1c ff 2f e1 bx r12
ARMFUNCTION 46 ARMFUNCTION 46
THUMBFUNCTION 47 THUMBFUNCTION 47
ARMFUNCTION 48 ARMFUNCTION 48
THUMBFUNCTION 49 THUMBFUNCTION 49
ARMFUNCTION 50 ARMFUNCTION 50
// Expect precreated Thunk Section here // Expect precreated Thunk Section here
// CHECK9: __Thumbv7ABSLongThunk_afunc34: // CHECK9: <__Thumbv7ABSLongThunk_afunc34>:
// CHECK9-NEXT: 3300004: 40 f2 00 0c movw r12, #0 // CHECK9-NEXT: 3300004: 40 f2 00 0c movw r12, #0
// CHECK9-NEXT: 3300008: c0 f2 30 2c movt r12, #560 // CHECK9-NEXT: 3300008: c0 f2 30 2c movt r12, #560
// CHECK9-NEXT: 330000c: 60 47 bx r12 // CHECK9-NEXT: 330000c: 60 47 bx r12
// CHECK9: __Thumbv7ABSLongThunk_tfunc35: // CHECK9: <__Thumbv7ABSLongThunk_tfunc35>:
// CHECK9-NEXT: 330000e: ff f4 f7 97 b.w #-15728658 <tfunc35> // CHECK9-NEXT: 330000e: ff f4 f7 97 b.w #-15728658 <tfunc35>
THUMBFUNCTION 51 THUMBFUNCTION 51
ARMFUNCTION 52 ARMFUNCTION 52
THUMBFUNCTION 53 THUMBFUNCTION 53
ARMFUNCTION 54 ARMFUNCTION 54
THUMBFUNCTION 55 THUMBFUNCTION 55
ARMFUNCTION 56 ARMFUNCTION 56
THUMBFUNCTION 57 THUMBFUNCTION 57
ARMFUNCTION 58 ARMFUNCTION 58
THUMBFUNCTION 59 THUMBFUNCTION 59
ARMFUNCTION 60 ARMFUNCTION 60
THUMBFUNCTION 61 THUMBFUNCTION 61
ARMFUNCTION 62 ARMFUNCTION 62
THUMBFUNCTION 63 THUMBFUNCTION 63
ARMFUNCTION 64 ARMFUNCTION 64
// afunc34 is in range, as is tfunc35 but a branch needs a state change Thunk // afunc34 is in range, as is tfunc35 but a branch needs a state change Thunk
bl afunc34 bl afunc34
b tfunc35 b tfunc35
// CHECK10: afunc64: // CHECK10: <afunc64>:
// CHECK10-NEXT: 4100000: 1e ff 2f e1 bx lr // CHECK10-NEXT: 4100000: 1e ff 2f e1 bx lr
// CHECK10-NEXT: 4100004: fd ff 87 eb bl #-31457292 <afunc34> // CHECK10-NEXT: 4100004: fd ff 87 eb bl #-31457292 <afunc34>
// CHECK10-NEXT: 4100008: fd ff b3 ea b #-19922956 <__ARMv7ABSLongThunk_tfunc35> // CHECK10-NEXT: 4100008: fd ff b3 ea b #-19922956 <__ARMv7ABSLongThunk_tfunc35>
THUMBFUNCTION 65 THUMBFUNCTION 65
// afunc34 and tfunc35 are both out of range // afunc34 and tfunc35 are both out of range
bl afunc34 bl afunc34
bl tfunc35 bl tfunc35
// CHECK11: tfunc65: // CHECK11: <tfunc65>:
// CHECK11: 4200000: 70 47 bx lr // CHECK11: 4200000: 70 47 bx lr
// CHECK11-NEXT: 4200002: ff f4 ff d7 bl #-15728642 // CHECK11-NEXT: 4200002: ff f4 ff d7 bl #-15728642
// CHECK11-NEXT: 4200006: 00 f5 02 d0 bl #-15728636 // CHECK11-NEXT: 4200006: 00 f5 02 d0 bl #-15728636

lld/test/ELF/arm-thumb-narrow-branch-check.s

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
bx lr bx lr
.global callee_high_far .global callee_high_far
.type callee_high_far,%function .type callee_high_far,%function
callee_high_far = 0x180d callee_high_far = 0x180d
// CHECK: Disassembly of section .R_ARM_PC11_1: // CHECK: Disassembly of section .R_ARM_PC11_1:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: callee_low: // CHECK-NEXT: <callee_low>:
// CHECK-NEXT: 1000: 70 47 bx lr // CHECK-NEXT: 1000: 70 47 bx lr
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: Disassembly of section .caller: // CHECK-NEXT: Disassembly of section .caller:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: callers: // CHECK-NEXT: <callers>:
// 1004 - 0x800 (2048) + 4 = 0x808 = callee_low_far // 1004 - 0x800 (2048) + 4 = 0x808 = callee_low_far
// CHECK-NEXT: 1004: 00 e4 b #-2048 // CHECK-NEXT: 1004: 00 e4 b #-2048
// 1006 - 0xa (10) + 4 = 0x1000 = callee_low // 1006 - 0xa (10) + 4 = 0x1000 = callee_low
// CHECK-NEXT: 1006: fb e7 b #-10 // CHECK-NEXT: 1006: fb e7 b #-10
// 1008 + 4 + 4 = 0x1010 = callee_high // 1008 + 4 + 4 = 0x1010 = callee_high
// CHECK-NEXT: 1008: 02 e0 b #4 // CHECK-NEXT: 1008: 02 e0 b #4
// 100a + 0x7fe (2046) + 4 = 0x180c = callee_high_far // 100a + 0x7fe (2046) + 4 = 0x180c = callee_high_far
// CHECK-NEXT: 100a: ff e3 b #2046 // CHECK-NEXT: 100a: ff e3 b #2046
// CHECK-NEXT: 100c: 70 47 bx lr // CHECK-NEXT: 100c: 70 47 bx lr
// CHECK-NEXT: 100e: 00 bf nop // CHECK-NEXT: 100e: 00 bf nop
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: Disassembly of section .R_ARM_PC11_2: // CHECK-NEXT: Disassembly of section .R_ARM_PC11_2:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: callee_high: // CHECK-NEXT: <callee_high>:
// CHECK-NEXT: 1010: 70 47 bx lr // CHECK-NEXT: 1010: 70 47 bx lr
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: Disassembly of section .text: // CHECK-NEXT: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 1014: ff f7 f6 ff bl #-20 // CHECK-NEXT: 1014: ff f7 f6 ff bl #-20
// CHECK-NEXT: 1018: 70 47 bx lr // CHECK-NEXT: 1018: 70 47 bx lr

lld/test/ELF/arm-thumb-no-undefined-thunk.s

Show All 12 Lines
.global .global
_start: _start:
bl target bl target
b target b target
b.w target b.w target
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// 0x110b8 = next instruction // 0x110b8 = next instruction
// CHECK: 110b4: {{.*}} bl #0 // CHECK: 110b4: {{.*}} bl #0
// CHECK-NEXT: 110b8: {{.*}} b.w #0 <_start+0x8> // CHECK-NEXT: 110b8: {{.*}} b.w #0 <_start+0x8>
// CHECK-NEXT: 110bc: {{.*}} b.w #0 <_start+0xc> // CHECK-NEXT: 110bc: {{.*}} b.w #0 <_start+0xc>

lld/test/ELF/arm-thumb-plt-range-thunk-os.s

Show All 30 Lines
bx lr bx lr
preemptible: preemptible:
bl far_preemptible bl far_preemptible
bl far_nonpreemptible bl far_nonpreemptible
bl far_nonpreemptible_alias bl far_nonpreemptible_alias
bx lr bx lr
// CHECK1: Disassembly of section .text: // CHECK1: Disassembly of section .text:
// CHECK1-EMPTY: // CHECK1-EMPTY:
// CHECK1-NEXT: sym1: // CHECK1-NEXT: <sym1>:
// CHECK1-NEXT: 2000000: 00 f0 00 d8 bl #8388608 // CHECK1-NEXT: 2000000: 00 f0 00 d8 bl #8388608
// CHECK1-NEXT: 2000004: 00 f0 04 d8 bl #8388616 // CHECK1-NEXT: 2000004: 00 f0 04 d8 bl #8388616
// CHECK1-NEXT: 2000008: 70 47 bx lr // CHECK1-NEXT: 2000008: 70 47 bx lr
// CHECK1: preemptible: // CHECK1: <preemptible>:
// CHECK1-NEXT: 200000a: 00 f0 07 d8 bl #8388622 // CHECK1-NEXT: 200000a: 00 f0 07 d8 bl #8388622
// CHECK1-NEXT: 200000e: 00 f0 0b d8 bl #8388630 // CHECK1-NEXT: 200000e: 00 f0 0b d8 bl #8388630
// CHECK1-NEXT: 2000012: 00 f0 09 d8 bl #8388626 // CHECK1-NEXT: 2000012: 00 f0 09 d8 bl #8388626
// CHECK1-NEXT: 2000016: 70 47 bx lr // CHECK1-NEXT: 2000016: 70 47 bx lr
.section .text.2, "ax", %progbits .section .text.2, "ax", %progbits
.balign 0x0800000 .balign 0x0800000
bx lr bx lr
// CHECK2: __ThumbV7PILongThunk_elsewhere: // CHECK2: <__ThumbV7PILongThunk_elsewhere>:
// CHECK2-NEXT: 2800004: 40 f2 20 0c movw r12, #32 // CHECK2-NEXT: 2800004: 40 f2 20 0c movw r12, #32
// CHECK2-NEXT: 2800008: c0 f2 80 1c movt r12, #384 // CHECK2-NEXT: 2800008: c0 f2 80 1c movt r12, #384
// CHECK2-NEXT: 280000c: fc 44 add r12, pc // CHECK2-NEXT: 280000c: fc 44 add r12, pc
// CHECK2-NEXT: 280000e: 60 47 bx r12 // CHECK2-NEXT: 280000e: 60 47 bx r12
// CHECK2: __ThumbV7PILongThunk_preemptible: // CHECK2: <__ThumbV7PILongThunk_preemptible>:
// CHECK2-NEXT: 2800010: 40 f2 24 0c movw r12, #36 // CHECK2-NEXT: 2800010: 40 f2 24 0c movw r12, #36
// CHECK2-NEXT: 2800014: c0 f2 80 1c movt r12, #384 // CHECK2-NEXT: 2800014: c0 f2 80 1c movt r12, #384
// CHECK2-NEXT: 2800018: fc 44 add r12, pc // CHECK2-NEXT: 2800018: fc 44 add r12, pc
// CHECK2-NEXT: 280001a: 60 47 bx r12 // CHECK2-NEXT: 280001a: 60 47 bx r12
// CHECK2: __ThumbV7PILongThunk_far_preemptible: // CHECK2: <__ThumbV7PILongThunk_far_preemptible>:
// CHECK2-NEXT: 280001c: 40 f2 28 0c movw r12, #40 // CHECK2-NEXT: 280001c: 40 f2 28 0c movw r12, #40
// CHECK2-NEXT: 2800020: c0 f2 80 1c movt r12, #384 // CHECK2-NEXT: 2800020: c0 f2 80 1c movt r12, #384
// CHECK2-NEXT: 2800024: fc 44 add r12, pc // CHECK2-NEXT: 2800024: fc 44 add r12, pc
// CHECK2-NEXT: 2800026: 60 47 bx r12 // CHECK2-NEXT: 2800026: 60 47 bx r12
// CHECK2: __ThumbV7PILongThunk_far_nonpreemptible: // CHECK2: <__ThumbV7PILongThunk_far_nonpreemptible>:
// CHECK2-NEXT: 2800028: 4f f6 cd 7c movw r12, #65485 // CHECK2-NEXT: 2800028: 4f f6 cd 7c movw r12, #65485
// CHECK2-NEXT: 280002c: c0 f2 7f 1c movt r12, #383 // CHECK2-NEXT: 280002c: c0 f2 7f 1c movt r12, #383
// CHECK2-NEXT: 2800030: fc 44 add r12, pc // CHECK2-NEXT: 2800030: fc 44 add r12, pc
// CHECK2-NEXT: 2800032: 60 47 bx r12 // CHECK2-NEXT: 2800032: 60 47 bx r12
.section .text.3, "ax", %progbits .section .text.3, "ax", %progbits
.balign 0x2000000 .balign 0x2000000
far_preemptible: far_preemptible:
far_nonpreemptible: far_nonpreemptible:
bl elsewhere bl elsewhere
.section .text.4, "ax", %progbits .section .text.4, "ax", %progbits
.balign 0x2000000 .balign 0x2000000
far_nonpreemptible_alias: far_nonpreemptible_alias:
bl elsewhere bl elsewhere
// CHECK3: far_preemptible: // CHECK3: <far_preemptible>:
// CHECK3: 4000000: 00 f0 16 e8 blx #44 // CHECK3: 4000000: 00 f0 16 e8 blx #44
// CHECK4: Disassembly of section .plt: // CHECK4: Disassembly of section .plt:
// CHECK4-EMPTY: // CHECK4-EMPTY:
// CHECK4-NEXT: $a: // CHECK4-NEXT: <$a>:
// CHECK4-NEXT: 4000010: 04 e0 2d e5 str lr, [sp, #-4]! // CHECK4-NEXT: 4000010: 04 e0 2d e5 str lr, [sp, #-4]!
// CHECK4-NEXT: 4000014: 00 e6 8f e2 add lr, pc, #0, #12 // CHECK4-NEXT: 4000014: 00 e6 8f e2 add lr, pc, #0, #12
// CHECK4-NEXT: 4000018: 02 ea 8e e2 add lr, lr, #8192 // CHECK4-NEXT: 4000018: 02 ea 8e e2 add lr, lr, #8192
// CHECK4-NEXT: 400001c: a4 f0 be e5 ldr pc, [lr, #164]! // CHECK4-NEXT: 400001c: a4 f0 be e5 ldr pc, [lr, #164]!
// CHECK4: $d: // CHECK4: <$d>:
// CHECK4-NEXT: 4000020: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4-NEXT: 4000020: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK4-NEXT: 4000024: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4-NEXT: 4000024: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK4-NEXT: 4000028: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4-NEXT: 4000028: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK4-NEXT: 400002c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4-NEXT: 400002c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK4: $a: // CHECK4: <$a>:
// CHECK4-NEXT: 4000030: 00 c6 8f e2 add r12, pc, #0, #12 // CHECK4-NEXT: 4000030: 00 c6 8f e2 add r12, pc, #0, #12
// CHECK4-NEXT: 4000034: 02 ca 8c e2 add r12, r12, #8192 // CHECK4-NEXT: 4000034: 02 ca 8c e2 add r12, r12, #8192
// CHECK4-NEXT: 4000038: 8c f0 bc e5 ldr pc, [r12, #140]! // CHECK4-NEXT: 4000038: 8c f0 bc e5 ldr pc, [r12, #140]!
// CHECK4: $d: // CHECK4: <$d>:
// CHECK4-NEXT: 400003c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4-NEXT: 400003c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK4: $a: // CHECK4: <$a>:
// CHECK4-NEXT: 4000040: 00 c6 8f e2 add r12, pc, #0, #12 // CHECK4-NEXT: 4000040: 00 c6 8f e2 add r12, pc, #0, #12
// CHECK4-NEXT: 4000044: 02 ca 8c e2 add r12, r12, #8192 // CHECK4-NEXT: 4000044: 02 ca 8c e2 add r12, r12, #8192
// CHECK4-NEXT: 4000048: 80 f0 bc e5 ldr pc, [r12, #128]! // CHECK4-NEXT: 4000048: 80 f0 bc e5 ldr pc, [r12, #128]!
// CHECK4: $d: // CHECK4: <$d>:
// CHECK4-NEXT: 400004c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4-NEXT: 400004c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK4: $a: // CHECK4: <$a>:
// CHECK4-NEXT: 4000050: 00 c6 8f e2 add r12, pc, #0, #12 // CHECK4-NEXT: 4000050: 00 c6 8f e2 add r12, pc, #0, #12
// CHECK4-NEXT: 4000054: 02 ca 8c e2 add r12, r12, #8192 // CHECK4-NEXT: 4000054: 02 ca 8c e2 add r12, r12, #8192
// CHECK4-NEXT: 4000058: 74 f0 bc e5 ldr pc, [r12, #116]! // CHECK4-NEXT: 4000058: 74 f0 bc e5 ldr pc, [r12, #116]!
// CHECK4: $d: // CHECK4: <$d>:
// CHECK4-NEXT: 400005c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK4-NEXT: 400005c: d4 d4 d4 d4 .word 0xd4d4d4d4

lld/test/ELF/arm-thumb-plt-reloc.s

Show All 18 Lines
// to test the different forms of interworking. // to test the different forms of interworking.
bl func1 bl func1
bl func2 bl func2
bl func3 bl func3
// Executable, expect no PLT // Executable, expect no PLT
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: func1: // CHECK-NEXT: <func1>:
// CHECK-NEXT: 110b4: 70 47 bx lr // CHECK-NEXT: 110b4: 70 47 bx lr
// CHECK: func2: // CHECK: <func2>:
// CHECK-NEXT: 110b6: 70 47 bx lr // CHECK-NEXT: 110b6: 70 47 bx lr
// CHECK: func3: // CHECK: <func3>:
// CHECK-NEXT: 110b8: 70 47 bx lr // CHECK-NEXT: 110b8: 70 47 bx lr
// CHECK-NEXT: 110ba: d4 d4 // CHECK-NEXT: 110ba: d4 d4
// CHECK: _start: // CHECK: <_start>:
// . + 4 -12 = 0x110b4 = func1 // . + 4 -12 = 0x110b4 = func1
// CHECK-NEXT: 110bc: ff f7 fa ff bl #-12 // CHECK-NEXT: 110bc: ff f7 fa ff bl #-12
// . + 4 -14 = 0x110b6 = func2 // . + 4 -14 = 0x110b6 = func2
// CHECK-NEXT: 110c0: ff f7 f9 ff bl #-14 // CHECK-NEXT: 110c0: ff f7 f9 ff bl #-14
// . + 4 -16 = 0x110b8 = func3 // . + 4 -16 = 0x110b8 = func3
// CHECK-NEXT: 110c4: ff f7 f8 ff bl #-16 // CHECK-NEXT: 110c4: ff f7 f8 ff bl #-16
// Expect PLT entries as symbols can be preempted // Expect PLT entries as symbols can be preempted
// .text is Thumb and .plt is ARM, llvm-objdump can currently only disassemble // .text is Thumb and .plt is ARM, llvm-objdump can currently only disassemble
// as ARM or Thumb. Work around by disassembling twice. // as ARM or Thumb. Work around by disassembling twice.
// DSO: Disassembly of section .text: // DSO: Disassembly of section .text:
// DSO-EMPTY: // DSO-EMPTY:
// DSO-NEXT: func1: // DSO-NEXT: <func1>:
// DSO-NEXT: 1214: 70 47 bx lr // DSO-NEXT: 1214: 70 47 bx lr
// DSO: func2: // DSO: <func2>:
// DSO-NEXT: 1216: 70 47 bx lr // DSO-NEXT: 1216: 70 47 bx lr
// DSO: func3: // DSO: <func3>:
// DSO-NEXT: 1218: 70 47 bx lr // DSO-NEXT: 1218: 70 47 bx lr
// DSO-NEXT: 121a: d4 d4 bmi #-88 // DSO-NEXT: 121a: d4 d4 bmi #-88
// DSO: _start: // DSO: <_start>:
// . + 48 + 4 = 0x1250 = PLT func1 // . + 48 + 4 = 0x1250 = PLT func1
// DSO-NEXT: 121c: 00 f0 18 e8 blx #48 // DSO-NEXT: 121c: 00 f0 18 e8 blx #48
// . + 60 + 4 = 0x1260 = PLT func2 // . + 60 + 4 = 0x1260 = PLT func2
// DSO-NEXT: 1220: 00 f0 1e e8 blx #60 // DSO-NEXT: 1220: 00 f0 1e e8 blx #60
// . + 72 + 4 = 0x1270 = PLT func3 // . + 72 + 4 = 0x1270 = PLT func3
// DSO-NEXT: 1224: 00 f0 24 e8 blx #72 // DSO-NEXT: 1224: 00 f0 24 e8 blx #72
// DSO: Disassembly of section .plt: // DSO: Disassembly of section .plt:
// DSO-EMPTY: // DSO-EMPTY:
// DSO-NEXT: $a: // DSO-NEXT: <$a>:
// DSO-NEXT: 1230: 04 e0 2d e5 str lr, [sp, #-4]! // DSO-NEXT: 1230: 04 e0 2d e5 str lr, [sp, #-4]!
// (0x1234 + 8) + (0 RoR 12) + 8192 + 164 = 0x32e0 = .got.plt[3] // (0x1234 + 8) + (0 RoR 12) + 8192 + 164 = 0x32e0 = .got.plt[3]
// DSO-NEXT: 1234: 00 e6 8f e2 add lr, pc, #0, #12 // DSO-NEXT: 1234: 00 e6 8f e2 add lr, pc, #0, #12
// DSO-NEXT: 1238: 02 ea 8e e2 add lr, lr, #8192 // DSO-NEXT: 1238: 02 ea 8e e2 add lr, lr, #8192
// DSO-NEXT: 123c: a4 f0 be e5 ldr pc, [lr, #164]! // DSO-NEXT: 123c: a4 f0 be e5 ldr pc, [lr, #164]!
// DSO: $d: // DSO: <$d>:
// DSO-NEXT: 1240: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 1240: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO-NEXT: 1244: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 1244: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO-NEXT: 1248: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 1248: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO-NEXT: 124c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 124c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO: $a: // DSO: <$a>:
// (0x1250 + 8) + (0 RoR 12) + 8192 + 140 = 0x32e4 // (0x1250 + 8) + (0 RoR 12) + 8192 + 140 = 0x32e4
// DSO-NEXT: 1250: 00 c6 8f e2 add r12, pc, #0, #12 // DSO-NEXT: 1250: 00 c6 8f e2 add r12, pc, #0, #12
// DSO-NEXT: 1254: 02 ca 8c e2 add r12, r12, #8192 // DSO-NEXT: 1254: 02 ca 8c e2 add r12, r12, #8192
// DSO-NEXT: 1258: 8c f0 bc e5 ldr pc, [r12, #140]! // DSO-NEXT: 1258: 8c f0 bc e5 ldr pc, [r12, #140]!
// DSO: $d: // DSO: <$d>:
// DSO-NEXT: 125c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 125c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO: $a: // DSO: <$a>:
// (0x1260 + 8) + (0 RoR 12) + 8192 + 128 = 0x32e8 // (0x1260 + 8) + (0 RoR 12) + 8192 + 128 = 0x32e8
// DSO-NEXT: 1260: 00 c6 8f e2 add r12, pc, #0, #12 // DSO-NEXT: 1260: 00 c6 8f e2 add r12, pc, #0, #12
// DSO-NEXT: 1264: 02 ca 8c e2 add r12, r12, #8192 // DSO-NEXT: 1264: 02 ca 8c e2 add r12, r12, #8192
// DSO-NEXT: 1268: 80 f0 bc e5 ldr pc, [r12, #128]! // DSO-NEXT: 1268: 80 f0 bc e5 ldr pc, [r12, #128]!
// DSO: $d: // DSO: <$d>:
// DSO-NEXT: 126c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 126c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSO: $a: // DSO: <$a>:
// (0x1270 + 8) + (0 RoR 12) + 8192 + 116 = 0x32ec // (0x1270 + 8) + (0 RoR 12) + 8192 + 116 = 0x32ec
// DSO-NEXT: 1270: 00 c6 8f e2 add r12, pc, #0, #12 // DSO-NEXT: 1270: 00 c6 8f e2 add r12, pc, #0, #12
// DSO-NEXT: 1274: 02 ca 8c e2 add r12, r12, #8192 // DSO-NEXT: 1274: 02 ca 8c e2 add r12, r12, #8192
// DSO-NEXT: 1278: 74 f0 bc e5 ldr pc, [r12, #116]! // DSO-NEXT: 1278: 74 f0 bc e5 ldr pc, [r12, #116]!
// DSO: $d: // DSO: <$d>:
// DSO-NEXT: 127c: d4 d4 d4 d4 .word 0xd4d4d4d4 // DSO-NEXT: 127c: d4 d4 d4 d4 .word 0xd4d4d4d4
// DSOREL: Name: .got.plt // DSOREL: Name: .got.plt
// DSOREL-NEXT: Type: SHT_PROGBITS // DSOREL-NEXT: Type: SHT_PROGBITS
// DSOREL-NEXT: Flags [ // DSOREL-NEXT: Flags [
// DSOREL-NEXT: SHF_ALLOC // DSOREL-NEXT: SHF_ALLOC
// DSOREL-NEXT: SHF_WRITE // DSOREL-NEXT: SHF_WRITE
// DSOREL-NEXT: ] // DSOREL-NEXT: ]
Show All 12 Lines

lld/test/ELF/arm-thumb-range-thunk-os.s

Show All 38 Lines
// tfunc00 and tfunc15 are within 16Mb no Range Thunks expected // tfunc00 and tfunc15 are within 16Mb no Range Thunks expected
bl tfunc00 bl tfunc00
bl tfunc15 bl tfunc15
// tfunc16 is > 16Mb away, expect a Range Thunk to be generated, to go into // tfunc16 is > 16Mb away, expect a Range Thunk to be generated, to go into
// the first of the pre-created ThunkSections. // the first of the pre-created ThunkSections.
bl tfunc16 bl tfunc16
// CHECK1: Disassembly of section .text: // CHECK1: Disassembly of section .text:
// CHECK1-EMPTY: // CHECK1-EMPTY:
// CHECK1-NEXT: _start: // CHECK1-NEXT: <_start>:
// CHECK1-NEXT: 100000: ff f0 fe ff bl #1048572 // CHECK1-NEXT: 100000: ff f0 fe ff bl #1048572
// CHECK1-NEXT: 100004: ff f3 fc d7 bl #16777208 // CHECK1-NEXT: 100004: ff f3 fc d7 bl #16777208
// CHECK1-NEXT: 100008: ff f2 fc d7 bl #15728632 // CHECK1-NEXT: 100008: ff f2 fc d7 bl #15728632
FUNCTION 00 FUNCTION 00
// CHECK2: tfunc00: // CHECK2: <tfunc00>:
// CHECK2-NEXT: 200000: 70 47 bx lr // CHECK2-NEXT: 200000: 70 47 bx lr
FUNCTION 01 FUNCTION 01
// CHECK3: tfunc01: // CHECK3: <tfunc01>:
// CHECK3-NEXT: 300000: 70 47 bx lr // CHECK3-NEXT: 300000: 70 47 bx lr
FUNCTION 02 FUNCTION 02
// tfunc28 is > 16Mb away, expect a Range Thunk to be generated, to go into // tfunc28 is > 16Mb away, expect a Range Thunk to be generated, to go into
// the first of the pre-created ThunkSections. // the first of the pre-created ThunkSections.
b.w tfunc28 b.w tfunc28
// CHECK4: tfunc02: // CHECK4: <tfunc02>:
// CHECK4-NEXT: 400000: 70 47 bx lr // CHECK4-NEXT: 400000: 70 47 bx lr
// CHECK4-NEXT: 400002: 00 f0 01 90 b.w #12582914 <__Thumbv7ABSLongThunk_tfunc28> // CHECK4-NEXT: 400002: 00 f0 01 90 b.w #12582914 <__Thumbv7ABSLongThunk_tfunc28>
FUNCTION 03 FUNCTION 03
FUNCTION 04 FUNCTION 04
FUNCTION 05 FUNCTION 05
FUNCTION 06 FUNCTION 06
FUNCTION 07 FUNCTION 07
FUNCTION 08 FUNCTION 08
FUNCTION 09 FUNCTION 09
FUNCTION 10 FUNCTION 10
FUNCTION 11 FUNCTION 11
FUNCTION 12 FUNCTION 12
FUNCTION 13 FUNCTION 13
FUNCTION 14 FUNCTION 14
// Expect precreated ThunkSection here // Expect precreated ThunkSection here
// CHECK5: __Thumbv7ABSLongThunk_tfunc16: // CHECK5: <__Thumbv7ABSLongThunk_tfunc16>:
// CHECK5-NEXT: 1000004: ff f1 fc bf b.w #2097144 <tfunc16> // CHECK5-NEXT: 1000004: ff f1 fc bf b.w #2097144 <tfunc16>
// CHECK5: __Thumbv7ABSLongThunk_tfunc28: // CHECK5: <__Thumbv7ABSLongThunk_tfunc28>:
// CHECK5-NEXT: 1000008: ff f1 fa 97 b.w #14680052 <tfunc28> // CHECK5-NEXT: 1000008: ff f1 fa 97 b.w #14680052 <tfunc28>
// CHECK5: __Thumbv7ABSLongThunk_tfunc32: // CHECK5: <__Thumbv7ABSLongThunk_tfunc32>:
// CHECK5-NEXT: 100000c: 40 f2 01 0c movw r12, #1 // CHECK5-NEXT: 100000c: 40 f2 01 0c movw r12, #1
// CHECK5-NEXT: 1000010: c0 f2 20 2c movt r12, #544 // CHECK5-NEXT: 1000010: c0 f2 20 2c movt r12, #544
// CHECK5-NEXT: 1000014: 60 47 bx r12 // CHECK5-NEXT: 1000014: 60 47 bx r12
// CHECK5: __Thumbv7ABSLongThunk_tfunc33: // CHECK5: <__Thumbv7ABSLongThunk_tfunc33>:
// CHECK5-NEXT: 1000016: 40 f2 01 0c movw r12, #1 // CHECK5-NEXT: 1000016: 40 f2 01 0c movw r12, #1
// CHECK5-NEXT: 100001a: c0 f2 30 2c movt r12, #560 // CHECK5-NEXT: 100001a: c0 f2 30 2c movt r12, #560
// CHECK5-NEXT: 100001e: 60 47 bx r12 // CHECK5-NEXT: 100001e: 60 47 bx r12
// CHECK5: __Thumbv7ABSLongThunk_tfunc02: // CHECK5: <__Thumbv7ABSLongThunk_tfunc02>:
// CHECK5-NEXT: 1000020: ff f7 ee 97 b.w #-12582948 <tfunc02> // CHECK5-NEXT: 1000020: ff f7 ee 97 b.w #-12582948 <tfunc02>
FUNCTION 15 FUNCTION 15
// tfunc00 and tfunc01 are < 16Mb away, expect no range extension thunks // tfunc00 and tfunc01 are < 16Mb away, expect no range extension thunks
bl tfunc00 bl tfunc00
bl tfunc01 bl tfunc01
// tfunc32 and tfunc33 are > 16Mb away, expect range extension thunks in the // tfunc32 and tfunc33 are > 16Mb away, expect range extension thunks in the
// precreated thunk section // precreated thunk section
bl tfunc32 bl tfunc32
bl tfunc33 bl tfunc33
// CHECK6: tfunc15: // CHECK6: <tfunc15>:
// CHECK6-NEXT: 1100000: 70 47 bx lr // CHECK6-NEXT: 1100000: 70 47 bx lr
// CHECK6-NEXT: 1100002: ff f4 fd d7 bl #-15728646 // CHECK6-NEXT: 1100002: ff f4 fd d7 bl #-15728646
// CHECK6-NEXT: 1100006: ff f5 fb d7 bl #-14680074 // CHECK6-NEXT: 1100006: ff f5 fb d7 bl #-14680074
// CHECK6-NEXT: 110000a: ff f6 ff ff bl #-1048578 // CHECK6-NEXT: 110000a: ff f6 ff ff bl #-1048578
// CHECK6-NEXT: 110000e: 00 f7 02 f8 bl #-1048572 // CHECK6-NEXT: 110000e: 00 f7 02 f8 bl #-1048572
FUNCTION 16 FUNCTION 16
FUNCTION 17 FUNCTION 17
FUNCTION 18 FUNCTION 18
// Expect another precreated thunk section here // Expect another precreated thunk section here
// CHECK7: __Thumbv7ABSLongThunk_tfunc15: // CHECK7: <__Thumbv7ABSLongThunk_tfunc15>:
// CHECK7-NEXT: 1400004: ff f4 fc bf b.w #-3145736 <tfunc15> // CHECK7-NEXT: 1400004: ff f4 fc bf b.w #-3145736 <tfunc15>
// CHECK7: __Thumbv7ABSLongThunk_tfunc16: // CHECK7: <__Thumbv7ABSLongThunk_tfunc16>:
// CHECK7-NEXT: 1400008: ff f5 fa bf b.w #-2097164 <tfunc16> // CHECK7-NEXT: 1400008: ff f5 fa bf b.w #-2097164 <tfunc16>
FUNCTION 19 FUNCTION 19
FUNCTION 20 FUNCTION 20
FUNCTION 21 FUNCTION 21
FUNCTION 22 FUNCTION 22
FUNCTION 23 FUNCTION 23
FUNCTION 24 FUNCTION 24
FUNCTION 25 FUNCTION 25
FUNCTION 26 FUNCTION 26
FUNCTION 27 FUNCTION 27
FUNCTION 28 FUNCTION 28
// tfunc02 is > 16Mb away, expect range extension thunks in precreated thunk // tfunc02 is > 16Mb away, expect range extension thunks in precreated thunk
// section // section
// CHECK8: tfunc28: // CHECK8: <tfunc28>:
// CHECK8-NEXT: 1e00000: 70 47 bx lr // CHECK8-NEXT: 1e00000: 70 47 bx lr
// CHECK8-NEXT: 1e00002: 00 f6 0d 90 b.w #-14680038 <__Thumbv7ABSLongThunk_tfunc02> // CHECK8-NEXT: 1e00002: 00 f6 0d 90 b.w #-14680038 <__Thumbv7ABSLongThunk_tfunc02>
b.w tfunc02 b.w tfunc02
FUNCTION 29 FUNCTION 29
FUNCTION 30 FUNCTION 30
FUNCTION 31 FUNCTION 31
FUNCTION 32 FUNCTION 32
// tfunc15 and tfunc16 are > 16 Mb away expect Thunks in the nearest // tfunc15 and tfunc16 are > 16 Mb away expect Thunks in the nearest
// precreated thunk section. // precreated thunk section.
bl tfunc15 bl tfunc15
bl tfunc16 bl tfunc16
// CHECK9: tfunc32: // CHECK9: <tfunc32>:
// CHECK9: 2200000: 70 47 bx lr // CHECK9: 2200000: 70 47 bx lr
// CHECK9-NEXT: 2200002: ff f5 ff d7 bl #-14680066 // CHECK9-NEXT: 2200002: ff f5 ff d7 bl #-14680066
// CHECK9-NEXT: 2200006: ff f5 ff d7 bl #-14680066 // CHECK9-NEXT: 2200006: ff f5 ff d7 bl #-14680066
FUNCTION 33 FUNCTION 33
bl tfunc15 bl tfunc15
bl tfunc16 bl tfunc16
// CHECK10: tfunc33: // CHECK10: <tfunc33>:
// CHECK10: 2300000: 70 47 bx lr // CHECK10: 2300000: 70 47 bx lr
// CHECK10-NEXT: 2300002: ff f4 ff d7 bl #-15728642 // CHECK10-NEXT: 2300002: ff f4 ff d7 bl #-15728642
// CHECK10-NEXT: 2300006: ff f4 ff d7 bl #-15728642 // CHECK10-NEXT: 2300006: ff f4 ff d7 bl #-15728642

lld/test/ELF/arm-thumb-thunk-empty-pass.s

Show All 11 Lines
.space 0xfffffe .space 0xfffffe
.section .text.foo,"ax",%progbits .section .text.foo,"ax",%progbits
.type foo, %function .type foo, %function
foo: foo:
bl _start bl _start
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 110b4: ff f7 fe ff bl #-4 // CHECK-NEXT: 110b4: ff f7 fe ff bl #-4
// CHECK: __Thumbv7ABSLongThunk__start: // CHECK: <__Thumbv7ABSLongThunk__start>:
// CHECK-NEXT: 110b8: ff f7 fc bf b.w #-8 <_start> // CHECK-NEXT: 110b8: ff f7 fc bf b.w #-8 <_start>
// CHECK: __Thumbv7ABSLongThunk__start: // CHECK: <__Thumbv7ABSLongThunk__start>:
// CHECK: 10110bc: 41 f2 b5 0c movw r12, #4277 // CHECK: 10110bc: 41 f2 b5 0c movw r12, #4277
// CHECK-NEXT: 10110c0: c0 f2 01 0c movt r12, #1 // CHECK-NEXT: 10110c0: c0 f2 01 0c movt r12, #1
// CHECK-NEXT: 10110c4: 60 47 bx r12 // CHECK-NEXT: 10110c4: 60 47 bx r12
// CHECK: foo: // CHECK: <foo>:
// CHECK-NEXT: 10110c6: ff f7 f9 ff bl #-14 // CHECK-NEXT: 10110c6: ff f7 f9 ff bl #-14

lld/test/ELF/arm-thumb-thunk-v6m.s

Show All 26 Lines
.section .text_high, "ax", %progbits .section .text_high, "ax", %progbits
.globl far .globl far
.type far, %function .type far, %function
far: far:
bx lr bx lr
// CHECK: Disassembly of section .text_low: // CHECK: Disassembly of section .text_low:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 94: 00 f0 00 f8 bl #0 // CHECK-NEXT: 94: 00 f0 00 f8 bl #0
// CHECK: __Thumbv6MABSLongThunk_far: // CHECK: <__Thumbv6MABSLongThunk_far>:
// CHECK-NEXT: 98: 03 b4 push {r0, r1} // CHECK-NEXT: 98: 03 b4 push {r0, r1}
// CHECK-NEXT: 9a: 01 48 ldr r0, [pc, #4] // CHECK-NEXT: 9a: 01 48 ldr r0, [pc, #4]
// CHECK-NEXT: 9c: 01 90 str r0, [sp, #4] // CHECK-NEXT: 9c: 01 90 str r0, [sp, #4]
// CHECK-NEXT: 9e: 01 bd pop {r0, pc} // CHECK-NEXT: 9e: 01 bd pop {r0, pc}
// CHECK: a0: 01 00 00 02 .word 0x02000001 // CHECK: a0: 01 00 00 02 .word 0x02000001
// CHECK: Disassembly of section .text_high: // CHECK: Disassembly of section .text_high:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: far: // CHECK-NEXT: <far>:
// CHECK-NEXT: 2000000: 70 47 bx lr // CHECK-NEXT: 2000000: 70 47 bx lr
// CHECK-PI: Disassembly of section .text_low: // CHECK-PI: Disassembly of section .text_low:
// CHECK-PI-EMPTY: // CHECK-PI-EMPTY:
// CHECK-PI-NEXT: _start: // CHECK-PI-NEXT: <_start>:
// CHECK-PI-NEXT: 130: 00 f0 00 f8 bl #0 // CHECK-PI-NEXT: 130: 00 f0 00 f8 bl #0
// CHECK-PI: __Thumbv6MPILongThunk_far: // CHECK-PI: <__Thumbv6MPILongThunk_far>:
// CHECK-PI-NEXT: 134: 01 b4 push {r0} // CHECK-PI-NEXT: 134: 01 b4 push {r0}
// CHECK-PI-NEXT: 136: 02 48 ldr r0, [pc, #8] // CHECK-PI-NEXT: 136: 02 48 ldr r0, [pc, #8]
// CHECK-PI-NEXT: 138: 84 46 mov r12, r0 // CHECK-PI-NEXT: 138: 84 46 mov r12, r0
// CHECK-PI-NEXT: 13a: 01 bc pop {r0} // CHECK-PI-NEXT: 13a: 01 bc pop {r0}
// pc = pc (0x13c + 4) + r12 (1fffec1) = 0x2000001 = .far // pc = pc (0x13c + 4) + r12 (1fffec1) = 0x2000001 = .far
// CHECK-PI-NEXT: 13c: e7 44 add pc, r12 // CHECK-PI-NEXT: 13c: e7 44 add pc, r12
// CHECK-PI-NEXT: 13e: c0 46 mov r8, r8 // CHECK-PI-NEXT: 13e: c0 46 mov r8, r8
// CHECK-PI: 140: c1 fe ff 01 .word 0x01fffec1 // CHECK-PI: 140: c1 fe ff 01 .word 0x01fffec1
// CHECK-PI: Disassembly of section .text_high: // CHECK-PI: Disassembly of section .text_high:
// CHECK-PI-EMPTY: // CHECK-PI-EMPTY:
// CHECK-PI-NEXT: far: // CHECK-PI-NEXT: <far>:
// CHECK-PI-NEXT: 2000000: 70 47 bx lr // CHECK-PI-NEXT: 2000000: 70 47 bx lr

lld/test/ELF/arm-thumb-undefined-weak-narrow.test

# REQUIRES: arm # REQUIRES: arm
# RUN: yaml2obj %s -o %t.o # RUN: yaml2obj %s -o %t.o
# RUN: ld.lld %t.o -o %t # RUN: ld.lld %t.o -o %t
# RUN: llvm-objdump -triple=thumbv7a-linux-gnueabi -d %t | FileCheck %s # RUN: llvm-objdump -triple=thumbv7a-linux-gnueabi -d %t | FileCheck %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT:_start: # CHECK-NEXT: <_start>:
# CHECK-NEXT: ff e7 b #-2 # CHECK-NEXT: ff e7 b #-2
# Test the R_ARM_THM_JUMP11 relocation (102) to an undefined weak reference # Test the R_ARM_THM_JUMP11 relocation (102) to an undefined weak reference
# It should resolve to the next instruction, which is an offset of -2 which # It should resolve to the next instruction, which is an offset of -2 which
# when added to the Thumb PC-bias of 4 is +2. We can't use llvm-mc to construct # when added to the Thumb PC-bias of 4 is +2. We can't use llvm-mc to construct
# the object as it relaxes b.n to b.w (R_ARM_JUMP24). # the object as it relaxes b.n to b.w (R_ARM_JUMP24).
!ELF !ELF
Show All 33 Lines

lld/test/ELF/arm-thumb2-adr.s

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
// SYMS-NEXT: Value: 0x8012 // SYMS-NEXT: Value: 0x8012
// SYMS: Name: dat2 // SYMS: Name: dat2
// SYMS-NEXT: Value: 0x8013 // SYMS-NEXT: Value: 0x8013
// SYMS: Name: dat3 // SYMS: Name: dat3
// SYMS-NEXT: Value: 0x8014 // SYMS-NEXT: Value: 0x8014
// SYMS: Name: dat4 // SYMS: Name: dat4
// SYMS-NEXT: Value: 0x8015 // SYMS-NEXT: Value: 0x8015
// CHECK: 00008f00 target1: // CHECK: 00008f00 <target1>:
// CHECK-NEXT: 8f00: bx lr // CHECK-NEXT: 8f00: bx lr
// CHECK: 00008f02 target2: // CHECK: 00008f02 <target2>:
// CHECK-NEXT: 8f02: bx lr // CHECK-NEXT: 8f02: bx lr
// CHECK: 00009000 _start: // CHECK: 00009000 <_start>:
// CHECK-NEXT: 9000: nop // CHECK-NEXT: 9000: nop
/// AlignDown(0x9002+4, 4) - 0xff2 = 0x8012 /// AlignDown(0x9002+4, 4) - 0xff2 = 0x8012
// CHECK-NEXT: 9002: adr.w r0, #-4082 // CHECK-NEXT: 9002: adr.w r0, #-4082
/// AlignDown(0x9006+4, 4) - 0xff5 = 0x8013 /// AlignDown(0x9006+4, 4) - 0xff5 = 0x8013
// CHECK-NEXT: 9006: adr.w r1, #-4085 // CHECK-NEXT: 9006: adr.w r1, #-4085
// CHECK-NEXT: 900a: nop // CHECK-NEXT: 900a: nop
/// AlignDown(0x900c+4, 4) - 0xffc = 0x8014 /// AlignDown(0x900c+4, 4) - 0xffc = 0x8014
// CHECK-NEXT: 900c: adr.w r2, #-4092 // CHECK-NEXT: 900c: adr.w r2, #-4092
/// AlignDown(0x9010+4, 4) - 0xfff = 0x8015 /// AlignDown(0x9010+4, 4) - 0xfff = 0x8015
// CHECK-NEXT: 9010: adr.w r3, #-4095 // CHECK-NEXT: 9010: adr.w r3, #-4095
/// AlignDown(0x9014+4, 4) - 0x117 = 0x8f01 /// AlignDown(0x9014+4, 4) - 0x117 = 0x8f01
// CHECK-NEXT: 9014: adr.w r0, #-279 // CHECK-NEXT: 9014: adr.w r0, #-279
// CHECK-NEXT: 9018: nop // CHECK-NEXT: 9018: nop
/// AlignDown(0x901a+4, 4) - 0x119 = 0x8f03 /// AlignDown(0x901a+4, 4) - 0x119 = 0x8f03
// CHECK-NEXT: 901a: adr.w r1, #-281 // CHECK-NEXT: 901a: adr.w r1, #-281
// CHECK: 00010000 pos: // CHECK: 00010000 <pos>:
/// AlignDown(0x10000+4, 4) + 0xfd = 0x10101 /// AlignDown(0x10000+4, 4) + 0xfd = 0x10101
// CHECK-NEXT: 10000: adr.w r2, #253 // CHECK-NEXT: 10000: adr.w r2, #253
// CHECK-NEXT: 10004: nop // CHECK-NEXT: 10004: nop
/// AlignDown(0x10006+4, 4) + 0xfb = 0x10103 /// AlignDown(0x10006+4, 4) + 0xfb = 0x10103
// CHECK-NEXT: 10006: adr.w r3, #251 // CHECK-NEXT: 10006: adr.w r3, #251
// CHECK-NEXT: 1000a: nop // CHECK-NEXT: 1000a: nop
/// AlignDown(0x1000c+4, 4) + 0xfff = 0x1100f /// AlignDown(0x1000c+4, 4) + 0xfff = 0x1100f
// CHECK-NEXT: 1000c: adr.w r0, #4095 // CHECK-NEXT: 1000c: adr.w r0, #4095
/// AlignDown(0x10010+4, 4) + 0xffc = 0x11010 /// AlignDown(0x10010+4, 4) + 0xffc = 0x11010
// CHECK-NEXT: 10010: adr.w r1, #4092 // CHECK-NEXT: 10010: adr.w r1, #4092
// CHECK-NEXT: 10014: nop // CHECK-NEXT: 10014: nop
/// AlignDown(0x10016+4, 4) + 0xff9 = 0x11011 /// AlignDown(0x10016+4, 4) + 0xff9 = 0x11011
// CHECK-NEXT: 10016: adr.w r2, #4089 // CHECK-NEXT: 10016: adr.w r2, #4089
/// AlignDown(0x1001a+4, 4) + 0xff6 = 0x11012 /// AlignDown(0x1001a+4, 4) + 0xff6 = 0x11012
// CHECK-NEXT: 1001a: adr.w r3, #4086 // CHECK-NEXT: 1001a: adr.w r3, #4086
/// AlignDown(0x1001e+4, 4) + 0xff7 = 0x11017 = dat5 + 8 /// AlignDown(0x1001e+4, 4) + 0xff7 = 0x11017 = dat5 + 8
// CHECK-NEXT: 1001e: adr.w r4, #4087 // CHECK-NEXT: 1001e: adr.w r4, #4087
// CHECK: 00010100 target3: // CHECK: 00010100 <target3>:
// CHECK-NEXT: 10100: bx lr // CHECK-NEXT: 10100: bx lr
// CHECK: 00010102 target4: // CHECK: 00010102 <target4>:
// CHECK-NEXT: 10102: bx lr // CHECK-NEXT: 10102: bx lr
// SYMS: Name: dat5 // SYMS: Name: dat5
// SYMS-NEXT: Value: 0x1100F // SYMS-NEXT: Value: 0x1100F
// SYMS: Name: dat6 // SYMS: Name: dat6
// SYMS-NEXT: Value: 0x11010 // SYMS-NEXT: Value: 0x11010
// SYMS: Name: dat7 // SYMS: Name: dat7
// SYMS-NEXT: Value: 0x11011 // SYMS-NEXT: Value: 0x11011
// SYMS: Name: dat8 // SYMS: Name: dat8
// SYMS-NEXT: Value: 0x11012 // SYMS-NEXT: Value: 0x11012

lld/test/ELF/arm-thumb2-ldrlit.s

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
// SYMS-NEXT: Value: 0x8012 // SYMS-NEXT: Value: 0x8012
// SYMS: Name: dat2 // SYMS: Name: dat2
// SYMS-NEXT: Value: 0x8013 // SYMS-NEXT: Value: 0x8013
// SYMS: Name: dat3 // SYMS: Name: dat3
// SYMS-NEXT: Value: 0x8014 // SYMS-NEXT: Value: 0x8014
// SYMS: Name: dat4 // SYMS: Name: dat4
// SYMS-NEXT: Value: 0x8015 // SYMS-NEXT: Value: 0x8015
// CHECK: 00008f00 target1: // CHECK: 00008f00 <target1>:
// CHECK-NEXT: 8f00: bx lr // CHECK-NEXT: 8f00: bx lr
// CHECK: 00008f02 target2: // CHECK: 00008f02 <target2>:
// CHECK-NEXT: 8f02: bx lr // CHECK-NEXT: 8f02: bx lr
// CHECK: 00009000 _start: // CHECK: 00009000 <_start>:
// CHECK-NEXT: 9000: nop // CHECK-NEXT: 9000: nop
/// AlignDown(0x9002+4, 4) - 0xff2 = 0x8012 /// AlignDown(0x9002+4, 4) - 0xff2 = 0x8012
// CHECK-NEXT: 9002: ldr.w r0, [pc, #-4082] // CHECK-NEXT: 9002: ldr.w r0, [pc, #-4082]
/// AlignDown(0x9006+4, 4) - 0xff5 = 0x8013 /// AlignDown(0x9006+4, 4) - 0xff5 = 0x8013
// CHECK-NEXT: 9006: ldr.w r1, [pc, #-4085] // CHECK-NEXT: 9006: ldr.w r1, [pc, #-4085]
// CHECK-NEXT: 900a: nop // CHECK-NEXT: 900a: nop
/// AlignDown(0x900c+4, 4) - 0xffc = 0x8014 /// AlignDown(0x900c+4, 4) - 0xffc = 0x8014
// CHECK-NEXT: 900c: ldr.w r2, [pc, #-4092] // CHECK-NEXT: 900c: ldr.w r2, [pc, #-4092]
/// AlignDown(0x9010+4, 4) - 0xfff = 0x8015 /// AlignDown(0x9010+4, 4) - 0xfff = 0x8015
// CHECK-NEXT: 9010: ldr.w r3, [pc, #-4095] // CHECK-NEXT: 9010: ldr.w r3, [pc, #-4095]
/// AlignDown(0x9014+4, 4) - 0x118 = 0x8f00 /// AlignDown(0x9014+4, 4) - 0x118 = 0x8f00
// CHECK-NEXT: 9014: ldr.w r0, [pc, #-280] // CHECK-NEXT: 9014: ldr.w r0, [pc, #-280]
// CHECK-NEXT: 9018: nop // CHECK-NEXT: 9018: nop
/// AlignDown(0x901a+4, 4) - 0x11a = 0x8f02 /// AlignDown(0x901a+4, 4) - 0x11a = 0x8f02
// CHECK-NEXT: 901a: ldr.w r1, [pc, #-282] // CHECK-NEXT: 901a: ldr.w r1, [pc, #-282]
// CHECK: 00010000 pos: // CHECK: 00010000 <pos>:
/// AlignDown(0x10000+4, 4) + 0x1c = 0x10100 /// AlignDown(0x10000+4, 4) + 0x1c = 0x10100
// CHECK-NEXT: 10000: ldr.w r2, [pc, #252] // CHECK-NEXT: 10000: ldr.w r2, [pc, #252]
// CHECK-NEXT: 10004: nop // CHECK-NEXT: 10004: nop
/// AlignDown(0x10006+4, 4) + 0x1a = 0x10122 /// AlignDown(0x10006+4, 4) + 0x1a = 0x10122
// CHECK-NEXT: 10006: ldr.w r3, [pc, #250] // CHECK-NEXT: 10006: ldr.w r3, [pc, #250]
// CHECK-NEXT: 1000a: nop // CHECK-NEXT: 1000a: nop
/// AlignDown(0x1000c+4, 4) + 0xfff = 0x1100f /// AlignDown(0x1000c+4, 4) + 0xfff = 0x1100f
// CHECK-NEXT: 1000c: ldr.w r0, [pc, #4095] // CHECK-NEXT: 1000c: ldr.w r0, [pc, #4095]
/// AlignDown(0x10010+4, 4) + 0xffc = 0x11010 /// AlignDown(0x10010+4, 4) + 0xffc = 0x11010
// CHECK-NEXT: 10010: ldr.w r1, [pc, #4092] // CHECK-NEXT: 10010: ldr.w r1, [pc, #4092]
// CHECK-NEXT: 10014: nop // CHECK-NEXT: 10014: nop
/// AlignDown(0x10016+4, 4) + 0xff9 = 0x11011 /// AlignDown(0x10016+4, 4) + 0xff9 = 0x11011
// CHECK-NEXT: 10016: ldr.w r2, [pc, #4089] // CHECK-NEXT: 10016: ldr.w r2, [pc, #4089]
/// AlignDown(0x1001a+4, 4) + 0xff6 = 0x11012 /// AlignDown(0x1001a+4, 4) + 0xff6 = 0x11012
// CHECK-NEXT: 1001a: ldr.w r3, [pc, #4086] // CHECK-NEXT: 1001a: ldr.w r3, [pc, #4086]
/// AlignDown(0x1001e+4, 4) + 0xff7 = 0x11017 = dat5 + 8 /// AlignDown(0x1001e+4, 4) + 0xff7 = 0x11017 = dat5 + 8
// CHECK-NEXT: 1001e: ldr.w r4, [pc, #4087] // CHECK-NEXT: 1001e: ldr.w r4, [pc, #4087]
// CHECK: 00010100 target3: // CHECK: 00010100 <target3>:
// CHECK-NEXT: 10100: bx lr // CHECK-NEXT: 10100: bx lr
// CHECK: 00010102 target4: // CHECK: 00010102 <target4>:
// CHECK-NEXT: 10102: bx lr // CHECK-NEXT: 10102: bx lr
// SYMS: Name: dat5 // SYMS: Name: dat5
// SYMS-NEXT: Value: 0x1100F // SYMS-NEXT: Value: 0x1100F
// SYMS: Name: dat6 // SYMS: Name: dat6
// SYMS-NEXT: Value: 0x11010 // SYMS-NEXT: Value: 0x11010
// SYMS: Name: dat7 // SYMS: Name: dat7
// SYMS-NEXT: Value: 0x11011 // SYMS-NEXT: Value: 0x11011
// SYMS: Name: dat8 // SYMS: Name: dat8
// SYMS-NEXT: Value: 0x11012 // SYMS-NEXT: Value: 0x11012

lld/test/ELF/arm-thunk-edgecase.s

Show All 23 Lines
.thumb .thumb
.section .text_thumbfunc, "ax", %progbits .section .text_thumbfunc, "ax", %progbits
.globl thumbfunc .globl thumbfunc
.thumb_func .thumb_func
thumbfunc: thumbfunc:
b.w armfunc b.w armfunc
// ARM-TO-THUMB: __ARMV7PILongThunk_thumbfunc: // ARM-TO-THUMB: <__ARMV7PILongThunk_thumbfunc>:
// ARM-TO-THUMB-NEXT: 1004: fd cf 0f e3 movw r12, #65533 // ARM-TO-THUMB-NEXT: 1004: fd cf 0f e3 movw r12, #65533
// ARM-TO-THUMB-NEXT: 1008: 00 c0 40 e3 movt r12, #0 // ARM-TO-THUMB-NEXT: 1008: 00 c0 40 e3 movt r12, #0
// THUMB-TO-ARM: __ThumbV7PILongThunk_armfunc: // THUMB-TO-ARM: <__ThumbV7PILongThunk_armfunc>:
// THUMB-TO-ARM-NEXT: 1004: 4f f6 fc 7c movw r12, #65532 // THUMB-TO-ARM-NEXT: 1004: 4f f6 fc 7c movw r12, #65532
// THUMB-TO-ARM-NEXT: 1008: c0 f2 00 0c movt r12, #0 // THUMB-TO-ARM-NEXT: 1008: c0 f2 00 0c movt r12, #0

lld/test/ELF/arm-thunk-largesection.s

Show All 11 Lines
.text .text
.globl _start .globl _start
.type _start, %function .type _start, %function
_start: _start:
bx lr bx lr
.space 0x1000 .space 0x1000
// CHECK1: Disassembly of section .text: // CHECK1: Disassembly of section .text:
// CHECK1-EMPTY: // CHECK1-EMPTY:
// CHECK1-NEXT:_start: // CHECK1-NEXT: <_start>:
// CHECK1-NEXT: 12000: 70 47 bx lr // CHECK1-NEXT: 12000: 70 47 bx lr
// CHECK1-EMPTY: // CHECK1-EMPTY:
// CHECK1-NEXT:$d.1: // CHECK1-NEXT: <$d.1>:
// CHECK1-NEXT: 12002: 00 00 00 00 .word 0x00000000 // CHECK1-NEXT: 12002: 00 00 00 00 .word 0x00000000
// CHECK2: __Thumbv7ABSLongThunk__start: // CHECK2: <__Thumbv7ABSLongThunk__start>:
// CHECK2-NEXT: 13004: fe f7 fc bf b.w #-4104 <_start> // CHECK2-NEXT: 13004: fe f7 fc bf b.w #-4104 <_start>
// Gigantic section where we need a ThunkSection either side of it // Gigantic section where we need a ThunkSection either side of it
.section .text.large1, "ax", %progbits .section .text.large1, "ax", %progbits
.balign 4 .balign 4
.space (16 * 1024 * 1024) - 16 .space (16 * 1024 * 1024) - 16
bl _start bl _start
.space (16 * 1024 * 1024) - 4 .space (16 * 1024 * 1024) - 4
bl _start bl _start
.space (16 * 1024 * 1024) - 16 .space (16 * 1024 * 1024) - 16
// CHECK3: 1012ff8: 00 f4 04 d0 bl #-16777208 // CHECK3: 1012ff8: 00 f4 04 d0 bl #-16777208
// CHECK4: 2012ff8: ff f3 f8 d7 bl #16777200 // CHECK4: 2012ff8: ff f3 f8 d7 bl #16777200
// CHECK5: __Thumbv7ABSLongThunk__start: // CHECK5: <__Thumbv7ABSLongThunk__start>:
// CHECK5-NEXT: 3012fec: 42 f2 01 0c movw r12, #8193 // CHECK5-NEXT: 3012fec: 42 f2 01 0c movw r12, #8193
// CHECK5-NEXT: 3012ff0: c0 f2 01 0c movt r12, #1 // CHECK5-NEXT: 3012ff0: c0 f2 01 0c movt r12, #1
// CHECK5-NEXT: 3012ff4: 60 47 bx r12 // CHECK5-NEXT: 3012ff4: 60 47 bx r12

lld/test/ELF/arm-thunk-linkerscript-dotexpr.s

Show All 23 Lines
.thumb .thumb
.globl low_target2 .globl low_target2
.type low_target2, %function .type low_target2, %function
low_target2: low_target2:
bl high_target bl high_target
bl high_target2 bl high_target2
// CHECK1: Disassembly of section .text_low: // CHECK1: Disassembly of section .text_low:
// CHECK1-EMPTY: // CHECK1-EMPTY:
// CHECK1-NEXT: _start: // CHECK1-NEXT: <_start>:
// CHECK1-NEXT: 94: 70 47 bx lr // CHECK1-NEXT: 94: 70 47 bx lr
// CHECK1: low_target: // CHECK1: <low_target>:
// CHECK1-NEXT: 96: 00 f0 03 f8 bl #6 // CHECK1-NEXT: 96: 00 f0 03 f8 bl #6
// CHECK1-NEXT: 9a: 00 f0 06 f8 bl #12 // CHECK1-NEXT: 9a: 00 f0 06 f8 bl #12
// CHECK1: __Thumbv7ABSLongThunk_high_target: // CHECK1: <__Thumbv7ABSLongThunk_high_target>:
// CHECK1-NEXT: a0: 40 f2 bd 0c movw r12, #189 // CHECK1-NEXT: a0: 40 f2 bd 0c movw r12, #189
// CHECK1-NEXT: a4: c0 f2 00 2c movt r12, #512 // CHECK1-NEXT: a4: c0 f2 00 2c movt r12, #512
// CHECK1-NEXT: a8: 60 47 bx r12 // CHECK1-NEXT: a8: 60 47 bx r12
// CHECK1: __Thumbv7ABSLongThunk_high_target2: // CHECK1: <__Thumbv7ABSLongThunk_high_target2>:
// CHECK1-NEXT: aa: 40 f2 d9 0c movw r12, #217 // CHECK1-NEXT: aa: 40 f2 d9 0c movw r12, #217
// CHECK1-NEXT: ae: c0 f2 00 2c movt r12, #512 // CHECK1-NEXT: ae: c0 f2 00 2c movt r12, #512
// CHECK1-NEXT: b2: 60 47 bx r12 // CHECK1-NEXT: b2: 60 47 bx r12
// CHECK1: low_target2: // CHECK1: <low_target2>:
// CHECK1-NEXT: b4: ff f7 f4 ff bl #-24 // CHECK1-NEXT: b4: ff f7 f4 ff bl #-24
// CHECK1-NEXT: b8: ff f7 f7 ff bl #-18 // CHECK1-NEXT: b8: ff f7 f7 ff bl #-18
.section .text_high, "ax", %progbits .section .text_high, "ax", %progbits
.thumb .thumb
.globl high_target .globl high_target
.type high_target, %function .type high_target, %function
high_target: high_target:
bl low_target bl low_target
bl low_target2 bl low_target2
.section .text_high2, "ax", %progbits .section .text_high2, "ax", %progbits
.thumb .thumb
.globl high_target2 .globl high_target2
.type high_target2, %function .type high_target2, %function
high_target2: high_target2:
bl low_target bl low_target
bl low_target2 bl low_target2
// CHECK2: high_target: // CHECK2: <high_target>:
// CHECK2-NEXT: 20000bc: 00 f0 02 f8 bl #4 // CHECK2-NEXT: 20000bc: 00 f0 02 f8 bl #4
// CHECK2-NEXT: 20000c0: 00 f0 05 f8 bl #10 // CHECK2-NEXT: 20000c0: 00 f0 05 f8 bl #10
// CHECK2: __Thumbv7ABSLongThunk_low_target: // CHECK2: <__Thumbv7ABSLongThunk_low_target>:
// CHECK2-NEXT: 20000c4: 40 f2 97 0c movw r12, #151 // CHECK2-NEXT: 20000c4: 40 f2 97 0c movw r12, #151
// CHECK2-NEXT: 20000c8: c0 f2 00 0c movt r12, #0 // CHECK2-NEXT: 20000c8: c0 f2 00 0c movt r12, #0
// CHECK2-NEXT: 20000cc: 60 47 bx r12 // CHECK2-NEXT: 20000cc: 60 47 bx r12
// CHECK2: __Thumbv7ABSLongThunk_low_target2: // CHECK2: <__Thumbv7ABSLongThunk_low_target2>:
// CHECK2-NEXT: 20000ce: 40 f2 b5 0c movw r12, #181 // CHECK2-NEXT: 20000ce: 40 f2 b5 0c movw r12, #181
// CHECK2-NEXT: 20000d2: c0 f2 00 0c movt r12, #0 // CHECK2-NEXT: 20000d2: c0 f2 00 0c movt r12, #0
// CHECK2-NEXT: 20000d6: 60 47 bx r12 // CHECK2-NEXT: 20000d6: 60 47 bx r12
// CHECK2: high_target2: // CHECK2: <high_target2>:
// CHECK2-NEXT: 20000d8: ff f7 f4 ff bl #-24 // CHECK2-NEXT: 20000d8: ff f7 f4 ff bl #-24
// CHECK2-NEXT: 20000dc: ff f7 f7 ff bl #-18 // CHECK2-NEXT: 20000dc: ff f7 f7 ff bl #-18

lld/test/ELF/arm-thunk-linkerscript-large.s

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
.thumb .thumb
.globl _start .globl _start
_start: _start:
bl tfuncl00 bl tfuncl00
// Expect a range extension thunk in .text OutputSection // Expect a range extension thunk in .text OutputSection
bl tfunch31 bl tfunch31
// CHECK1: Disassembly of section .text: // CHECK1: Disassembly of section .text:
// CHECK1-EMPTY: // CHECK1-EMPTY:
// CHECK1-NEXT: _start: // CHECK1-NEXT: <_start>:
// CHECK1-NEXT: 100000: ff f0 fe ff bl #1048572 // CHECK1-NEXT: 100000: ff f0 fe ff bl #1048572
// CHECK1-NEXT: 100004: 00 f0 00 f8 bl #0 // CHECK1-NEXT: 100004: 00 f0 00 f8 bl #0
// CHECK1: __Thumbv7ABSLongThunk_tfunch31: // CHECK1: <__Thumbv7ABSLongThunk_tfunch31>:
// CHECK1-NEXT: 100008: 40 f2 01 0c movw r12, #1 // CHECK1-NEXT: 100008: 40 f2 01 0c movw r12, #1
// CHECK1-NEXT: 10000c: c0 f2 10 4c movt r12, #1040 // CHECK1-NEXT: 10000c: c0 f2 10 4c movt r12, #1040
// CHECK1-NEXT: 100010: 60 47 bx r12 // CHECK1-NEXT: 100010: 60 47 bx r12
FUNCTIONL 00 FUNCTIONL 00
// Create a range extension thunk in .textl // Create a range extension thunk in .textl
bl tfuncl24 bl tfuncl24
// We can reuse existing thunk in .text // We can reuse existing thunk in .text
bl tfunch31 bl tfunch31
// CHECK2: Disassembly of section .textl: // CHECK2: Disassembly of section .textl:
// CHECK2-EMPTY: // CHECK2-EMPTY:
// CHECK2-NEXT: tfuncl00: // CHECK2-NEXT: <tfuncl00>:
// CHECK2-NEXT: 200000: 70 47 bx lr // CHECK2-NEXT: 200000: 70 47 bx lr
// CHECK2-NEXT: 200002: ff f0 ff df bl #9437182 // CHECK2-NEXT: 200002: ff f0 ff df bl #9437182
// CHECK2-NEXT: 200006: ff f6 ff ff bl #-1048578 // CHECK2-NEXT: 200006: ff f6 ff ff bl #-1048578
FUNCTIONL 01 FUNCTIONL 01
FUNCTIONL 02 FUNCTIONL 02
FUNCTIONL 03 FUNCTIONL 03
FUNCTIONL 04 FUNCTIONL 04
FUNCTIONL 05 FUNCTIONL 05
FUNCTIONL 06 FUNCTIONL 06
FUNCTIONL 07 FUNCTIONL 07
FUNCTIONL 08 FUNCTIONL 08
FUNCTIONL 09 FUNCTIONL 09
// CHECK3: __Thumbv7ABSLongThunk_tfuncl24: // CHECK3: <__Thumbv7ABSLongThunk_tfuncl24>:
// CHECK3-NEXT: b00004: ff f2 fc 97 b.w #15728632 <tfuncl24> // CHECK3-NEXT: b00004: ff f2 fc 97 b.w #15728632 <tfuncl24>
FUNCTIONL 10 FUNCTIONL 10
FUNCTIONL 11 FUNCTIONL 11
FUNCTIONL 12 FUNCTIONL 12
FUNCTIONL 13 FUNCTIONL 13
FUNCTIONL 14 FUNCTIONL 14
FUNCTIONL 15 FUNCTIONL 15
FUNCTIONL 16 FUNCTIONL 16
Show All 15 Lines
// Create range extension thunks in .textl // Create range extension thunks in .textl
bl tfuncl00 bl tfuncl00
bl tfuncl24 bl tfuncl24
// Shouldn't need a thunk // Shouldn't need a thunk
bl tfunch00 bl tfunch00
// CHECK4: 2100002: 00 f0 05 f8 bl #10 // CHECK4: 2100002: 00 f0 05 f8 bl #10
// CHECK4-NEXT: 2100006: ff f4 fb f7 bl #-7340042 // CHECK4-NEXT: 2100006: ff f4 fb f7 bl #-7340042
// CHECK4-NEXT: 210000a: ff f0 f9 ff bl #1048562 // CHECK4-NEXT: 210000a: ff f0 f9 ff bl #1048562
// CHECK4: __Thumbv7ABSLongThunk_tfuncl00: // CHECK4: <__Thumbv7ABSLongThunk_tfuncl00>:
// CHECK4-NEXT: 2100010: 40 f2 01 0c movw r12, #1 // CHECK4-NEXT: 2100010: 40 f2 01 0c movw r12, #1
// CHECK4-NEXT: 2100014: c0 f2 20 0c movt r12, #32 // CHECK4-NEXT: 2100014: c0 f2 20 0c movt r12, #32
// CHECK4-NEXT: 2100018: 60 47 bx r12 // CHECK4-NEXT: 2100018: 60 47 bx r12
FUNCTIONH 00 FUNCTIONH 00
// Can reuse existing thunks in .textl // Can reuse existing thunks in .textl
bl tfuncl00 bl tfuncl00
bl tfuncl24 bl tfuncl24
// Shouldn't need a thunk // Shouldn't need a thunk
bl tfuncl31 bl tfuncl31
// CHECK5: Disassembly of section .texth: // CHECK5: Disassembly of section .texth:
// CHECK5-EMPTY: // CHECK5-EMPTY:
// CHECK5-NEXT: tfunch00: // CHECK5-NEXT: <tfunch00>:
// CHECK5-NEXT: 2200000: 70 47 bx lr // CHECK5-NEXT: 2200000: 70 47 bx lr
// CHECK5-NEXT: 2200002: 00 f7 05 f8 bl #-1048566 // CHECK5-NEXT: 2200002: 00 f7 05 f8 bl #-1048566
// CHECK5-NEXT: 2200006: ff f7 fb df bl #-8388618 // CHECK5-NEXT: 2200006: ff f7 fb df bl #-8388618
// CHECK5-NEXT: 220000a: ff f6 f9 ff bl #-1048590 // CHECK5-NEXT: 220000a: ff f6 f9 ff bl #-1048590
FUNCTIONH 01 FUNCTIONH 01
FUNCTIONH 02 FUNCTIONH 02
FUNCTIONH 03 FUNCTIONH 03
FUNCTIONH 04 FUNCTIONH 04
Show All 22 Lines
FUNCTIONH 27 FUNCTIONH 27
FUNCTIONH 28 FUNCTIONH 28
FUNCTIONH 29 FUNCTIONH 29
FUNCTIONH 30 FUNCTIONH 30
FUNCTIONH 31 FUNCTIONH 31
// expect Thunks in .texth // expect Thunks in .texth
bl tfuncl00 bl tfuncl00
bl tfunch00 bl tfunch00
// CHECK6: tfunch31: // CHECK6: <tfunch31>:
// CHECK6-NEXT: 4100000: 70 47 bx lr // CHECK6-NEXT: 4100000: 70 47 bx lr
// CHECK6-NEXT: 4100002: 00 f0 03 f8 bl #6 // CHECK6-NEXT: 4100002: 00 f0 03 f8 bl #6
// CHECK6-NEXT: 4100006: 00 f0 06 f8 bl #12 // CHECK6-NEXT: 4100006: 00 f0 06 f8 bl #12
// CHECK6: __Thumbv7ABSLongThunk_tfuncl00: // CHECK6: <__Thumbv7ABSLongThunk_tfuncl00>:
// CHECK6-NEXT: 410000c: 40 f2 01 0c movw r12, #1 // CHECK6-NEXT: 410000c: 40 f2 01 0c movw r12, #1
// CHECK6-NEXT: 4100010: c0 f2 20 0c movt r12, #32 // CHECK6-NEXT: 4100010: c0 f2 20 0c movt r12, #32
// CHECK6-NEXT: 4100014: 60 47 bx r12 // CHECK6-NEXT: 4100014: 60 47 bx r12
// CHECK6: __Thumbv7ABSLongThunk_tfunch00: // CHECK6: <__Thumbv7ABSLongThunk_tfunch00>:
// CHECK6-NEXT: 4100016: 40 f2 01 0c movw r12, #1 // CHECK6-NEXT: 4100016: 40 f2 01 0c movw r12, #1
// CHECK6-NEXT: 410001a: c0 f2 20 2c movt r12, #544 // CHECK6-NEXT: 410001a: c0 f2 20 2c movt r12, #544
// CHECK6-NEXT: 410001e: 60 47 bx r12 // CHECK6-NEXT: 410001e: 60 47 bx r12

lld/test/ELF/arm-thunk-linkerscript-orphan.s

Show All 13 Lines
_start: bx lr _start: bx lr
.globl low_target .globl low_target
.type low_target, %function .type low_target, %function
low_target: low_target:
bl high_target bl high_target
bl orphan_target bl orphan_target
// CHECK: Disassembly of section .text_low: // CHECK: Disassembly of section .text_low:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 100000: 70 47 bx lr // CHECK-NEXT: 100000: 70 47 bx lr
// CHECK: low_target: // CHECK: <low_target>:
// CHECK-NEXT: 100002: 00 f0 03 f8 bl #6 // CHECK-NEXT: 100002: 00 f0 03 f8 bl #6
// CHECK-NEXT: 100006: 00 f0 06 f8 bl #12 // CHECK-NEXT: 100006: 00 f0 06 f8 bl #12
// CHECK: __Thumbv7ABSLongThunk_high_target: // CHECK: <__Thumbv7ABSLongThunk_high_target>:
// CHECK-NEXT: 10000c: 40 f2 01 0c movw r12, #1 // CHECK-NEXT: 10000c: 40 f2 01 0c movw r12, #1
// CHECK-NEXT: 100010: c0 f2 00 2c movt r12, #512 // CHECK-NEXT: 100010: c0 f2 00 2c movt r12, #512
// CHECK-NEXT: 100014: 60 47 bx r12 // CHECK-NEXT: 100014: 60 47 bx r12
// CHECK: __Thumbv7ABSLongThunk_orphan_target: // CHECK: <__Thumbv7ABSLongThunk_orphan_target>:
// CHECK-NEXT: 100016: 40 f2 15 0c movw r12, #21 // CHECK-NEXT: 100016: 40 f2 15 0c movw r12, #21
// CHECK-NEXT: 10001a: c0 f2 00 2c movt r12, #512 // CHECK-NEXT: 10001a: c0 f2 00 2c movt r12, #512
// CHECK-NEXT: 10001e: 60 47 bx r12 // CHECK-NEXT: 10001e: 60 47 bx r12
.section .text_high, "ax", %progbits .section .text_high, "ax", %progbits
.thumb .thumb
.globl high_target .globl high_target
.type high_target, %function .type high_target, %function
high_target: high_target:
bl low_target bl low_target
bl orphan_target bl orphan_target
// CHECK: Disassembly of section .text_high: // CHECK: Disassembly of section .text_high:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: high_target: // CHECK-NEXT: <high_target>:
// CHECK-NEXT: 2000000: 00 f0 02 f8 bl #4 // CHECK-NEXT: 2000000: 00 f0 02 f8 bl #4
// CHECK-NEXT: 2000004: 00 f0 06 f8 bl #12 // CHECK-NEXT: 2000004: 00 f0 06 f8 bl #12
// CHECK: __Thumbv7ABSLongThunk_low_target: // CHECK: <__Thumbv7ABSLongThunk_low_target>:
// CHECK-NEXT: 2000008: 40 f2 03 0c movw r12, #3 // CHECK-NEXT: 2000008: 40 f2 03 0c movw r12, #3
// CHECK-NEXT: 200000c: c0 f2 10 0c movt r12, #16 // CHECK-NEXT: 200000c: c0 f2 10 0c movt r12, #16
// CHECK-NEXT: 2000010: 60 47 bx r12 // CHECK-NEXT: 2000010: 60 47 bx r12
.section orphan, "ax", %progbits .section orphan, "ax", %progbits
.thumb .thumb
.globl orphan_target .globl orphan_target
.type orphan_target, %function .type orphan_target, %function
orphan_target: orphan_target:
bl low_target bl low_target
bl high_target bl high_target
// CHECK: Disassembly of section orphan: // CHECK: Disassembly of section orphan:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: orphan_target: // CHECK-NEXT: <orphan_target>:
// CHECK-NEXT: 2000014: ff f7 f8 ff bl #-16 // CHECK-NEXT: 2000014: ff f7 f8 ff bl #-16
// CHECK-NEXT: 2000018: ff f7 f2 ff bl #-28 // CHECK-NEXT: 2000018: ff f7 f2 ff bl #-28
.data .data
.word 10 .word 10

lld/test/ELF/arm-thunk-linkerscript-sort.s

Show All 34 Lines
FUNCTION 22 FUNCTION 22
FUNCTION 21 FUNCTION 21
FUNCTION 20 FUNCTION 20
FUNCTION 19 FUNCTION 19
FUNCTION 18 FUNCTION 18
FUNCTION 17 FUNCTION 17
FUNCTION 16 FUNCTION 16
FUNCTION 15 FUNCTION 15
// CHECK2: __Thumbv7ABSLongThunk_tfunc31: // CHECK2: <__Thumbv7ABSLongThunk_tfunc31>:
// CHECK2-NEXT: 1000004: ff f3 fc 97 b.w #16777208 <tfunc31> // CHECK2-NEXT: 1000004: ff f3 fc 97 b.w #16777208 <tfunc31>
FUNCTION 14 FUNCTION 14
FUNCTION 13 FUNCTION 13
FUNCTION 12 FUNCTION 12
FUNCTION 11 FUNCTION 11
FUNCTION 10 FUNCTION 10
FUNCTION 09 FUNCTION 09
FUNCTION 08 FUNCTION 08
FUNCTION 07 FUNCTION 07
FUNCTION 06 FUNCTION 06
FUNCTION 05 FUNCTION 05
FUNCTION 04 FUNCTION 04
FUNCTION 03 FUNCTION 03
FUNCTION 02 FUNCTION 02
FUNCTION 01 FUNCTION 01
.section .text.00, "ax", %progbits .section .text.00, "ax", %progbits
.thumb .thumb
.globl _start .globl _start
_start: _start:
// Expect no range extension needed for tfunc01 and an extension needed for // Expect no range extension needed for tfunc01 and an extension needed for
// tfunc31 // tfunc31
bl tfunc01 bl tfunc01
bl tfunc31 bl tfunc31
// CHECK1: _start: // CHECK1: <_start>:
// CHECK1-NEXT: 100000: ff f0 fe ff bl #1048572 // CHECK1-NEXT: 100000: ff f0 fe ff bl #1048572
// CHECK1-NEXT: 100004: ff f2 fe d7 bl #15728636 // CHECK1-NEXT: 100004: ff f2 fe d7 bl #15728636

lld/test/ELF/arm-thunk-linkerscript.s

Show All 23 Lines
.globl low_target2 .globl low_target2
.type low_target2, %function .type low_target2, %function
low_target2: low_target2:
bl high_target bl high_target
bl high_target2 bl high_target2
// CHECK: Disassembly of section .text_low: // CHECK: Disassembly of section .text_low:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 94: 70 47 bx lr // CHECK-NEXT: 94: 70 47 bx lr
// CHECK: low_target: // CHECK: <low_target>:
// CHECK-NEXT: 96: 00 f0 03 f8 bl #6 // CHECK-NEXT: 96: 00 f0 03 f8 bl #6
// CHECK-NEXT: 9a: 00 f0 06 f8 bl #12 // CHECK-NEXT: 9a: 00 f0 06 f8 bl #12
// CHECK: __Thumbv7ABSLongThunk_high_target: // CHECK: <__Thumbv7ABSLongThunk_high_target>:
// CHECK-NEXT: a0: 40 f2 01 0c movw r12, #1 // CHECK-NEXT: a0: 40 f2 01 0c movw r12, #1
// CHECK-NEXT: a4: c0 f2 00 2c movt r12, #512 // CHECK-NEXT: a4: c0 f2 00 2c movt r12, #512
// CHECK-NEXT: a8: 60 47 bx r12 // CHECK-NEXT: a8: 60 47 bx r12
// CHECK: __Thumbv7ABSLongThunk_high_target2: // CHECK: <__Thumbv7ABSLongThunk_high_target2>:
// CHECK-NEXT: aa: 40 f2 1d 0c movw r12, #29 // CHECK-NEXT: aa: 40 f2 1d 0c movw r12, #29
// CHECK-NEXT: ae: c0 f2 00 2c movt r12, #512 // CHECK-NEXT: ae: c0 f2 00 2c movt r12, #512
// CHECK-NEXT: b2: 60 47 bx r12 // CHECK-NEXT: b2: 60 47 bx r12
// CHECK: low_target2: // CHECK: <low_target2>:
// CHECK-NEXT: b4: ff f7 f4 ff bl #-24 // CHECK-NEXT: b4: ff f7 f4 ff bl #-24
// CHECK-NEXT: b8: ff f7 f7 ff bl #-18 // CHECK-NEXT: b8: ff f7 f7 ff bl #-18
.section .text_high, "ax", %progbits .section .text_high, "ax", %progbits
.thumb .thumb
.globl high_target .globl high_target
.type high_target, %function .type high_target, %function
high_target: high_target:
bl low_target bl low_target
bl low_target2 bl low_target2
.section .text_high2, "ax", %progbits .section .text_high2, "ax", %progbits
.thumb .thumb
.globl high_target2 .globl high_target2
.type high_target2, %function .type high_target2, %function
high_target2: high_target2:
bl low_target bl low_target
bl low_target2 bl low_target2
// CHECK: Disassembly of section .text_high: // CHECK: Disassembly of section .text_high:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: high_target: // CHECK-NEXT: <high_target>:
// CHECK-NEXT: 2000000: 00 f0 02 f8 bl #4 // CHECK-NEXT: 2000000: 00 f0 02 f8 bl #4
// CHECK-NEXT: 2000004: 00 f0 05 f8 bl #10 // CHECK-NEXT: 2000004: 00 f0 05 f8 bl #10
// CHECK: __Thumbv7ABSLongThunk_low_target: // CHECK: <__Thumbv7ABSLongThunk_low_target>:
// CHECK-NEXT: 2000008: 40 f2 97 0c movw r12, #151 // CHECK-NEXT: 2000008: 40 f2 97 0c movw r12, #151
// CHECK-NEXT: 200000c: c0 f2 00 0c movt r12, #0 // CHECK-NEXT: 200000c: c0 f2 00 0c movt r12, #0
// CHECK-NEXT: 2000010: 60 47 bx r12 // CHECK-NEXT: 2000010: 60 47 bx r12
// CHECK: __Thumbv7ABSLongThunk_low_target2: // CHECK: <__Thumbv7ABSLongThunk_low_target2>:
// CHECK-NEXT: 2000012: 40 f2 b5 0c movw r12, #181 // CHECK-NEXT: 2000012: 40 f2 b5 0c movw r12, #181
// CHECK-NEXT: 2000016: c0 f2 00 0c movt r12, #0 // CHECK-NEXT: 2000016: c0 f2 00 0c movt r12, #0
// CHECK-NEXT: 200001a: 60 47 bx r12 // CHECK-NEXT: 200001a: 60 47 bx r12
// CHECK: high_target2: // CHECK: <high_target2>:
// CHECK-NEXT: 200001c: ff f7 f4 ff bl #-24 // CHECK-NEXT: 200001c: ff f7 f4 ff bl #-24
// CHECK-NEXT: 2000020: ff f7 f7 ff bl #-18 // CHECK-NEXT: 2000020: ff f7 f7 ff bl #-18

lld/test/ELF/arm-thunk-many-passes.s

Show All 28 Lines
// CHECK-ELF-NEXT: SHF_EXECINSTR // CHECK-ELF-NEXT: SHF_EXECINSTR
// CHECK-ELF-NEXT: ] // CHECK-ELF-NEXT: ]
// CHECK-ELF-NEXT: Address: 0x11000 // CHECK-ELF-NEXT: Address: 0x11000
// CHECK-ELF-NEXT: Offset: 0x1000 // CHECK-ELF-NEXT: Offset: 0x1000
// CHECK-ELF-NEXT: Size: 16777292 // CHECK-ELF-NEXT: Size: 16777292
// CHECK-ELF: Name: sym // CHECK-ELF: Name: sym
// CHECK-ELF-NEXT: Value: 0x101104C // CHECK-ELF-NEXT: Value: 0x101104C
// CHECK: 00011000 _start: // CHECK: 00011000 <_start>:
// CHECK-NEXT: 11000: b.w #14680132 <__Thumbv7ABSLongThunk_f3> // CHECK-NEXT: 11000: b.w #14680132 <__Thumbv7ABSLongThunk_f3>
// CHECK-NEXT: 11004: b.w #14680128 <__Thumbv7ABSLongThunk_f3> // CHECK-NEXT: 11004: b.w #14680128 <__Thumbv7ABSLongThunk_f3>
// CHECK-NEXT: 11008: b.w #14680128 <__Thumbv7ABSLongThunk_f4> // CHECK-NEXT: 11008: b.w #14680128 <__Thumbv7ABSLongThunk_f4>
// CHECK-NEXT: 1100c: b.w #14680124 <__Thumbv7ABSLongThunk_f4> // CHECK-NEXT: 1100c: b.w #14680124 <__Thumbv7ABSLongThunk_f4>
// CHECK-NEXT: 11010: b.w #14680124 <__Thumbv7ABSLongThunk_f5> // CHECK-NEXT: 11010: b.w #14680124 <__Thumbv7ABSLongThunk_f5>
// CHECK-NEXT: 11014: b.w #14680120 <__Thumbv7ABSLongThunk_f5> // CHECK-NEXT: 11014: b.w #14680120 <__Thumbv7ABSLongThunk_f5>
// CHECK-NEXT: 11018: b.w #14680120 <__Thumbv7ABSLongThunk_f6> // CHECK-NEXT: 11018: b.w #14680120 <__Thumbv7ABSLongThunk_f6>
// CHECK-NEXT: 1101c: b.w #14680116 <__Thumbv7ABSLongThunk_f6> // CHECK-NEXT: 1101c: b.w #14680116 <__Thumbv7ABSLongThunk_f6>
▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines

lld/test/ELF/arm-thunk-multipass-plt.s

Show All 36 Linesneedsplt:
.space (1024 * 1024) .space (1024 * 1024)
.section .text.06, "ax", %progbits .section .text.06, "ax", %progbits
.space (1024 * 1024) .space (1024 * 1024)
.section .text.07, "ax", %progbits .section .text.07, "ax", %progbits
.space (1024 * 1024) .space (1024 * 1024)
// 0x70000c + 8 + 0x60002c = 0xd00040 = preemptible@plt // 0x70000c + 8 + 0x60002c = 0xd00040 = preemptible@plt
// CHECK: 0070000c __ARMV5PILongThunk_preemptible: // CHECK: 0070000c <__ARMV5PILongThunk_preemptible>:
// CHECK-NEXT: 70000c: 0b 00 18 ea b #6291500 // CHECK-NEXT: 70000c: 0b 00 18 ea b #6291500
.section .text.08, "ax", %progbits .section .text.08, "ax", %progbits
.space (1024 * 1024) - 4 .space (1024 * 1024) - 4
.section .text.10, "ax", %progbits .section .text.10, "ax", %progbits
.balign 2 .balign 2
bl preemptible bl preemptible
Show All 12 Linespreemptible2:
.section .text.11, "ax", %progbits .section .text.11, "ax", %progbits
.space (5 * 1024 * 1024) .space (5 * 1024 * 1024)
// CHECK-PLT: Disassembly of section .plt: // CHECK-PLT: Disassembly of section .plt:
// CHECK-PLT-EMPTY: // CHECK-PLT-EMPTY:
// CHECK-PLT-NEXT: 00d00020 $a: // CHECK-PLT-NEXT: 00d00020 <$a>:
// CHECK-PLT-NEXT: d00020: 04 e0 2d e5 str lr, [sp, #-4]! // CHECK-PLT-NEXT: d00020: 04 e0 2d e5 str lr, [sp, #-4]!
// CHECK-PLT-NEXT: d00024: 00 e6 8f e2 add lr, pc, #0, #12 // CHECK-PLT-NEXT: d00024: 00 e6 8f e2 add lr, pc, #0, #12
// CHECK-PLT-NEXT: d00028: 02 ea 8e e2 add lr, lr, #8192 // CHECK-PLT-NEXT: d00028: 02 ea 8e e2 add lr, lr, #8192
// CHECK-PLT-NEXT: d0002c: 94 f0 be e5 ldr pc, [lr, #148]! // CHECK-PLT-NEXT: d0002c: 94 f0 be e5 ldr pc, [lr, #148]!
// CHECK-PLT: 00d00030 $d: // CHECK-PLT: 00d00030 <$d>:
// CHECK-PLT-NEXT: d00030: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK-PLT-NEXT: d00030: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK-PLT-NEXT: d00034: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK-PLT-NEXT: d00034: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK-PLT-NEXT: d00038: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK-PLT-NEXT: d00038: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK-PLT-NEXT: d0003c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK-PLT-NEXT: d0003c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK-PLT: 00d00040 $a: // CHECK-PLT: 00d00040 <$a>:
// CHECK-PLT-NEXT: d00040: 00 c6 8f e2 add r12, pc, #0, #12 // CHECK-PLT-NEXT: d00040: 00 c6 8f e2 add r12, pc, #0, #12
// CHECK-PLT-NEXT: d00044: 02 ca 8c e2 add r12, r12, #8192 // CHECK-PLT-NEXT: d00044: 02 ca 8c e2 add r12, r12, #8192
// CHECK-PLT-NEXT: d00048: 7c f0 bc e5 ldr pc, [r12, #124]! // CHECK-PLT-NEXT: d00048: 7c f0 bc e5 ldr pc, [r12, #124]!
// CHECK-PLT: 00d0004c $d: // CHECK-PLT: 00d0004c <$d>:
// CHECK-PLT-NEXT: d0004c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK-PLT-NEXT: d0004c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK-PLT: 00d00050 $a: // CHECK-PLT: 00d00050 <$a>:
// CHECK-PLT-NEXT: d00050: 00 c6 8f e2 add r12, pc, #0, #12 // CHECK-PLT-NEXT: d00050: 00 c6 8f e2 add r12, pc, #0, #12
// CHECK-PLT-NEXT: d00054: 02 ca 8c e2 add r12, r12, #8192 // CHECK-PLT-NEXT: d00054: 02 ca 8c e2 add r12, r12, #8192
// CHECK-PLT-NEXT: d00058: 70 f0 bc e5 ldr pc, [r12, #112]! // CHECK-PLT-NEXT: d00058: 70 f0 bc e5 ldr pc, [r12, #112]!
// CHECK-PLT: 00d0005c $d: // CHECK-PLT: 00d0005c <$d>:
// CHECK-PLT-NEXT: d0005c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK-PLT-NEXT: d0005c: d4 d4 d4 d4 .word 0xd4d4d4d4

lld/test/ELF/arm-thunk-multipass.s

Show All 20 Lines
.endm .endm
FUNCTION 00 FUNCTION 00
.globl _start .globl _start
_start: _start:
bl target bl target
b.w arm_target b.w arm_target
// arm_target is in range but needs an interworking thunk // arm_target is in range but needs an interworking thunk
// CHECK1: _start: // CHECK1: <_start>:
// CHECK1-NEXT: 100002: 00 f3 06 d0 bl #15728652 // CHECK1-NEXT: 100002: 00 f3 06 d0 bl #15728652
// CHECK1-NEXT: 100006: ff f2 ff 97 b.w #15728638 <__Thumbv7ABSLongThunk_arm_target> // CHECK1-NEXT: 100006: ff f2 ff 97 b.w #15728638 <__Thumbv7ABSLongThunk_arm_target>
nop nop
nop nop
nop nop
.globl target2 .globl target2
.type target2, %function .type target2, %function
nop nop
Show All 16 Lines
FUNCTION 15 FUNCTION 15
.section .text.16, "ax", %progbits .section .text.16, "ax", %progbits
.arm .arm
.globl arm_target .globl arm_target
.type arm_target, %function .type arm_target, %function
arm_target: arm_target:
bx lr bx lr
// CHECK2: __Thumbv7ABSLongThunk_arm_target: // CHECK2: <__Thumbv7ABSLongThunk_arm_target>:
// CHECK2-NEXT: 1000008: 40 f2 02 0c movw r12, #2 // CHECK2-NEXT: 1000008: 40 f2 02 0c movw r12, #2
// CHECK2-NEXT: 100000c: c0 f2 00 1c movt r12, #256 // CHECK2-NEXT: 100000c: c0 f2 00 1c movt r12, #256
// CHECK2-NEXT: 1000010: 60 47 bx r12 // CHECK2-NEXT: 1000010: 60 47 bx r12
// CHECK2: __Thumbv7ABSLongThunk_target: // CHECK2: <__Thumbv7ABSLongThunk_target>:
// CHECK2-NEXT: 1000012: ff f0 ff bf b.w #1048574 <target> // CHECK2-NEXT: 1000012: ff f0 ff bf b.w #1048574 <target>
// CHECK2: __Thumbv7ABSLongThunk_target2: // CHECK2: <__Thumbv7ABSLongThunk_target2>:
// CHECK2-NEXT: 1000016: ff f4 fc 97 b.w #-15728648 <target2> // CHECK2-NEXT: 1000016: ff f4 fc 97 b.w #-15728648 <target2>
.section .text.17, "ax", %progbits .section .text.17, "ax", %progbits
// Just enough space so that bl target is in range if no extension thunks are // Just enough space so that bl target is in range if no extension thunks are
// generated. // generated.
.space 0x100000 - 6 .space 0x100000 - 6
.section .text.18, "ax", %progbits .section .text.18, "ax", %progbits
.thumb .thumb
.globl target .globl target
.type target, %function .type target, %function
// target is at maximum ARM branch range away from caller. // target is at maximum ARM branch range away from caller.
target: target:
// Similar case in the backwards direction // Similar case in the backwards direction
bl target2 bl target2
nop nop
nop nop
bx lr bx lr
// CHECK3: target: // CHECK3: <target>:
// CHECK3-NEXT: 1100014: ff f6 ff ff bl #-1048578 // CHECK3-NEXT: 1100014: ff f6 ff ff bl #-1048578
// CHECK3-NEXT: 1100018: 00 bf nop // CHECK3-NEXT: 1100018: 00 bf nop
// CHECK3-NEXT: 110001a: 00 bf nop // CHECK3-NEXT: 110001a: 00 bf nop
// CHECK3-NEXT: 110001c: 70 47 bx lr // CHECK3-NEXT: 110001c: 70 47 bx lr

lld/test/ELF/arm-thunk-nosuitable.s

Show All 13 Lines// RUN: llvm-objdump -triple=thumbv7a -d --start-address=0x2110b4 --stop-address=0x2110be %t | FileCheck %s
.type _start, %function .type _start, %function
_start: _start:
// Range of +/- 1 Megabyte, new ThunkSection will need creating after // Range of +/- 1 Megabyte, new ThunkSection will need creating after
// .text.1 // .text.1
beq.w target beq.w target
.section .text.1, "ax", %progbits .section .text.1, "ax", %progbits
bx lr bx lr
// CHECK: _start: // CHECK: <_start>:
// CHECK-NEXT: 2110b4: 00 f0 00 80 beq.w #0 // CHECK-NEXT: 2110b4: 00 f0 00 80 beq.w #0
// CHECK: __Thumbv7ABSLongThunk_target: // CHECK: <__Thumbv7ABSLongThunk_target>:
// CHECK-NEXT: 2110b8: 00 f0 01 90 b.w #12582914 // CHECK-NEXT: 2110b8: 00 f0 01 90 b.w #12582914
// CHECK: 2110bc: 70 47 bx lr // CHECK: 2110bc: 70 47 bx lr
.section .text.2, "ax", %progbits .section .text.2, "ax", %progbits
.space 12 * 1024 * 1024 .space 12 * 1024 * 1024
.globl target .globl target
.type target, %function .type target, %function
target: bx lr target: bx lr

lld/test/ELF/arm-thunk-re-add.s

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
FUNCTION 25 FUNCTION 25
FUNCTION 26 FUNCTION 26
FUNCTION 27 FUNCTION 27
FUNCTION 28 FUNCTION 28
FUNCTION 29 FUNCTION 29
FUNCTION 30 FUNCTION 30
FUNCTION 31 FUNCTION 31
// Precreated Thunk Pool goes here // Precreated Thunk Pool goes here
// CHECK1: __ThumbV7PILongThunk_imported: // CHECK1: <__ThumbV7PILongThunk_imported>:
// CHECK1-NEXT: 1000004: 40 f2 30 0c movw r12, #48 // CHECK1-NEXT: 1000004: 40 f2 30 0c movw r12, #48
// CHECK1-NEXT: 1000008: c0 f2 10 0c movt r12, #16 // CHECK1-NEXT: 1000008: c0 f2 10 0c movt r12, #16
// CHECK1-NEXT: 100000c: fc 44 add r12, pc // CHECK1-NEXT: 100000c: fc 44 add r12, pc
// CHECK1-NEXT: 100000e: 60 47 bx r12 // CHECK1-NEXT: 100000e: 60 47 bx r12
// CHECK1: __ThumbV7PILongThunk_imported2: // CHECK1: <__ThumbV7PILongThunk_imported2>:
// CHECK1-NEXT: 1000010: 40 f2 34 0c movw r12, #52 // CHECK1-NEXT: 1000010: 40 f2 34 0c movw r12, #52
// CHECK1-NEXT: 1000014: c0 f2 10 0c movt r12, #16 // CHECK1-NEXT: 1000014: c0 f2 10 0c movt r12, #16
// CHECK1-NEXT: 1000018: fc 44 add r12, pc // CHECK1-NEXT: 1000018: fc 44 add r12, pc
// CHECK1-NEXT: 100001a: 60 47 bx r12 // CHECK1-NEXT: 100001a: 60 47 bx r12
.section .text.32, "ax", %progbits .section .text.32, "ax", %progbits
.space 0x80000 .space 0x80000
.section .text.33, "ax", %progbits .section .text.33, "ax", %progbits
.space 0x80000 - 0x14 .space 0x80000 - 0x14
.section .text.34, "ax", %progbits .section .text.34, "ax", %progbits
// Need a Thunk to the PLT entry, can use precreated ThunkSection // Need a Thunk to the PLT entry, can use precreated ThunkSection
.globl callers .globl callers
.type callers, %function .type callers, %function
callers: callers:
b.w imported b.w imported
beq.w imported beq.w imported
b.w imported2 b.w imported2
// CHECK2: __ThumbV7PILongThunk_imported: // CHECK2: <__ThumbV7PILongThunk_imported>:
// CHECK2-NEXT: 1100008: 40 f2 2c 0c movw r12, #44 // CHECK2-NEXT: 1100008: 40 f2 2c 0c movw r12, #44
// CHECK2-NEXT: 110000c: c0 f2 00 0c movt r12, #0 // CHECK2-NEXT: 110000c: c0 f2 00 0c movt r12, #0
// CHECK2-NEXT: 1100010: fc 44 add r12, pc // CHECK2-NEXT: 1100010: fc 44 add r12, pc
// CHECK2-NEXT: 1100012: 60 47 bx r12 // CHECK2-NEXT: 1100012: 60 47 bx r12
// CHECK2: callers: // CHECK2: <callers>:
// CHECK2-NEXT: 1100014: ff f6 f6 bf b.w #-1048596 <__ThumbV7PILongThunk_imported> // CHECK2-NEXT: 1100014: ff f6 f6 bf b.w #-1048596 <__ThumbV7PILongThunk_imported>
// CHECK2-NEXT: 1100018: 3f f4 f6 af beq.w #-20 <__ThumbV7PILongThunk_imported> // CHECK2-NEXT: 1100018: 3f f4 f6 af beq.w #-20 <__ThumbV7PILongThunk_imported>
// CHECK2-NEXT: 110001c: ff f6 f8 bf b.w #-1048592 <__ThumbV7PILongThunk_imported2> // CHECK2-NEXT: 110001c: ff f6 f8 bf b.w #-1048592 <__ThumbV7PILongThunk_imported2>
// CHECK3: Disassembly of section .plt: // CHECK3: Disassembly of section .plt:
// CHECK3-EMPTY: // CHECK3-EMPTY:
// CHECK3-NEXT: $a: // CHECK3-NEXT: <$a>:
// CHECK3-NEXT: 1100020: 04 e0 2d e5 str lr, [sp, #-4]! // CHECK3-NEXT: 1100020: 04 e0 2d e5 str lr, [sp, #-4]!
// CHECK3-NEXT: 1100024: 00 e6 8f e2 add lr, pc, #0, #12 // CHECK3-NEXT: 1100024: 00 e6 8f e2 add lr, pc, #0, #12
// CHECK3-NEXT: 1100028: 02 ea 8e e2 add lr, lr, #8192 // CHECK3-NEXT: 1100028: 02 ea 8e e2 add lr, lr, #8192
// CHECK3-NEXT: 110002c: 94 f0 be e5 ldr pc, [lr, #148]! // CHECK3-NEXT: 110002c: 94 f0 be e5 ldr pc, [lr, #148]!
// CHECK3: $d: // CHECK3: <$d>:
// CHECK3-NEXT: 1100030: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3-NEXT: 1100030: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK3-NEXT: 1100034: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3-NEXT: 1100034: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK3-NEXT: 1100038: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3-NEXT: 1100038: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK3-NEXT: 110003c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3-NEXT: 110003c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK3: $a: // CHECK3: <$a>:
// CHECK3-NEXT: 1100040: 00 c6 8f e2 add r12, pc, #0, #12 // CHECK3-NEXT: 1100040: 00 c6 8f e2 add r12, pc, #0, #12
// CHECK3-NEXT: 1100044: 02 ca 8c e2 add r12, r12, #8192 // CHECK3-NEXT: 1100044: 02 ca 8c e2 add r12, r12, #8192
// CHECK3-NEXT: 1100048: 7c f0 bc e5 ldr pc, [r12, #124]! // CHECK3-NEXT: 1100048: 7c f0 bc e5 ldr pc, [r12, #124]!
// CHECK3: $d: // CHECK3: <$d>:
// CHECK3-NEXT: 110004c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3-NEXT: 110004c: d4 d4 d4 d4 .word 0xd4d4d4d4
// CHECK3: $a: // CHECK3: <$a>:
// CHECK3-NEXT: 1100050: 00 c6 8f e2 add r12, pc, #0, #12 // CHECK3-NEXT: 1100050: 00 c6 8f e2 add r12, pc, #0, #12
// CHECK3-NEXT: 1100054: 02 ca 8c e2 add r12, r12, #8192 // CHECK3-NEXT: 1100054: 02 ca 8c e2 add r12, r12, #8192
// CHECK3-NEXT: 1100058: 70 f0 bc e5 ldr pc, [r12, #112]! // CHECK3-NEXT: 1100058: 70 f0 bc e5 ldr pc, [r12, #112]!
// CHECK3: $d: // CHECK3: <$d>:
// CHECK3-NEXT: 110005c: d4 d4 d4 d4 .word 0xd4d4d4d4 // CHECK3-NEXT: 110005c: d4 d4 d4 d4 .word 0xd4d4d4d4

lld/test/ELF/arm-tls-gd32.s

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
// SEC: Dynamic Relocations { // SEC: Dynamic Relocations {
// SEC-NEXT: 0x2274 R_ARM_TLS_DTPMOD32 - // SEC-NEXT: 0x2274 R_ARM_TLS_DTPMOD32 -
// SEC-NEXT: 0x2264 R_ARM_TLS_DTPMOD32 x // SEC-NEXT: 0x2264 R_ARM_TLS_DTPMOD32 x
// SEC-NEXT: 0x2268 R_ARM_TLS_DTPOFF32 x // SEC-NEXT: 0x2268 R_ARM_TLS_DTPOFF32 x
// SEC-NEXT: 0x226C R_ARM_TLS_DTPMOD32 y // SEC-NEXT: 0x226C R_ARM_TLS_DTPMOD32 y
// SEC-NEXT: 0x2270 R_ARM_TLS_DTPOFF32 y // SEC-NEXT: 0x2270 R_ARM_TLS_DTPOFF32 y
// CHECK-LABEL: 000011f8 func: // CHECK-LABEL: 000011f8 <func>:
// CHECK-NEXT: 11f8: 00 f0 20 e3 nop // CHECK-NEXT: 11f8: 00 f0 20 e3 nop
// CHECK-NEXT: 11fc: 00 f0 20 e3 nop // CHECK-NEXT: 11fc: 00 f0 20 e3 nop
// CHECK-NEXT: 1200: 00 f0 20 e3 nop // CHECK-NEXT: 1200: 00 f0 20 e3 nop
// (0x2264 - 0x1204) + (0x1204 - 0x11f8 - 8) = 0x1064 // (0x2264 - 0x1204) + (0x1204 - 0x11f8 - 8) = 0x1064
// CHECK: 1204: 64 10 00 00 // CHECK: 1204: 64 10 00 00
// (0x226c - 0x1204) + (0x1204 - 0x11fc - 8) = 0x1068 // (0x226c - 0x1204) + (0x1204 - 0x11fc - 8) = 0x1068
// CHECK-NEXT: 1208: 68 10 00 00 // CHECK-NEXT: 1208: 68 10 00 00
// (0x2274 - 0x1204) + (0x1204 - 0x1200 - 8) = 0x106c // (0x2274 - 0x1204) + (0x1204 - 0x1200 - 8) = 0x106c
// CHECK-NEXT: 120c: 6c 10 00 00 // CHECK-NEXT: 120c: 6c 10 00 00

lld/test/ELF/arm-tls-ie32.s

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
// SEC: Dynamic Relocations { // SEC: Dynamic Relocations {
// SEC: 0x225C R_ARM_TLS_TPOFF32 // SEC: 0x225C R_ARM_TLS_TPOFF32
// SEC: 0x2254 R_ARM_TLS_TPOFF32 x // SEC: 0x2254 R_ARM_TLS_TPOFF32 x
// SEC: 0x2258 R_ARM_TLS_TPOFF32 y // SEC: 0x2258 R_ARM_TLS_TPOFF32 y
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: func: // CHECK-NEXT: <func>:
// CHECK-NEXT: 11e8: 00 f0 20 e3 nop // CHECK-NEXT: 11e8: 00 f0 20 e3 nop
// CHECK-NEXT: 11ec: 00 f0 20 e3 nop // CHECK-NEXT: 11ec: 00 f0 20 e3 nop
// CHECK-NEXT: 11f0: 00 f0 20 e3 nop // CHECK-NEXT: 11f0: 00 f0 20 e3 nop
// (0x2254 - 0x11f4) + (0x11f4 - 0x11e8 - 8) = 0x1064 // (0x2254 - 0x11f4) + (0x11f4 - 0x11e8 - 8) = 0x1064
// CHECK: 11f4: 64 10 00 00 // CHECK: 11f4: 64 10 00 00
// (0x2258 - 0x11f8) + (0x11f8 - 0x11ec - 8) = 0x1064 // (0x2258 - 0x11f8) + (0x11f8 - 0x11ec - 8) = 0x1064
// CHECK-NEXT: 11f8: 64 10 00 00 // CHECK-NEXT: 11f8: 64 10 00 00
// (0x225c - 0x11f8) + (0x11f8 - 0x11f0 - 8) = 0x1064 // (0x225c - 0x11f8) + (0x11f8 - 0x11f0 - 8) = 0x1064
// CHECK-NEXT: 11fc: 64 10 00 00 // CHECK-NEXT: 11fc: 64 10 00 00

lld/test/ELF/arm-tls-ldm32.s

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
// SEC-NEXT: Address: 0x21D4 // SEC-NEXT: Address: 0x21D4
// SEC: Size: 4 // SEC: Size: 4
// SEC: Dynamic Relocations { // SEC: Dynamic Relocations {
// SEC-NEXT: 0x2224 R_ARM_TLS_DTPMOD32 - 0x0 // SEC-NEXT: 0x2224 R_ARM_TLS_DTPMOD32 - 0x0
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 11c0: 00 f0 20 e3 nop // CHECK-NEXT: 11c0: 00 f0 20 e3 nop
// (0x2224 - 0x11c4) + (0x11c4 - 0x11c0 - 8) = 0x105c // (0x2224 - 0x11c4) + (0x11c4 - 0x11c0 - 8) = 0x105c
// CHECK: 11c4: 5c 10 00 00 // CHECK: 11c4: 5c 10 00 00
// CHECK-NEXT: 11c8: 00 00 00 00 // CHECK-NEXT: 11c8: 00 00 00 00
// CHECK-NEXT: 11cc: 04 00 00 00 // CHECK-NEXT: 11cc: 04 00 00 00
// CHECK-EXE: _start: // CHECK-EXE: <_start>:
// CHECK-EXE-NEXT: 11114: 00 f0 20 e3 nop // CHECK-EXE-NEXT: 11114: 00 f0 20 e3 nop
// CHECK-EXE: 11118: 0c 10 00 00 // CHECK-EXE: 11118: 0c 10 00 00
// CHECK-EXE-NEXT: 1111c: 00 00 00 00 // CHECK-EXE-NEXT: 1111c: 00 00 00 00
// CHECK-EXE-NEXT: 11120: 04 00 00 00 // CHECK-EXE-NEXT: 11120: 04 00 00 00

lld/test/ELF/arm-tls-le32.s

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// SEC-NEXT: Address: 0x12124 // SEC-NEXT: Address: 0x12124
// SEC: Size: 8 // SEC: Size: 8
// SEC: Dynamic Relocations { // SEC: Dynamic Relocations {
// SEC-NEXT: } // SEC-NEXT: }
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// offset of x from Thread pointer = (TcbSize + 0x0 = 0x8) // offset of x from Thread pointer = (TcbSize + 0x0 = 0x8)
// CHECK-NEXT: 11114: 08 00 00 00 // CHECK-NEXT: 11114: 08 00 00 00
// offset of z from Thread pointer = (TcbSize + 0x8 = 0x10) // offset of z from Thread pointer = (TcbSize + 0x8 = 0x10)
// CHECK-NEXT: 11118: 10 00 00 00 // CHECK-NEXT: 11118: 10 00 00 00
// offset of y from Thread pointer = (TcbSize + 0x4 = 0xc) // offset of y from Thread pointer = (TcbSize + 0x4 = 0xc)
// CHECK-NEXT: 1111c: 0c 00 00 00 // CHECK-NEXT: 1111c: 0c 00 00 00

lld/test/ELF/arm-undefined-weak.s

Show All 26 Lines
movt r0, :upper16:target - . movt r0, :upper16:target - .
// R_ARM_MOVW_PREL_NC // R_ARM_MOVW_PREL_NC
movw r0, :lower16:target - . movw r0, :lower16:target - .
// R_ARM_REL32 // R_ARM_REL32
.word target - . .word target - .
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: 100010b4 _start: // CHECK-NEXT: 100010b4 <_start>:
// CHECK-NEXT: 100010b4: b #-4 // CHECK-NEXT: 100010b4: b #-4
// CHECK-NEXT: 100010b8: bl #-4 // CHECK-NEXT: 100010b8: bl #-4
// CHECK-NEXT: 100010bc: bl #-4 // CHECK-NEXT: 100010bc: bl #-4
// CHECK-NEXT: 100010c0: movt r0, #0 // CHECK-NEXT: 100010c0: movt r0, #0
// CHECK-NEXT: 100010c4: movw r0, #0 // CHECK-NEXT: 100010c4: movw r0, #0
// CHECK: 100010c8: 00 00 00 00 .word 0x00000000 // CHECK: 100010c8: 00 00 00 00 .word 0x00000000

lld/test/ELF/basic-avr.s

# REQUIRES: avr # REQUIRES: avr
# RUN: llvm-mc -filetype=obj -triple=avr-unknown-linux -mcpu=atmega328p %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=avr-unknown-linux -mcpu=atmega328p %s -o %t.o
# RUN: ld.lld %t.o -o %t.exe -Ttext=0 # RUN: ld.lld %t.o -o %t.exe -Ttext=0
# RUN: llvm-objdump -d %t.exe | FileCheck %s # RUN: llvm-objdump -d %t.exe | FileCheck %s
main: main:
call foo call foo
foo: foo:
jmp foo jmp foo
# CHECK: main: # CHECK: <main>:
# CHECK-NEXT: 0: 0e 94 02 00 <unknown> # CHECK-NEXT: 0: 0e 94 02 00 <unknown>
# CHECK: foo: # CHECK: <foo>:
# CHECK-NEXT: 4: 0c 94 02 00 <unknown> # CHECK-NEXT: 4: 0c 94 02 00 <unknown>

lld/test/ELF/canonical-plt-pcrel.s

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# CHECK: Relocations [ # CHECK: Relocations [
# CHECK-NEXT: .rela.plt { # CHECK-NEXT: .rela.plt {
# CHECK-NEXT: R_X86_64_JUMP_SLOT func 0x0 # CHECK-NEXT: R_X86_64_JUMP_SLOT func 0x0
# CHECK-NEXT: R_X86_64_JUMP_SLOT ifunc 0x0 # CHECK-NEXT: R_X86_64_JUMP_SLOT ifunc 0x0
# CHECK-NEXT: } # CHECK-NEXT: }
# CHECK-NEXT: ] # CHECK-NEXT: ]
# DISASM: _start: # DISASM: <_start>:
# DISASM-NEXT: callq {{.*}} <func@plt> # DISASM-NEXT: callq {{.*}} <func@plt>
# DISASM-NEXT: callq {{.*}} <ifunc@plt> # DISASM-NEXT: callq {{.*}} <ifunc@plt>
.globl _start .globl _start
_start: _start:
.byte 0xe8 .byte 0xe8
.long func - . -4 # STT_FUNC .long func - . -4 # STT_FUNC
.byte 0xe8 .byte 0xe8
.long ifunc - . -4 # STT_GNU_IFUNC .long ifunc - . -4 # STT_GNU_IFUNC

lld/test/ELF/comdat.s

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// GC: removing unused section {{.*}}.o:(.text) // GC: removing unused section {{.*}}.o:(.text)
.section .text2,"axG",@progbits,foo,comdat,unique,0 .section .text2,"axG",@progbits,foo,comdat,unique,0
foo: foo:
nop nop
// CHECK: Disassembly of section .text2: // CHECK: Disassembly of section .text2:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: foo: // CHECK-NEXT: <foo>:
// CHECK-NEXT: 1234: {{.*}} nop // CHECK-NEXT: 1234: {{.*}} nop
// CHECK-NOT: nop // CHECK-NOT: nop
.section bar, "ax" .section bar, "ax"
call foo call foo
// CHECK: Disassembly of section bar: // CHECK: Disassembly of section bar:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: bar: // CHECK-NEXT: <bar>:
// 0x1234 - 0x1235 - 5 = -6 // 0x1234 - 0x1235 - 5 = -6
// CHECK-NEXT: 1235: {{.*}} callq -6 // CHECK-NEXT: 1235: {{.*}} callq -6
.section .text3,"axG",@progbits,zed,comdat,unique,0 .section .text3,"axG",@progbits,zed,comdat,unique,0
// READ: Name: .text2 // READ: Name: .text2
// READ-NEXT: Type: SHT_PROGBITS // READ-NEXT: Type: SHT_PROGBITS
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lld/test/ELF/defsym.s

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# CHECK-NEXT: Type: # CHECK-NEXT: Type:
# CHECK-NEXT: Other: # CHECK-NEXT: Other:
# CHECK-NEXT: Section: Absolute # CHECK-NEXT: Section: Absolute
# CHECK-NEXT: } # CHECK-NEXT: }
## Check we can use foo2 and it that it is an alias for foo1. ## Check we can use foo2 and it that it is an alias for foo1.
# USE: Disassembly of section .text: # USE: Disassembly of section .text:
# USE-EMPTY: # USE-EMPTY:
# USE-NEXT: _start: # USE-NEXT: <_start>:
# USE-NEXT: movl $0x123, %edx # USE-NEXT: movl $0x123, %edx
# RUN: ld.lld -o %t %t.o --defsym=foo2=1 # RUN: ld.lld -o %t %t.o --defsym=foo2=1
# RUN: llvm-readobj --symbols -S %t | FileCheck %s --check-prefix=ABS # RUN: llvm-readobj --symbols -S %t | FileCheck %s --check-prefix=ABS
# ABS: Symbol { # ABS: Symbol {
# ABS: Name: foo2 # ABS: Name: foo2
# ABS-NEXT: Value: 0x1 # ABS-NEXT: Value: 0x1
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lld/test/ELF/eh-frame-hdr.s

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// NOHDR: Sections [ // NOHDR: Sections [
// NOHDR-NOT: Name: .eh_frame_hdr // NOHDR-NOT: Name: .eh_frame_hdr
// NOHDR: ProgramHeaders [ // NOHDR: ProgramHeaders [
// NOHDR-NOT: PT_GNU_EH_FRAME // NOHDR-NOT: PT_GNU_EH_FRAME
// HDRDISASM: Disassembly of section foo: // HDRDISASM: Disassembly of section foo:
// HDRDISASM-EMPTY: // HDRDISASM-EMPTY:
// HDRDISASM-NEXT: foo: // HDRDISASM-NEXT: <foo>:
// HDRDISASM-NEXT: 2011e4: 90 nop // HDRDISASM-NEXT: 2011e4: 90 nop
// HDRDISASM-EMPTY: // HDRDISASM-EMPTY:
// HDRDISASM-NEXT: Disassembly of section bar: // HDRDISASM-NEXT: Disassembly of section bar:
// HDRDISASM-EMPTY: // HDRDISASM-EMPTY:
// HDRDISASM-NEXT: bar: // HDRDISASM-NEXT: <bar>:
// HDRDISASM-NEXT: 2011e5: 90 nop // HDRDISASM-NEXT: 2011e5: 90 nop
// HDRDISASM-EMPTY: // HDRDISASM-EMPTY:
// HDRDISASM-NEXT: Disassembly of section dah: // HDRDISASM-NEXT: Disassembly of section dah:
// HDRDISASM-EMPTY: // HDRDISASM-EMPTY:
// HDRDISASM-NEXT: dah: // HDRDISASM-NEXT: <dah>:
// HDRDISASM-NEXT: 2011e6: 90 nop // HDRDISASM-NEXT: 2011e6: 90 nop
// HDR: Section { // HDR: Section {
// HDR: Index: // HDR: Index:
// HDR: Name: .eh_frame_hdr // HDR: Name: .eh_frame_hdr
// HDR-NEXT: Type: SHT_PROGBITS // HDR-NEXT: Type: SHT_PROGBITS
// HDR-NEXT: Flags [ // HDR-NEXT: Flags [
// HDR-NEXT: SHF_ALLOC // HDR-NEXT: SHF_ALLOC
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lld/test/ELF/ehframe-relocation.s

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// CHECK-NEXT: Offset: // CHECK-NEXT: Offset:
// CHECK-NEXT: Size: 52 // CHECK-NEXT: Size: 52
// CHECK-NOT: .eh_frame // CHECK-NOT: .eh_frame
// 0x200120 = 2097440 // 0x200120 = 2097440
// 0x200120 + 5 = 2097445 // 0x200120 + 5 = 2097445
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: _start: // DISASM-NEXT: <_start>:
// DISASM-NEXT: 201154: {{.*}} movq 2097440, %rax // DISASM-NEXT: 201154: {{.*}} movq 2097440, %rax
// DISASM-NEXT: 20115c: {{.*}} movq 2097445, %rax // DISASM-NEXT: 20115c: {{.*}} movq 2097445, %rax
.section .eh_frame,"a",@unwind .section .eh_frame,"a",@unwind
.section .text .section .text
.globl _start .globl _start
_start: _start:
movq .eh_frame, %rax movq .eh_frame, %rax
movq .eh_frame + 5, %rax movq .eh_frame + 5, %rax

lld/test/ELF/gdb-index.s

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# RUN: ld.lld --gdb-index %t1.o %t2.o -o %t # RUN: ld.lld --gdb-index %t1.o %t2.o -o %t
# RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=DISASM # RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=DISASM
# RUN: llvm-dwarfdump -gdb-index %t | FileCheck %s --check-prefix=DWARF # RUN: llvm-dwarfdump -gdb-index %t | FileCheck %s --check-prefix=DWARF
# RUN: llvm-readelf -sections %t | FileCheck %s --check-prefix=SECTION # RUN: llvm-readelf -sections %t | FileCheck %s --check-prefix=SECTION
# DISASM: Disassembly of section .text: # DISASM: Disassembly of section .text:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM: entrypoint: # DISASM: <entrypoint>:
# DISASM-CHECK: 201000: 90 nop # DISASM-CHECK: 201000: 90 nop
# DISASM-CHECK: 201001: cc int3 # DISASM-CHECK: 201001: cc int3
# DISASM-CHECK: 201002: cc int3 # DISASM-CHECK: 201002: cc int3
# DISASM-CHECK: 201003: cc int3 # DISASM-CHECK: 201003: cc int3
# DISASM: aaaaaaaaaaaaaaaa: # DISASM: <aaaaaaaaaaaaaaaa>:
# DISASM-CHECK: 201004: 90 nop # DISASM-CHECK: 201004: 90 nop
# DISASM-CHECK: 201005: 90 nop # DISASM-CHECK: 201005: 90 nop
# DWARF: .gdb_index contents: # DWARF: .gdb_index contents:
# DWARF-NEXT: Version = 7 # DWARF-NEXT: Version = 7
# DWARF: CU list offset = 0x18, has 2 entries: # DWARF: CU list offset = 0x18, has 2 entries:
# DWARF-NEXT: 0: Offset = 0x0, Length = 0x34 # DWARF-NEXT: 0: Offset = 0x0, Length = 0x34
# DWARF-NEXT: 1: Offset = 0x34, Length = 0x34 # DWARF-NEXT: 1: Offset = 0x34, Length = 0x34
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lld/test/ELF/gnu-ifunc-i386.s

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// CHECK-NEXT: Type: Function // CHECK-NEXT: Type: Function
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .text // CHECK-NEXT: Section: .text
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT:] // CHECK-NEXT:]
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: foo_resolver: // DISASM-NEXT: <foo_resolver>:
// DISASM-NEXT: 4010e4: retl // DISASM-NEXT: 4010e4: retl
// DISASM: bar_resolver: // DISASM: <bar_resolver>:
// DISASM-NEXT: 4010e5: retl // DISASM-NEXT: 4010e5: retl
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 4010e6: calll 21 <foo> // DISASM-NEXT: 4010e6: calll 21 <foo>
// DISASM-NEXT: calll 32 <bar> // DISASM-NEXT: calll 32 <bar>
// DISASM-NEXT: movl $4194516, %edx // DISASM-NEXT: movl $4194516, %edx
// DISASM-NEXT: movl $4194532, %edx // DISASM-NEXT: movl $4194532, %edx
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .iplt: // DISASM-NEXT: Disassembly of section .iplt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: foo: // DISASM-NEXT: <foo>:
// DISASM-NEXT: 401100: jmpl *4202784 // DISASM-NEXT: 401100: jmpl *4202784
// DISASM-NEXT: pushl $0 // DISASM-NEXT: pushl $0
// DISASM-NEXT: jmp -4198672 // DISASM-NEXT: jmp -4198672
// DISASM: bar: // DISASM: <bar>:
// DISASM-NEXT: 401110: jmpl *4202788 // DISASM-NEXT: 401110: jmpl *4202788
// DISASM-NEXT: pushl $8 // DISASM-NEXT: pushl $8
// DISASM-NEXT: jmp -4198688 // DISASM-NEXT: jmp -4198688
.text .text
.type foo STT_GNU_IFUNC .type foo STT_GNU_IFUNC
.globl foo .globl foo
foo: foo:
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lld/test/ELF/gnu-ifunc-noplt-i386.s

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// CHECK-NEXT: Section (5) .rel.plt { // CHECK-NEXT: Section (5) .rel.plt {
// CHECK-NEXT: 0x4032D4 R_386_JUMP_SLOT bar2 // CHECK-NEXT: 0x4032D4 R_386_JUMP_SLOT bar2
// CHECK-NEXT: 0x4032D8 R_386_JUMP_SLOT zed2 // CHECK-NEXT: 0x4032D8 R_386_JUMP_SLOT zed2
// CHECK-NEXT: } // CHECK-NEXT: }
// Check that ifunc call sites still require relocation // Check that ifunc call sites still require relocation
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 004011ec foo: // DISASM-NEXT: 004011ec <foo>:
// DISASM-NEXT: retl // DISASM-NEXT: retl
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 004011ed bar: // DISASM-NEXT: 004011ed <bar>:
// DISASM-NEXT: retl // DISASM-NEXT: retl
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 004011ee _start: // DISASM-NEXT: 004011ee <_start>:
// DISASM-NEXT: calll -0x4 <_start+0x1> // DISASM-NEXT: calll -0x4 <_start+0x1>
// DISASM-NEXT: calll -0x4 <_start+0x6> // DISASM-NEXT: calll -0x4 <_start+0x6>
// DISASM-NEXT: calll 0x23 <bar2@plt> // DISASM-NEXT: calll 0x23 <bar2@plt>
// DISASM-NEXT: calll 0x2e <zed2@plt> // DISASM-NEXT: calll 0x2e <zed2@plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .plt: // DISASM-NEXT: Disassembly of section .plt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 00401210 .plt: // DISASM-NEXT: 00401210 <.plt>:
// DISASM-NEXT: pushl 0x4032cc // DISASM-NEXT: pushl 0x4032cc
// DISASM-NEXT: jmpl *0x4032d0 // DISASM-NEXT: jmpl *0x4032d0
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 00401220 bar2@plt: // DISASM-NEXT: 00401220 <bar2@plt>:
// DISASM-NEXT: jmpl *0x4032d4 // DISASM-NEXT: jmpl *0x4032d4
// DISASM-NEXT: pushl $0x0 // DISASM-NEXT: pushl $0x0
// DISASM-NEXT: jmp -0x20 <.plt> // DISASM-NEXT: jmp -0x20 <.plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 00401230 zed2@plt: // DISASM-NEXT: 00401230 <zed2@plt>:
// DISASM-NEXT: jmpl *0x4032d8 // DISASM-NEXT: jmpl *0x4032d8
// DISASM-NEXT: pushl $0x8 // DISASM-NEXT: pushl $0x8
// DISASM-NEXT: jmp -0x30 <.plt> // DISASM-NEXT: jmp -0x30 <.plt>
.text .text
.type foo STT_GNU_IFUNC .type foo STT_GNU_IFUNC
.globl foo .globl foo
foo: foo:
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lld/test/ELF/gnu-ifunc-noplt.s

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// CHECK-NEXT: Section (5) .rela.plt { // CHECK-NEXT: Section (5) .rela.plt {
// CHECK-NEXT: 0x203498 R_X86_64_JUMP_SLOT bar2 0x0 // CHECK-NEXT: 0x203498 R_X86_64_JUMP_SLOT bar2 0x0
// CHECK-NEXT: 0x2034A0 R_X86_64_JUMP_SLOT zed2 0x0 // CHECK-NEXT: 0x2034A0 R_X86_64_JUMP_SLOT zed2 0x0
// CHECK-NEXT: } // CHECK-NEXT: }
// Check that ifunc call sites still require relocation // Check that ifunc call sites still require relocation
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 0000000000201320 foo: // DISASM-NEXT: 0000000000201320 <foo>:
// DISASM-NEXT: 201320: retq // DISASM-NEXT: 201320: retq
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 0000000000201321 bar: // DISASM-NEXT: 0000000000201321 <bar>:
// DISASM-NEXT: 201321: retq // DISASM-NEXT: 201321: retq
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 0000000000201322 _start: // DISASM-NEXT: 0000000000201322 <_start>:
// DISASM-NEXT: 201322: callq 0 <_start+0x5> // DISASM-NEXT: 201322: callq 0 <_start+0x5>
// DISASM-NEXT: 201327: callq 0 <_start+0xa> // DISASM-NEXT: 201327: callq 0 <_start+0xa>
// DISASM-NEXT: 20132c: callq 31 <bar2@plt> // DISASM-NEXT: 20132c: callq 31 <bar2@plt>
// DISASM-NEXT: 201331: callq 42 <zed2@plt> // DISASM-NEXT: 201331: callq 42 <zed2@plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .plt: // DISASM-NEXT: Disassembly of section .plt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 0000000000201340 .plt: // DISASM-NEXT: 0000000000201340 <.plt>:
// DISASM-NEXT: 201340: pushq 8514(%rip) // DISASM-NEXT: 201340: pushq 8514(%rip)
// DISASM-NEXT: 201346: jmpq *8516(%rip) // DISASM-NEXT: 201346: jmpq *8516(%rip)
// DISASM-NEXT: 20134c: nopl (%rax) // DISASM-NEXT: 20134c: nopl (%rax)
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 0000000000201350 bar2@plt: // DISASM-NEXT: 0000000000201350 <bar2@plt>:
// DISASM-NEXT: 201350: jmpq *8514(%rip) // DISASM-NEXT: 201350: jmpq *8514(%rip)
// DISASM-NEXT: 201356: pushq $0 // DISASM-NEXT: 201356: pushq $0
// DISASM-NEXT: 20135b: jmp -32 <.plt> // DISASM-NEXT: 20135b: jmp -32 <.plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: 0000000000201360 zed2@plt: // DISASM-NEXT: 0000000000201360 <zed2@plt>:
// DISASM-NEXT: 201360: jmpq *8506(%rip) // DISASM-NEXT: 201360: jmpq *8506(%rip)
// DISASM-NEXT: 201366: pushq $1 // DISASM-NEXT: 201366: pushq $1
// DISASM-NEXT: 20136b: jmp -48 <.plt> // DISASM-NEXT: 20136b: jmp -48 <.plt>
.text .text
.type foo STT_GNU_IFUNC .type foo STT_GNU_IFUNC
.globl foo .globl foo
foo: foo:
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lld/test/ELF/gnu-ifunc-plt-i386.s

Show All 26 Lines
// back to the plt entry + 6. // back to the plt entry + 6.
// GOTPLT: Contents of section .got.plt: // GOTPLT: Contents of section .got.plt:
// GOTPLT: 403298 20224000 00000000 00000000 e6114000 // GOTPLT: 403298 20224000 00000000 00000000 e6114000
// GOTPLT-NEXT: 4032a8 f6114000 b4114000 b5114000 // GOTPLT-NEXT: 4032a8 f6114000 b4114000 b5114000
// Check that a PLT header is written and the ifunc entries appear last // Check that a PLT header is written and the ifunc entries appear last
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: foo: // DISASM-NEXT: <foo>:
// DISASM-NEXT: 4011b4: retl // DISASM-NEXT: 4011b4: retl
// DISASM: bar: // DISASM: <bar>:
// DISASM-NEXT: 4011b5: retl // DISASM-NEXT: 4011b5: retl
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 4011b6: calll 69 <zed2+0x401200> // DISASM-NEXT: 4011b6: calll 69 <zed2+0x401200>
// DISASM-NEXT: calll 80 <zed2+0x401210> // DISASM-NEXT: calll 80 <zed2+0x401210>
// DISASM-NEXT: calll 27 <bar2@plt> // DISASM-NEXT: calll 27 <bar2@plt>
// DISASM-NEXT: calll 38 <zed2@plt> // DISASM-NEXT: calll 38 <zed2@plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .plt: // DISASM-NEXT: Disassembly of section .plt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .plt: // DISASM-NEXT: <.plt>:
// DISASM-NEXT: 4011d0: pushl 4207260 // DISASM-NEXT: 4011d0: pushl 4207260
// DISASM-NEXT: jmpl *4207264 // DISASM-NEXT: jmpl *4207264
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: bar2@plt: // DISASM-NEXT: <bar2@plt>:
// DISASM-NEXT: 4011e0: jmpl *4207268 // DISASM-NEXT: 4011e0: jmpl *4207268
// DISASM-NEXT: pushl $0 // DISASM-NEXT: pushl $0
// DISASM-NEXT: jmp -32 <.plt> // DISASM-NEXT: jmp -32 <.plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: zed2@plt: // DISASM-NEXT: <zed2@plt>:
// DISASM-NEXT: 4011f0: jmpl *4207272 // DISASM-NEXT: 4011f0: jmpl *4207272
// DISASM-NEXT: pushl $8 // DISASM-NEXT: pushl $8
// DISASM-NEXT: jmp -48 <.plt> // DISASM-NEXT: jmp -48 <.plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .iplt: // DISASM-NEXT: Disassembly of section .iplt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .iplt: // DISASM-NEXT: <.iplt>:
// DISASM-NEXT: jmpl *4207276 // DISASM-NEXT: jmpl *4207276
// DISASM-NEXT: pushl $0 // DISASM-NEXT: pushl $0
// DISASM-NEXT: jmp -64 <.plt> // DISASM-NEXT: jmp -64 <.plt>
// DISASM-NEXT: jmpl *4207280 // DISASM-NEXT: jmpl *4207280
// DISASM-NEXT: pushl $8 // DISASM-NEXT: pushl $8
// DISASM-NEXT: jmp -80 <.plt> // DISASM-NEXT: jmp -80 <.plt>
.text .text
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lld/test/ELF/gnu-ifunc-plt.s

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// GOTPLT-NEXT: 203430 40232000 00000000 00000000 00000000 // GOTPLT-NEXT: 203430 40232000 00000000 00000000 00000000
// GOTPLT-NEXT: 203440 00000000 00000000 06132000 00000000 // GOTPLT-NEXT: 203440 00000000 00000000 06132000 00000000
// GOTPLT-NEXT: 203450 16132000 00000000 00000000 00000000 // GOTPLT-NEXT: 203450 16132000 00000000 00000000 00000000
// GOTPLT-NEXT: 203460 00000000 00000000 // GOTPLT-NEXT: 203460 00000000 00000000
// Check that a PLT header is written and the ifunc entries appear last // Check that a PLT header is written and the ifunc entries appear last
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: foo: // DISASM-NEXT: <foo>:
// DISASM-NEXT: 2012d8: retq // DISASM-NEXT: 2012d8: retq
// DISASM: bar: // DISASM: <bar>:
// DISASM-NEXT: 2012d9: retq // DISASM-NEXT: 2012d9: retq
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 2012da: callq 65 // DISASM-NEXT: 2012da: callq 65
// DISASM-NEXT: 2012df: callq 76 // DISASM-NEXT: 2012df: callq 76
// DISASM-NEXT: callq {{.*}} <bar2@plt> // DISASM-NEXT: callq {{.*}} <bar2@plt>
// DISASM-NEXT: callq {{.*}} <zed2@plt> // DISASM-NEXT: callq {{.*}} <zed2@plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .plt: // DISASM-NEXT: Disassembly of section .plt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .plt: // DISASM-NEXT: <.plt>:
// DISASM-NEXT: 2012f0: pushq 8514(%rip) // DISASM-NEXT: 2012f0: pushq 8514(%rip)
// DISASM-NEXT: 2012f6: jmpq *8516(%rip) // DISASM-NEXT: 2012f6: jmpq *8516(%rip)
// DISASM-NEXT: 2012fc: nopl (%rax) // DISASM-NEXT: 2012fc: nopl (%rax)
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: bar2@plt: // DISASM-NEXT: <bar2@plt>:
// DISASM-NEXT: 201300: jmpq *8514(%rip) // DISASM-NEXT: 201300: jmpq *8514(%rip)
// DISASM-NEXT: 201306: pushq $0 // DISASM-NEXT: 201306: pushq $0
// DISASM-NEXT: 20130b: jmp -32 <.plt> // DISASM-NEXT: 20130b: jmp -32 <.plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: zed2@plt: // DISASM-NEXT: <zed2@plt>:
// DISASM-NEXT: 201310: jmpq *8506(%rip) // DISASM-NEXT: 201310: jmpq *8506(%rip)
// DISASM-NEXT: 201316: pushq $1 // DISASM-NEXT: 201316: pushq $1
// DISASM-NEXT: 20131b: jmp -48 <.plt> // DISASM-NEXT: 20131b: jmp -48 <.plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .iplt: // DISASM-NEXT: Disassembly of section .iplt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .iplt: // DISASM-NEXT: <.iplt>:
// DISASM-NEXT: 201320: jmpq *8498(%rip) // DISASM-NEXT: 201320: jmpq *8498(%rip)
// DISASM-NEXT: 201326: pushq $0 // DISASM-NEXT: 201326: pushq $0
// DISASM-NEXT: 20132b: jmp -64 <.plt> // DISASM-NEXT: 20132b: jmp -64 <.plt>
// DISASM-NEXT: 201330: jmpq *8490(%rip) // DISASM-NEXT: 201330: jmpq *8490(%rip)
// DISASM-NEXT: 201336: pushq $1 // DISASM-NEXT: 201336: pushq $1
// DISASM-NEXT: 20133b: jmp -80 <.plt> // DISASM-NEXT: 20133b: jmp -80 <.plt>
.text .text
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lld/test/ELF/gnu-ifunc-shared.s

// REQUIRES: x86 // REQUIRES: x86
/// For non-preemptable ifunc, place ifunc PLT entries after regular PLT entries. /// For non-preemptable ifunc, place ifunc PLT entries after regular PLT entries.
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
// RUN: ld.lld --shared -o %t.so %t.o // RUN: ld.lld --shared -o %t.so %t.o
// RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s --check-prefix=DISASM // RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s --check-prefix=DISASM
// RUN: llvm-readobj -r %t.so | FileCheck %s // RUN: llvm-readobj -r %t.so | FileCheck %s
// Check that an IRELATIVE relocation is used for a non-preemptible ifunc // Check that an IRELATIVE relocation is used for a non-preemptible ifunc
// handler and a JUMP_SLOT is used for a preemptible ifunc // handler and a JUMP_SLOT is used for a preemptible ifunc
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: fct: // DISASM-NEXT: <fct>:
// DISASM-NEXT: 1308: retq // DISASM-NEXT: 1308: retq
// DISASM: fct2: // DISASM: <fct2>:
// DISASM-NEXT: 1309: retq // DISASM-NEXT: 1309: retq
// DISASM: f1: // DISASM: <f1>:
// DISASM-NEXT: 130a: callq 65 // DISASM-NEXT: 130a: callq 65
// DISASM-NEXT: 130f: callq 28 // DISASM-NEXT: 130f: callq 28
// DISASM-NEXT: 1314: callq 39 // DISASM-NEXT: 1314: callq 39
// DISASM-NEXT: 1319: retq // DISASM-NEXT: 1319: retq
// DISASM: f2: // DISASM: <f2>:
// DISASM-NEXT: 131a: retq // DISASM-NEXT: 131a: retq
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .plt: // DISASM-NEXT: Disassembly of section .plt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .plt: // DISASM-NEXT: <.plt>:
// DISASM-NEXT: 1320: pushq 8482(%rip) // DISASM-NEXT: 1320: pushq 8482(%rip)
// DISASM-NEXT: 1326: jmpq *8484(%rip) // DISASM-NEXT: 1326: jmpq *8484(%rip)
// DISASM-NEXT: 132c: nopl (%rax) // DISASM-NEXT: 132c: nopl (%rax)
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: fct2@plt: // DISASM-NEXT: <fct2@plt>:
// DISASM-NEXT: 1330: jmpq *8482(%rip) // DISASM-NEXT: 1330: jmpq *8482(%rip)
// DISASM-NEXT: 1336: pushq $0 // DISASM-NEXT: 1336: pushq $0
// DISASM-NEXT: 133b: jmp -32 <.plt> // DISASM-NEXT: 133b: jmp -32 <.plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: f2@plt: // DISASM-NEXT: <f2@plt>:
// DISASM-NEXT: 1340: jmpq *8474(%rip) // DISASM-NEXT: 1340: jmpq *8474(%rip)
// DISASM-NEXT: 1346: pushq $1 // DISASM-NEXT: 1346: pushq $1
// DISASM-NEXT: 134b: jmp -48 <.plt> // DISASM-NEXT: 134b: jmp -48 <.plt>
// DISASM: Disassembly of section .iplt: // DISASM: Disassembly of section .iplt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM: .iplt: // DISASM: <.iplt>:
// DISASM-NEXT: 1350: jmpq *8466(%rip) // DISASM-NEXT: 1350: jmpq *8466(%rip)
// DISASM-NEXT: 1356: pushq $0 // DISASM-NEXT: 1356: pushq $0
// DISASM-NEXT: 135b: jmp -64 <.plt> // DISASM-NEXT: 135b: jmp -64 <.plt>
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK-NEXT: Section (5) .rela.dyn { // CHECK-NEXT: Section (5) .rela.dyn {
// CHECK-NEXT: 0x3468 R_X86_64_IRELATIVE - 0x1308 // CHECK-NEXT: 0x3468 R_X86_64_IRELATIVE - 0x1308
// CHECK-NEXT: } // CHECK-NEXT: }
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lld/test/ELF/gnu-ifunc.s

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
// CHECK-NEXT: Type: GNU_IFunc // CHECK-NEXT: Type: GNU_IFunc
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .text // CHECK-NEXT: Section: .text
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: ] // CHECK-NEXT: ]
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: foo: // DISASM-NEXT: <foo>:
// DISASM-NEXT: 201188: {{.*}} retq // DISASM-NEXT: 201188: {{.*}} retq
// DISASM: bar: // DISASM: <bar>:
// DISASM-NEXT: 201189: {{.*}} retq // DISASM-NEXT: 201189: {{.*}} retq
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 20118a: {{.*}} callq 33 // DISASM-NEXT: 20118a: {{.*}} callq 33
// DISASM-NEXT: 20118f: {{.*}} callq 44 // DISASM-NEXT: 20118f: {{.*}} callq 44
// DISASM-NEXT: 201194: {{.*}} movl $2097496, %edx // DISASM-NEXT: 201194: {{.*}} movl $2097496, %edx
// DISASM-NEXT: 201199: {{.*}} movl $2097544, %edx // DISASM-NEXT: 201199: {{.*}} movl $2097544, %edx
// DISASM-NEXT: 20119e: {{.*}} movl $2097545, %edx // DISASM-NEXT: 20119e: {{.*}} movl $2097545, %edx
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: Disassembly of section .iplt: // DISASM-NEXT: Disassembly of section .iplt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .iplt: // DISASM-NEXT: <.iplt>:
// DISASM-NEXT: 2011b0: {{.*}} jmpq *4122(%rip) // DISASM-NEXT: 2011b0: {{.*}} jmpq *4122(%rip)
// DISASM-NEXT: 2011b6: {{.*}} pushq $0 // DISASM-NEXT: 2011b6: {{.*}} pushq $0
// DISASM-NEXT: 2011bb: {{.*}} jmp -2101696 // DISASM-NEXT: 2011bb: {{.*}} jmp -2101696
// DISASM-NEXT: 2011c0: {{.*}} jmpq *4114(%rip) // DISASM-NEXT: 2011c0: {{.*}} jmpq *4114(%rip)
// DISASM-NEXT: 2011c6: {{.*}} pushq $1 // DISASM-NEXT: 2011c6: {{.*}} pushq $1
// DISASM-NEXT: 2011cb: {{.*}} jmp -2101712 // DISASM-NEXT: 2011cb: {{.*}} jmp -2101712
.text .text
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lld/test/ELF/got-i386.s

Show All 35 Lines
// CHECK-NEXT: Section: .bss // CHECK-NEXT: Section: .bss
// CHECK-NEXT: } // CHECK-NEXT: }
// 0x402000 - 0 = addr(.got) = 0x402000 // 0x402000 - 0 = addr(.got) = 0x402000
// 0x40200A - 10 = addr(.got) = 0x402000 // 0x40200A - 10 = addr(.got) = 0x402000
// 0x40200A + 5 - 15 = addr(.got) = 0x402000 // 0x40200A + 5 - 15 = addr(.got) = 0x402000
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: _start: // DISASM-NEXT: <_start>:
// DISASM-NEXT: 4010d4: c7 81 0c 00 00 00 01 00 00 00 movl $1, 12(%ecx) // DISASM-NEXT: 4010d4: c7 81 0c 00 00 00 01 00 00 00 movl $1, 12(%ecx)
// DISASM-NEXT: 4010de: c7 81 16 00 00 00 02 00 00 00 movl $2, 22(%ecx) // DISASM-NEXT: 4010de: c7 81 16 00 00 00 02 00 00 00 movl $2, 22(%ecx)
// DISASM-NEXT: 4010e8: c7 81 1b 00 00 00 03 00 00 00 movl $3, 27(%ecx) // DISASM-NEXT: 4010e8: c7 81 1b 00 00 00 03 00 00 00 movl $3, 27(%ecx)
.global _start .global _start
_start: _start:
movl $1, bar@GOTOFF(%ecx) movl $1, bar@GOTOFF(%ecx)
movl $2, obj@GOTOFF(%ecx) movl $2, obj@GOTOFF(%ecx)
movl $3, obj+5@GOTOFF(%ecx) movl $3, obj+5@GOTOFF(%ecx)
.type bar, @object .type bar, @object
.comm bar, 10 .comm bar, 10
.type obj, @object .type obj, @object
.comm obj, 10 .comm obj, 10

lld/test/ELF/got.s

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// Unfortunately FileCheck can't do math, so we have to check for explicit // Unfortunately FileCheck can't do math, so we have to check for explicit
// values: // values:
// 0x202338 - (0x201270 + 2) - 4 = 4290 // 0x202338 - (0x201270 + 2) - 4 = 4290
// 0x202338 - (0x201276 + 2) - 4 = 4284 // 0x202338 - (0x201276 + 2) - 4 = 4284
// 0x202340 - (0x20127c + 2) - 4 = 4286 // 0x202340 - (0x20127c + 2) - 4 = 4286
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 201270: {{.*}} jmpq *4290(%rip) // DISASM-NEXT: 201270: {{.*}} jmpq *4290(%rip)
// DISASM-NEXT: 201276: {{.*}} jmpq *4284(%rip) // DISASM-NEXT: 201276: {{.*}} jmpq *4284(%rip)
// DISASM-NEXT: 20127c: {{.*}} jmpq *4286(%rip) // DISASM-NEXT: 20127c: {{.*}} jmpq *4286(%rip)
.global _start .global _start
_start: _start:
jmp *bar@GOTPCREL(%rip) jmp *bar@GOTPCREL(%rip)
jmp *bar@GOTPCREL(%rip) jmp *bar@GOTPCREL(%rip)
jmp *zed@GOTPCREL(%rip) jmp *zed@GOTPCREL(%rip)

lld/test/ELF/got32-i386.s

Show All 10 Lines
_start: _start:
movl foo@GOT, %ebx movl foo@GOT, %ebx
## 73728 == 0x12000 == ADDR(.got) ## 73728 == 0x12000 == ADDR(.got)
# CHECK: Sections: # CHECK: Sections:
# CHECK: Name Size VMA # CHECK: Name Size VMA
# CHECK: .got 00000004 004020fc # CHECK: .got 00000004 004020fc
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: 4010f5: 8b 1d {{.*}} movl 4202748, %ebx # CHECK-NEXT: 4010f5: 8b 1d {{.*}} movl 4202748, %ebx
# RUN: not ld.lld %t.o -o /dev/null -pie 2>&1 | FileCheck %s --check-prefix=ERR # RUN: not ld.lld %t.o -o /dev/null -pie 2>&1 | FileCheck %s --check-prefix=ERR
# ERR: error: symbol 'foo' cannot be preempted; recompile with -fPIE # ERR: error: symbol 'foo' cannot be preempted; recompile with -fPIE

lld/test/ELF/got32x-i386.s

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## ##
# RUN: ld.lld %S/Inputs/i386-got32x-baseless.elf -o %t1 # RUN: ld.lld %S/Inputs/i386-got32x-baseless.elf -o %t1
# RUN: llvm-objdump -section-headers -d %t1 | FileCheck %s # RUN: llvm-objdump -section-headers -d %t1 | FileCheck %s
## 73728 == 0x12000 == ADDR(.got) ## 73728 == 0x12000 == ADDR(.got)
# CHECK: Sections: # CHECK: Sections:
# CHECK: Name Size VMA # CHECK: Name Size VMA
# CHECK: .got.plt 0000000c 00403134 # CHECK: .got.plt 0000000c 00403134
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: 401115: 8b 05 {{.*}} movl 4202800, %eax # CHECK-NEXT: 401115: 8b 05 {{.*}} movl 4202800, %eax
# CHECK-NEXT: 40111b: 8b 1d {{.*}} movl 4202800, %ebx # CHECK-NEXT: 40111b: 8b 1d {{.*}} movl 4202800, %ebx
# CHECK-NEXT: 401121: 8b 80 {{.*}} movl -4100(%eax), %eax # CHECK-NEXT: 401121: 8b 80 {{.*}} movl -4100(%eax), %eax
# CHECK-NEXT: 401127: 8b 83 {{.*}} movl -4100(%ebx), %eax # CHECK-NEXT: 401127: 8b 83 {{.*}} movl -4100(%ebx), %eax
# RUN: not ld.lld %S/Inputs/i386-got32x-baseless.elf -o /dev/null -pie 2>&1 | \ # RUN: not ld.lld %S/Inputs/i386-got32x-baseless.elf -o /dev/null -pie 2>&1 | \
# RUN: FileCheck %s --check-prefix=ERR # RUN: FileCheck %s --check-prefix=ERR
# ERR-COUNT-2: error: symbol 'foo' cannot be preempted; recompile with -fPIE # ERR-COUNT-2: error: symbol 'foo' cannot be preempted; recompile with -fPIE

lld/test/ELF/hexagon-plt.s

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# RELOC: .rela.plt { # RELOC: .rela.plt {
# RELOC-NEXT: 0x40078 R_HEX_JMP_SLOT bar 0x0 # RELOC-NEXT: 0x40078 R_HEX_JMP_SLOT bar 0x0
# RELOC-NEXT: 0x4007C R_HEX_JMP_SLOT weak 0x0 # RELOC-NEXT: 0x4007C R_HEX_JMP_SLOT weak 0x0
# RELOC-NEXT: } # RELOC-NEXT: }
# GOTPLT: section '.got.plt' # GOTPLT: section '.got.plt'
# GOTPLT-NEXT: 0x00040068 00000000 00000000 00000000 00000000 # GOTPLT-NEXT: 0x00040068 00000000 00000000 00000000 00000000
# GOTPLT-NEXT: 0x00040078 00000000 00000000 # GOTPLT-NEXT: 0x00040078 00000000 00000000
# DIS: _start: # DIS: <_start>:
## Direct call ## Direct call
## Call foo directly ## Call foo directly
# DIS-NEXT: { call 0x2003c } # DIS-NEXT: { call 0x2003c }
## Call bar via plt ## Call bar via plt
# DIS-NEXT: { call 0x20060 } # DIS-NEXT: { call 0x20060 }
## Call weak via plt ## Call weak via plt
# DIS-NEXT: { call 0x20070 } # DIS-NEXT: { call 0x20070 }
# DIS-NEXT: { immext(#0) # DIS-NEXT: { immext(#0)
Show All 12 Lines
# DIS-NEXT: r0 = #0 ; jump 0x2003c } # DIS-NEXT: r0 = #0 ; jump 0x2003c }
# DIS-NEXT: { immext(#0) # DIS-NEXT: { immext(#0)
## Call bar via plt ## Call bar via plt
# DIS-NEXT: r0 = #0 ; jump 0x20060 } # DIS-NEXT: r0 = #0 ; jump 0x20060 }
# DIS-NEXT: { immext(#0) # DIS-NEXT: { immext(#0)
## Call weak via plt ## Call weak via plt
# DIS-NEXT: r0 = #0 ; jump 0x20070 } # DIS-NEXT: r0 = #0 ; jump 0x20070 }
# DIS: foo: # DIS: <foo>:
# DIS-NEXT: 2003c: # DIS-NEXT: 2003c:
# DIS: Disassembly of section .plt: # DIS: Disassembly of section .plt:
# DIS: 00020040 .plt: # DIS: 00020040 <.plt>:
# DIS-NEXT: 20040: { immext(#131072) # DIS-NEXT: 20040: { immext(#131072)
# DIS-NEXT: 20044: r28 = add(pc,##131112) } # DIS-NEXT: 20044: r28 = add(pc,##131112) }
# DIS-NEXT: 20048: { r14 -= add(r28,#16) # DIS-NEXT: 20048: { r14 -= add(r28,#16)
# DIS-NEXT: 2004c: r15 = memw(r28+#8) # DIS-NEXT: 2004c: r15 = memw(r28+#8)
# DIS-NEXT: 20050: r28 = memw(r28+#4) } # DIS-NEXT: 20050: r28 = memw(r28+#4) }
# DIS-NEXT: 20054: { r14 = asr(r14,#2) # DIS-NEXT: 20054: { r14 = asr(r14,#2)
# DIS-NEXT: 20058: jumpr r28 } # DIS-NEXT: 20058: jumpr r28 }
# DIS-NEXT: 2005c: { trap0(#219) } # DIS-NEXT: 2005c: { trap0(#219) }
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lld/test/ELF/i386-feature-cet.s

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# RUN: llvm-readelf -x .got.plt %t | FileCheck --check-prefix=GOTPLT %s # RUN: llvm-readelf -x .got.plt %t | FileCheck --check-prefix=GOTPLT %s
# RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t | FileCheck --check-prefix=DISASM %s # RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t | FileCheck --check-prefix=DISASM %s
# GOTPLT: Hex dump of section '.got.plt': # GOTPLT: Hex dump of section '.got.plt':
# GOTPLT-NEXT: 0x004032d0 50224000 00000000 00000000 20124000 # GOTPLT-NEXT: 0x004032d0 50224000 00000000 00000000 20124000
# GOTPLT-NEXT: 0x004032e0 0b124000 # GOTPLT-NEXT: 0x004032e0 0b124000
# DISASM: Disassembly of section .text: # DISASM: Disassembly of section .text:
# DISASM: 00401200 func1: # DISASM: 00401200 <func1>:
# DISASM-NEXT: 401200: calll 0x2b <func2+0x401230> # DISASM-NEXT: 401200: calll 0x2b <func2+0x401230>
# DISASM-NEXT: 401205: calll 0x36 <ifunc> # DISASM-NEXT: 401205: calll 0x36 <ifunc>
# DISASM-NEXT: retl # DISASM-NEXT: retl
# DISASM: Disassembly of section .plt: # DISASM: Disassembly of section .plt:
# DISASM: 00401210 .plt: # DISASM: 00401210 <.plt>:
# DISASM-NEXT: 401210: pushl 0x4032d4 # DISASM-NEXT: 401210: pushl 0x4032d4
# DISASM-NEXT: jmpl *0x4032d8 # DISASM-NEXT: jmpl *0x4032d8
# DISASM-NEXT: nop # DISASM-NEXT: nop
# DISASM-NEXT: nop # DISASM-NEXT: nop
# DISASM-NEXT: nop # DISASM-NEXT: nop
# DISASM-NEXT: nop # DISASM-NEXT: nop
# DISASM-NEXT: endbr32 # DISASM-NEXT: endbr32
# DISASM-NEXT: pushl $0x0 # DISASM-NEXT: pushl $0x0
# DISASM-NEXT: jmp -0x1e <.plt> # DISASM-NEXT: jmp -0x1e <.plt>
# DISASM-NEXT: nop # DISASM-NEXT: nop
# DISASM: Disassembly of section .plt.sec: # DISASM: Disassembly of section .plt.sec:
# DISASM: 00401230 .plt.sec: # DISASM: 00401230 <.plt.sec>:
# DISASM-NEXT: 401230: endbr32 # DISASM-NEXT: 401230: endbr32
# DISASM-NEXT: jmpl *0x4032dc # DISASM-NEXT: jmpl *0x4032dc
# DISASM-NEXT: nopw (%eax,%eax) # DISASM-NEXT: nopw (%eax,%eax)
# DISASM: Disassembly of section .iplt: # DISASM: Disassembly of section .iplt:
# DISASM: 00401240 ifunc: # DISASM: 00401240 <ifunc>:
# DISASM-NEXT: 401240: endbr32 # DISASM-NEXT: 401240: endbr32
# DISASM-NEXT: jmpl *0x4032e0 # DISASM-NEXT: jmpl *0x4032e0
# DISASM-NEXT: nopw (%eax,%eax) # DISASM-NEXT: nopw (%eax,%eax)
.section ".note.gnu.property", "a" .section ".note.gnu.property", "a"
.long 4 .long 4
.long 0xc .long 0xc
.long 0x5 .long 0x5
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lld/test/ELF/i386-gotpc.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=i686-pc-linux %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=i686-pc-linux %s -o %t.o
// RUN: ld.lld --hash-style=sysv %t.o -o %t.so -shared // RUN: ld.lld --hash-style=sysv %t.o -o %t.so -shared
// RUN: llvm-readelf -S %t.so | FileCheck %s // RUN: llvm-readelf -S %t.so | FileCheck %s
// RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck --check-prefix=DISASM %s // RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck --check-prefix=DISASM %s
movl $_GLOBAL_OFFSET_TABLE_, %eax movl $_GLOBAL_OFFSET_TABLE_, %eax
// CHECK: .got.plt PROGBITS 00003190 // CHECK: .got.plt PROGBITS 00003190
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .text: // DISASM-NEXT: <.text>:
// DISASM-NEXT: 1158: movl $8248, %eax // DISASM-NEXT: 1158: movl $8248, %eax
// ^-- 0x3190 (.got.plt) - 0x1158 = 8248 // ^-- 0x3190 (.got.plt) - 0x1158 = 8248

lld/test/ELF/i386-plt.s

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// &.got.plt[4] = 0x403278 + 16 = 0x403288 // &.got.plt[4] = 0x403278 + 16 = 0x403288
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK-NEXT: Section ({{.*}}) .rel.plt { // CHECK-NEXT: Section ({{.*}}) .rel.plt {
// CHECK-NEXT: 0x403284 R_386_JUMP_SLOT bar 0x0 // CHECK-NEXT: 0x403284 R_386_JUMP_SLOT bar 0x0
// CHECK-NEXT: 0x403288 R_386_JUMP_SLOT zed 0x0 // CHECK-NEXT: 0x403288 R_386_JUMP_SLOT zed 0x0
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: ] // CHECK-NEXT: ]
// DISASM: local: // DISASM: <local>:
// DISASM-NEXT: 4011bc: // DISASM-NEXT: 4011bc:
// DISASM-NEXT: 4011be: // DISASM-NEXT: 4011be:
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 4011c0: jmp 0x2b <bar@plt> // DISASM-NEXT: 4011c0: jmp 0x2b <bar@plt>
// DISASM-NEXT: 4011c5: jmp 0x26 <bar@plt> // DISASM-NEXT: 4011c5: jmp 0x26 <bar@plt>
// DISASM-NEXT: 4011ca: jmp 0x31 <zed@plt> // DISASM-NEXT: 4011ca: jmp 0x31 <zed@plt>
// DISASM-NEXT: 4011cf: jmp -0x18 <local> // DISASM-NEXT: 4011cf: jmp -0x18 <local>
// DISASM: Disassembly of section .plt: // DISASM: Disassembly of section .plt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .plt: // DISASM-NEXT: <.plt>:
/// Push .got.plt[1], then jump to .got.plt[2] /// Push .got.plt[1], then jump to .got.plt[2]
// DISASM-NEXT: 4011e0: pushl 0x40327c // DISASM-NEXT: 4011e0: pushl 0x40327c
// DISASM-NEXT: jmpl *0x403280 // DISASM-NEXT: jmpl *0x403280
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-NEXT: nop // DISASM-NEXT: nop
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: bar@plt: // DISASM-NEXT: <bar@plt>:
/// .got.plt[3] = 0x403278 + 12 = 0x403284 /// .got.plt[3] = 0x403278 + 12 = 0x403284
// DISASM-NEXT: 4011f0: jmpl *0x403284 // DISASM-NEXT: 4011f0: jmpl *0x403284
// DISASM-NEXT: pushl $0x0 // DISASM-NEXT: pushl $0x0
// DISASM-NEXT: jmp -0x20 <.plt> // DISASM-NEXT: jmp -0x20 <.plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: zed@plt: // DISASM-NEXT: <zed@plt>:
/// .got.plt[4] = 0x403278 + 16 = 0x403288 /// .got.plt[4] = 0x403278 + 16 = 0x403288
// DISASM-NEXT: 401200: jmpl *0x403288 // DISASM-NEXT: 401200: jmpl *0x403288
// DISASM-NEXT: pushl $0x8 // DISASM-NEXT: pushl $0x8
// DISASM-NEXT: jmp -0x30 <.plt> // DISASM-NEXT: jmp -0x30 <.plt>
// CHECKSHARED: Name: .plt // CHECKSHARED: Name: .plt
// CHECKSHARED-NEXT: Type: SHT_PROGBITS // CHECKSHARED-NEXT: Type: SHT_PROGBITS
// CHECKSHARED-NEXT: Flags [ // CHECKSHARED-NEXT: Flags [
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// 0x3000 + got.plt.reserved(12) + 4 = 0x3010 // 0x3000 + got.plt.reserved(12) + 4 = 0x3010
// CHECKSHARED: Relocations [ // CHECKSHARED: Relocations [
// CHECKSHARED-NEXT: Section ({{.*}}) .rel.plt { // CHECKSHARED-NEXT: Section ({{.*}}) .rel.plt {
// CHECKSHARED-NEXT: 0x329C R_386_JUMP_SLOT bar 0x0 // CHECKSHARED-NEXT: 0x329C R_386_JUMP_SLOT bar 0x0
// CHECKSHARED-NEXT: 0x32A0 R_386_JUMP_SLOT zed 0x0 // CHECKSHARED-NEXT: 0x32A0 R_386_JUMP_SLOT zed 0x0
// CHECKSHARED-NEXT: } // CHECKSHARED-NEXT: }
// CHECKSHARED-NEXT: ] // CHECKSHARED-NEXT: ]
// DISASMSHARED: local: // DISASMSHARED: <local>:
// DISASMSHARED-NEXT: 11e0: // DISASMSHARED-NEXT: 11e0:
// DISASMSHARED-NEXT: 11e2: // DISASMSHARED-NEXT: 11e2:
// DISASMSHARED: _start: // DISASMSHARED: <_start>:
// DISASMSHARED-NEXT: 11e4: jmp 39 <bar@plt> // DISASMSHARED-NEXT: 11e4: jmp 39 <bar@plt>
// DISASMSHARED-NEXT: jmp 34 <bar@plt> // DISASMSHARED-NEXT: jmp 34 <bar@plt>
// DISASMSHARED-NEXT: jmp 45 <zed@plt> // DISASMSHARED-NEXT: jmp 45 <zed@plt>
// DISASMSHARED-NEXT: jmp -24 <local> // DISASMSHARED-NEXT: jmp -24 <local>
// DISASMSHARED-EMPTY: // DISASMSHARED-EMPTY:
// DISASMSHARED-NEXT: Disassembly of section .plt: // DISASMSHARED-NEXT: Disassembly of section .plt:
// DISASMSHARED-EMPTY: // DISASMSHARED-EMPTY:
// DISASMSHARED-NEXT: .plt: // DISASMSHARED-NEXT: <.plt>:
// DISASMSHARED-NEXT: 1200: pushl 4(%ebx) // DISASMSHARED-NEXT: 1200: pushl 4(%ebx)
// DISASMSHARED-NEXT: jmpl *8(%ebx) // DISASMSHARED-NEXT: jmpl *8(%ebx)
// DISASMSHARED-NEXT: nop // DISASMSHARED-NEXT: nop
// DISASMSHARED-NEXT: nop // DISASMSHARED-NEXT: nop
// DISASMSHARED-NEXT: nop // DISASMSHARED-NEXT: nop
// DISASMSHARED-NEXT: nop // DISASMSHARED-NEXT: nop
// DISASMSHARED: bar@plt: // DISASMSHARED: <bar@plt>:
// DISASMSHARED-NEXT: 1210: jmpl *12(%ebx) // DISASMSHARED-NEXT: 1210: jmpl *12(%ebx)
// DISASMSHARED-NEXT: pushl $0 // DISASMSHARED-NEXT: pushl $0
// DISASMSHARED-NEXT: jmp -32 <.plt> // DISASMSHARED-NEXT: jmp -32 <.plt>
// DISASMSHARED: zed@plt: // DISASMSHARED: <zed@plt>:
// DISASMSHARED-NEXT: 1220: jmpl *16(%ebx) // DISASMSHARED-NEXT: 1220: jmpl *16(%ebx)
// DISASMSHARED-NEXT: pushl $8 // DISASMSHARED-NEXT: pushl $8
// DISASMSHARED-NEXT: jmp -48 <.plt> // DISASMSHARED-NEXT: jmp -48 <.plt>
// DISASMPIE: Disassembly of section .plt: // DISASMPIE: Disassembly of section .plt:
// DISASMPIE-EMPTY: // DISASMPIE-EMPTY:
// DISASMPIE-NEXT: .plt: // DISASMPIE-NEXT: <.plt>:
// DISASMPIE-NEXT: 11e0: pushl 4(%ebx) // DISASMPIE-NEXT: 11e0: pushl 4(%ebx)
// DISASMPIE-NEXT: jmpl *8(%ebx) // DISASMPIE-NEXT: jmpl *8(%ebx)
// DISASMPIE-NEXT: nop // DISASMPIE-NEXT: nop
// DISASMPIE-NEXT: nop // DISASMPIE-NEXT: nop
// DISASMPIE-NEXT: nop // DISASMPIE-NEXT: nop
// DISASMPIE-NEXT: nop // DISASMPIE-NEXT: nop
// DISASMPIE-EMPTY: // DISASMPIE-EMPTY:
// DISASMPIE-NEXT: bar@plt: // DISASMPIE-NEXT: <bar@plt>:
// DISASMPIE-NEXT: 11f0: jmpl *12(%ebx) // DISASMPIE-NEXT: 11f0: jmpl *12(%ebx)
// DISASMPIE-NEXT: pushl $0 // DISASMPIE-NEXT: pushl $0
// DISASMPIE-NEXT: jmp -32 <.plt> // DISASMPIE-NEXT: jmp -32 <.plt>
// DISASMPIE-EMPTY: // DISASMPIE-EMPTY:
// DISASMPIE-NEXT: zed@plt: // DISASMPIE-NEXT: <zed@plt>:
// DISASMPIE-NEXT: 1200: jmpl *16(%ebx) // DISASMPIE-NEXT: 1200: jmpl *16(%ebx)
// DISASMPIE-NEXT: pushl $8 // DISASMPIE-NEXT: pushl $8
// DISASMPIE-NEXT: jmp -48 <.plt> // DISASMPIE-NEXT: jmp -48 <.plt>
local: local:
.long 0 .long 0
.global _start .global _start
_start: _start:
jmp bar@PLT jmp bar@PLT
jmp bar@PLT jmp bar@PLT
jmp zed@PLT jmp zed@PLT
jmp local@plt jmp local@plt

lld/test/ELF/i386-relax-reloc.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=i686-pc-linux %s -o %t.o -relax-relocations // RUN: llvm-mc -filetype=obj -triple=i686-pc-linux %s -o %t.o -relax-relocations
// RUN: ld.lld -shared %t.o -o %t.so // RUN: ld.lld -shared %t.o -o %t.so
// RUN: llvm-readelf -S %t.so | FileCheck --check-prefix=SEC %s // RUN: llvm-readelf -S %t.so | FileCheck --check-prefix=SEC %s
// RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s // RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s
// SEC: .got PROGBITS 000021f0 // SEC: .got PROGBITS 000021f0
// SEC-NEXT: .got.plt PROGBITS 000031f4 // SEC-NEXT: .got.plt PROGBITS 000031f4
// CHECK: foo: // CHECK: <foo>:
// CHECK-NEXT: 1194: movl -4100(%ebx), %eax // CHECK-NEXT: 1194: movl -4100(%ebx), %eax
// CHECK-NEXT: movl -4092(%ebx), %eax // CHECK-NEXT: movl -4092(%ebx), %eax
foo: foo:
movl bar@GOT(%ebx), %eax movl bar@GOT(%ebx), %eax
movl bar+8@GOT(%ebx), %eax movl bar+8@GOT(%ebx), %eax

lld/test/ELF/i386-reloc-large-addend.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc %s -o %t.o -triple i386-pc-linux-code16 -filetype=obj // RUN: llvm-mc %s -o %t.o -triple i386-pc-linux-code16 -filetype=obj
// RUN: echo ".global foo; foo = 0x1" > %t1.s // RUN: echo ".global foo; foo = 0x1" > %t1.s
// RUN: llvm-mc %t1.s -o %t1.o -triple i386-pc-linux -filetype=obj // RUN: llvm-mc %t1.s -o %t1.o -triple i386-pc-linux -filetype=obj
// RUN: ld.lld -Ttext 0x7000 %t.o %t1.o -o %t // RUN: ld.lld -Ttext 0x7000 %t.o %t1.o -o %t
// RUN: llvm-objdump -d -triple=i386-pc-linux-code16 %t | FileCheck %s // RUN: llvm-objdump -d -triple=i386-pc-linux-code16 %t | FileCheck %s
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 7000: e9 fe 1f jmp 8190 // CHECK-NEXT: 7000: e9 fe 1f jmp 8190
// 0x1 + 0x9000 - 0x7003 == 8190 // 0x1 + 0x9000 - 0x7003 == 8190
.global _start .global _start
_start: _start:
jmp foo + 0x9000 jmp foo + 0x9000

lld/test/ELF/i386-reloc-range.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc %s -o %t.o -triple i386-pc-linux-code16 -filetype=obj // RUN: llvm-mc %s -o %t.o -triple i386-pc-linux-code16 -filetype=obj
// RUN: echo ".global foo; foo = 0x10202" > %t1.s // RUN: echo ".global foo; foo = 0x10202" > %t1.s
// RUN: llvm-mc %t1.s -o %t1.o -triple i386-pc-linux -filetype=obj // RUN: llvm-mc %t1.s -o %t1.o -triple i386-pc-linux -filetype=obj
// RUN: echo ".global foo; foo = 0x10203" > %t2.s // RUN: echo ".global foo; foo = 0x10203" > %t2.s
// RUN: llvm-mc %t2.s -o %t2.o -triple i386-pc-linux -filetype=obj // RUN: llvm-mc %t2.s -o %t2.o -triple i386-pc-linux -filetype=obj
// RUN: ld.lld -Ttext 0x200 %t.o %t1.o -o %t1 // RUN: ld.lld -Ttext 0x200 %t.o %t1.o -o %t1
// RUN: llvm-objdump -d --no-show-raw-insn -triple=i386-pc-linux-code16 %t1 | FileCheck %s // RUN: llvm-objdump -d --no-show-raw-insn -triple=i386-pc-linux-code16 %t1 | FileCheck %s
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 200: jmp -1 // CHECK-NEXT: 200: jmp -1
// 0x10202 - 0x203 == 0xffff // 0x10202 - 0x203 == 0xffff
// RUN: not ld.lld -Ttext 0x200 %t.o %t2.o -o /dev/null 2>&1 | FileCheck --check-prefix=ERR %s // RUN: not ld.lld -Ttext 0x200 %t.o %t2.o -o /dev/null 2>&1 | FileCheck --check-prefix=ERR %s
// ERR: {{.*}}:(.text+0x1): relocation R_386_PC16 out of range: 65536 is not in [-65536, 65535]; references foo // ERR: {{.*}}:(.text+0x1): relocation R_386_PC16 out of range: 65536 is not in [-65536, 65535]; references foo
.global _start .global _start
_start: _start:
jmp foo jmp foo

lld/test/ELF/i386-retpoline-nopic-linkerscript.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux %s -o %t1.o
// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux %p/Inputs/shared.s -o %t2.o // RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux %p/Inputs/shared.s -o %t2.o
// RUN: ld.lld -shared -soname=t2.so %t2.o -o %t2.so // RUN: ld.lld -shared -soname=t2.so %t2.o -o %t2.so
// RUN: echo "SECTIONS { \ // RUN: echo "SECTIONS { \
// RUN: .text : { *(.text) } \ // RUN: .text : { *(.text) } \
// RUN: .plt : { *(.plt) } \ // RUN: .plt : { *(.plt) } \
// RUN: .got.plt : { *(.got.plt) } \ // RUN: .got.plt : { *(.got.plt) } \
// RUN: .dynstr : { *(.dynstr) } \ // RUN: .dynstr : { *(.dynstr) } \
// RUN: }" > %t.script // RUN: }" > %t.script
// RUN: ld.lld %t1.o %t2.so -o %t.exe -z retpolineplt --script %t.script // RUN: ld.lld %t1.o %t2.so -o %t.exe -z retpolineplt --script %t.script
// RUN: llvm-objdump -d -s --no-show-raw-insn %t.exe | FileCheck %s // RUN: llvm-objdump -d -s --no-show-raw-insn %t.exe | FileCheck %s
// CHECK: Disassembly of section .plt: // CHECK: Disassembly of section .plt:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: .plt: // CHECK-NEXT: <.plt>:
// CHECK-NEXT: 10: pushl 236 // CHECK-NEXT: 10: pushl 236
// CHECK-NEXT: 16: pushl %eax // CHECK-NEXT: 16: pushl %eax
// CHECK-NEXT: 17: movl 240, %eax // CHECK-NEXT: 17: movl 240, %eax
// CHECK-NEXT: 1c: calll 15 <.plt+0x20> // CHECK-NEXT: 1c: calll 15 <.plt+0x20>
// CHECK-NEXT: 21: pause // CHECK-NEXT: 21: pause
// CHECK-NEXT: 23: lfence // CHECK-NEXT: 23: lfence
// CHECK-NEXT: 26: jmp -7 <.plt+0x11> // CHECK-NEXT: 26: jmp -7 <.plt+0x11>
// CHECK-NEXT: 28: int3 // CHECK-NEXT: 28: int3
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lld/test/ELF/i386-retpoline-nopic.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux %s -o %t1.o
// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux %p/Inputs/shared.s -o %t2.o // RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux %p/Inputs/shared.s -o %t2.o
// RUN: ld.lld -shared -soname=t2.so %t2.o -o %t2.so // RUN: ld.lld -shared -soname=t2.so %t2.o -o %t2.so
// RUN: ld.lld %t1.o %t2.so -o %t.exe -z retpolineplt // RUN: ld.lld %t1.o %t2.so -o %t.exe -z retpolineplt
// RUN: llvm-objdump -d -s --no-show-raw-insn %t.exe | FileCheck %s // RUN: llvm-objdump -d -s --no-show-raw-insn %t.exe | FileCheck %s
// CHECK: Contents of section .got.plt: // CHECK: Contents of section .got.plt:
// CHECK-NEXT: 40224000 00000000 00000000 10124000 // CHECK-NEXT: 40224000 00000000 00000000 10124000
// CHECK-NEXT: 30124000 // CHECK-NEXT: 30124000
// CHECK: Disassembly of section .plt: // CHECK: Disassembly of section .plt:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: .plt: // CHECK-NEXT: <.plt>:
// CHECK-NEXT: 4011d0: pushl 4207276 // CHECK-NEXT: 4011d0: pushl 4207276
// CHECK-NEXT: 4011d6: pushl %eax // CHECK-NEXT: 4011d6: pushl %eax
// CHECK-NEXT: 4011d7: movl 4207280, %eax // CHECK-NEXT: 4011d7: movl 4207280, %eax
// CHECK-NEXT: 4011dc: calll 15 <.plt+0x20> // CHECK-NEXT: 4011dc: calll 15 <.plt+0x20>
// CHECK-NEXT: 4011e1: pause // CHECK-NEXT: 4011e1: pause
// CHECK-NEXT: 4011e3: lfence // CHECK-NEXT: 4011e3: lfence
// CHECK-NEXT: 4011e6: jmp -7 <.plt+0x11> // CHECK-NEXT: 4011e6: jmp -7 <.plt+0x11>
// CHECK-NEXT: 4011e8: int3 // CHECK-NEXT: 4011e8: int3
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lld/test/ELF/i386-retpoline-pic-linkerscript.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux -position-independent %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux -position-independent %s -o %t1.o
// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux -position-independent %p/Inputs/shared.s -o %t2.o // RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux -position-independent %p/Inputs/shared.s -o %t2.o
// RUN: ld.lld -shared %t2.o -o %t2.so // RUN: ld.lld -shared %t2.o -o %t2.so
// RUN: echo "SECTIONS { \ // RUN: echo "SECTIONS { \
// RUN: .text : { *(.text) } \ // RUN: .text : { *(.text) } \
// RUN: .plt : { *(.plt) } \ // RUN: .plt : { *(.plt) } \
// RUN: .got.plt : { *(.got.plt) } \ // RUN: .got.plt : { *(.got.plt) } \
// RUN: .dynstr : { *(.dynstr) } \ // RUN: .dynstr : { *(.dynstr) } \
// RUN: }" > %t.script // RUN: }" > %t.script
// RUN: ld.lld %t1.o %t2.so -o %t.exe -z retpolineplt -pie --script %t.script // RUN: ld.lld %t1.o %t2.so -o %t.exe -z retpolineplt -pie --script %t.script
// RUN: llvm-objdump -d -s %t.exe | FileCheck %s // RUN: llvm-objdump -d -s %t.exe | FileCheck %s
// CHECK: Disassembly of section .plt: // CHECK: Disassembly of section .plt:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: .plt: // CHECK-NEXT: <.plt>:
// CHECK-NEXT: 10: ff b3 04 00 00 00 pushl 4(%ebx) // CHECK-NEXT: 10: ff b3 04 00 00 00 pushl 4(%ebx)
// CHECK-NEXT: 16: 50 pushl %eax // CHECK-NEXT: 16: 50 pushl %eax
// CHECK-NEXT: 17: 8b 83 08 00 00 00 movl 8(%ebx), %eax // CHECK-NEXT: 17: 8b 83 08 00 00 00 movl 8(%ebx), %eax
// CHECK-NEXT: 1d: e8 0e 00 00 00 calll 14 <.plt+0x20> // CHECK-NEXT: 1d: e8 0e 00 00 00 calll 14 <.plt+0x20>
// CHECK-NEXT: 22: f3 90 pause // CHECK-NEXT: 22: f3 90 pause
// CHECK-NEXT: 24: 0f ae e8 lfence // CHECK-NEXT: 24: 0f ae e8 lfence
// CHECK-NEXT: 27: eb f9 jmp -7 <.plt+0x12> // CHECK-NEXT: 27: eb f9 jmp -7 <.plt+0x12>
// CHECK-NEXT: 29: cc int3 // CHECK-NEXT: 29: cc int3
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lld/test/ELF/i386-retpoline-pic.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux -position-independent %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux -position-independent %s -o %t1.o
// RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux -position-independent %p/Inputs/shared.s -o %t2.o // RUN: llvm-mc -filetype=obj -triple=i386-unknown-linux -position-independent %p/Inputs/shared.s -o %t2.o
// RUN: ld.lld -shared -soname=t2.so %t2.o -o %t2.so // RUN: ld.lld -shared -soname=t2.so %t2.o -o %t2.so
// RUN: ld.lld %t1.o %t2.so -o %t.exe -z retpolineplt -pie // RUN: ld.lld %t1.o %t2.so -o %t.exe -z retpolineplt -pie
// RUN: llvm-objdump -d -s --no-show-raw-insn %t.exe | FileCheck %s // RUN: llvm-objdump -d -s --no-show-raw-insn %t.exe | FileCheck %s
// CHECK: Contents of section .got.plt: // CHECK: Contents of section .got.plt:
// CHECK-NEXT: 32a8 40220000 00000000 00000000 11120000 // CHECK-NEXT: 32a8 40220000 00000000 00000000 11120000
// CHECK-NEXT: 32b8 31120000 // CHECK-NEXT: 32b8 31120000
// CHECK: Disassembly of section .plt: // CHECK: Disassembly of section .plt:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: .plt: // CHECK-NEXT: <.plt>:
// CHECK-NEXT: 11d0: pushl 4(%ebx) // CHECK-NEXT: 11d0: pushl 4(%ebx)
// CHECK-NEXT: 11d6: pushl %eax // CHECK-NEXT: 11d6: pushl %eax
// CHECK-NEXT: 11d7: movl 8(%ebx), %eax // CHECK-NEXT: 11d7: movl 8(%ebx), %eax
// CHECK-NEXT: 11dd: calll 14 <.plt+0x20> // CHECK-NEXT: 11dd: calll 14 <.plt+0x20>
// CHECK-NEXT: 11e2: pause // CHECK-NEXT: 11e2: pause
// CHECK-NEXT: 11e4: lfence // CHECK-NEXT: 11e4: lfence
// CHECK-NEXT: 11e7: jmp -7 <.plt+0x12> // CHECK-NEXT: 11e7: jmp -7 <.plt+0x12>
// CHECK-NEXT: 11e9: int3 // CHECK-NEXT: 11e9: int3
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lld/test/ELF/i386-tls-dynamic.s

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# CHECK-NEXT: 0x2370 R_386_TLS_TPOFF tls0 0x0 # CHECK-NEXT: 0x2370 R_386_TLS_TPOFF tls0 0x0
# CHECK-NEXT: 0x2360 R_386_TLS_DTPMOD32 tls1 0x0 # CHECK-NEXT: 0x2360 R_386_TLS_DTPMOD32 tls1 0x0
# CHECK-NEXT: 0x2364 R_386_TLS_DTPOFF32 tls1 0x0 # CHECK-NEXT: 0x2364 R_386_TLS_DTPOFF32 tls1 0x0
# CHECK-NEXT: 0x2374 R_386_TLS_TPOFF tls1 0x0 # CHECK-NEXT: 0x2374 R_386_TLS_TPOFF tls1 0x0
# CHECK-NEXT: } # CHECK-NEXT: }
# DIS: Disassembly of section .text: # DIS: Disassembly of section .text:
# DIS-EMPTY: # DIS-EMPTY:
# DIS-NEXT: _start: # DIS-NEXT: <_start>:
## General dynamic model: ## General dynamic model:
## -4128 and -4120 are first and second GOT entries offsets. ## -4128 and -4120 are first and second GOT entries offsets.
## Each one is a pair of records. ## Each one is a pair of records.
# DIS-NEXT: 1260: leal -4128(,%ebx), %eax # DIS-NEXT: 1260: leal -4128(,%ebx), %eax
# DIS-NEXT: 1267: calll 100 # DIS-NEXT: 1267: calll 100
# DIS-NEXT: 126c: leal -4120(,%ebx), %eax # DIS-NEXT: 126c: leal -4120(,%ebx), %eax
# DIS-NEXT: 1273: calll 88 # DIS-NEXT: 1273: calll 88
## Local dynamic model: ## Local dynamic model:
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lld/test/ELF/i386-tls-gdiele.s

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// NORELOC-NEXT: Section ({{.*}}) .rel.dyn { // NORELOC-NEXT: Section ({{.*}}) .rel.dyn {
// NORELOC-NEXT: 0x402258 R_386_TLS_TPOFF tlsshared0 0x0 // NORELOC-NEXT: 0x402258 R_386_TLS_TPOFF tlsshared0 0x0
// NORELOC-NEXT: 0x40225C R_386_TLS_TPOFF tlsshared1 0x0 // NORELOC-NEXT: 0x40225C R_386_TLS_TPOFF tlsshared1 0x0
// NORELOC-NEXT: } // NORELOC-NEXT: }
// NORELOC-NEXT: ] // NORELOC-NEXT: ]
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: _start: // DISASM-NEXT: <_start>:
// DISASM-NEXT: 4011d0: movl %gs:0, %eax // DISASM-NEXT: 4011d0: movl %gs:0, %eax
// DISASM-NEXT: addl -4104(%ebx), %eax // DISASM-NEXT: addl -4104(%ebx), %eax
// DISASM-NEXT: movl %gs:0, %eax // DISASM-NEXT: movl %gs:0, %eax
// DISASM-NEXT: addl -4100(%ebx), %eax // DISASM-NEXT: addl -4100(%ebx), %eax
// DISASM-NEXT: movl %gs:0, %eax // DISASM-NEXT: movl %gs:0, %eax
// DISASM-NEXT: subl $8, %eax // DISASM-NEXT: subl $8, %eax
// DISASM-NEXT: movl %gs:0, %eax // DISASM-NEXT: movl %gs:0, %eax
// DISASM-NEXT: subl $4, %eax // DISASM-NEXT: subl $4, %eax
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lld/test/ELF/i386-tls-ie-shared.s

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// GOTRELSHARED-NEXT: 0x3394 R_386_TLS_TPOFF tlsshared1 0x0 // GOTRELSHARED-NEXT: 0x3394 R_386_TLS_TPOFF tlsshared1 0x0
// GOTRELSHARED-NEXT: 0x3388 R_386_TLS_TPOFF tlslocal0 0x0 // GOTRELSHARED-NEXT: 0x3388 R_386_TLS_TPOFF tlslocal0 0x0
// GOTRELSHARED-NEXT: 0x338C R_386_TLS_TPOFF tlslocal1 0x0 // GOTRELSHARED-NEXT: 0x338C R_386_TLS_TPOFF tlslocal1 0x0
// GOTRELSHARED-NEXT: } // GOTRELSHARED-NEXT: }
// GOTRELSHARED-NEXT: ] // GOTRELSHARED-NEXT: ]
// DISASMSHARED: Disassembly of section test: // DISASMSHARED: Disassembly of section test:
// DISASMSHARED-EMPTY: // DISASMSHARED-EMPTY:
// DISASMSHARED-NEXT: _start: // DISASMSHARED-NEXT: <_start>:
// (.got)[0] = 0x3388 = 13192 // (.got)[0] = 0x3388 = 13192
// (.got)[1] = 13196 // (.got)[1] = 13196
// (.got)[2] = 13200 // (.got)[2] = 13200
// (.got)[3] = 13204 // (.got)[3] = 13204
// DISASMSHARED-NEXT: 22d8: movl 13192, %ecx // DISASMSHARED-NEXT: 22d8: movl 13192, %ecx
// DISASMSHARED-NEXT: 22de: movl %gs:(%ecx), %eax // DISASMSHARED-NEXT: 22de: movl %gs:(%ecx), %eax
// DISASMSHARED-NEXT: 22e1: movl 13192, %eax // DISASMSHARED-NEXT: 22e1: movl 13192, %eax
// DISASMSHARED-NEXT: 22e6: movl %gs:(%eax), %eax // DISASMSHARED-NEXT: 22e6: movl %gs:(%eax), %eax
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lld/test/ELF/i386-tls-le.s

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movl %gs:0, %ecx movl %gs:0, %ecx
leal var@ntpoff(%ecx), %eax leal var@ntpoff(%ecx), %eax
movl %gs:0, %ecx movl %gs:0, %ecx
leal var1@ntpoff+123(%ecx), %eax leal var1@ntpoff+123(%ecx), %eax
# DIS: Disassembly of section test: # DIS: Disassembly of section test:
# DIS-EMPTY: # DIS-EMPTY:
# DIS-NEXT: _start: # DIS-NEXT: <_start>:
# DIS-NEXT: 402134: movl $8, %edx # DIS-NEXT: 402134: movl $8, %edx
# DIS-NEXT: 402139: movl %gs:0, %ecx # DIS-NEXT: 402139: movl %gs:0, %ecx
# DIS-NEXT: 402140: subl %edx, %eax # DIS-NEXT: 402140: subl %edx, %eax
# DIS-NEXT: 402142: movl $4, %edx # DIS-NEXT: 402142: movl $4, %edx
# DIS-NEXT: 402147: movl %gs:0, %ecx # DIS-NEXT: 402147: movl %gs:0, %ecx
# DIS-NEXT: 40214e: subl %edx, %eax # DIS-NEXT: 40214e: subl %edx, %eax
# DIS-NEXT: 402150: movl %gs:0, %ecx # DIS-NEXT: 402150: movl %gs:0, %ecx
# DIS-NEXT: 402157: leal -8(%ecx), %eax # DIS-NEXT: 402157: leal -8(%ecx), %eax
# DIS-NEXT: 40215d: movl %gs:0, %ecx # DIS-NEXT: 40215d: movl %gs:0, %ecx
# DIS-NEXT: 402164: leal 119(%ecx), %eax # DIS-NEXT: 402164: leal 119(%ecx), %eax
# RELOC: Relocations [ # RELOC: Relocations [
# RELOC-NEXT: ] # RELOC-NEXT: ]
# DISSHARED: Disassembly of section test: # DISSHARED: Disassembly of section test:
# DISSHARED-EMPTY: # DISSHARED-EMPTY:
# DISSHARED-NEXT: _start: # DISSHARED-NEXT: <_start>:
# DISSHARED-NEXT: 2218: movl $0, %edx # DISSHARED-NEXT: 2218: movl $0, %edx
# DISSHARED-NEXT: 221d: movl %gs:0, %ecx # DISSHARED-NEXT: 221d: movl %gs:0, %ecx
# DISSHARED-NEXT: 2224: subl %edx, %eax # DISSHARED-NEXT: 2224: subl %edx, %eax
# DISSHARED-NEXT: 2226: movl $0, %edx # DISSHARED-NEXT: 2226: movl $0, %edx
# DISSHARED-NEXT: 222b: movl %gs:0, %ecx # DISSHARED-NEXT: 222b: movl %gs:0, %ecx
# DISSHARED-NEXT: 2232: subl %edx, %eax # DISSHARED-NEXT: 2232: subl %edx, %eax
# DISSHARED-NEXT: 2234: movl %gs:0, %ecx # DISSHARED-NEXT: 2234: movl %gs:0, %ecx
# DISSHARED-NEXT: 223b: leal (%ecx), %eax # DISSHARED-NEXT: 223b: leal (%ecx), %eax
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lld/test/ELF/i386-tls-opt-iele-nopic.s

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// GOTREL-NEXT: Section ({{.*}}) .rel.dyn { // GOTREL-NEXT: Section ({{.*}}) .rel.dyn {
// GOTREL-NEXT: 0x402258 R_386_TLS_TPOFF tlsshared0 0x0 // GOTREL-NEXT: 0x402258 R_386_TLS_TPOFF tlsshared0 0x0
// GOTREL-NEXT: 0x40225C R_386_TLS_TPOFF tlsshared1 0x0 // GOTREL-NEXT: 0x40225C R_386_TLS_TPOFF tlsshared1 0x0
// GOTREL-NEXT: } // GOTREL-NEXT: }
// GOTREL-NEXT: ] // GOTREL-NEXT: ]
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: _start: // DISASM-NEXT: <_start>:
// DISASM-NEXT: 4011b0: movl $0xfffffff8, %ecx // DISASM-NEXT: 4011b0: movl $0xfffffff8, %ecx
// DISASM-NEXT: movl %gs:(%ecx), %eax // DISASM-NEXT: movl %gs:(%ecx), %eax
// DISASM-NEXT: movl $0xfffffff8, %eax // DISASM-NEXT: movl $0xfffffff8, %eax
// DISASM-NEXT: movl %gs:(%eax), %eax // DISASM-NEXT: movl %gs:(%eax), %eax
// DISASM-NEXT: addl $0xfffffff8, %ecx // DISASM-NEXT: addl $0xfffffff8, %ecx
// DISASM-NEXT: movl %gs:(%ecx), %eax // DISASM-NEXT: movl %gs:(%ecx), %eax
// DISASM-NEXT: movl $0xfffffffc, %ecx // DISASM-NEXT: movl $0xfffffffc, %ecx
// DISASM-NEXT: movl %gs:(%ecx), %eax // DISASM-NEXT: movl %gs:(%ecx), %eax
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lld/test/ELF/i386-tls-opt.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=i686-pc-linux %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=i686-pc-linux %s -o %t.o
// RUN: ld.lld %t.o -o %t1 // RUN: ld.lld %t.o -o %t1
// RUN: llvm-readobj -r %t1 | FileCheck --check-prefix=NORELOC %s // RUN: llvm-readobj -r %t1 | FileCheck --check-prefix=NORELOC %s
// RUN: llvm-objdump -d %t1 | FileCheck --check-prefix=DISASM %s // RUN: llvm-objdump -d %t1 | FileCheck --check-prefix=DISASM %s
// NORELOC: Relocations [ // NORELOC: Relocations [
// NORELOC-NEXT: ] // NORELOC-NEXT: ]
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: _start: // DISASM-NEXT: <_start>:
// LD -> LE: // LD -> LE:
// DISASM-NEXT: 4010f4: 65 a1 00 00 00 00 movl %gs:0, %eax // DISASM-NEXT: 4010f4: 65 a1 00 00 00 00 movl %gs:0, %eax
// DISASM-NEXT: 4010fa: 90 nop // DISASM-NEXT: 4010fa: 90 nop
// DISASM-NEXT: 4010fb: 8d 74 26 00 leal (%esi,%eiz), %esi // DISASM-NEXT: 4010fb: 8d 74 26 00 leal (%esi,%eiz), %esi
// DISASM-NEXT: 4010ff: 8d 90 f8 ff ff ff leal -8(%eax), %edx // DISASM-NEXT: 4010ff: 8d 90 f8 ff ff ff leal -8(%eax), %edx
// DISASM-NEXT: 401105: 65 a1 00 00 00 00 movl %gs:0, %eax // DISASM-NEXT: 401105: 65 a1 00 00 00 00 movl %gs:0, %eax
// DISASM-NEXT: 40110b: 90 nop // DISASM-NEXT: 40110b: 90 nop
// DISASM-NEXT: 40110c: 8d 74 26 00 leal (%esi,%eiz), %esi // DISASM-NEXT: 40110c: 8d 74 26 00 leal (%esi,%eiz), %esi
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lld/test/ELF/linkerscript/excludefile.s

# REQUIRES: x86 # REQUIRES: x86
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux \ # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux \
# RUN: %p/Inputs/include.s -o %t2 # RUN: %p/Inputs/include.s -o %t2
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux \ # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux \
# RUN: %p/Inputs/notinclude.s -o %t3.notinclude # RUN: %p/Inputs/notinclude.s -o %t3.notinclude
# RUN: echo "SECTIONS {} " > %t.script # RUN: echo "SECTIONS {} " > %t.script
# RUN: ld.lld -o %t --script %t.script %t1 %t2 %t3.notinclude # RUN: ld.lld -o %t --script %t.script %t1 %t2 %t3.notinclude
# RUN: llvm-objdump -d %t | FileCheck %s # RUN: llvm-objdump -d %t | FileCheck %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: : 48 c7 c0 3c 00 00 00 movq $60, %rax # CHECK-NEXT: : 48 c7 c0 3c 00 00 00 movq $60, %rax
# CHECK-NEXT: : 48 c7 c7 2a 00 00 00 movq $42, %rdi # CHECK-NEXT: : 48 c7 c7 2a 00 00 00 movq $42, %rdi
# CHECK-NEXT: : cc int3 # CHECK-NEXT: : cc int3
# CHECK-NEXT: : cc int3 # CHECK-NEXT: : cc int3
# CHECK: _potato: # CHECK: <_potato>:
# CHECK-NEXT: : 90 nop # CHECK-NEXT: : 90 nop
# CHECK-NEXT: : 90 nop # CHECK-NEXT: : 90 nop
# CHECK-NEXT: : cc int3 # CHECK-NEXT: : cc int3
# CHECK-NEXT: : cc int3 # CHECK-NEXT: : cc int3
# CHECK: tomato: # CHECK: <tomato>:
# CHECK-NEXT: : b8 01 00 00 00 movl $1, %eax # CHECK-NEXT: : b8 01 00 00 00 movl $1, %eax
# RUN: echo "SECTIONS { .patatino : \ # RUN: echo "SECTIONS { .patatino : \
# RUN: { KEEP(*(EXCLUDE_FILE(*notinclude) .text)) } }" \ # RUN: { KEEP(*(EXCLUDE_FILE(*notinclude) .text)) } }" \
# RUN: > %t.script # RUN: > %t.script
# RUN: ld.lld -o %t4 --script %t.script %t1 %t2 %t3.notinclude # RUN: ld.lld -o %t4 --script %t.script %t1 %t2 %t3.notinclude
# RUN: llvm-objdump -d %t4 | FileCheck %s --check-prefix=EXCLUDE # RUN: llvm-objdump -d %t4 | FileCheck %s --check-prefix=EXCLUDE
# EXCLUDE: Disassembly of section .patatino: # EXCLUDE: Disassembly of section .patatino:
# EXCLUDE-EMPTY: # EXCLUDE-EMPTY:
# EXCLUDE: _start: # EXCLUDE: <_start>:
# EXCLUDE-NEXT: : 48 c7 c0 3c 00 00 00 movq $60, %rax # EXCLUDE-NEXT: : 48 c7 c0 3c 00 00 00 movq $60, %rax
# EXCLUDE-NEXT: : 48 c7 c7 2a 00 00 00 movq $42, %rdi # EXCLUDE-NEXT: : 48 c7 c7 2a 00 00 00 movq $42, %rdi
# EXCLUDE-NEXT: : cc int3 # EXCLUDE-NEXT: : cc int3
# EXCLUDE-NEXT: : cc int3 # EXCLUDE-NEXT: : cc int3
# EXCLUDE: _potato: # EXCLUDE: <_potato>:
# EXCLUDE-NEXT: : 90 nop # EXCLUDE-NEXT: : 90 nop
# EXCLUDE-NEXT: : 90 nop # EXCLUDE-NEXT: : 90 nop
# EXCLUDE: Disassembly of section .text: # EXCLUDE: Disassembly of section .text:
# EXCLUDE-EMPTY: # EXCLUDE-EMPTY:
# EXCLUDE: tomato: # EXCLUDE: <tomato>:
# EXCLUDE-NEXT: : b8 01 00 00 00 movl $1, %eax # EXCLUDE-NEXT: : b8 01 00 00 00 movl $1, %eax
.section .text .section .text
.globl _start .globl _start
_start: _start:
mov $60, %rax mov $60, %rax
mov $42, %rdi mov $42, %rdi

lld/test/ELF/linkerscript/non-absolute.s

# REQUIRES: x86 # REQUIRES: x86
# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t1.o # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t1.o
# RUN: echo "SECTIONS { A = . - 0x10; B = A + 0x1; }" > %t.script # RUN: echo "SECTIONS { A = . - 0x10; B = A + 0x1; }" > %t.script
# RUN: ld.lld -shared %t1.o --script %t.script -o %t # RUN: ld.lld -shared %t1.o --script %t.script -o %t
# RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=DUMP # RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=DUMP
# RUN: llvm-readobj --symbols %t | FileCheck %s --check-prefix=SYMBOL # RUN: llvm-readobj --symbols %t | FileCheck %s --check-prefix=SYMBOL
# B = A + 0x1 = -0x10 + 0x1 = -0xf -> 0xFFFFFFFFFFFFFFF1 # B = A + 0x1 = -0x10 + 0x1 = -0xf -> 0xFFFFFFFFFFFFFFF1
# B - (0x94+6) = -0xf - (0x94+6) = -169 # B - (0x94+6) = -0xf - (0x94+6) = -169
# DUMP: Disassembly of section .text: # DUMP: Disassembly of section .text:
# DUMP-EMPTY: # DUMP-EMPTY:
# DUMP-NEXT: foo: # DUMP-NEXT: <foo>:
# DUMP-NEXT: 94: {{.*}} -169(%rip), %eax # DUMP-NEXT: 94: {{.*}} -169(%rip), %eax
# SYMBOL: Symbol { # SYMBOL: Symbol {
# SYMBOL: Name: B # SYMBOL: Name: B
# SYMBOL-NEXT: Value: 0xFFFFFFFFFFFFFFF1 # SYMBOL-NEXT: Value: 0xFFFFFFFFFFFFFFF1
# SYMBOL-NEXT: Size: 0 # SYMBOL-NEXT: Size: 0
# SYMBOL-NEXT: Binding: Local # SYMBOL-NEXT: Binding: Local
# SYMBOL-NEXT: Type: None # SYMBOL-NEXT: Type: None
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lld/test/ELF/local-got-pie.s

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.hidden foo .hidden foo
.global foo .global foo
foo: foo:
nop nop
// 0x22C8 - 0x1210 - 5 = 4275 // 0x22C8 - 0x1210 - 5 = 4275
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: _start: // DISASM-NEXT: <_start>:
// DISASM-NEXT: 1210: {{.*}} callq 4275 // DISASM-NEXT: 1210: {{.*}} callq 4275
// DISASM: foo: // DISASM: <foo>:
// DISASM-NEXT: 1215: {{.*}} nop // DISASM-NEXT: 1215: {{.*}} nop
// CHECK: Name: .got // CHECK: Name: .got
// CHECK-NEXT: Type: SHT_PROGBITS // CHECK-NEXT: Type: SHT_PROGBITS
// CHECK-NEXT: Flags [ // CHECK-NEXT: Flags [
// CHECK-NEXT: SHF_ALLOC // CHECK-NEXT: SHF_ALLOC
// CHECK-NEXT: SHF_WRITE // CHECK-NEXT: SHF_WRITE
// CHECK-NEXT: ] // CHECK-NEXT: ]
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lld/test/ELF/local-got-shared.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
// RUN: ld.lld %t.o -o %t -shared // RUN: ld.lld %t.o -o %t -shared
// RUN: llvm-readobj -S -d -r %t | FileCheck %s // RUN: llvm-readobj -S -d -r %t | FileCheck %s
// RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=DISASM %s // RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=DISASM %s
bar: bar:
call foo@gotpcrel call foo@gotpcrel
.hidden foo .hidden foo
.global foo .global foo
foo: foo:
nop nop
// 0x22E0 - 0x1228 - 5 = 4275 // 0x22E0 - 0x1228 - 5 = 4275
// DISASM: bar: // DISASM: <bar>:
// DISASM-NEXT: 1228: callq 4275 // DISASM-NEXT: 1228: callq 4275
// DISASM: foo: // DISASM: <foo>:
// DISASM-NEXT: 122d: nop // DISASM-NEXT: 122d: nop
// CHECK: Name: .got // CHECK: Name: .got
// CHECK-NEXT: Type: SHT_PROGBITS // CHECK-NEXT: Type: SHT_PROGBITS
// CHECK-NEXT: Flags [ // CHECK-NEXT: Flags [
// CHECK-NEXT: SHF_ALLOC // CHECK-NEXT: SHF_ALLOC
// CHECK-NEXT: SHF_WRITE // CHECK-NEXT: SHF_WRITE
// CHECK-NEXT: ] // CHECK-NEXT: ]
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lld/test/ELF/local-got.s

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call foo@gotpcrel call foo@gotpcrel
.global foo .global foo
foo: foo:
nop nop
// 0x202320 - 0x201250 - 5 = 4299 // 0x202320 - 0x201250 - 5 = 4299
// 0x202328 - 0x201255 - 5 = 4302 // 0x202328 - 0x201255 - 5 = 4302
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: 201250: callq 4299 // DISASM-NEXT: 201250: callq 4299
// DISASM-NEXT: 201255: callq 4302 // DISASM-NEXT: 201255: callq 4302
// DISASM: foo: // DISASM: <foo>:
// DISASM-NEXT: 20125a: nop // DISASM-NEXT: 20125a: nop
// CHECK: Name: .got // CHECK: Name: .got
// CHECK-NEXT: Type: SHT_PROGBITS // CHECK-NEXT: Type: SHT_PROGBITS
// CHECK-NEXT: Flags [ // CHECK-NEXT: Flags [
// CHECK-NEXT: SHF_ALLOC // CHECK-NEXT: SHF_ALLOC
// CHECK-NEXT: SHF_WRITE // CHECK-NEXT: SHF_WRITE
// CHECK-NEXT: ] // CHECK-NEXT: ]
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lld/test/ELF/lto/codemodel.ll

; REQUIRES: x86 ; REQUIRES: x86
; RUN: llvm-as %s -o %t.o ; RUN: llvm-as %s -o %t.o
; RUN: ld.lld %t.o -o %ts -mllvm -code-model=small ; RUN: ld.lld %t.o -o %ts -mllvm -code-model=small
; RUN: ld.lld %t.o -o %tl -mllvm -code-model=large ; RUN: ld.lld %t.o -o %tl -mllvm -code-model=large
; RUN: llvm-objdump -d %ts | FileCheck %s --check-prefix=CHECK-SMALL ; RUN: llvm-objdump -d %ts | FileCheck %s --check-prefix=CHECK-SMALL
; RUN: llvm-objdump -d %tl | FileCheck %s --check-prefix=CHECK-LARGE ; RUN: llvm-objdump -d %tl | FileCheck %s --check-prefix=CHECK-LARGE
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
@data = internal constant [0 x i32] [] @data = internal constant [0 x i32] []
define i32* @_start() nounwind readonly { define i32* @_start() nounwind readonly {
entry: entry:
; CHECK-SMALL-LABEL: _start: ; CHECK-SMALL-LABEL: <_start>:
; CHECK-SMALL: movl $2097440, %eax ; CHECK-SMALL: movl $2097440, %eax
; CHECK-LARGE-LABEL: _start: ; CHECK-LARGE-LABEL: <_start>:
; CHECK-LARGE: movabsq $2097440, %rax ; CHECK-LARGE: movabsq $2097440, %rax
ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0) ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0)
} }

lld/test/ELF/lto/defsym.ll

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; RUN: llvm-readelf --symbols %t2.so1.lto.o | FileCheck --check-prefix=OBJ %s ; RUN: llvm-readelf --symbols %t2.so1.lto.o | FileCheck --check-prefix=OBJ %s
; RUN: llvm-objdump -d %t2.so | FileCheck %s ; RUN: llvm-objdump -d %t2.so | FileCheck %s
; OBJ: UND bar2 ; OBJ: UND bar2
; Call to bar2() should not be inlined and should be routed to bar3() ; Call to bar2() should not be inlined and should be routed to bar3()
; Symbol bar3 should not be eliminated ; Symbol bar3 should not be eliminated
; CHECK: foo: ; CHECK: <foo>:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq ; CHECK-NEXT: callq
; CHECK-NEXT: callq{{.*}}<bar3> ; CHECK-NEXT: callq{{.*}}<bar3>
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: jmp ; CHECK-NEXT: jmp
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
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lld/test/ELF/lto/linker-script-symbols-ipo.ll

; REQUIRES: x86 ; REQUIRES: x86
; RUN: llvm-as %s -o %t1.o ; RUN: llvm-as %s -o %t1.o
; RUN: llvm-as %S/Inputs/linker-script-symbols-ipo.ll -o %t2.o ; RUN: llvm-as %S/Inputs/linker-script-symbols-ipo.ll -o %t2.o
; RUN: echo "bar = foo;" > %t.script ; RUN: echo "bar = foo;" > %t.script
;; Check that without linkerscript bar is inlined. ;; Check that without linkerscript bar is inlined.
; RUN: ld.lld %t1.o %t2.o -o %t3 -save-temps ; RUN: ld.lld %t1.o %t2.o -o %t3 -save-temps
; RUN: llvm-objdump -d %t3 | FileCheck %s --check-prefix=IPO ; RUN: llvm-objdump -d %t3 | FileCheck %s --check-prefix=IPO
; IPO: Disassembly of section .text: ; IPO: Disassembly of section .text:
; IPO: _start: ; IPO: <_start>:
; IPO-NEXT: movl $1, %eax ; IPO-NEXT: movl $1, %eax
; IPO-NEXT: retq ; IPO-NEXT: retq
;; Check that LTO does not do IPO for symbols assigned by script. ;; Check that LTO does not do IPO for symbols assigned by script.
; RUN: ld.lld %t1.o %t2.o -o %t4 --script %t.script -save-temps ; RUN: ld.lld %t1.o %t2.o -o %t4 --script %t.script -save-temps
; RUN: llvm-objdump -d %t4 | FileCheck %s --check-prefix=NOIPO ; RUN: llvm-objdump -d %t4 | FileCheck %s --check-prefix=NOIPO
; NOIPO: Disassembly of section .text: ; NOIPO: Disassembly of section .text:
; NOIPO: foo: ; NOIPO: <foo>:
; NOIPO-NEXT: movl $2, %eax ; NOIPO-NEXT: movl $2, %eax
; NOIPO: _start: ; NOIPO: <_start>:
; NOIPO-NEXT: jmp -21 <foo> ; NOIPO-NEXT: jmp -21 <foo>
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define i32 @bar() { define i32 @bar() {
ret i32 1 ret i32 1
} }
define i32 @foo() { define i32 @foo() {
ret i32 2 ret i32 2
} }

lld/test/ELF/lto/weakodr-visibility.ll

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; CHECK-NEXT: Size: ; CHECK-NEXT: Size:
; CHECK-NEXT: Binding: Weak ; CHECK-NEXT: Binding: Weak
; CHECK-NEXT: Type: Function ; CHECK-NEXT: Type: Function
; CHECK-NEXT: Other [ ; CHECK-NEXT: Other [
; CHECK-NEXT: STV_PROTECTED ; CHECK-NEXT: STV_PROTECTED
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK-NEXT: Section: ; CHECK-NEXT: Section:
; CHECK-NEXT: } ; CHECK-NEXT: }
; FIRST: foo: ; FIRST: <foo>:
; FIRST-NEXT: movl $41, %eax ; FIRST-NEXT: movl $41, %eax
; Now swap the files order. ; Now swap the files order.
; RUN: ld.lld %t2.o %t1.o -o %t.so -shared ; RUN: ld.lld %t2.o %t1.o -o %t.so -shared
; RUN: llvm-readobj --symbols %t.so | FileCheck %s ; RUN: llvm-readobj --symbols %t.so | FileCheck %s
; RUN: llvm-objdump -d %t.so | FileCheck %s --check-prefix=SECOND ; RUN: llvm-objdump -d %t.so | FileCheck %s --check-prefix=SECOND
; SECOND: foo: ; SECOND: <foo>:
; SECOND-NEXT: movl $42, %eax ; SECOND-NEXT: movl $42, %eax
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define weak_odr i32 @foo(i8* %this) { define weak_odr i32 @foo(i8* %this) {
ret i32 41 ret i32 41
} }

lld/test/ELF/lto/wrap-2.ll

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; RUN: opt -module-summary %S/Inputs/wrap-bar.ll -o %t1.o ; RUN: opt -module-summary %S/Inputs/wrap-bar.ll -o %t1.o
; RUN: ld.lld %t.o %t1.o -shared -o %t.so -wrap=bar ; RUN: ld.lld %t.o %t1.o -shared -o %t.so -wrap=bar
; RUN: llvm-objdump -d %t.so | FileCheck %s ; RUN: llvm-objdump -d %t.so | FileCheck %s
; RUN: llvm-readobj --symbols %t.so | FileCheck -check-prefix=BIND %s ; RUN: llvm-readobj --symbols %t.so | FileCheck -check-prefix=BIND %s
; Make sure that calls in foo() are not eliminated and that bar is ; Make sure that calls in foo() are not eliminated and that bar is
; routed to __wrap_bar and __real_bar is routed to bar. ; routed to __wrap_bar and __real_bar is routed to bar.
; CHECK: foo: ; CHECK: <foo>:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq{{.*}}<__wrap_bar> ; CHECK-NEXT: callq{{.*}}<__wrap_bar>
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: jmp{{.*}}<bar> ; CHECK-NEXT: jmp{{.*}}<bar>
; Check that bar and __wrap_bar retain their original binding. ; Check that bar and __wrap_bar retain their original binding.
; BIND: Name: bar ; BIND: Name: bar
; BIND-NEXT: Value: ; BIND-NEXT: Value:
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lld/test/ELF/merge.s

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// CHECK: ] // CHECK: ]
.text .text
.globl _start .globl _start
_start: _start:
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: _start: // DISASM-NEXT: <_start>:
movl .mysec, %eax movl .mysec, %eax
// addr(0x10) = 2097440 // addr(0x10) = 2097440
// DISASM-NEXT: movl 2097440, %eax // DISASM-NEXT: movl 2097440, %eax
movl .mysec+7, %eax movl .mysec+7, %eax
// addr(0x42) + 3 = 2097444 + 3 = 2097447 // addr(0x42) + 3 = 2097444 + 3 = 2097447
// DISASM-NEXT: movl 2097447, %eax // DISASM-NEXT: movl 2097447, %eax
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lld/test/ELF/mips-26-mask.s

# REQUIRES: mips # REQUIRES: mips
# Check reading/writing implicit addend for R_MIPS_26 relocation. # Check reading/writing implicit addend for R_MIPS_26 relocation.
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
# RUN: ld.lld %t.o -o %t.exe # RUN: ld.lld %t.o -o %t.exe
# RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t.exe | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t.exe | FileCheck %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: [[ADDR:[0-9a-f]+]]: jal 0x80[[ADDR]] # CHECK-NEXT: [[ADDR:[0-9a-f]+]]: jal 0x80[[ADDR]]
.text .text
.global __start .global __start
__start: __start:
jal __start+0x8000000 jal __start+0x8000000

lld/test/ELF/mips-26.s

# REQUIRES: mips # REQUIRES: mips
# Check R_MIPS_26 relocation handling. # Check R_MIPS_26 relocation handling.
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t1.o # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t1.o
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \ # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
# RUN: %S/Inputs/mips-dynamic.s -o %t2.o # RUN: %S/Inputs/mips-dynamic.s -o %t2.o
# RUN: ld.lld %t2.o -shared -o %t.so # RUN: ld.lld %t2.o -shared -o %t.so
# RUN: ld.lld %t1.o %t.so -o %t.exe # RUN: ld.lld %t1.o %t.so -o %t.exe
# RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t.exe | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t.exe | FileCheck %s
# RUN: llvm-readobj -S --dynamic-table -r -A %t.exe \ # RUN: llvm-readobj -S --dynamic-table -r -A %t.exe \
# RUN: | FileCheck -check-prefix=REL %s # RUN: | FileCheck -check-prefix=REL %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: bar: # CHECK-NEXT: <bar>:
# CHECK-NEXT: [[BAR:[0-9a-f]+]]: jal 0x[[LOC:[0-9a-f]+]] <loc> # CHECK-NEXT: [[BAR:[0-9a-f]+]]: jal 0x[[LOC:[0-9a-f]+]] <loc>
# CHECK-NEXT: {{.*}}: nop # CHECK-NEXT: {{.*}}: nop
# #
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: {{.*}}: jal 0x[[BAR]] <bar> # CHECK-NEXT: {{.*}}: jal 0x[[BAR]] <bar>
# CHECK-NEXT: {{.*}}: nop # CHECK-NEXT: {{.*}}: nop
# CHECK-NEXT: {{.*}}: jal 0x[[FOO0:[0-9a-f]+]] # CHECK-NEXT: {{.*}}: jal 0x[[FOO0:[0-9a-f]+]]
# ^-- gotplt[foo0] # ^-- gotplt[foo0]
# CHECK-NEXT: {{.*}}: nop # CHECK-NEXT: {{.*}}: nop
# #
# CHECK: loc: # CHECK: <loc>:
# CHECK-NEXT: [[LOC]]: nop # CHECK-NEXT: [[LOC]]: nop
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: Disassembly of section .plt: # CHECK-NEXT: Disassembly of section .plt:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: .plt: # CHECK-NEXT: <.plt>:
# CHECK-NEXT: {{.*}}: lui $gp, 0x3 # CHECK-NEXT: {{.*}}: lui $gp, 0x3
# CHECK-NEXT: {{.*}}: lw $25, {{.*}}($gp) # CHECK-NEXT: {{.*}}: lw $25, {{.*}}($gp)
# CHECK-NEXT: {{.*}}: addiu $gp, $gp, {{.*}} # CHECK-NEXT: {{.*}}: addiu $gp, $gp, {{.*}}
# CHECK-NEXT: {{.*}}: subu $24, $24, $gp # CHECK-NEXT: {{.*}}: subu $24, $24, $gp
# CHECK-NEXT: {{.*}}: move $15, $ra # CHECK-NEXT: {{.*}}: move $15, $ra
# CHECK-NEXT: {{.*}}: srl $24, $24, 0x2 # CHECK-NEXT: {{.*}}: srl $24, $24, 0x2
# CHECK-NEXT: {{.*}}: jalr $25 # CHECK-NEXT: {{.*}}: jalr $25
# CHECK-NEXT: {{.*}}: addiu $24, $24, -0x2 # CHECK-NEXT: {{.*}}: addiu $24, $24, -0x2
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lld/test/ELF/mips-64-disp.s

# REQUIRES: mips # REQUIRES: mips
# Check R_MIPS_GOT_DISP relocations against various kind of symbols. # Check R_MIPS_GOT_DISP relocations against various kind of symbols.
# RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux \ # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux \
# RUN: %p/Inputs/mips-pic.s -o %t.so.o # RUN: %p/Inputs/mips-pic.s -o %t.so.o
# RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux %s -o %t.exe.o # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux %s -o %t.exe.o
# RUN: ld.lld %t.so.o -shared -soname=t.so -o %t.so # RUN: ld.lld %t.so.o -shared -soname=t.so -o %t.so
# RUN: ld.lld %t.exe.o %t.so -o %t.exe # RUN: ld.lld %t.exe.o %t.so -o %t.exe
# RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck %s # RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck %s
# RUN: llvm-readelf -r -s -A %t.exe | FileCheck -check-prefix=GOT %s # RUN: llvm-readelf -r -s -A %t.exe | FileCheck -check-prefix=GOT %s
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: {{.*}}: addiu $2, $2, -32704 # CHECK-NEXT: {{.*}}: addiu $2, $2, -32704
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: b4: # CHECK-NEXT: <b4>:
# CHECK-NEXT: {{.*}}: addiu $2, $2, -32736 # CHECK-NEXT: {{.*}}: addiu $2, $2, -32736
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: b8: # CHECK-NEXT: <b8>:
# CHECK-NEXT: {{.*}}: addiu $2, $2, -32728 # CHECK-NEXT: {{.*}}: addiu $2, $2, -32728
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: b12: # CHECK-NEXT: <b12>:
# CHECK-NEXT: {{.*}}: addiu $2, $2, -32720 # CHECK-NEXT: {{.*}}: addiu $2, $2, -32720
# CHECK-NEXT: {{.*}}: addiu $2, $2, -32712 # CHECK-NEXT: {{.*}}: addiu $2, $2, -32712
# GOT: Symbol table '.symtab' # GOT: Symbol table '.symtab'
# GOT: {{.*}} [[B12:[0-9a-f]+]] {{.*}} b12 # GOT: {{.*}} [[B12:[0-9a-f]+]] {{.*}} b12
# GOT: {{.*}} [[B04:[0-9a-f]+]] {{.*}} b4 # GOT: {{.*}} [[B04:[0-9a-f]+]] {{.*}} b4
# GOT: {{.*}} [[B08:[0-9a-f]+]] {{.*}} b8 # GOT: {{.*}} [[B08:[0-9a-f]+]] {{.*}} b8
# GOT: {{.*}} [[FOO:[0-9a-f]+]] {{.*}} foo # GOT: {{.*}} [[FOO:[0-9a-f]+]] {{.*}} foo
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lld/test/ELF/mips-64-got.s

# REQUIRES: mips # REQUIRES: mips
# Check MIPS N64 ABI GOT relocations # Check MIPS N64 ABI GOT relocations
# RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux \ # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux \
# RUN: %p/Inputs/mips-pic.s -o %t.so.o # RUN: %p/Inputs/mips-pic.s -o %t.so.o
# RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux %s -o %t.exe.o # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux %s -o %t.exe.o
# RUN: echo "SECTIONS { . = 0x30000; .text : { *(.text) } }" > %t.script # RUN: echo "SECTIONS { . = 0x30000; .text : { *(.text) } }" > %t.script
# RUN: ld.lld %t.so.o -shared -soname=t.so -o %t.so # RUN: ld.lld %t.so.o -shared -soname=t.so -o %t.so
# RUN: ld.lld %t.exe.o --script %t.script %t.so -o %t.exe # RUN: ld.lld %t.exe.o --script %t.script %t.so -o %t.exe
# RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck %s # RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck %s
# RUN: llvm-readelf -r -s -A %t.exe | FileCheck -check-prefix=GOT %s # RUN: llvm-readelf -r -s -A %t.exe | FileCheck -check-prefix=GOT %s
# CHECK: {{[0-9a-f]+}}1c8 l .text 0000000000000000 foo # CHECK: {{[0-9a-f]+}}1c8 l .text 0000000000000000 foo
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: {{.*}} ld $2, -32736($gp) # CHECK-NEXT: {{.*}} ld $2, -32736($gp)
# CHECK-NEXT: {{.*}} daddiu $2, $2, 456 # CHECK-NEXT: {{.*}} daddiu $2, $2, 456
# CHECK-NEXT: {{.*}} addiu $2, $2, -32704 # CHECK-NEXT: {{.*}} addiu $2, $2, -32704
# CHECK-NEXT: {{.*}} addiu $2, $2, -32720 # CHECK-NEXT: {{.*}} addiu $2, $2, -32720
# CHECK-NEXT: {{.*}} addiu $2, $2, -32712 # CHECK-NEXT: {{.*}} addiu $2, $2, -32712
# GOT: There are no relocations in this file. # GOT: There are no relocations in this file.
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lld/test/ELF/mips-64-rels.s

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# RUN: llvm-readobj -r %t.exe | FileCheck -check-prefix=REL %s # RUN: llvm-readobj -r %t.exe | FileCheck -check-prefix=REL %s
# CHECK: 0000000000037ff0 l .got 0000000000000000 .hidden _gp # CHECK: 0000000000037ff0 l .got 0000000000000000 .hidden _gp
# CHECK: Contents of section .rodata: # CHECK: Contents of section .rodata:
# CHECK-NEXT: {{[0-9a-f]+}} ffffffff fffe9014 # CHECK-NEXT: {{[0-9a-f]+}} ffffffff fffe9014
# ^-- 0x21004 - 0x37ff0 = 0xfffffffffffe9014 # ^-- 0x21004 - 0x37ff0 = 0xfffffffffffe9014
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: 21000: lui $gp, 0x1 # CHECK-NEXT: 21000: lui $gp, 0x1
# ^-- 0x21000 - 0x37ff0 # ^-- 0x21000 - 0x37ff0
# ^-- 0 - 0xffffffffffff9010 # ^-- 0 - 0xffffffffffff9010
# ^-- %hi(0x16ff0) # ^-- %hi(0x16ff0)
# CHECK: loc: # CHECK: <loc>:
# CHECK-NEXT: 21004: daddiu $gp, $gp, 0x6ff0 # CHECK-NEXT: 21004: daddiu $gp, $gp, 0x6ff0
# ^-- 0x21000 - 0x37ff0 # ^-- 0x21000 - 0x37ff0
# ^-- 0 - 0xfffffffffffe9010 # ^-- 0 - 0xfffffffffffe9010
# ^-- %lo(0x16ff0) # ^-- %lo(0x16ff0)
# REL: Relocations [ # REL: Relocations [
# REL-NEXT: ] # REL-NEXT: ]
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lld/test/ELF/mips-call-hilo.s

# REQUIRES: mips # REQUIRES: mips
# Check R_MIPS_CALL_HI16 / R_MIPS_CALL_LO16 relocations calculation. # Check R_MIPS_CALL_HI16 / R_MIPS_CALL_LO16 relocations calculation.
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
# RUN: ld.lld %t.o -shared -o %t.so # RUN: ld.lld %t.o -shared -o %t.so
# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s
# RUN: llvm-readelf -r -s -A %t.so | FileCheck -check-prefix=GOT %s # RUN: llvm-readelf -r -s -A %t.so | FileCheck -check-prefix=GOT %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: foo: # CHECK-NEXT: <foo>:
# CHECK-NEXT: {{.*}}: lui $2, 0 # CHECK-NEXT: {{.*}}: lui $2, 0
# CHECK-NEXT: {{.*}}: lw $2, -32736($2) # CHECK-NEXT: {{.*}}: lw $2, -32736($2)
# CHECK-NEXT: {{.*}}: lui $2, 0 # CHECK-NEXT: {{.*}}: lui $2, 0
# CHECK-NEXT: {{.*}}: lw $2, -32744($2) # CHECK-NEXT: {{.*}}: lw $2, -32744($2)
# CHECK-NEXT: {{.*}}: lui $2, 0 # CHECK-NEXT: {{.*}}: lui $2, 0
# CHECK-NEXT: {{.*}}: lw $2, -32740($2) # CHECK-NEXT: {{.*}}: lw $2, -32740($2)
# GOT: There are no relocations in this file. # GOT: There are no relocations in this file.
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lld/test/ELF/mips-call16.s

Show All 12 Lines__start:
.globl g1 .globl g1
.type g1,@function .type g1,@function
g1: g1:
nop nop
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __start: # CHECK-NEXT: <__start>:
# CHECK-NEXT: {{.*}}: lw $8, -32744 # CHECK-NEXT: {{.*}}: lw $8, -32744
# GOT: Symbol table '.symtab' # GOT: Symbol table '.symtab'
# GOT: {{.*}}: [[G1:[0-9a-f]+]] {{.*}} g1 # GOT: {{.*}}: [[G1:[0-9a-f]+]] {{.*}} g1
# GOT: Primary GOT: # GOT: Primary GOT:
# GOT: Global entries: # GOT: Global entries:
# GOT: {{.*}} -32744(gp) [[G1]] [[G1]] FUNC 7 g1 # GOT: {{.*}} -32744(gp) [[G1]] [[G1]] FUNC 7 g1

lld/test/ELF/mips-got-hilo.s

# REQUIRES: mips # REQUIRES: mips
# Check R_MIPS_GOT_HI16 / R_MIPS_GOT_LO16 relocations calculation. # Check R_MIPS_GOT_HI16 / R_MIPS_GOT_LO16 relocations calculation.
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
# RUN: ld.lld %t.o -shared -o %t.so # RUN: ld.lld %t.o -shared -o %t.so
# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s
# RUN: llvm-readelf -r -s -A %t.so | FileCheck -check-prefix=GOT %s # RUN: llvm-readelf -r -s -A %t.so | FileCheck -check-prefix=GOT %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: foo: # CHECK-NEXT: <foo>:
# CHECK-NEXT: {{.*}}: lui $2, 0 # CHECK-NEXT: {{.*}}: lui $2, 0
# CHECK-NEXT: {{.*}}: lw $2, -32736($2) # CHECK-NEXT: {{.*}}: lw $2, -32736($2)
# CHECK-NEXT: {{.*}}: lui $2, 0 # CHECK-NEXT: {{.*}}: lui $2, 0
# CHECK-NEXT: {{.*}}: lw $2, -32744($2) # CHECK-NEXT: {{.*}}: lw $2, -32744($2)
# CHECK-NEXT: {{.*}}: lui $2, 0 # CHECK-NEXT: {{.*}}: lui $2, 0
# CHECK-NEXT: {{.*}}: lw $2, -32740($2) # CHECK-NEXT: {{.*}}: lw $2, -32740($2)
# GOT: There are no relocations in this file # GOT: There are no relocations in this file
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lld/test/ELF/mips-got16-relocatable.s

# REQUIRES: mips # REQUIRES: mips
# Check writing updated addend for R_MIPS_GOT16 relocation, # Check writing updated addend for R_MIPS_GOT16 relocation,
# when produce a relocatable output. # when produce a relocatable output.
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux -o %t.o %s # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux -o %t.o %s
# RUN: ld.lld -r -o %t %t.o %t.o # RUN: ld.lld -r -o %t %t.o %t.o
# RUN: llvm-objdump -d -r --no-show-raw-insn %t | FileCheck -check-prefix=OBJ %s # RUN: llvm-objdump -d -r --no-show-raw-insn %t | FileCheck -check-prefix=OBJ %s
# RUN: ld.lld -shared -o %t.so %t # RUN: ld.lld -shared -o %t.so %t
# RUN: llvm-objdump -d -t --print-imm-hex --no-show-raw-insn %t.so \ # RUN: llvm-objdump -d -t --print-imm-hex --no-show-raw-insn %t.so \
# RUN: | FileCheck -check-prefix=SO %s # RUN: | FileCheck -check-prefix=SO %s
# OBJ: Disassembly of section .text: # OBJ: Disassembly of section .text:
# OBJ-EMPTY: # OBJ-EMPTY:
# OBJ-NEXT: .text: # OBJ-NEXT: <.text>:
# OBJ-NEXT: lw $25, 0($gp) # OBJ-NEXT: lw $25, 0($gp)
# OBJ-NEXT: 00000000: R_MIPS_GOT16 .data # OBJ-NEXT: 00000000: R_MIPS_GOT16 .data
# OBJ-NEXT: addiu $4, $25, 0 # OBJ-NEXT: addiu $4, $25, 0
# OBJ-NEXT: 00000004: R_MIPS_LO16 .data # OBJ-NEXT: 00000004: R_MIPS_LO16 .data
# OBJ: lw $25, 0($gp) # OBJ: lw $25, 0($gp)
# OBJ-NEXT: 00000010: R_MIPS_GOT16 .data # OBJ-NEXT: 00000010: R_MIPS_GOT16 .data
# OBJ-NEXT: addiu $4, $25, 16 # OBJ-NEXT: addiu $4, $25, 16
# OBJ-NEXT: 00000014: R_MIPS_LO16 .data # OBJ-NEXT: 00000014: R_MIPS_LO16 .data
# SO: SYMBOL TABLE # SO: SYMBOL TABLE
# SO: {{0*}}[[D1:[0-9a-f]{1,4}]] l .data {{0+}} data # SO: {{0*}}[[D1:[0-9a-f]{1,4}]] l .data {{0+}} data
# SO: {{0*}}[[D2:[0-9a-f]{1,4}]] l .data {{0+}} data # SO: {{0*}}[[D2:[0-9a-f]{1,4}]] l .data {{0+}} data
# SO: Disassembly of section .text: # SO: Disassembly of section .text:
# SO-EMPTY: # SO-EMPTY:
# SO-NEXT: .text: # SO-NEXT: <.text>:
# SO-NEXT: lw $25, -0x7fe8($gp) # SO-NEXT: lw $25, -0x7fe8($gp)
# SO-NEXT: addiu $4, $25, 0x[[D1]] # SO-NEXT: addiu $4, $25, 0x[[D1]]
# SO: lw $25, -0x7fe8($gp) # SO: lw $25, -0x7fe8($gp)
# SO-NEXT: addiu $4, $25, 0x[[D2]] # SO-NEXT: addiu $4, $25, 0x[[D2]]
.text .text
lw $t9, %got(.data)($gp) lw $t9, %got(.data)($gp)
addiu $a0, $t9, %lo(.data) addiu $a0, $t9, %lo(.data)
.data .data
data: data:
.word 0 .word 0

lld/test/ELF/mips-got16.s

# REQUIRES: mips # REQUIRES: mips
# Check R_MIPS_GOT16 relocation calculation. # Check R_MIPS_GOT16 relocation calculation.
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
# RUN: echo "SECTIONS { \ # RUN: echo "SECTIONS { \
# RUN: . = 0x1000; .text ALIGN(0x1000) : { *(.text) } \ # RUN: . = 0x1000; .text ALIGN(0x1000) : { *(.text) } \
# RUN: . = 0x3000; .data : { *(.data) } \ # RUN: . = 0x3000; .data : { *(.data) } \
# RUN: }" > %t.script # RUN: }" > %t.script
# RUN: ld.lld %t.o -shared --script %t.script -o %t.so # RUN: ld.lld %t.o -shared --script %t.script -o %t.so
# RUN: llvm-objdump -d -t --no-show-raw-insn %t.so | FileCheck %s # RUN: llvm-objdump -d -t --no-show-raw-insn %t.so | FileCheck %s
# RUN: llvm-readelf -r -A %t.so | FileCheck -check-prefix=GOT %s # RUN: llvm-readelf -r -A %t.so | FileCheck -check-prefix=GOT %s
# CHECK: SYMBOL TABLE: # CHECK: SYMBOL TABLE:
# CHECK: 00024008 l .data 00000000 .hidden bar # CHECK: 00024008 l .data 00000000 .hidden bar
# CHECK: 00000000 *UND* 00000000 foo # CHECK: 00000000 *UND* 00000000 foo
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: lw $8, -32744($gp) # CHECK-NEXT: lw $8, -32744($gp)
# CHECK-NEXT: addi $8, $8, 8236 # CHECK-NEXT: addi $8, $8, 8236
# CHECK-NEXT: lw $8, -32732($gp) # CHECK-NEXT: lw $8, -32732($gp)
# CHECK-NEXT: addi $8, $8, -16384 # CHECK-NEXT: addi $8, $8, -16384
# CHECK-NEXT: lw $8, -32728($gp) # CHECK-NEXT: lw $8, -32728($gp)
# CHECK-NEXT: addi $8, $8, -16380 # CHECK-NEXT: addi $8, $8, -16380
# CHECK-NEXT: lw $8, -32728($gp) # CHECK-NEXT: lw $8, -32728($gp)
# CHECK-NEXT: addi $8, $8, 16388 # CHECK-NEXT: addi $8, $8, 16388
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

lld/test/ELF/mips-gp-disp.s

Show All 15 Lines
# INT-SO: 00000000 0 NOTYPE LOCAL HIDDEN ABS _gp_disp # INT-SO: 00000000 0 NOTYPE LOCAL HIDDEN ABS _gp_disp
# EXT-SO: 00020000 0 NOTYPE GLOBAL DEFAULT 9 _gp_disp # EXT-SO: 00020000 0 NOTYPE GLOBAL DEFAULT 9 _gp_disp
# DIS: 00037ff0 l .got 00000000 .hidden _gp # DIS: 00037ff0 l .got 00000000 .hidden _gp
# DIS: 00002000 g .text 00000000 __start # DIS: 00002000 g .text 00000000 __start
# DIS: Disassembly of section .text: # DIS: Disassembly of section .text:
# DIS-EMPTY: # DIS-EMPTY:
# DIS-NEXT: __start: # DIS-NEXT: <__start>:
# DIS-NEXT: lui $8, 3 # DIS-NEXT: lui $8, 3
# DIS-NEXT: addi $8, $8, 24560 # DIS-NEXT: addi $8, $8, 24560
# ^-- (_gp - __start) & 0xffff # ^-- (_gp - __start) & 0xffff
# REL: There are no relocations in this file # REL: There are no relocations in this file
.text .text
.globl __start .globl __start
__start: __start:
lui $t0,%hi(_gp_disp) lui $t0,%hi(_gp_disp)
addi $t0,$t0,%lo(_gp_disp) addi $t0,$t0,%lo(_gp_disp)
lw $v0,%call16(_foo)($gp) lw $v0,%call16(_foo)($gp)

lld/test/ELF/mips-gp-local.s

# REQUIRES: mips # REQUIRES: mips
# Check handling of relocations against __gnu_local_gp symbol. # Check handling of relocations against __gnu_local_gp symbol.
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
# RUN: echo "SECTIONS { \ # RUN: echo "SECTIONS { \
# RUN: . = 0x10000; .text ALIGN(0x1000) : { *(.text) } \ # RUN: . = 0x10000; .text ALIGN(0x1000) : { *(.text) } \
# RUN: . = 0x30000; .got : { *(.got) } \ # RUN: . = 0x30000; .got : { *(.got) } \
# RUN: }" > %t.script # RUN: }" > %t.script
# RUN: ld.lld --script %t.script -o %t.exe %t.o # RUN: ld.lld --script %t.script -o %t.exe %t.o
# RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck %s # RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck %s
# CHECK: 00037ff0 l .got 00000000 .hidden _gp # CHECK: 00037ff0 l .got 00000000 .hidden _gp
# CHECK: 00011000 g .text 00000000 __start # CHECK: 00011000 g .text 00000000 __start
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: lui $8, 3 # CHECK-NEXT: lui $8, 3
# CHECK-NEXT: addi $8, $8, 32752 # CHECK-NEXT: addi $8, $8, 32752
.text .text
.globl __start .globl __start
__start: __start:
lui $t0,%hi(__gnu_local_gp) lui $t0,%hi(__gnu_local_gp)
addi $t0,$t0,%lo(__gnu_local_gp) addi $t0,$t0,%lo(__gnu_local_gp)

lld/test/ELF/mips-higher-highest.s

# REQUIRES: mips # REQUIRES: mips
# Check R_MIPS_HIGHER / R_MIPS_HIGHEST relocations calculation. # Check R_MIPS_HIGHER / R_MIPS_HIGHEST relocations calculation.
# RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux %s -o %t1.o # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux %s -o %t1.o
# RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux \ # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux \
# RUN: %S/Inputs/mips-dynamic.s -o %t2.o # RUN: %S/Inputs/mips-dynamic.s -o %t2.o
# RUN: ld.lld %t1.o %t2.o -o %t.exe # RUN: ld.lld %t1.o %t2.o -o %t.exe
# RUN: llvm-objdump -d --no-show-raw-insn %t.exe | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t.exe | FileCheck %s
.global __start .global __start
__start: __start:
lui $6, %highest(_foo+0x300047FFF7FF7) lui $6, %highest(_foo+0x300047FFF7FF7)
daddiu $6, $6, %higher(_foo+0x300047FFF7FF7) daddiu $6, $6, %higher(_foo+0x300047FFF7FF7)
lui $7, %highest(_foo+0x300047FFF7FF8) lui $7, %highest(_foo+0x300047FFF7FF8)
ld $7, %higher (_foo+0x300047FFF7FF8)($7) ld $7, %higher (_foo+0x300047FFF7FF8)($7)
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: lui $6, 3 # CHECK-NEXT: lui $6, 3
# CHECK-NEXT: daddiu $6, $6, 5 # CHECK-NEXT: daddiu $6, $6, 5
# CHECK-NEXT: lui $7, 3 # CHECK-NEXT: lui $7, 3
# CHECK-NEXT: ld $7, 5($7) # CHECK-NEXT: ld $7, 5($7)
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: _foo: # CHECK-NEXT: <_foo>:

lld/test/ELF/mips-hilo-gp-disp.s

Show All 24 Lines
# CHECK: SYMBOL TABLE: # CHECK: SYMBOL TABLE:
# CHECK: 0001100c l .text 00000000 bar # CHECK: 0001100c l .text 00000000 bar
# CHECK: 00037ff0 l .got 00000000 .hidden _gp # CHECK: 00037ff0 l .got 00000000 .hidden _gp
# CHECK: 00011000 g .text 00000000 __start # CHECK: 00011000 g .text 00000000 __start
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __start: # CHECK-NEXT: <__start>:
# CHECK-NEXT: 11000: lui $8, 2 # CHECK-NEXT: 11000: lui $8, 2
# ^-- %hi(0x37ff0-0x11000) # ^-- %hi(0x37ff0-0x11000)
# CHECK-NEXT: 11004: addi $8, $8, 28656 # CHECK-NEXT: 11004: addi $8, $8, 28656
# ^-- %lo(0x37ff0-0x11004+4) # ^-- %lo(0x37ff0-0x11004+4)
# CHECK: bar: # CHECK: <bar>:
# CHECK-NEXT: 1100c: lui $8, 2 # CHECK-NEXT: 1100c: lui $8, 2
# ^-- %hi(0x37ff0-0x1100c) # ^-- %hi(0x37ff0-0x1100c)
# CHECK-NEXT: 11010: addi $8, $8, 28644 # CHECK-NEXT: 11010: addi $8, $8, 28644
# ^-- %lo(0x37ff0-0x11010+4) # ^-- %lo(0x37ff0-0x11010+4)

lld/test/ELF/mips-hilo-hi-only.s

Show All 13 Lines_label:
nop nop
# WARN: can't find matching R_MIPS_LO16 relocation for R_MIPS_HI16 # WARN: can't find matching R_MIPS_LO16 relocation for R_MIPS_HI16
# CHECK: SYMBOL TABLE: # CHECK: SYMBOL TABLE:
# CHECK: 00020{{0*}}[[VAL:[0-9a-f]+]] l .text 00000000 _label # CHECK: 00020{{0*}}[[VAL:[0-9a-f]+]] l .text 00000000 _label
# CHECK: 00020{{.*}} g .text 00000000 __start # CHECK: 00020{{.*}} g .text 00000000 __start
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: lui $8, 0x3 # CHECK-NEXT: lui $8, 0x3
# ^-- %hi(__start) w/o addend # ^-- %hi(__start) w/o addend
# CHECK-NEXT: addi $8, $8, 0x[[VAL]] # CHECK-NEXT: addi $8, $8, 0x[[VAL]]
# ^-- %lo(_label) # ^-- %lo(_label)

lld/test/ELF/mips-hilo.s

Show All 29 Lines
g1: g1:
.word 0 .word 0
# CHECK: SYMBOL TABLE: # CHECK: SYMBOL TABLE:
# CHECK: 0021020 l O .data 00000004 l1 # CHECK: 0021020 l O .data 00000004 l1
# CHECK: 0021000 g .text 00000000 __start # CHECK: 0021000 g .text 00000000 __start
# CHECK: 0021024 g O .data 00000004 g1 # CHECK: 0021024 g O .data 00000004 g1
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: 21000: lui $8, 2 # CHECK-NEXT: 21000: lui $8, 2
# ^-- %hi(__start+4) # ^-- %hi(__start+4)
# CHECK-NEXT: 21004: lui $9, 2 # CHECK-NEXT: 21004: lui $9, 2
# ^-- %hi(g1+8) # ^-- %hi(g1+8)
# CHECK-NEXT: 21008: addi $8, $8, 4100 # CHECK-NEXT: 21008: addi $8, $8, 4100
# ^-- %lo(__start+4) # ^-- %lo(__start+4)
# CHECK-NEXT: 2100c: addi $8, $8, 4140 # CHECK-NEXT: 2100c: addi $8, $8, 4140
# ^-- %lo(g1+8) # ^-- %lo(g1+8)
# CHECK-NEXT: 21010: lui $8, 3 # CHECK-NEXT: 21010: lui $8, 3
# ^-- %hi(l1+0x10000-4) # ^-- %hi(l1+0x10000-4)
# CHECK-NEXT: 21014: lui $9, 4 # CHECK-NEXT: 21014: lui $9, 4
# ^-- %hi(l1+0x20000-4) # ^-- %hi(l1+0x20000-4)
# CHECK-NEXT: 21018: addi $8, $8, 4124 # CHECK-NEXT: 21018: addi $8, $8, 4124
# ^-- %lo(l1-4) # ^-- %lo(l1-4)

lld/test/ELF/mips-jalr-non-functions.s

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Linestls_obj:
.type reg_obj,@object .type reg_obj,@object
.data .data
reg_obj: reg_obj:
.word 0 .word 0
# CHECK-LABEL: Disassembly of section .text: # CHECK-LABEL: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: test: # CHECK-NEXT: <test>:
# CHECK-NEXT: jr $25 # CHECK-NEXT: jr $25
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: jr $25 # CHECK-NEXT: jr $25
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: b 8 <untyped> # CHECK-NEXT: b 8 <untyped>
# CHECK-NEXT: nop # CHECK-NEXT: nop

lld/test/ELF/mips-micro-cross-calls.s

Show All 12 Lines
# RUN: llvm-objdump -d -t -mattr=+micromips \ # RUN: llvm-objdump -d -t -mattr=+micromips \
# RUN: --no-show-raw-insn --print-imm-hex %t-eb.exe \ # RUN: --no-show-raw-insn --print-imm-hex %t-eb.exe \
# RUN: | FileCheck --check-prefixes=SYM,MICRO %s # RUN: | FileCheck --check-prefixes=SYM,MICRO %s
# REG: {{0*}}[[FOOT:[0-9a-f]+]] l F .text 0000000e 0x80 __microLA25Thunk_foo # REG: {{0*}}[[FOOT:[0-9a-f]+]] l F .text 0000000e 0x80 __microLA25Thunk_foo
# REG: {{0*}}[[BAR:[0-9a-f]+]] g F .text 00000000 bar # REG: {{0*}}[[BAR:[0-9a-f]+]] g F .text 00000000 bar
# REG: {{0*}}[[MIC:[0-9a-f]+]] g .text 00000000 0x80 micro # REG: {{0*}}[[MIC:[0-9a-f]+]] g .text 00000000 0x80 micro
# REG: __start: # REG: <__start>:
# REG-NEXT: jalx 0x[[MIC]] <micro> # REG-NEXT: jalx 0x[[MIC]] <micro>
# REG-NEXT: nop # REG-NEXT: nop
# REG-NEXT: jalx 0x[[FOOT]] <__microLA25Thunk_foo> # REG-NEXT: jalx 0x[[FOOT]] <__microLA25Thunk_foo>
# REG: __LA25Thunk_bar: # REG: <__LA25Thunk_bar>:
# REG-NEXT: lui $25, 0x2 # REG-NEXT: lui $25, 0x2
# REG-NEXT: j 0x[[BAR]] <bar> # REG-NEXT: j 0x[[BAR]] <bar>
# MICRO: {{0*}}[[BART:[0-9a-f]+]] l F .text 00000010 __LA25Thunk_bar # MICRO: {{0*}}[[BART:[0-9a-f]+]] l F .text 00000010 __LA25Thunk_bar
# MICRO: {{0*}}[[START:[0-9a-f]+]] g .text 00000000 __start # MICRO: {{0*}}[[START:[0-9a-f]+]] g .text 00000000 __start
# MICRO: {{0*}}[[FOO:[0-9a-f]+]] g F .text 00000000 0x80 foo # MICRO: {{0*}}[[FOO:[0-9a-f]+]] g F .text 00000000 0x80 foo
# MICRO: micro: # MICRO: <micro>:
# MICRO-NEXT: jalx 0x[[START]] # MICRO-NEXT: jalx 0x[[START]]
# MICRO-NEXT: nop # MICRO-NEXT: nop
# MICRO-NEXT: jalx 0x[[BART]] # MICRO-NEXT: jalx 0x[[BART]]
# MICRO: __microLA25Thunk_foo: # MICRO: <__microLA25Thunk_foo>:
# MICRO-NEXT: lui $25, 0x2 # MICRO-NEXT: lui $25, 0x2
# MICRO-NEXT: j 0x[[FOO]] <foo> # MICRO-NEXT: j 0x[[FOO]] <foo>
.text .text
.set nomicromips .set nomicromips
.global __start .global __start
__start: __start:
jal micro jal micro
jal foo jal foo
.set micromips .set micromips
.global micro .global micro
micro: micro:
jal __start jal __start
jal bar jal bar

lld/test/ELF/mips-micro-plt.s

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# CHECK: Address Access Initial # CHECK: Address Access Initial
# CHECK: -32744(gp) 00020211 # CHECK: -32744(gp) 00020211
# CHECK: PLT GOT: # CHECK: PLT GOT:
# CHECK: Entries: # CHECK: Entries:
# CHECK: Address Initial Sym.Val. Type Ndx Name # CHECK: Address Initial Sym.Val. Type Ndx Name
# CHECK: 00020301 00020321 FUNC UND foo0 # CHECK: 00020301 00020321 FUNC UND foo0
# ASM: __start: # ASM: <__start>:
# ASM-NEXT: 20200: lw $8, -32744($gp) # ASM-NEXT: 20200: lw $8, -32744($gp)
# ASM-NEXT: addi $8, $8, 529 # ASM-NEXT: addi $8, $8, 529
# ASM-NEXT: lui $8, 2 # ASM-NEXT: lui $8, 2
# ASM-NEXT: addi $8, $8, 801 # ASM-NEXT: addi $8, $8, 801
# #
# ASM: foo: # ASM: <foo>:
# ASM-NEXT: 20210: jal 131872 # ASM-NEXT: 20210: jal 131872
.text .text
.set micromips .set micromips
.global foo .global foo
.hidden foo .hidden foo
.global __start .global __start
__start: __start:
lw $t0,%got(foo)($gp) lw $t0,%got(foo)($gp)
addi $t0,$t0,%lo(foo) addi $t0,$t0,%lo(foo)
lui $t0,%hi(foo0) lui $t0,%hi(foo0)
addi $t0,$t0,%lo(foo0) addi $t0,$t0,%lo(foo0)
foo: foo:
jal foo0 jal foo0

lld/test/ELF/mips-micro-relocs.s

Show All 35 Lines
# EB-NEXT: 0000 00020111 # EB-NEXT: 0000 00020111
# EL: Contents of section .data: # EL: Contents of section .data:
# EL-NEXT: 30000 1181feff # EL-NEXT: 30000 1181feff
# EL: Contents of section .debug_info # EL: Contents of section .debug_info
# EL-NEXT: 0000 11010200 # EL-NEXT: 0000 11010200
# ASM: __start: # ASM: <__start>:
# ASM-NEXT: 20110: lui $3, 1 # ASM-NEXT: 20110: lui $3, 1
# ASM-NEXT: addiu $3, $3, 32495 # ASM-NEXT: addiu $3, $3, 32495
# ASM-NEXT: lw $3, -32744($gp) # ASM-NEXT: lw $3, -32744($gp)
# ASM-NEXT: lw $3, -32744($3) # ASM-NEXT: lw $3, -32744($3)
# ASM-NEXT: beqz16 $6, -32 # ASM-NEXT: beqz16 $6, -32
# ASM-NEXT: sll $3, $fp, 0 # ASM-NEXT: sll $3, $fp, 0
# ASM-NEXT: b16 -40 # ASM-NEXT: b16 -40
# ASM-NEXT: nop # ASM-NEXT: nop
Show All 23 Lines

lld/test/ELF/mips-micro-thunks.s

Show All 35 Lines
# RUN: -mcpu=mips32r6 -mattr=micromips %s -o %t-el-r6.o # RUN: -mcpu=mips32r6 -mattr=micromips %s -o %t-el-r6.o
# RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \ # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
# RUN: -position-independent -mcpu=mips32r6 -mattr=micromips \ # RUN: -position-independent -mcpu=mips32r6 -mattr=micromips \
# RUN: %S/Inputs/mips-micro.s -o %t-el-pic-r6.o # RUN: %S/Inputs/mips-micro.s -o %t-el-pic-r6.o
# RUN: ld.lld -o %t-el-r6.exe -script %t.script %t-el-r6.o %t-el-pic-r6.o # RUN: ld.lld -o %t-el-r6.exe -script %t.script %t-el-r6.o %t-el-pic-r6.o
# RUN: llvm-objdump -d -mattr=+micromips --no-show-raw-insn %t-el-r6.exe \ # RUN: llvm-objdump -d -mattr=+micromips --no-show-raw-insn %t-el-r6.exe \
# RUN: | FileCheck --check-prefix=R6 %s # RUN: | FileCheck --check-prefix=R6 %s
# R2: __start: # R2: <__start>:
# R2-NEXT: 20100: jal 131336 <__microLA25Thunk_foo> # R2-NEXT: 20100: jal 131336 <__microLA25Thunk_foo>
# R2-NEXT: nop # R2-NEXT: nop
# R2: __microLA25Thunk_foo: # R2: <__microLA25Thunk_foo>:
# R2-NEXT: 20108: lui $25, 2 # R2-NEXT: 20108: lui $25, 2
# R2-NEXT: j 131360 <foo> # R2-NEXT: j 131360 <foo>
# R2-NEXT: addiu $25, $25, 289 # R2-NEXT: addiu $25, $25, 289
# R2-NEXT: nop # R2-NEXT: nop
# R6: __start: # R6: <__start>:
# R6-NEXT: 20100: balc 0 <__start> # R6-NEXT: 20100: balc 0 <__start>
# R6: __microLA25Thunk_foo: # R6: <__microLA25Thunk_foo>:
# R6-NEXT: 20104: lui $25, 2 # R6-NEXT: 20104: lui $25, 2
# R6-NEXT: addiu $25, $25, 273 # R6-NEXT: addiu $25, $25, 273
# R6-NEXT: bc 0 <__microLA25Thunk_foo+0x8> # R6-NEXT: bc 0 <__microLA25Thunk_foo+0x8>
.text .text
.set micromips .set micromips
.global __start .global __start
__start: __start:
jal foo jal foo

lld/test/ELF/mips-micror6-relocs.s

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# RUN: llvm-mc -filetype=obj -triple=mipsel -mcpu=mips32r6 %s -o %t2el.o # RUN: llvm-mc -filetype=obj -triple=mipsel -mcpu=mips32r6 %s -o %t2el.o
# RUN: ld.lld -o %tel.exe -script %t.script %t1el.o %t2el.o # RUN: ld.lld -o %tel.exe -script %t.script %t1el.o %t2el.o
# RUN: llvm-objdump -d -t -mattr=micromips --no-show-raw-insn %tel.exe \ # RUN: llvm-objdump -d -t -mattr=micromips --no-show-raw-insn %tel.exe \
# RUN: | FileCheck %s # RUN: | FileCheck %s
# CHECK: 00020100 g F .text 00000000 0x80 foo # CHECK: 00020100 g F .text 00000000 0x80 foo
# CHECK: 00020110 g .text 00000000 0x80 __start # CHECK: 00020110 g .text 00000000 0x80 __start
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: 20110: lapc $2, -12 # CHECK-NEXT: 20110: lapc $2, -12
# CHECK-NEXT: beqzc $3, -36 # CHECK-NEXT: beqzc $3, -36
# CHECK-NEXT: balc -24 <foo> # CHECK-NEXT: balc -24 <foo>
.text .text
.set micromips .set micromips
.global __start .global __start
__start: __start:
addiupc $2, foo+4 # R_MICROMIPS_PC19_S2 addiupc $2, foo+4 # R_MICROMIPS_PC19_S2
beqzc $3, foo+4 # R_MICROMIPS_PC21_S1 beqzc $3, foo+4 # R_MICROMIPS_PC21_S1
balc foo+4 # R_MICROMIPS_PC26_S1 balc foo+4 # R_MICROMIPS_PC26_S1

lld/test/ELF/mips-n32-rels.s

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# CHECK: 00020100 g F .text 00000000 __start # CHECK: 00020100 g F .text 00000000 __start
# CHECK: Contents of section .rodata: # CHECK: Contents of section .rodata:
# CHECK-NEXT: {{[0-9a-f]+}} ffff8004 # CHECK-NEXT: {{[0-9a-f]+}} ffff8004
# ^-- loc - _gp # ^-- loc - _gp
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __start: # CHECK-NEXT: <__start>:
# CHECK-NEXT: 20100: lui $gp, 1 # CHECK-NEXT: 20100: lui $gp, 1
# ^-- 0x20100 - 0x28100 # ^-- 0x20100 - 0x28100
# ^-- 0 - 0xffff8000 # ^-- 0 - 0xffff8000
# ^-- %hi(0x8000) # ^-- %hi(0x8000)
# CHECK: loc: # CHECK: <loc>:
# CHECK-NEXT: 20104: daddiu $gp, $gp, -32768 # CHECK-NEXT: 20104: daddiu $gp, $gp, -32768
# ^-- 0x20100 - 0x28100 # ^-- 0x20100 - 0x28100
# ^-- 0 - 0xffff8000 # ^-- 0 - 0xffff8000
# ^-- %lo(0x8000) # ^-- %lo(0x8000)
# ELF: Class: ELF32 # ELF: Class: ELF32
# ELF: Data: 2's complement, big endian # ELF: Data: 2's complement, big endian
# ELF: Version: 1 (current) # ELF: Version: 1 (current)
# ELF: OS/ABI: UNIX - System V # ELF: OS/ABI: UNIX - System V
# ELF: ABI Version: 0 # ELF: ABI Version: 0
# ELF: Type: EXEC (Executable file) # ELF: Type: EXEC (Executable file)
# ELF: Machine: MIPS R3000 # ELF: Machine: MIPS R3000
# ELF: Version: 0x1 # ELF: Version: 0x1
# ELF: Entry point address: 0x20100 # ELF: Entry point address: 0x20100
# ELF: Flags: 0x60000026, pic, cpic, abi2, mips64 # ELF: Flags: 0x60000026, pic, cpic, abi2, mips64

lld/test/ELF/mips-npic-call-pic-os.s

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# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \ # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
# RUN: %p/Inputs/mips-pic.s -o %t-pic.o # RUN: %p/Inputs/mips-pic.s -o %t-pic.o
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t-npic.o # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t-npic.o
# RUN: ld.lld %t-npic.o %t-pic.o %t-sto-pic.o -o %t.exe # RUN: ld.lld %t-npic.o %t-pic.o %t-sto-pic.o -o %t.exe
# RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t.exe | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t.exe | FileCheck %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __LA25Thunk_foo1a: # CHECK-NEXT: <__LA25Thunk_foo1a>:
# CHECK-NEXT: lui $25, 0x2 # CHECK-NEXT: lui $25, 0x2
# CHECK-NEXT: j {{.*}} <foo1a> # CHECK-NEXT: j {{.*}} <foo1a>
# CHECK-NEXT: addiu $25, $25, {{.*}} # CHECK-NEXT: addiu $25, $25, {{.*}}
# CHECK: __LA25Thunk_foo1b: # CHECK: <__LA25Thunk_foo1b>:
# CHECK-NEXT: lui $25, 0x2 # CHECK-NEXT: lui $25, 0x2
# CHECK-NEXT: j {{.*}} <foo1b> # CHECK-NEXT: j {{.*}} <foo1b>
# CHECK-NEXT: addiu $25, $25, {{.*}} # CHECK-NEXT: addiu $25, $25, {{.*}}
# CHECK: foo1a: # CHECK: <foo1a>:
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK: foo1b: # CHECK: <foo1b>:
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK: __LA25Thunk_foo2: # CHECK: <__LA25Thunk_foo2>:
# CHECK-NEXT: lui $25, 0x2 # CHECK-NEXT: lui $25, 0x2
# CHECK-NEXT: j {{.*}} <foo2> # CHECK-NEXT: j {{.*}} <foo2>
# CHECK-NEXT: addiu $25, $25, {{.*}} # CHECK-NEXT: addiu $25, $25, {{.*}}
# CHECK: foo2: # CHECK: <foo2>:
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK: __LA25Thunk_fpic: # CHECK: <__LA25Thunk_fpic>:
# CHECK-NEXT: lui $25, 0x2 # CHECK-NEXT: lui $25, 0x2
# CHECK-NEXT: j {{.*}} <fpic> # CHECK-NEXT: j {{.*}} <fpic>
# CHECK-NEXT: addiu $25, $25, {{.*}} # CHECK-NEXT: addiu $25, $25, {{.*}}
# CHECK: fpic: # CHECK: <fpic>:
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK: fnpic: # CHECK: <fnpic>:
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: Disassembly of section .differentos: # CHECK-NEXT: Disassembly of section .differentos:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __start: # CHECK-NEXT: <__start>:
# CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo1a> # CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo1a>
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo2> # CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo2>
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo1b> # CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo1b>
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo2> # CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo2>
# CHECK-NEXT: nop # CHECK-NEXT: nop
Show All 13 Lines

lld/test/ELF/mips-npic-call-pic-script.s

Show All 9 Lines
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \ # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
# RUN: %p/Inputs/mips-pic.s -o %t-pic.o # RUN: %p/Inputs/mips-pic.s -o %t-pic.o
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t-npic.o # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t-npic.o
# RUN: ld.lld --script %t1.script %t-npic.o %t-pic.o %t-sto-pic.o -o %t.exe # RUN: ld.lld --script %t1.script %t-npic.o %t-pic.o %t-sto-pic.o -o %t.exe
# RUN: llvm-objdump -d --no-show-raw-insn %t.exe | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t.exe | FileCheck %s
# CHECK: Disassembly of section .out: # CHECK: Disassembly of section .out:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __LA25Thunk_foo1a: # CHECK-NEXT: <__LA25Thunk_foo1a>:
# CHECK-NEXT: 20000: lui $25, 2 # CHECK-NEXT: 20000: lui $25, 2
# CHECK-NEXT: 20004: j 131104 <foo1a> # CHECK-NEXT: 20004: j 131104 <foo1a>
# CHECK-NEXT: 20008: addiu $25, $25, 32 # CHECK-NEXT: 20008: addiu $25, $25, 32
# CHECK-NEXT: 2000c: nop # CHECK-NEXT: 2000c: nop
# CHECK: __LA25Thunk_foo1b: # CHECK: <__LA25Thunk_foo1b>:
# CHECK-NEXT: 20010: lui $25, 2 # CHECK-NEXT: 20010: lui $25, 2
# CHECK-NEXT: 20014: j 131108 <foo1b> # CHECK-NEXT: 20014: j 131108 <foo1b>
# CHECK-NEXT: 20018: addiu $25, $25, 36 # CHECK-NEXT: 20018: addiu $25, $25, 36
# CHECK-NEXT: 2001c: nop # CHECK-NEXT: 2001c: nop
# CHECK: foo1a: # CHECK: <foo1a>:
# CHECK-NEXT: 20020: nop # CHECK-NEXT: 20020: nop
# CHECK: foo1b: # CHECK: <foo1b>:
# CHECK-NEXT: 20024: nop # CHECK-NEXT: 20024: nop
# CHECK: __LA25Thunk_foo2: # CHECK: <__LA25Thunk_foo2>:
# CHECK-NEXT: 20028: lui $25, 2 # CHECK-NEXT: 20028: lui $25, 2
# CHECK-NEXT: 2002c: j 131136 <foo2> # CHECK-NEXT: 2002c: j 131136 <foo2>
# CHECK-NEXT: 20030: addiu $25, $25, 64 # CHECK-NEXT: 20030: addiu $25, $25, 64
# CHECK-NEXT: 20034: nop # CHECK-NEXT: 20034: nop
# CHECK: foo2: # CHECK: <foo2>:
# CHECK-NEXT: 20040: nop # CHECK-NEXT: 20040: nop
# CHECK: __start: # CHECK: <__start>:
# CHECK-NEXT: 20150: jal 131072 <__LA25Thunk_foo1a> # CHECK-NEXT: 20150: jal 131072 <__LA25Thunk_foo1a>
# CHECK-NEXT: 20154: nop # CHECK-NEXT: 20154: nop
# CHECK-NEXT: 20158: jal 131112 <__LA25Thunk_foo2> # CHECK-NEXT: 20158: jal 131112 <__LA25Thunk_foo2>
# CHECK-NEXT: 2015c: nop # CHECK-NEXT: 2015c: nop
# CHECK-NEXT: 20160: jal 131088 <__LA25Thunk_foo1b> # CHECK-NEXT: 20160: jal 131088 <__LA25Thunk_foo1b>
# CHECK-NEXT: 20164: nop # CHECK-NEXT: 20164: nop
# CHECK-NEXT: 20168: jal 131112 <__LA25Thunk_foo2> # CHECK-NEXT: 20168: jal 131112 <__LA25Thunk_foo2>
# CHECK-NEXT: 2016c: nop # CHECK-NEXT: 2016c: nop
# CHECK-NEXT: 20170: jal 131456 <__LA25Thunk_fpic> # CHECK-NEXT: 20170: jal 131456 <__LA25Thunk_fpic>
# CHECK-NEXT: 20174: nop # CHECK-NEXT: 20174: nop
# CHECK-NEXT: 20178: jal 131488 <fnpic> # CHECK-NEXT: 20178: jal 131488 <fnpic>
# CHECK-NEXT: 2017c: nop # CHECK-NEXT: 2017c: nop
# CHECK: __LA25Thunk_fpic: # CHECK: <__LA25Thunk_fpic>:
# CHECK-NEXT: 20180: lui $25, 2 # CHECK-NEXT: 20180: lui $25, 2
# CHECK-NEXT: 20184: j 131472 <fpic> # CHECK-NEXT: 20184: j 131472 <fpic>
# CHECK-NEXT: 20188: addiu $25, $25, 400 # CHECK-NEXT: 20188: addiu $25, $25, 400
# CHECK-NEXT: 2018c: nop # CHECK-NEXT: 2018c: nop
# CHECK: fpic: # CHECK: <fpic>:
# CHECK-NEXT: 20190: nop # CHECK-NEXT: 20190: nop
# CHECK: fnpic: # CHECK: <fnpic>:
# CHECK-NEXT: 201a0: nop # CHECK-NEXT: 201a0: nop
.text .text
.globl __start .globl __start
__start: __start:
jal foo1a jal foo1a
jal foo2 jal foo2
jal foo1b jal foo1b
jal foo2 jal foo2
jal fpic jal fpic
jal fnpic jal fnpic
# Test script with orphans added to existing OutputSection, the .text.1 and # Test script with orphans added to existing OutputSection, the .text.1 and
# .text.2 sections will be added to .text # .text.2 sections will be added to .text
# RUN: echo "SECTIONS { .text 0x20000 : { *(.text) } }" > %t2.script # RUN: echo "SECTIONS { .text 0x20000 : { *(.text) } }" > %t2.script
# RUN: ld.lld --script %t2.script %t-npic.o %t-pic.o %t-sto-pic.o -o %t2.exe # RUN: ld.lld --script %t2.script %t-npic.o %t-pic.o %t-sto-pic.o -o %t2.exe
# RUN: llvm-objdump -d --no-show-raw-insn %t2.exe | FileCheck -check-prefix=ORPH1 %s # RUN: llvm-objdump -d --no-show-raw-insn %t2.exe | FileCheck -check-prefix=ORPH1 %s
# ORPH1: Disassembly of section .text: # ORPH1: Disassembly of section .text:
# ORPH1-EMPTY: # ORPH1-EMPTY:
# ORPH1-NEXT: __start: # ORPH1-NEXT: <__start>:
# ORPH1-NEXT: 20000: jal 131156 <__LA25Thunk_foo1a> # ORPH1-NEXT: 20000: jal 131156 <__LA25Thunk_foo1a>
# ORPH1-NEXT: 20004: nop # ORPH1-NEXT: 20004: nop
# ORPH1-NEXT: 20008: jal 131208 <__LA25Thunk_foo2> # ORPH1-NEXT: 20008: jal 131208 <__LA25Thunk_foo2>
# ORPH1-NEXT: 2000c: nop # ORPH1-NEXT: 2000c: nop
# ORPH1-NEXT: 20010: jal 131172 <__LA25Thunk_foo1b> # ORPH1-NEXT: 20010: jal 131172 <__LA25Thunk_foo1b>
# ORPH1-NEXT: 20014: nop # ORPH1-NEXT: 20014: nop
# ORPH1-NEXT: 20018: jal 131208 <__LA25Thunk_foo2> # ORPH1-NEXT: 20018: jal 131208 <__LA25Thunk_foo2>
# ORPH1-NEXT: 2001c: nop # ORPH1-NEXT: 2001c: nop
# ORPH1-NEXT: 20020: jal 131120 <__LA25Thunk_fpic> # ORPH1-NEXT: 20020: jal 131120 <__LA25Thunk_fpic>
# ORPH1-NEXT: 20024: nop # ORPH1-NEXT: 20024: nop
# ORPH1-NEXT: 20028: jal 131152 <fnpic> # ORPH1-NEXT: 20028: jal 131152 <fnpic>
# ORPH1-NEXT: 2002c: nop # ORPH1-NEXT: 2002c: nop
# ORPH1: __LA25Thunk_fpic: # ORPH1: <__LA25Thunk_fpic>:
# ORPH1-NEXT: 20030: lui $25, 2 # ORPH1-NEXT: 20030: lui $25, 2
# ORPH1-NEXT: 20034: j 131136 <fpic> # ORPH1-NEXT: 20034: j 131136 <fpic>
# ORPH1-NEXT: 20038: addiu $25, $25, 64 # ORPH1-NEXT: 20038: addiu $25, $25, 64
# ORPH1-NEXT: 2003c: nop # ORPH1-NEXT: 2003c: nop
# ORPH1: fpic: # ORPH1: <fpic>:
# ORPH1-NEXT: 20040: nop # ORPH1-NEXT: 20040: nop
# ORPH1: fnpic: # ORPH1: <fnpic>:
# ORPH1-NEXT: 20050: nop # ORPH1-NEXT: 20050: nop
# ORPH1: __LA25Thunk_foo1a: # ORPH1: <__LA25Thunk_foo1a>:
# ORPH1-NEXT: 20054: lui $25, 2 # ORPH1-NEXT: 20054: lui $25, 2
# ORPH1-NEXT: 20058: j 131200 <foo1a> # ORPH1-NEXT: 20058: j 131200 <foo1a>
# ORPH1-NEXT: 2005c: addiu $25, $25, 128 # ORPH1-NEXT: 2005c: addiu $25, $25, 128
# ORPH1-NEXT: 20060: nop # ORPH1-NEXT: 20060: nop
# ORPH1: __LA25Thunk_foo1b: # ORPH1: <__LA25Thunk_foo1b>:
# ORPH1-NEXT: 20064: lui $25, 2 # ORPH1-NEXT: 20064: lui $25, 2
# ORPH1-NEXT: 20068: j 131204 <foo1b> # ORPH1-NEXT: 20068: j 131204 <foo1b>
# ORPH1-NEXT: 2006c: addiu $25, $25, 132 # ORPH1-NEXT: 2006c: addiu $25, $25, 132
# ORPH1-NEXT: 20070: nop # ORPH1-NEXT: 20070: nop
# ORPH1: foo1a: # ORPH1: <foo1a>:
# ORPH1-NEXT: 20080: nop # ORPH1-NEXT: 20080: nop
# ORPH1: foo1b: # ORPH1: <foo1b>:
# ORPH1-NEXT: 20084: nop # ORPH1-NEXT: 20084: nop
# ORPH1: __LA25Thunk_foo2: # ORPH1: <__LA25Thunk_foo2>:
# ORPH1-NEXT: 20088: lui $25, 2 # ORPH1-NEXT: 20088: lui $25, 2
# ORPH1-NEXT: 2008c: j 131232 <foo2> # ORPH1-NEXT: 2008c: j 131232 <foo2>
# ORPH1-NEXT: 20090: addiu $25, $25, 160 # ORPH1-NEXT: 20090: addiu $25, $25, 160
# ORPH1-NEXT: 20094: nop # ORPH1-NEXT: 20094: nop
# ORPH1: foo2: # ORPH1: <foo2>:
# ORPH1-NEXT: 200a0: nop # ORPH1-NEXT: 200a0: nop
# Test script with orphans added to new OutputSection, the .text.1 and # Test script with orphans added to new OutputSection, the .text.1 and
# .text.2 sections will form a new OutputSection .text # .text.2 sections will form a new OutputSection .text
# RUN: echo "SECTIONS { .out 0x20000 : { *(.text) } }" > %t3.script # RUN: echo "SECTIONS { .out 0x20000 : { *(.text) } }" > %t3.script
# RUN: ld.lld --script %t3.script %t-npic.o %t-pic.o %t-sto-pic.o -o %t3.exe # RUN: ld.lld --script %t3.script %t-npic.o %t-pic.o %t-sto-pic.o -o %t3.exe
# RUN: llvm-objdump -d --no-show-raw-insn %t3.exe | FileCheck -check-prefix=ORPH2 %s # RUN: llvm-objdump -d --no-show-raw-insn %t3.exe | FileCheck -check-prefix=ORPH2 %s
# ORPH2: Disassembly of section .out: # ORPH2: Disassembly of section .out:
# ORPH2-EMPTY: # ORPH2-EMPTY:
# ORPH2-NEXT: __start: # ORPH2-NEXT: <__start>:
# ORPH2-NEXT: 20000: jal 131168 <__LA25Thunk_foo1a> # ORPH2-NEXT: 20000: jal 131168 <__LA25Thunk_foo1a>
# ORPH2-NEXT: 20004: nop # ORPH2-NEXT: 20004: nop
# ORPH2-NEXT: 20008: jal 131208 <__LA25Thunk_foo2> # ORPH2-NEXT: 20008: jal 131208 <__LA25Thunk_foo2>
# ORPH2-NEXT: 2000c: nop # ORPH2-NEXT: 2000c: nop
# ORPH2-NEXT: 20010: jal 131184 <__LA25Thunk_foo1b> # ORPH2-NEXT: 20010: jal 131184 <__LA25Thunk_foo1b>
# ORPH2-NEXT: 20014: nop # ORPH2-NEXT: 20014: nop
# ORPH2-NEXT: 20018: jal 131208 <__LA25Thunk_foo2> # ORPH2-NEXT: 20018: jal 131208 <__LA25Thunk_foo2>
# ORPH2-NEXT: 2001c: nop # ORPH2-NEXT: 2001c: nop
# ORPH2-NEXT: 20020: jal 131120 <__LA25Thunk_fpic> # ORPH2-NEXT: 20020: jal 131120 <__LA25Thunk_fpic>
# ORPH2-NEXT: 20024: nop # ORPH2-NEXT: 20024: nop
# ORPH2-NEXT: 20028: jal 131152 <fnpic> # ORPH2-NEXT: 20028: jal 131152 <fnpic>
# ORPH2-NEXT: 2002c: nop # ORPH2-NEXT: 2002c: nop
# ORPH2: __LA25Thunk_fpic: # ORPH2: <__LA25Thunk_fpic>:
# ORPH2-NEXT: 20030: lui $25, 2 # ORPH2-NEXT: 20030: lui $25, 2
# ORPH2-NEXT: 20034: j 131136 <fpic> # ORPH2-NEXT: 20034: j 131136 <fpic>
# ORPH2-NEXT: 20038: addiu $25, $25, 64 # ORPH2-NEXT: 20038: addiu $25, $25, 64
# ORPH2-NEXT: 2003c: nop # ORPH2-NEXT: 2003c: nop
# ORPH2: fpic: # ORPH2: <fpic>:
# ORPH2-NEXT: 20040: nop # ORPH2-NEXT: 20040: nop
# ORPH2: fnpic: # ORPH2: <fnpic>:
# ORPH2-NEXT: 20050: nop # ORPH2-NEXT: 20050: nop
# ORPH2-EMPTY: # ORPH2-EMPTY:
# ORPH2-NEXT: Disassembly of section .text: # ORPH2-NEXT: Disassembly of section .text:
# ORPH2-EMPTY: # ORPH2-EMPTY:
# ORPH2-NEXT: __LA25Thunk_foo1a: # ORPH2-NEXT: <__LA25Thunk_foo1a>:
# ORPH2-NEXT: 20060: lui $25, 2 # ORPH2-NEXT: 20060: lui $25, 2
# ORPH2-NEXT: 20064: j 131200 <foo1a> # ORPH2-NEXT: 20064: j 131200 <foo1a>
# ORPH2-NEXT: 20068: addiu $25, $25, 128 # ORPH2-NEXT: 20068: addiu $25, $25, 128
# ORPH2-NEXT: 2006c: nop # ORPH2-NEXT: 2006c: nop
# ORPH2: __LA25Thunk_foo1b: # ORPH2: <__LA25Thunk_foo1b>:
# ORPH2-NEXT: 20070: lui $25, 2 # ORPH2-NEXT: 20070: lui $25, 2
# ORPH2-NEXT: 20074: j 131204 <foo1b> # ORPH2-NEXT: 20074: j 131204 <foo1b>
# ORPH2-NEXT: 20078: addiu $25, $25, 132 # ORPH2-NEXT: 20078: addiu $25, $25, 132
# ORPH2-NEXT: 2007c: nop # ORPH2-NEXT: 2007c: nop
# ORPH2: foo1a: # ORPH2: <foo1a>:
# ORPH2-NEXT: 20080: nop # ORPH2-NEXT: 20080: nop
# ORPH2: foo1b: # ORPH2: <foo1b>:
# ORPH2-NEXT: 20084: nop # ORPH2-NEXT: 20084: nop
# ORPH2: __LA25Thunk_foo2: # ORPH2: <__LA25Thunk_foo2>:
# ORPH2-NEXT: 20088: lui $25, 2 # ORPH2-NEXT: 20088: lui $25, 2
# ORPH2-NEXT: 2008c: j 131232 <foo2> # ORPH2-NEXT: 2008c: j 131232 <foo2>
# ORPH2-NEXT: 20090: addiu $25, $25, 160 # ORPH2-NEXT: 20090: addiu $25, $25, 160
# ORPH2-NEXT: 20094: nop # ORPH2-NEXT: 20094: nop
# ORPH2: foo2: # ORPH2: <foo2>:
# ORPH2-NEXT: 200a0: nop # ORPH2-NEXT: 200a0: nop

lld/test/ELF/mips-npic-call-pic.s

Show All 30 Lines
# RUN: %s -o %t-npic-r6.o # RUN: %s -o %t-npic-r6.o
# RUN: ld.lld %t-npic-r6.o %t-pic-r6.o %t-sto-pic-r6.o \ # RUN: ld.lld %t-npic-r6.o %t-pic-r6.o %t-sto-pic-r6.o \
# RUN: -script %t.script -o %t-r6.exe # RUN: -script %t.script -o %t-r6.exe
# RUN: llvm-objdump -d --no-show-raw-insn %t-r6.exe \ # RUN: llvm-objdump -d --no-show-raw-insn %t-r6.exe \
# RUN: | FileCheck --check-prefixes=CHECK,R6 %s # RUN: | FileCheck --check-prefixes=CHECK,R6 %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __start: # CHECK-NEXT: <__start>:
# CHECK-NEXT: 20100: jal 131412 <__LA25Thunk_foo1a> # CHECK-NEXT: 20100: jal 131412 <__LA25Thunk_foo1a>
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: jal 131464 <__LA25Thunk_foo2> # CHECK-NEXT: jal 131464 <__LA25Thunk_foo2>
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: jal 131428 <__LA25Thunk_foo1b> # CHECK-NEXT: jal 131428 <__LA25Thunk_foo1b>
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: jal 131464 <__LA25Thunk_foo2> # CHECK-NEXT: jal 131464 <__LA25Thunk_foo2>
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: jal 131376 <__LA25Thunk_fpic> # CHECK-NEXT: jal 131376 <__LA25Thunk_fpic>
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: jal 131408 <fnpic> # CHECK-NEXT: jal 131408 <fnpic>
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK: __LA25Thunk_fpic: # CHECK: <__LA25Thunk_fpic>:
# R2: 20130: lui $25, 2 # R2: 20130: lui $25, 2
# R6: 20130: aui $25, $zero, 2 # R6: 20130: aui $25, $zero, 2
# CHECK-NEXT: j 131392 <fpic> # CHECK-NEXT: j 131392 <fpic>
# CHECK-NEXT: addiu $25, $25, 320 # CHECK-NEXT: addiu $25, $25, 320
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK: fpic: # CHECK: <fpic>:
# CHECK-NEXT: 20140: nop # CHECK-NEXT: 20140: nop
# CHECK: fnpic: # CHECK: <fnpic>:
# CHECK-NEXT: 20150: nop # CHECK-NEXT: 20150: nop
# CHECK: __LA25Thunk_foo1a: # CHECK: <__LA25Thunk_foo1a>:
# R2: 20154: lui $25, 2 # R2: 20154: lui $25, 2
# R6: 20154: aui $25, $zero, 2 # R6: 20154: aui $25, $zero, 2
# CHECK: j 131456 <foo1a> # CHECK: j 131456 <foo1a>
# CHECK-NEXT: addiu $25, $25, 384 # CHECK-NEXT: addiu $25, $25, 384
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK: __LA25Thunk_foo1b: # CHECK: <__LA25Thunk_foo1b>:
# R2: 20164: lui $25, 2 # R2: 20164: lui $25, 2
# R6: aui $25, $zero, 2 # R6: aui $25, $zero, 2
# CHECK-NEXT: j 131460 <foo1b> # CHECK-NEXT: j 131460 <foo1b>
# CHECK-NEXT: addiu $25, $25, 388 # CHECK-NEXT: addiu $25, $25, 388
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK: foo1a: # CHECK: <foo1a>:
# CHECK-NEXT: 20180: nop # CHECK-NEXT: 20180: nop
# CHECK: foo1b: # CHECK: <foo1b>:
# CHECK-NEXT: 20184: nop # CHECK-NEXT: 20184: nop
# CHECK: __LA25Thunk_foo2: # CHECK: <__LA25Thunk_foo2>:
# R2: 20188: lui $25, 2 # R2: 20188: lui $25, 2
# R6: aui $25, $zero, 2 # R6: aui $25, $zero, 2
# CHECK-NEXT: j 131488 <foo2> # CHECK-NEXT: j 131488 <foo2>
# CHECK-NEXT: addiu $25, $25, 416 # CHECK-NEXT: addiu $25, $25, 416
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK: foo2: # CHECK: <foo2>:
# CHECK-NEXT: 201a0: nop # CHECK-NEXT: 201a0: nop
.text .text
.globl __start .globl __start
__start: __start:
jal foo1a jal foo1a
jal foo2 jal foo2
jal foo1b jal foo1b
jal foo2 jal foo2
jal fpic jal fpic
jal fnpic jal fnpic

lld/test/ELF/mips-pc-relocs.s

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# CHECK: 00020020 g .text 00000000 _foo # CHECK: 00020020 g .text 00000000 _foo
# CHECK: Contents of section .data: # CHECK: Contents of section .data:
# CHECK-NEXT: 30000 ffff0028 00000000 00000000 00000000 # CHECK-NEXT: 30000 ffff0028 00000000 00000000 00000000
# ^-- 0x20020 + 8 - 0x30000 # ^-- 0x20020 + 8 - 0x30000
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __start: # CHECK-NEXT: <__start>:
# CHECK-NEXT: 20000: lwpc $6, 32 # CHECK-NEXT: 20000: lwpc $6, 32
# ^-- (0x20020-0x20000)>>2 # ^-- (0x20020-0x20000)>>2
# CHECK-NEXT: 20004: beqc $5, $6, 28 # CHECK-NEXT: 20004: beqc $5, $6, 28
# ^-- (0x20020-4-0x20004)>>2 # ^-- (0x20020-4-0x20004)>>2
# CHECK-NEXT: 20008: beqzc $9, 24 # CHECK-NEXT: 20008: beqzc $9, 24
# ^-- (0x20020-4-0x20008)>>2 # ^-- (0x20020-4-0x20008)>>2
# CHECK-NEXT: 2000c: bc 20 # CHECK-NEXT: 2000c: bc 20
# ^-- (0x20020-4-0x2000c)>>2 # ^-- (0x20020-4-0x2000c)>>2
# CHECK-NEXT: 20010: aluipc $2, 0 # CHECK-NEXT: 20010: aluipc $2, 0
# ^-- %hi(0x20020-0x20010) # ^-- %hi(0x20020-0x20010)
# CHECK-NEXT: 20014: addiu $2, $2, 12 # CHECK-NEXT: 20014: addiu $2, $2, 12
# ^-- %lo(0x20020-0x20014) # ^-- %lo(0x20020-0x20014)

lld/test/ELF/mips-plt-n32.s

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# RUN: | FileCheck %s --check-prefixes=DEFAULT,CHECK # RUN: | FileCheck %s --check-prefixes=DEFAULT,CHECK
# RUN: ld.lld %t2.o -shared -soname=t.so -o %t.so -z hazardplt # RUN: ld.lld %t2.o -shared -soname=t.so -o %t.so -z hazardplt
# RUN: ld.lld %t1.o %t.so -script %t.script -o %t.exe -z hazardplt # RUN: ld.lld %t1.o %t.so -script %t.script -o %t.exe -z hazardplt
# RUN: llvm-objdump -d --no-show-raw-insn %t.exe \ # RUN: llvm-objdump -d --no-show-raw-insn %t.exe \
# RUN: | FileCheck %s --check-prefixes=HAZARDPLT,CHECK # RUN: | FileCheck %s --check-prefixes=HAZARDPLT,CHECK
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __start: # CHECK-NEXT: <__start>:
# CHECK-NEXT: 20000: jal 131120 # CHECK-NEXT: 20000: jal 131120
# ^-- 0x20030 gotplt[foo0] # ^-- 0x20030 gotplt[foo0]
# CHECK-NEXT: 20004: nop # CHECK-NEXT: 20004: nop
# #
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: Disassembly of section .plt: # CHECK-NEXT: Disassembly of section .plt:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: .plt: # CHECK-NEXT: <.plt>:
# CHECK-NEXT: 20010: lui $14, 3 # CHECK-NEXT: 20010: lui $14, 3
# CHECK-NEXT: 20014: lw $25, 4($14) # CHECK-NEXT: 20014: lw $25, 4($14)
# CHECK-NEXT: 20018: addiu $14, $14, 4 # CHECK-NEXT: 20018: addiu $14, $14, 4
# CHECK-NEXT: 2001c: subu $24, $24, $14 # CHECK-NEXT: 2001c: subu $24, $24, $14
# CHECK-NEXT: 20020: move $15, $ra # CHECK-NEXT: 20020: move $15, $ra
# CHECK-NEXT: 20024: srl $24, $24, 2 # CHECK-NEXT: 20024: srl $24, $24, 2
# DEFAULT: 20028: jalr $25 # DEFAULT: 20028: jalr $25
# HAZARDPLT: 20028: jalr.hb $25 # HAZARDPLT: 20028: jalr.hb $25
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lld/test/ELF/mips-plt-n64.s

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# RUN: | FileCheck %s --check-prefixes=CHECK,DEFAULT # RUN: | FileCheck %s --check-prefixes=CHECK,DEFAULT
# RUN: ld.lld %t-so.o -shared -soname=t.so -o %t.so -z hazardplt # RUN: ld.lld %t-so.o -shared -soname=t.so -o %t.so -z hazardplt
# RUN: ld.lld %t.o %t.so -script %t.script -o %t.exe -z hazardplt # RUN: ld.lld %t.o %t.so -script %t.script -o %t.exe -z hazardplt
# RUN: llvm-objdump -d --no-show-raw-insn %t.exe \ # RUN: llvm-objdump -d --no-show-raw-insn %t.exe \
# RUN: | FileCheck %s --check-prefixes=CHECK,HAZARDPLT # RUN: | FileCheck %s --check-prefixes=CHECK,HAZARDPLT
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __start: # CHECK-NEXT: <__start>:
# CHECK-NEXT: 20000: jal 131120 # CHECK-NEXT: 20000: jal 131120
# CHECK-NEXT: 20004: nop # CHECK-NEXT: 20004: nop
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: Disassembly of section .plt: # CHECK-NEXT: Disassembly of section .plt:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: .plt: # CHECK-NEXT: <.plt>:
# CHECK-NEXT: 20010: lui $14, 3 # CHECK-NEXT: 20010: lui $14, 3
# CHECK-NEXT: 20014: ld $25, 8($14) # CHECK-NEXT: 20014: ld $25, 8($14)
# CHECK-NEXT: 20018: addiu $14, $14, 8 # CHECK-NEXT: 20018: addiu $14, $14, 8
# CHECK-NEXT: 2001c: subu $24, $24, $14 # CHECK-NEXT: 2001c: subu $24, $24, $14
# CHECK-NEXT: 20020: move $15, $ra # CHECK-NEXT: 20020: move $15, $ra
# CHECK-NEXT: 20024: srl $24, $24, 3 # CHECK-NEXT: 20024: srl $24, $24, 3
# DEFAULT: 20028: jalr $25 # DEFAULT: 20028: jalr $25
# HAZARDPLT: 20028: jalr.hb $25 # HAZARDPLT: 20028: jalr.hb $25
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lld/test/ELF/mips-plt-r6.s

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# RUN: ld.lld %t1.o %t.so -script %t.script -o %t.exe # RUN: ld.lld %t1.o %t.so -script %t.script -o %t.exe
# RUN: llvm-objdump -d --no-show-raw-insn %t.exe | FileCheck %s --check-prefixes=DEFAULT,CHECK # RUN: llvm-objdump -d --no-show-raw-insn %t.exe | FileCheck %s --check-prefixes=DEFAULT,CHECK
# RUN: ld.lld %t2.o -shared -soname=t.so -o %t.so -z hazardplt # RUN: ld.lld %t2.o -shared -soname=t.so -o %t.so -z hazardplt
# RUN: ld.lld %t1.o %t.so -script %t.script -o %t.exe -z hazardplt # RUN: ld.lld %t1.o %t.so -script %t.script -o %t.exe -z hazardplt
# RUN: llvm-objdump -d --no-show-raw-insn %t.exe | FileCheck %s --check-prefixes=HAZARDPLT,CHECK # RUN: llvm-objdump -d --no-show-raw-insn %t.exe | FileCheck %s --check-prefixes=HAZARDPLT,CHECK
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __start: # CHECK-NEXT: <__start>:
# CHECK-NEXT: 20000: jal 131120 # CHECK-NEXT: 20000: jal 131120
# ^-- 0x20030 gotplt[foo0] # ^-- 0x20030 gotplt[foo0]
# CHECK-NEXT: 20004: nop # CHECK-NEXT: 20004: nop
# #
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: Disassembly of section .plt: # CHECK-NEXT: Disassembly of section .plt:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: .plt: # CHECK-NEXT: <.plt>:
# CHECK-NEXT: 20010: aui $gp, $zero, 3 # CHECK-NEXT: 20010: aui $gp, $zero, 3
# CHECK-NEXT: 20014: lw $25, 4($gp) # CHECK-NEXT: 20014: lw $25, 4($gp)
# CHECK-NEXT: 20018: addiu $gp, $gp, 4 # CHECK-NEXT: 20018: addiu $gp, $gp, 4
# CHECK-NEXT: 2001c: subu $24, $24, $gp # CHECK-NEXT: 2001c: subu $24, $24, $gp
# CHECK-NEXT: 20020: move $15, $ra # CHECK-NEXT: 20020: move $15, $ra
# CHECK-NEXT: 20024: srl $24, $24, 2 # CHECK-NEXT: 20024: srl $24, $24, 2
# DEFAULT: 20028: jalr $25 # DEFAULT: 20028: jalr $25
# HAZARDPLT: 20028: jalr.hb $25 # HAZARDPLT: 20028: jalr.hb $25
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lld/test/ELF/mips-tls-64.s

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# DIS: Contents of section .got: # DIS: Contents of section .got:
# DIS-NEXT: 30000 00000000 00000000 80000000 00000000 # DIS-NEXT: 30000 00000000 00000000 80000000 00000000
# DIS-NEXT: 30010 00000000 00000000 ffffffff ffff9004 # DIS-NEXT: 30010 00000000 00000000 ffffffff ffff9004
# DIS-NEXT: 30020 00000000 00000000 00000000 00000000 # DIS-NEXT: 30020 00000000 00000000 00000000 00000000
# DIS-NEXT: 30030 00000000 00000001 00000000 00000000 # DIS-NEXT: 30030 00000000 00000001 00000000 00000000
# DIS-NEXT: 30040 00000000 00000001 ffffffff ffff8004 # DIS-NEXT: 30040 00000000 00000001 ffffffff ffff8004
# DIS: __start: # DIS: <__start>:
# DIS-NEXT: addiu $2, $3, -32720 # DIS-NEXT: addiu $2, $3, -32720
# DIS-NEXT: addiu $2, $3, -32736 # DIS-NEXT: addiu $2, $3, -32736
# DIS-NEXT: addiu $2, $3, -32704 # DIS-NEXT: addiu $2, $3, -32704
# DIS-NEXT: addiu $2, $3, -32688 # DIS-NEXT: addiu $2, $3, -32688
# DIS-NEXT: addiu $2, $3, -32728 # DIS-NEXT: addiu $2, $3, -32728
# CHECK: Relocations [ # CHECK: Relocations [
# CHECK-NEXT: Section (7) .rel.dyn { # CHECK-NEXT: Section (7) .rel.dyn {
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lld/test/ELF/mips-tls-hilo.s

# REQUIRES: mips # REQUIRES: mips
# Check MIPS R_MIPS_TLS_DTPREL_HI16/LO16 and R_MIPS_TLS_TPREL_HI16/LO16 # Check MIPS R_MIPS_TLS_DTPREL_HI16/LO16 and R_MIPS_TLS_TPREL_HI16/LO16
# relocations handling. # relocations handling.
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
# RUN: ld.lld %t.o -o %t.exe # RUN: ld.lld %t.o -o %t.exe
# RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck -check-prefix=DIS %s # RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck -check-prefix=DIS %s
# RUN: llvm-readobj -r -A %t.exe | FileCheck %s # RUN: llvm-readobj -r -A %t.exe | FileCheck %s
# RUN: ld.lld %t.o -shared -o %t.so # RUN: ld.lld %t.o -shared -o %t.so
# RUN: llvm-readobj -r -A %t.so | FileCheck -check-prefix=SO %s # RUN: llvm-readobj -r -A %t.so | FileCheck -check-prefix=SO %s
# DIS: 00000000 l O .tdata 00000000 loc0 # DIS: 00000000 l O .tdata 00000000 loc0
# DIS: __start: # DIS: <__start>:
# DIS-NEXT: addiu $2, $3, 0 # DIS-NEXT: addiu $2, $3, 0
# ^-- %hi(loc0 - .tdata - 0x8000) # ^-- %hi(loc0 - .tdata - 0x8000)
# DIS-NEXT: addiu $2, $3, -32768 # DIS-NEXT: addiu $2, $3, -32768
# ^-- %lo(loc0 - .tdata - 0x8000) # ^-- %lo(loc0 - .tdata - 0x8000)
# DIS-NEXT: addiu $2, $3, 0 # DIS-NEXT: addiu $2, $3, 0
# ^-- %hi(loc0 - .tdata - 0x7000) # ^-- %hi(loc0 - .tdata - 0x7000)
# DIS-NEXT: addiu $2, $3, -28672 # DIS-NEXT: addiu $2, $3, -28672
# ^-- %lo(loc0 - .tdata - 0x7000) # ^-- %lo(loc0 - .tdata - 0x7000)
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lld/test/ELF/mips-tls.s

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# DIS: 00000004 g O .tdata 00000000 bar # DIS: 00000004 g O .tdata 00000000 bar
# DIS: 00000000 O *UND* 00000000 foo # DIS: 00000000 O *UND* 00000000 foo
# DIS: Contents of section .got: # DIS: Contents of section .got:
# DIS-NEXT: 30000 00000000 80000000 00000000 ffff9004 # DIS-NEXT: 30000 00000000 80000000 00000000 ffff9004
# DIS-NEXT: 30010 00000000 00000000 00000001 00000000 # DIS-NEXT: 30010 00000000 00000000 00000001 00000000
# DIS-NEXT: 30020 00000001 ffff8004 # DIS-NEXT: 30020 00000001 ffff8004
# DIS: __start: # DIS: <__start>:
# DIS-NEXT: addiu $2, $3, -32736 # DIS-NEXT: addiu $2, $3, -32736
# DIS-NEXT: addiu $2, $3, -32744 # DIS-NEXT: addiu $2, $3, -32744
# DIS-NEXT: addiu $2, $3, -32728 # DIS-NEXT: addiu $2, $3, -32728
# DIS-NEXT: addiu $2, $3, -32720 # DIS-NEXT: addiu $2, $3, -32720
# DIS-NEXT: addiu $2, $3, -32740 # DIS-NEXT: addiu $2, $3, -32740
# CHECK: Relocations [ # CHECK: Relocations [
# CHECK-NEXT: Section (7) .rel.dyn { # CHECK-NEXT: Section (7) .rel.dyn {
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lld/test/ELF/mips-xgot-order.s

# REQUIRES: mips # REQUIRES: mips
# Check that GOT entries accessed via 16-bit indexing are allocated # Check that GOT entries accessed via 16-bit indexing are allocated
# in the beginning of the GOT. # in the beginning of the GOT.
# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
# RUN: ld.lld %t.o -o %t.exe # RUN: ld.lld %t.o -o %t.exe
# RUN: llvm-objdump -d --no-show-raw-insn %t.exe | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t.exe | FileCheck %s
# RUN: llvm-readelf -s -A %t.exe | FileCheck -check-prefix=GOT %s # RUN: llvm-readelf -s -A %t.exe | FileCheck -check-prefix=GOT %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: __start: # CHECK-NEXT: <__start>:
# CHECK-NEXT: lui $2, 0 # CHECK-NEXT: lui $2, 0
# CHECK-NEXT: lw $2, -32732($2) # CHECK-NEXT: lw $2, -32732($2)
# CHECK-NEXT: lui $2, 0 # CHECK-NEXT: lui $2, 0
# CHECK-NEXT: lw $2, -32728($2) # CHECK-NEXT: lw $2, -32728($2)
# #
# CHECK: bar: # CHECK: <bar>:
# CHECK-NEXT: lw $2, -32736($2) # CHECK-NEXT: lw $2, -32736($2)
# CHECK-NEXT: lw $2, -32744($2) # CHECK-NEXT: lw $2, -32744($2)
# CHECK-NEXT: addi $2, $2, {{.*}} # CHECK-NEXT: addi $2, $2, {{.*}}
# GOT: Symbol table '.symtab' # GOT: Symbol table '.symtab'
# GOT: Num: Value Size Type Bind Vis Ndx Name # GOT: Num: Value Size Type Bind Vis Ndx Name
# GOT: [[LOC:[0-9a-f]+]] 0 NOTYPE LOCAL DEFAULT 4 loc # GOT: [[LOC:[0-9a-f]+]] 0 NOTYPE LOCAL DEFAULT 4 loc
# GOT: [[START:[0-9a-f]+]] 0 NOTYPE GLOBAL DEFAULT 3 __start # GOT: [[START:[0-9a-f]+]] 0 NOTYPE GLOBAL DEFAULT 3 __start
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lld/test/ELF/msp430.s

Show All 19 Lines; CHECK-NEXT: 2000 21008000 800000
.text .text
.global foo .global foo
foo: foo:
;; R_MSP430_10_PCREL ;; R_MSP430_10_PCREL
jmp _start jmp _start
; CHECK: Disassembly of section .text: ; CHECK: Disassembly of section .text:
; CHECK-EMPTY: ; CHECK-EMPTY:
; CHECK-NEXT: _start: ; CHECK-NEXT: <_start>:
; CHECK-NEXT: 8000: {{.*}} nop ; CHECK-NEXT: 8000: {{.*}} nop
; CHECK: foo: ; CHECK: <foo>:
; CHECK-NEXT: 8004: {{.*}} jmp $-4 ; CHECK-NEXT: 8004: {{.*}} jmp $-4
;; R_MSP430_16_BYTE ;; R_MSP430_16_BYTE
call #_start call #_start
; CHECK: call #32768 ; CHECK: call #32768
;; R_MSP430_16_PCREL_BYTE ;; R_MSP430_16_PCREL_BYTE
mov #-1, _start mov #-1, _start
; CHECK: 800a: {{.*}} mov #-1, -12 ; CHECK: 800a: {{.*}} mov #-1, -12
; RUN: od -x %t.exe | FileCheck -check-prefix=TRAP %s ; RUN: od -x %t.exe | FileCheck -check-prefix=TRAP %s
; TRAP: 4343 4343 4343 4343 4343 4343 4343 4343 ; TRAP: 4343 4343 4343 4343 4343 4343 4343 4343

lld/test/ELF/non-abs-reloc.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
// RUN: ld.lld %t.o -o %t 2>&1 | FileCheck %s // RUN: ld.lld %t.o -o %t 2>&1 | FileCheck %s
// CHECK: (.nonalloc+0x1): has non-ABS relocation R_X86_64_PC32 against symbol '_start' // CHECK: (.nonalloc+0x1): has non-ABS relocation R_X86_64_PC32 against symbol '_start'
// CHECK: (.nonalloc+0x6): has non-ABS relocation R_X86_64_PC32 against symbol '_start' // CHECK: (.nonalloc+0x6): has non-ABS relocation R_X86_64_PC32 against symbol '_start'
// RUN: llvm-objdump -D %t | FileCheck --check-prefix=DISASM %s // RUN: llvm-objdump -D %t | FileCheck --check-prefix=DISASM %s
// DISASM: Disassembly of section .nonalloc: // DISASM: Disassembly of section .nonalloc:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .nonalloc: // DISASM-NEXT: <.nonalloc>:
// DISASM-NEXT: 0: {{.*}} callq {{.*}} <_start> // DISASM-NEXT: 0: {{.*}} callq {{.*}} <_start>
// DISASM-NEXT: 5: {{.*}} callq {{.*}} <_start> // DISASM-NEXT: 5: {{.*}} callq {{.*}} <_start>
.globl _start .globl _start
_start: _start:
nop nop
.section .nonalloc .section .nonalloc
.byte 0xe8 .byte 0xe8
.long _start - . - 4 .long _start - . - 4
.byte 0xe8 .byte 0xe8
.long _start - . - 4 .long _start - . - 4

lld/test/ELF/non-alloc-link-order-gc.s

# REQUIRES: x86 # REQUIRES: x86
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
# RUN: ld.lld %t.o -o %t1 --gc-sections # RUN: ld.lld %t.o -o %t1 --gc-sections
# RUN: llvm-objdump -section-headers -D %t1 | FileCheck %s # RUN: llvm-objdump -section-headers -D %t1 | FileCheck %s
## Check that we are able to GC non-allocatable metadata sections without crash. ## Check that we are able to GC non-allocatable metadata sections without crash.
# CHECK: Name Size # CHECK: Name Size
# CHECK: .stack_sizes 00000001 # CHECK: .stack_sizes 00000001
# CHECK: Disassembly of section .stack_sizes: # CHECK: Disassembly of section .stack_sizes:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: .stack_sizes: # CHECK-NEXT: <.stack_sizes>:
# CHECK-NEXT: 01 # CHECK-NEXT: 01
.section .text.live,"ax",@progbits .section .text.live,"ax",@progbits
.globl live .globl live
live: live:
nop nop
.section .stack_sizes,"o",@progbits,.text.live,unique,0 .section .stack_sizes,"o",@progbits,.text.live,unique,0
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lld/test/ELF/ppc32-call-stub-nopic.s

Show All 13 Lines
# RELOC: PPC_GOT 0x100202B8 # RELOC: PPC_GOT 0x100202B8
# RELOC: .rela.plt { # RELOC: .rela.plt {
# RELOC-NEXT: 0x100302C4 R_PPC_JMP_SLOT f 0x0 # RELOC-NEXT: 0x100302C4 R_PPC_JMP_SLOT f 0x0
# RELOC-NEXT: 0x100302C8 R_PPC_JMP_SLOT g 0x0 # RELOC-NEXT: 0x100302C8 R_PPC_JMP_SLOT g 0x0
# RELOC-NEXT: } # RELOC-NEXT: }
## .got2+0x8000-0x10004 = 0x30000+0x8000-0x10004 = 65536*2+32764 ## .got2+0x8000-0x10004 = 0x30000+0x8000-0x10004 = 65536*2+32764
# CHECK-LABEL: _start: # CHECK-LABEL: <_start>:
# CHECK-NEXT: bl .+16 # CHECK-NEXT: bl .+16
# CHECK-NEXT: bl .+12 # CHECK-NEXT: bl .+12
# CHECK-NEXT: bl .+24 # CHECK-NEXT: bl .+24
# CHECK-NEXT: bl .+20 # CHECK-NEXT: bl .+20
# CHECK-EMPTY: # CHECK-EMPTY:
## -fno-PIC call stubs of f and g. ## -fno-PIC call stubs of f and g.
## .plt[0] = 0x100302c4 = 65536*4099+708 ## .plt[0] = 0x100302c4 = 65536*4099+708
## .plt[1] = 0x100302c8 = 65536*4099+712 ## .plt[1] = 0x100302c8 = 65536*4099+712
# CHECK-NEXT: 00000000.plt_call32.f: # CHECK-NEXT: <00000000.plt_call32.f>:
# CHECK-NEXT: lis 11, 4099 # CHECK-NEXT: lis 11, 4099
# CHECK-NEXT: lwz 11, 708(11) # CHECK-NEXT: lwz 11, 708(11)
# CHECK-NEXT: mtctr 11 # CHECK-NEXT: mtctr 11
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 00000000.plt_call32.g: # CHECK-NEXT: <00000000.plt_call32.g>:
# CHECK-NEXT: lis 11, 4099 # CHECK-NEXT: lis 11, 4099
# CHECK-NEXT: lwz 11, 712(11) # CHECK-NEXT: lwz 11, 712(11)
# CHECK-NEXT: mtctr 11 # CHECK-NEXT: mtctr 11
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# CHECK-EMPTY: # CHECK-EMPTY:
## In Secure PLT ABI, .plt stores function pointers to first instructions of .glink ## In Secure PLT ABI, .plt stores function pointers to first instructions of .glink
# HEX: 0x100302c4 10010200 10010204 # HEX: 0x100302c4 10010200 10010204
## These instructions are referenced by .plt entries. ## These instructions are referenced by .plt entries.
# CHECK: 10010200 .glink: # CHECK: 10010200 <.glink>:
# CHECK-NEXT: b .+8 # CHECK-NEXT: b .+8
# CHECK-NEXT: b .+4 # CHECK-NEXT: b .+4
## PLTresolve ## PLTresolve
## Operands of lis & lwz: .got+4 = 0x10020070+4 = 65536*4098+700 ## Operands of lis & lwz: .got+4 = 0x10020070+4 = 65536*4098+700
## Operands of addis & addi: -.glink = -0x10010200 = 65536*-4097-512 ## Operands of addis & addi: -.glink = -0x10010200 = 65536*-4097-512
# CHECK-NEXT: lis 12, 4098 # CHECK-NEXT: lis 12, 4098
# CHECK-NEXT: addis 11, 11, -4097 # CHECK-NEXT: addis 11, 11, -4097
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lld/test/ELF/ppc32-call-stub-pic.s

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# RELOC-NEXT: R_PPC_JMP_SLOT g 0x0 # RELOC-NEXT: R_PPC_JMP_SLOT g 0x0
# RELOC-NEXT: R_PPC_JMP_SLOT h 0x0 # RELOC-NEXT: R_PPC_JMP_SLOT h 0x0
# RELOC-NEXT: } # RELOC-NEXT: }
# SEC: .got PROGBITS 00020368 # SEC: .got PROGBITS 00020368
# DYN: PPC_GOT 0x20368 # DYN: PPC_GOT 0x20368
## .got2+0x8000-0x10004 = 0x30000+0x8000-0x10004 = 65536*2+32764 ## .got2+0x8000-0x10004 = 0x30000+0x8000-0x10004 = 65536*2+32764
# CHECK-LABEL: _start: # CHECK-LABEL: <_start>:
# CHECK-NEXT: bcl 20, 31, .+4 # CHECK-NEXT: bcl 20, 31, .+4
# PIE-NEXT: 10210: mflr 30 # PIE-NEXT: 10210: mflr 30
# PIE-NEXT: addis 30, 30, 3 # PIE-NEXT: addis 30, 30, 3
# PIE-NEXT: addi 30, 30, -32412 # PIE-NEXT: addi 30, 30, -32412
# SHARED-NEXT: 10230: mflr 30 # SHARED-NEXT: 10230: mflr 30
# SHARED-NEXT: addis 30, 30, 3 # SHARED-NEXT: addis 30, 30, 3
# SHARED-NEXT: addi 30, 30, -32420 # SHARED-NEXT: addi 30, 30, -32420
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# CHECK-NEXT: addi 30, 30, {{.*}} # CHECK-NEXT: addi 30, 30, {{.*}}
## bl 00008000.plt_pic32.f ## bl 00008000.plt_pic32.f
# CHECK-NEXT: bl .+56 # CHECK-NEXT: bl .+56
## bl 00008000.plt_pic32.f ## bl 00008000.plt_pic32.f
# CHECK-NEXT: bl .+68 # CHECK-NEXT: bl .+68
# CHECK-EMPTY: # CHECK-EMPTY:
## -fPIC call stubs of f and g. ## -fPIC call stubs of f and g.
# CHECK-NEXT: 00008000.got2.plt_pic32.f: # CHECK-NEXT: <00008000.got2.plt_pic32.f>:
# CHECK-NEXT: lwz 11, 32760(30) # CHECK-NEXT: lwz 11, 32760(30)
# CHECK-NEXT: mtctr 11 # CHECK-NEXT: mtctr 11
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 00008000.got2.plt_pic32.g: # CHECK-NEXT: <00008000.got2.plt_pic32.g>:
# CHECK-NEXT: lwz 11, 32764(30) # CHECK-NEXT: lwz 11, 32764(30)
# CHECK-NEXT: mtctr 11 # CHECK-NEXT: mtctr 11
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-EMPTY: # CHECK-EMPTY:
## The -fPIC call stub of h needs two instructions addis+lwz to represent the offset 65536*1-32768. ## The -fPIC call stub of h needs two instructions addis+lwz to represent the offset 65536*1-32768.
# CHECK-NEXT: 00008000.got2.plt_pic32.h: # CHECK-NEXT: <00008000.got2.plt_pic32.h>:
# CHECK-NEXT: addis 11, 30, 1 # CHECK-NEXT: addis 11, 30, 1
# CHECK-NEXT: lwz 11, -32768(11) # CHECK-NEXT: lwz 11, -32768(11)
# CHECK-NEXT: mtctr 11 # CHECK-NEXT: mtctr 11
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# CHECK-EMPTY: # CHECK-EMPTY:
## -fpic call stub of f. ## -fpic call stub of f.
# CHECK-NEXT: 00000000.plt_pic32.f: # CHECK-NEXT: <00000000.plt_pic32.f>:
# CHECK-NEXT: addis 11, 30, 2 # CHECK-NEXT: addis 11, 30, 2
# CHECK-NEXT: lwz 11, 4(11) # CHECK-NEXT: lwz 11, 4(11)
# CHECK-NEXT: mtctr 11 # CHECK-NEXT: mtctr 11
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# CHECK-EMPTY: # CHECK-EMPTY:
## Another -fPIC call stub of f from another object file %t2.o ## Another -fPIC call stub of f from another object file %t2.o
## .got2 may have different addresses in different object files, ## .got2 may have different addresses in different object files,
## so the call stub cannot be shared. ## so the call stub cannot be shared.
# CHECK-NEXT: 00008000.got2.plt_pic32.f: # CHECK-NEXT: <00008000.got2.plt_pic32.f>:
## In Secure PLT ABI, .plt stores function pointers to first instructions of .glink ## In Secure PLT ABI, .plt stores function pointers to first instructions of .glink
# HEX: 0x0004036c 00010294 00010298 0001029c # HEX: 0x0004036c 00010294 00010298 0001029c
## These instructions are referenced by .plt entries. ## These instructions are referenced by .plt entries.
# PIE: 00010294 .glink: # PIE: 00010294 <.glink>:
# SHARED: 000102b4 .glink: # SHARED: 000102b4 <.glink>:
# CHECK-NEXT: b .+12 # CHECK-NEXT: b .+12
# CHECK-NEXT: b .+8 # CHECK-NEXT: b .+8
# CHECK-NEXT: b .+4 # CHECK-NEXT: b .+4
## PLTresolve ## PLTresolve
## Operand of addi: 0x100a8-.glink = 24 ## Operand of addi: 0x100a8-.glink = 24
# CHECK-NEXT: addis 11, 11, 0 # CHECK-NEXT: addis 11, 11, 0
# CHECK-NEXT: mflr 0 # CHECK-NEXT: mflr 0
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lld/test/ELF/ppc32-canonical-plt.s

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# SYM: 1001023c 0 FUNC GLOBAL DEFAULT UND func # SYM: 1001023c 0 FUNC GLOBAL DEFAULT UND func
# SYM: 1001022c 0 FUNC GLOBAL DEFAULT UND func2 # SYM: 1001022c 0 FUNC GLOBAL DEFAULT UND func2
# SYM: 1001024c 0 FUNC GLOBAL DEFAULT UND ifunc # SYM: 1001024c 0 FUNC GLOBAL DEFAULT UND ifunc
# HEX: 0x10030318 1001025c 10010260 10010264 # HEX: 0x10030318 1001025c 10010260 10010264
## Canonical PLT entry of func2. ## Canonical PLT entry of func2.
## 0x1003031C = 65536*4099+796 ## 0x1003031C = 65536*4099+796
# CHECK: 1001022c .glink: # CHECK: 1001022c <.glink>:
# CHECK-NEXT: lis 11, 4099 # CHECK-NEXT: lis 11, 4099
# CHECK-NEXT: lwz 11, 796(11) # CHECK-NEXT: lwz 11, 796(11)
# CHECK-NEXT: mtctr 11 # CHECK-NEXT: mtctr 11
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
## Canonical PLT entry of func. ## Canonical PLT entry of func.
## 0x10030318 = 65536*4099+792 ## 0x10030318 = 65536*4099+792
# CHECK-NEXT: 1001023c: lis 11, 4099 # CHECK-NEXT: 1001023c: lis 11, 4099
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lld/test/ELF/ppc32-ifunc-nonpreemptible-nopic.s

# REQUIRES: ppc # REQUIRES: ppc
# RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
# RUN: ld.lld %t.o -o %t # RUN: ld.lld %t.o -o %t
# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s # RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s
# RUN: llvm-readelf -s %t | FileCheck --check-prefix=SYM %s # RUN: llvm-readelf -s %t | FileCheck --check-prefix=SYM %s
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
# RELOC: .rela.dyn { # RELOC: .rela.dyn {
# RELOC-NEXT: 0x10020110 R_PPC_IRELATIVE - 0x100100E0 # RELOC-NEXT: 0x10020110 R_PPC_IRELATIVE - 0x100100E0
# RELOC-NEXT: } # RELOC-NEXT: }
# SYM: 10010100 0 FUNC GLOBAL DEFAULT {{.*}} func # SYM: 10010100 0 FUNC GLOBAL DEFAULT {{.*}} func
# HEX: 0x10020110 10010100 # HEX: 0x10020110 10010100
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK: .text: # CHECK: <.text>:
# CHECK-NEXT: 100100e0: blr # CHECK-NEXT: 100100e0: blr
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: bl .+12 # CHECK-NEXT: bl .+12
# CHECK-NEXT: lis 9, 4097 # CHECK-NEXT: lis 9, 4097
# CHECK-NEXT: addi 9, 9, 256 # CHECK-NEXT: addi 9, 9, 256
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 00000000.plt_call32.func: # CHECK-NEXT: <00000000.plt_call32.func>:
## 0x10020110 = 65536*4098+272 ## 0x10020110 = 65536*4098+272
# CHECK-NEXT: lis 11, 4098 # CHECK-NEXT: lis 11, 4098
# CHECK-NEXT: lwz 11, 272(11) # CHECK-NEXT: lwz 11, 272(11)
.text .text
.globl func .globl func
.type func, @gnu_indirect_function .type func, @gnu_indirect_function
func: func:
blr blr
.globl _start .globl _start
_start: _start:
bl func bl func
lis 9, func@ha lis 9, func@ha
la 9, func@l(9) la 9, func@l(9)

lld/test/ELF/ppc32-ifunc-nonpreemptible-pic.s

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# SYM: 000101a8 0 FUNC GLOBAL DEFAULT {{.*}} func # SYM: 000101a8 0 FUNC GLOBAL DEFAULT {{.*}} func
# HEX: 0x00030240 00000000 # HEX: 0x00030240 00000000
.section .got2,"aw" .section .got2,"aw"
.long func .long func
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK: .text: # CHECK: <.text>:
# CHECK-NEXT: 10188: blr # CHECK-NEXT: 10188: blr
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: bl .+12 # CHECK-NEXT: bl .+12
# CHECK-NEXT: lis 9, 1 # CHECK-NEXT: lis 9, 1
# CHECK-NEXT: addi 9, 9, 424 # CHECK-NEXT: addi 9, 9, 424
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 00008000.got2.plt_pic32.func: # CHECK-NEXT: <00008000.got2.plt_pic32.func>:
## 0x10020114 = 65536*4098+276 ## 0x10020114 = 65536*4098+276
# CHECK-NEXT: lwz 11, -32764(30) # CHECK-NEXT: lwz 11, -32764(30)
# CHECK-NEXT: mtctr 11 # CHECK-NEXT: mtctr 11
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# CHECK-NEXT: nop # CHECK-NEXT: nop
.text .text
.globl func .globl func
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lld/test/ELF/ppc32-local-branch.s

# REQUIRES: ppc # REQUIRES: ppc
# RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
# RUN: echo '.globl foo; foo: blr' | llvm-mc -filetype=obj -triple=powerpc - -o %t1.o # RUN: echo '.globl foo; foo: blr' | llvm-mc -filetype=obj -triple=powerpc - -o %t1.o
# RUN: ld.lld %t.o %t1.o -o %t # RUN: ld.lld %t.o %t1.o -o %t
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
## R_PPC_REL24 and R_PPC_PLTREL24 are converted to PC relative relocations if the ## R_PPC_REL24 and R_PPC_PLTREL24 are converted to PC relative relocations if the
## symbol is non-preemptable. The addend of R_PPC_PLTREL24 should be ignored. ## symbol is non-preemptable. The addend of R_PPC_PLTREL24 should be ignored.
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: b .+12 # CHECK-NEXT: b .+12
# CHECK-NEXT: b .+8 # CHECK-NEXT: b .+8
# CHECK-NEXT: b .+4 # CHECK-NEXT: b .+4
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: foo: # CHECK-NEXT: <foo>:
.globl _start .globl _start
_start: _start:
b foo # R_PPC_REL24 b foo # R_PPC_REL24
b foo@plt # R_PPC_PLTREL24 b foo@plt # R_PPC_PLTREL24
b foo+32768@plt #_PPC_PLTREL24 with addend b foo+32768@plt #_PPC_PLTREL24 with addend

lld/test/ELF/ppc32-long-thunk.s

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# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefixes=CHECK,PD %s # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefixes=CHECK,PD %s
# RUN: ld.lld -T %t.script -pie %t.o -o %t # RUN: ld.lld -T %t.script -pie %t.o -o %t
# RUN: llvm-readelf -r %t | FileCheck --check-prefix=SEC %s # RUN: llvm-readelf -r %t | FileCheck --check-prefix=SEC %s
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefixes=CHECK,PI %s # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefixes=CHECK,PI %s
# SEC: There are no relocations in this file. # SEC: There are no relocations in this file.
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: 2000: bl .+24 # CHECK-NEXT: 2000: bl .+24
# CHECK-NEXT: bl .+20 # CHECK-NEXT: bl .+20
# CHECK-NEXT: bl .+16 # CHECK-NEXT: bl .+16
# CHECK-NEXT: bl .+33554428 # CHECK-NEXT: bl .+33554428
# PD-NEXT: bl .+24 # PD-NEXT: bl .+24
# PI-NEXT: bl .+40 # PI-NEXT: bl .+40
## high = 0x02002008 = 65536*512+8200 ## high = 0x02002008 = 65536*512+8200
# PD: __LongThunk_high: # PD: <__LongThunk_high>:
# PD-NEXT: 2018: lis 12, 512 # PD-NEXT: 2018: lis 12, 512
# PD-NEXT: addi 12, 12, 8200 # PD-NEXT: addi 12, 12, 8200
# PD-NEXT: mtctr 12 # PD-NEXT: mtctr 12
# PD-NEXT: bctr # PD-NEXT: bctr
## .text_high+16 = 0x02002010 = 65536*512+8208 ## .text_high+16 = 0x02002010 = 65536*512+8208
# PD: __LongThunk_: # PD: <__LongThunk_>:
# PD-NEXT: 2028: lis 12, 512 # PD-NEXT: 2028: lis 12, 512
# PD-NEXT: addi 12, 12, 8208 # PD-NEXT: addi 12, 12, 8208
# PD-NEXT: mtctr 12 # PD-NEXT: mtctr 12
# PD-NEXT: bctr # PD-NEXT: bctr
## high-0x2028 = 0x02002008-0x2020 = 65536*512-24 ## high-0x2028 = 0x02002008-0x2020 = 65536*512-24
# PI: __LongThunk_high: # PI: <__LongThunk_high>:
# PI-NEXT: 2018: mflr 0 # PI-NEXT: 2018: mflr 0
# PI-NEXT: bcl 20, 31, .+4 # PI-NEXT: bcl 20, 31, .+4
# PI-NEXT: 2020: mflr 12 # PI-NEXT: 2020: mflr 12
# PI-NEXT: addis 12, 12, 512 # PI-NEXT: addis 12, 12, 512
# PI-NEXT: addi 12, 12, -24 # PI-NEXT: addi 12, 12, -24
# PI-NEXT: mtlr 0 # PI-NEXT: mtlr 0
# PI-NEXT: mtctr 12 # PI-NEXT: mtctr 12
# PI-NEXT: bctr # PI-NEXT: bctr
## .text_high+16-0x2048 = 0x02002010-0x2048 = 65536*512-48 ## .text_high+16-0x2048 = 0x02002010-0x2048 = 65536*512-48
# PI: __LongThunk_: # PI: <__LongThunk_>:
# PI-NEXT: 2038: mflr 0 # PI-NEXT: 2038: mflr 0
# PI-NEXT: bcl 20, 31, .+4 # PI-NEXT: bcl 20, 31, .+4
# PI-NEXT: 2040: mflr 12 # PI-NEXT: 2040: mflr 12
# PI-NEXT: addis 12, 12, 512 # PI-NEXT: addis 12, 12, 512
# PI-NEXT: addi 12, 12, -48 # PI-NEXT: addi 12, 12, -48
# PI-NEXT: mtlr 0 # PI-NEXT: mtlr 0
# PI-NEXT: mtctr 12 # PI-NEXT: mtctr 12
# PI-NEXT: bctr # PI-NEXT: bctr
.section .text_low, "ax", %progbits .section .text_low, "ax", %progbits
.globl _start .globl _start
_start: _start:
bl high@local # Need a thunk bl high@local # Need a thunk
bl high@local # Need a thunk bl high@local # Need a thunk
bl high+32768@plt # Need a thunk bl high+32768@plt # Need a thunk
bl high bl high
bl .text_high+16 # Need a thunk bl .text_high+16 # Need a thunk
blr blr
# PD: 02002008 high: # PD: 02002008 <high>:
# PD-NEXT: bl .-33554432 # PD-NEXT: bl .-33554432
# PD-NEXT: bl .+4 # PD-NEXT: bl .+4
# PD: __LongThunk_: # PD: <__LongThunk_>:
# PD-NEXT: 2002010: lis 12, 0 # PD-NEXT: 2002010: lis 12, 0
# PD-NEXT: addi 12, 12, 8200 # PD-NEXT: addi 12, 12, 8200
# PD-NEXT: mtctr 12 # PD-NEXT: mtctr 12
# PD-NEXT: bctr # PD-NEXT: bctr
.section .text_high, "ax", %progbits .section .text_high, "ax", %progbits
nop nop
nop nop
.globl high .globl high
high: high:
bl .text_low+8 bl .text_low+8
bl .text_low+8 # Need a thunk bl .text_low+8 # Need a thunk

lld/test/ELF/ppc32-weak-undef-call.s

# REQUIRES: ppc # REQUIRES: ppc
# RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
# RUN: ld.lld %t.o -o %t # RUN: ld.lld %t.o -o %t
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=PDE %s # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=PDE %s
# RUN: ld.lld -pie %t.o -o %t # RUN: ld.lld -pie %t.o -o %t
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=PIC %s # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=PIC %s
# RUN: ld.lld -shared %t.o -o %t # RUN: ld.lld -shared %t.o -o %t
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=PIC %s # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=PIC %s
## It does not really matter how we fixup it, but we cannot overflow and ## It does not really matter how we fixup it, but we cannot overflow and
## should not generate a call stub (this would waste space). ## should not generate a call stub (this would waste space).
# PDE: bl .+0 # PDE: bl .+0
## With -pie or -shared, create a call stub. ld.bfd produces bl .+0 ## With -pie or -shared, create a call stub. ld.bfd produces bl .+0
# PIC: bl .+4 # PIC: bl .+4
# PIC: 00000000.plt_pic32.foo: # PIC: <00000000.plt_pic32.foo>:
.weak foo .weak foo
bl foo bl foo

lld/test/ELF/ppc64-bsymbolic-toc-restore.s

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# CHECK-NEXT: bl .+44 # CHECK-NEXT: bl .+44
# CHECK-NEXT: ld 2, 24(1) # CHECK-NEXT: ld 2, 24(1)
# CHECK-NEXT: add 3, 3, 31 # CHECK-NEXT: add 3, 3, 31
# CHECK-NEXT: addi 1, 1, 32 # CHECK-NEXT: addi 1, 1, 32
# CHECK-NEXT: ld 0, -16(1) # CHECK-NEXT: ld 0, -16(1)
# CHECK-NEXT: mtlr 0 # CHECK-NEXT: mtlr 0
# CHECK-NEXT: blr # CHECK-NEXT: blr
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: def: # CHECK-NEXT: <def>:
# CHECK-NEXT: addis 2, 12, 2 # CHECK-NEXT: addis 2, 12, 2
# CHECK-NEXT: addi 2, 2, -32456 # CHECK-NEXT: addi 2, 2, -32456
# CHECK-NEXT: li 3, 55 # CHECK-NEXT: li 3, 55
# CHECK-NEXT: blr # CHECK-NEXT: blr

lld/test/ELF/ppc64-call-reach.s

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
# CHECK-LABEL: test # CHECK-LABEL: test
# CHECK: 10010014: bl .+33554428 # CHECK: 10010014: bl .+33554428
# CHECK: 10010024: b .+33554428 # CHECK: 10010024: b .+33554428
# NEGOFFSET-LABEL: test # NEGOFFSET-LABEL: test
# NEGOFFSET: 10010014: bl .-33554432 # NEGOFFSET: 10010014: bl .-33554432
# NEGOFFSET: 10010024: b .+33554432 # NEGOFFSET: 10010024: b .+33554432
# THUNK-LABEL: test: # THUNK-LABEL: <test>:
# THUNK: 10010014: bl .+20 # THUNK: 10010014: bl .+20
# THUNK: 10010024: b .+20 # THUNK: 10010024: b .+20
# .branch_lt[0] # .branch_lt[0]
# THUNK-LABEL: __long_branch_callee: # THUNK-LABEL: <__long_branch_callee>:
# THUNK-NEXT: 10010028: addis 12, 2, 1 # THUNK-NEXT: 10010028: addis 12, 2, 1
# THUNK-NEXT: ld 12, -32760(12) # THUNK-NEXT: ld 12, -32760(12)
# THUNK-NEXT: mtctr 12 # THUNK-NEXT: mtctr 12
# THUNK-NEXT: bctr # THUNK-NEXT: bctr
# .branch_lt[1] # .branch_lt[1]
# THUNK-LABEL: __long_branch_tail_callee: # THUNK-LABEL: <__long_branch_tail_callee>:
# THUNK-NEXT: 10010038: addis 12, 2, 1 # THUNK-NEXT: 10010038: addis 12, 2, 1
# THUNK-NEXT: ld 12, -32752(12) # THUNK-NEXT: ld 12, -32752(12)
# THUNK-NEXT: mtctr 12 # THUNK-NEXT: mtctr 12
# THUNK-NEXT: bctr # THUNK-NEXT: bctr
# The offset from the TOC to the .branch_lt section is (-1 << 16) - 32768. # The offset from the TOC to the .branch_lt section is (-1 << 16) - 32768.
# Name Type Address Off Size # Name Type Address Off Size
# BRANCHLT: .got PROGBITS 0000000010020000 020000 000008 # BRANCHLT: .got PROGBITS 0000000010020000 020000 000008
# BRANCHLT: .branch_lt PROGBITS 0000000010030008 020008 000010 # BRANCHLT: .branch_lt PROGBITS 0000000010030008 020008 000010
# BRANCHLT-NOT: .plt # BRANCHLT-NOT: .plt

lld/test/ELF/ppc64-dtprel.s

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
// HEX-LE: section '.got': // HEX-LE: section '.got':
// HEX-LE-NEXT: 4209c8 c8894200 00000000 00000000 00000000 // HEX-LE-NEXT: 4209c8 c8894200 00000000 00000000 00000000
// HEX-LE-NEXT: 4209d8 00000000 00000000 // HEX-LE-NEXT: 4209d8 00000000 00000000
// HEX-BE: section '.got': // HEX-BE: section '.got':
// HEX-BE-NEXT: 4209c8 00000000 004289c8 00000000 00000000 // HEX-BE-NEXT: 4209c8 00000000 004289c8 00000000 00000000
// HEX-BE-NEXT: 4209d8 00000000 00000000 // HEX-BE-NEXT: 4209d8 00000000 00000000
// Dis: test: // Dis: <test>:
// Dis: addi 4, 3, -31744 // Dis: addi 4, 3, -31744
// Dis-NEXT: lwa 4, -31744(3) // Dis-NEXT: lwa 4, -31744(3)
// #k@dtprel(1024 + 4 + 1024 * 1024 * 4) = 0x400404 // #k@dtprel(1024 + 4 + 1024 * 1024 * 4) = 0x400404
// #highesta(k@dtprel) --> ((0x400404 - 0x8000 + 0x8000) >> 48) & 0xffff = 0 // #highesta(k@dtprel) --> ((0x400404 - 0x8000 + 0x8000) >> 48) & 0xffff = 0
// #highera(k@dtprel) --> ((0x400404 - 0x8000 + 0x8000) >> 32) & 0xffff = 0 // #highera(k@dtprel) --> ((0x400404 - 0x8000 + 0x8000) >> 32) & 0xffff = 0
// #ha(k@dtprel) --> ((0x400404 - 0x8000 + 0x8000) >> 16) & 0xffff = 64 // #ha(k@dtprel) --> ((0x400404 - 0x8000 + 0x8000) >> 16) & 0xffff = 64
// #lo(k@dtprel) --> ((0x400404 - 0x8000) & 0xffff = -31740 // #lo(k@dtprel) --> ((0x400404 - 0x8000) & 0xffff = -31740
// Dis: test_adjusted: // Dis: <test_adjusted>:
// Dis: lis 4, 0 // Dis: lis 4, 0
// Dis: ori 4, 4, 0 // Dis: ori 4, 4, 0
// Dis: lis 5, 64 // Dis: lis 5, 64
// Dis: addi 5, 5, -31740 // Dis: addi 5, 5, -31740
// #highest(k@dtprel) --> ((0x400404 - 0x8000) >> 48) & 0xffff = 0 // #highest(k@dtprel) --> ((0x400404 - 0x8000) >> 48) & 0xffff = 0
// #higher(k@dtprel) --> ((0x400404 - 0x8000) >> 32) & 0xffff = 0 // #higher(k@dtprel) --> ((0x400404 - 0x8000) >> 32) & 0xffff = 0
// #hi(k@dtprel) --> ((0x400404 - 0x8000) >> 16) & 0xffff = 63 // #hi(k@dtprel) --> ((0x400404 - 0x8000) >> 16) & 0xffff = 63
// #lo(k@dtprel) --> ((0x400404 - 0x8000) & 0xffff = 33796 // #lo(k@dtprel) --> ((0x400404 - 0x8000) & 0xffff = 33796
// Dis: test_not_adjusted: // Dis: <test_not_adjusted>:
// Dis: lis 4, 0 // Dis: lis 4, 0
// Dis: ori 4, 4, 0 // Dis: ori 4, 4, 0
// Dis: oris 4, 4, 63 // Dis: oris 4, 4, 63
// Dis: ori 4, 4, 33796 // Dis: ori 4, 4, 33796

lld/test/ELF/ppc64-func-entry-points.s

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
glob: glob:
.long 10 # 0xa .long 10 # 0xa
.size glob, 4 .size glob, 4
# Check that foo_external_diff has a global entry point and we branch to # Check that foo_external_diff has a global entry point and we branch to
# foo_external_diff+8. Also check that foo_external_same has no global entry # foo_external_diff+8. Also check that foo_external_same has no global entry
# point and we branch to start of foo_external_same. # point and we branch to start of foo_external_same.
// CHECK-LABEL: _start: // CHECK-LABEL: <_start>:
// CHECK: 100101f0: bl .+144 // CHECK: 100101f0: bl .+144
// CHECK: 10010204: bl .+84 // CHECK: 10010204: bl .+84
// CHECK-LABEL: foo_external_diff: // CHECK-LABEL: <foo_external_diff>:
// CHECK-NEXT: 10010250: addis 2, 12, 2 // CHECK-NEXT: 10010250: addis 2, 12, 2
// CHECK-NEXT: 10010254: addi 2, 2, -32696 // CHECK-NEXT: 10010254: addi 2, 2, -32696
// CHECK-NEXT: 10010258: addis 5, 2, 1 // CHECK-NEXT: 10010258: addis 5, 2, 1
// CHECK-LABEL: foo_external_same: // CHECK-LABEL: <foo_external_same>:
// CHECK-NEXT: 10010280: add 3, 4, 3 // CHECK-NEXT: 10010280: add 3, 4, 3

lld/test/ELF/ppc64-ifunc.s

Show All 18 Lines
# SYM: 0000000010010284 0 FUNC GLOBAL DEFAULT 3 ifunc1 # SYM: 0000000010010284 0 FUNC GLOBAL DEFAULT 3 ifunc1
# SYM: 0000000010010210 0 IFUNC GLOBAL DEFAULT 2 ifunc2 # SYM: 0000000010010210 0 IFUNC GLOBAL DEFAULT 2 ifunc2
# SYM: 0000000010010274 0 FUNC GLOBAL DEFAULT 3 ifunc3 # SYM: 0000000010010274 0 FUNC GLOBAL DEFAULT 3 ifunc3
# SECTIONS: .plt NOBITS 00000000100302a0 0002a0 000018 00 WA 0 0 8 # SECTIONS: .plt NOBITS 00000000100302a0 0002a0 000018 00 WA 0 0 8
# __plt_ifunc - . = 0x10010218 - 0x10010208 = 16 # __plt_ifunc - . = 0x10010218 - 0x10010208 = 16
# __plt_ifunc2 - . = 0x1001022c - 0x10010210 = 28 # __plt_ifunc2 - . = 0x1001022c - 0x10010210 = 28
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: addis 2, 12, 2 # CHECK-NEXT: addis 2, 12, 2
# CHECK-NEXT: addi 2, 2, -32636 # CHECK-NEXT: addi 2, 2, -32636
# CHECK-NEXT: 1001021c: bl .+32 # CHECK-NEXT: 1001021c: bl .+32
# CHECK-NEXT: ld 2, 24(1) # CHECK-NEXT: ld 2, 24(1)
# CHECK-NEXT: 10010224: bl .+44 # CHECK-NEXT: 10010224: bl .+44
# CHECK-NEXT: ld 2, 24(1) # CHECK-NEXT: ld 2, 24(1)
# CHECK-NEXT: addis 3, 2, -2 # CHECK-NEXT: addis 3, 2, -2
# CHECK-NEXT: addi 3, 3, 32748 # CHECK-NEXT: addi 3, 3, 32748
# CHECK-NEXT: addis 3, 2, -2 # CHECK-NEXT: addis 3, 2, -2
# CHECK-NEXT: addi 3, 3, 32732 # CHECK-NEXT: addi 3, 3, 32732
# .plt[0] - .TOC. = 0x100302a0 - 0x10028298 = (1<<16) - 32760 # .plt[0] - .TOC. = 0x100302a0 - 0x10028298 = (1<<16) - 32760
# CHECK: __plt_ifunc2: # CHECK: <__plt_ifunc2>:
# CHECK-NEXT: std 2, 24(1) # CHECK-NEXT: std 2, 24(1)
# CHECK-NEXT: addis 12, 2, 1 # CHECK-NEXT: addis 12, 2, 1
# CHECK-NEXT: ld 12, -32760(12) # CHECK-NEXT: ld 12, -32760(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# .plt[1] - .TOC. = 0x100302a0+8 - 0x10028298 = (1<<16) - 32752 # .plt[1] - .TOC. = 0x100302a0+8 - 0x10028298 = (1<<16) - 32752
# CHECK: __plt_ifunc3: # CHECK: <__plt_ifunc3>:
# CHECK-NEXT: std 2, 24(1) # CHECK-NEXT: std 2, 24(1)
# CHECK-NEXT: addis 12, 2, 1 # CHECK-NEXT: addis 12, 2, 1
# CHECK-NEXT: ld 12, -32752(12) # CHECK-NEXT: ld 12, -32752(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# CHECK-EMPTY: # CHECK-EMPTY:
## .glink has 3 IPLT entries for ifunc1, ifunc2 and ifunc3. ## .glink has 3 IPLT entries for ifunc1, ifunc2 and ifunc3.
## ifunc2 and ifunc3 have the same code sequence as their PLT call stubs. ## ifunc2 and ifunc3 have the same code sequence as their PLT call stubs.
# CHECK: Disassembly of section .glink: # CHECK: Disassembly of section .glink:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 0000000010010264 .glink: # CHECK-NEXT: 0000000010010264 <.glink>:
# CHECK-NEXT: addis 12, 2, 1 # CHECK-NEXT: addis 12, 2, 1
# CHECK-NEXT: ld 12, -32760(12) # CHECK-NEXT: ld 12, -32760(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 0000000010010274 ifunc3: # CHECK-NEXT: 0000000010010274 <ifunc3>:
# CHECK-NEXT: addis 12, 2, 1 # CHECK-NEXT: addis 12, 2, 1
# CHECK-NEXT: ld 12, -32752(12) # CHECK-NEXT: ld 12, -32752(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 0000000010010284 ifunc1: # CHECK-NEXT: 0000000010010284 <ifunc1>:
# CHECK-NEXT: addis 12, 2, 1 # CHECK-NEXT: addis 12, 2, 1
# CHECK-NEXT: ld 12, -32744(12) # CHECK-NEXT: ld 12, -32744(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
## Check that we emit 3 R_PPC64_IRELATIVE in .rela.dyn. ## Check that we emit 3 R_PPC64_IRELATIVE in .rela.dyn.
# REL: .rela.dyn { # REL: .rela.dyn {
# REL-NEXT: 0x100302A0 R_PPC64_IRELATIVE - 0x10010210 # REL-NEXT: 0x100302A0 R_PPC64_IRELATIVE - 0x10010210
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lld/test/ELF/ppc64-local-dynamic.s

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// #ha(i@got@tlsld) --> (0x20108 - 0x28100 + 0x8000) >> 16 = 0 // #ha(i@got@tlsld) --> (0x20108 - 0x28100 + 0x8000) >> 16 = 0
// #lo(i@got@tlsld) --> (0x20108 - 0x28100) = -7ff8 = -32760 // #lo(i@got@tlsld) --> (0x20108 - 0x28100) = -7ff8 = -32760
// When calculating offset relative to the dynamic thread pointer we have to // When calculating offset relative to the dynamic thread pointer we have to
// adjust by 0x8000 since each DTV pointer points 0x8000 bytes past the start of // adjust by 0x8000 since each DTV pointer points 0x8000 bytes past the start of
// its TLS block. // its TLS block.
// #ha(i@dtprel) --> (0x0 -0x8000 + 0x8000) >> 16 = 0 // #ha(i@dtprel) --> (0x0 -0x8000 + 0x8000) >> 16 = 0
// #lo(i@dtprel) --> (0x0 -0x8000) = -0x8000 = -32768 // #lo(i@dtprel) --> (0x0 -0x8000) = -0x8000 = -32768
// Dis: test: // Dis: <test>:
// Dis: addis 3, 2, 0 // Dis: addis 3, 2, 0
// Dis-NEXT: addi 3, 3, -32760 // Dis-NEXT: addi 3, 3, -32760
// Dis-NEXT: bl .+60 // Dis-NEXT: bl .+60
// Dis-NEXT: ld 2, 24(1) // Dis-NEXT: ld 2, 24(1)
// Dis-NEXT: addis 3, 3, 0 // Dis-NEXT: addis 3, 3, 0
// Dis-NEXT: lwa 3, -32768(3) // Dis-NEXT: lwa 3, -32768(3)
// #hi(j@got@tlsld) --> (0x20108 - 0x28100 ) > 16 = -1 // #hi(j@got@tlsld) --> (0x20108 - 0x28100 ) > 16 = -1
// Dis: test_hi: // Dis: <test_hi>:
// Dis: lis 3, -1 // Dis: lis 3, -1
// k@got@tlsld --> (0x20108 - 0x28100) = -7ff8 = -32760 // k@got@tlsld --> (0x20108 - 0x28100) = -7ff8 = -32760
// Dis: test_16: // Dis: <test_16>:
// Dis: li 3, -32760 // Dis: li 3, -32760

lld/test/ELF/ppc64-local-exec-tls.s

Show First 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
// InputRelocs: R_PPC64_TPREL16_HIGHERA {{0+8}} b + 0 // InputRelocs: R_PPC64_TPREL16_HIGHERA {{0+8}} b + 0
// InputRelocs: R_PPC64_TPREL16_HIGHEST {{0+8}} b + 0 // InputRelocs: R_PPC64_TPREL16_HIGHEST {{0+8}} b + 0
// InputRelocs: R_PPC64_TPREL16_HIGHER {{0+8}} b + 0 // InputRelocs: R_PPC64_TPREL16_HIGHER {{0+8}} b + 0
// The start of the TLS storage area is 0x7000 bytes before the thread pointer (r13). // The start of the TLS storage area is 0x7000 bytes before the thread pointer (r13).
// We are building the address of the first TLS variable, relative to the thread pointer. // We are building the address of the first TLS variable, relative to the thread pointer.
// #ha(a@tprel) --> (0 - 0x7000 + 0x8000) >> 16 = 0 // #ha(a@tprel) --> (0 - 0x7000 + 0x8000) >> 16 = 0
// #lo(a@tprel)) --> (0 - 0x7000) & 0xFFFF = -0x7000 = -28672 // #lo(a@tprel)) --> (0 - 0x7000) & 0xFFFF = -0x7000 = -28672
// Dis: test_local_exec: // Dis: <test_local_exec>:
// Dis: addis 3, 13, 0 // Dis: addis 3, 13, 0
// Dis: addi 3, 3, -28672 // Dis: addi 3, 3, -28672
// We are building the offset for the second TLS variable // We are building the offset for the second TLS variable
// Offset within tls storage - 0x7000 // Offset within tls storage - 0x7000
// b@tprel = 8 - 0x7000 = 28664 // b@tprel = 8 - 0x7000 = 28664
// Dis: test_tprel: // Dis: <test_tprel>:
// Dis: addi 3, 13, -28664 // Dis: addi 3, 13, -28664
// #hi(b@tprel) --> (8 - 0x7000) >> 16 = -1 // #hi(b@tprel) --> (8 - 0x7000) >> 16 = -1
// Dis: test_hi: // Dis: <test_hi>:
// Dis: addis 3, 13, -1 // Dis: addis 3, 13, -1
// b@tprel = 8 - 0x7000 = -28664 // b@tprel = 8 - 0x7000 = -28664
// Dis: test_ds: // Dis: <test_ds>:
// Dis: ld 3, -28664(13) // Dis: ld 3, -28664(13)
// #lo(b@tprel) --> (8 - 0x7000) & 0xFFFF = -28664 // #lo(b@tprel) --> (8 - 0x7000) & 0xFFFF = -28664
// Dis: test_lo_ds: // Dis: <test_lo_ds>:
// Dis: ld 3, -28664(13) // Dis: ld 3, -28664(13)
// #highesta(b@tprel) --> ((0x8 - 0x7000 + 0x8000) >> 48) & 0xFFFF = 0 // #highesta(b@tprel) --> ((0x8 - 0x7000 + 0x8000) >> 48) & 0xFFFF = 0
// #highera(b@tprel) --> ((0x8 - 0x7000 + 0x8000) >> 32) & 0xFFFF = 0 // #highera(b@tprel) --> ((0x8 - 0x7000 + 0x8000) >> 32) & 0xFFFF = 0
// #ha(k@dtprel) --> ((0x8 - 0x7000 + 0x8000) >> 16) & 0xFFFF = 0 // #ha(k@dtprel) --> ((0x8 - 0x7000 + 0x8000) >> 16) & 0xFFFF = 0
// #lo(k@dtprel) --> ((0x8 - 0x7000) & 0xFFFF = -28664 // #lo(k@dtprel) --> ((0x8 - 0x7000) & 0xFFFF = -28664
// Dis: test_highest_a: // Dis: <test_highest_a>:
// Dis: lis 4, 0 // Dis: lis 4, 0
// Dis: ori 4, 4, 0 // Dis: ori 4, 4, 0
// Dis: lis 5, 0 // Dis: lis 5, 0
// Dis: addi 5, 5, -28664 // Dis: addi 5, 5, -28664
// #highest(b@tprel) --> ((0x8 - 0x7000) >> 48) & 0xFFFF = 0xFFFF = -1 // #highest(b@tprel) --> ((0x8 - 0x7000) >> 48) & 0xFFFF = 0xFFFF = -1
// #higher(b@tprel) --> ((0x8 - 0x7000) >> 32) & 0xFFFF = 0xFFFF = 65535 // #higher(b@tprel) --> ((0x8 - 0x7000) >> 32) & 0xFFFF = 0xFFFF = 65535
// #hi(k@dtprel) --> ((0x8 - 0x7000) >> 16) & 0xFFFF = 0xFFFF = 65535 // #hi(k@dtprel) --> ((0x8 - 0x7000) >> 16) & 0xFFFF = 0xFFFF = 65535
// #lo(k@dtprel) --> ((0x8 - 0x7000) & 0xFFFF = 33796 // #lo(k@dtprel) --> ((0x8 - 0x7000) & 0xFFFF = 33796
// Dis: test_highest: // Dis: <test_highest>:
// Dis: lis 4, -1 // Dis: lis 4, -1
// Dis: ori 4, 4, 65535 // Dis: ori 4, 4, 65535
// Dis: oris 4, 4, 65535 // Dis: oris 4, 4, 65535
// Dis: ori 4, 4, 36872 // Dis: ori 4, 4, 36872

lld/test/ELF/ppc64-long-branch-init.s

# REQUIRES: ppc # REQUIRES: ppc
# RUN: llvm-mc -filetype=obj -triple=powerpc64-pc-freebsd13.0 %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=powerpc64-pc-freebsd13.0 %s -o %t.o
# RUN: ld.lld %t.o -o %t # RUN: ld.lld %t.o -o %t
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
## .init consists of sections from several object files. Sections other than the ## .init consists of sections from several object files. Sections other than the
## last one do not have a terminator. Check we do not create a long branch stub ## last one do not have a terminator. Check we do not create a long branch stub
## in the middle. ## in the middle.
## We currently use thunk section spacing to ensure the stub is in the end. This ## We currently use thunk section spacing to ensure the stub is in the end. This
## is not foolproof but good enough to not break in practice. ## is not foolproof but good enough to not break in practice.
# CHECK: Disassembly of section .init: # CHECK: Disassembly of section .init:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-LABEL: _init: # CHECK-LABEL: <_init>:
# CHECK: blr # CHECK: blr
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-LABEL: __long_branch_foo: # CHECK-LABEL: <__long_branch_foo>:
.globl foo .globl foo
foo: foo:
.space 0x2000000 .space 0x2000000
blr blr
.section .init,"ax",@progbits,unique,0 .section .init,"ax",@progbits,unique,0
.globl _init .globl _init
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lld/test/ELF/ppc64-long-branch-pi.s

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# RELOC: .rela.dyn { # RELOC: .rela.dyn {
# RELOC-NEXT: 0x20020E8 R_PPC64_RELATIVE - 0x8000 # RELOC-NEXT: 0x20020E8 R_PPC64_RELATIVE - 0x8000
# RELOC-NEXT: 0x20020F0 R_PPC64_RELATIVE - 0x2002000 # RELOC-NEXT: 0x20020F0 R_PPC64_RELATIVE - 0x2002000
# RELOC-NEXT: 0x20020F8 R_PPC64_RELATIVE - 0x2002008 # RELOC-NEXT: 0x20020F8 R_PPC64_RELATIVE - 0x2002008
# RELOC-NEXT: 0x2002100 R_PPC64_RELATIVE - 0x200200C # RELOC-NEXT: 0x2002100 R_PPC64_RELATIVE - 0x200200C
# RELOC-NEXT: 0x2002108 R_PPC64_RELATIVE - 0x2000 # RELOC-NEXT: 0x2002108 R_PPC64_RELATIVE - 0x2000
# RELOC-NEXT: } # RELOC-NEXT: }
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: 2000: bl .+16 # CHECK-NEXT: 2000: bl .+16
# CHECK-NEXT: bl .+33554428 # CHECK-NEXT: bl .+33554428
# CHECK-NEXT: bl .+24 # CHECK-NEXT: bl .+24
# CHECK-NEXT: bl .+36 # CHECK-NEXT: bl .+36
## &.branch_lt[0] - .TOC. = .branch_lt - (.got+0x8000) = -32752 ## &.branch_lt[0] - .TOC. = .branch_lt - (.got+0x8000) = -32752
# CHECK: __long_branch_: # CHECK: <__long_branch_>:
# CHECK-NEXT: 2010: addis 12, 2, 0 # CHECK-NEXT: 2010: addis 12, 2, 0
# CHECK-NEXT: ld 12, -32752(12) # CHECK-NEXT: ld 12, -32752(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
## &.branch_lt[1] - .TOC. = .branch_lt - (.got+0x8000) = -32744 ## &.branch_lt[1] - .TOC. = .branch_lt - (.got+0x8000) = -32744
# CHECK: __long_branch_: # CHECK: <__long_branch_>:
# CHECK-NEXT: 2020: addis 12, 2, 0 # CHECK-NEXT: 2020: addis 12, 2, 0
# CHECK-NEXT: ld 12, -32744(12) # CHECK-NEXT: ld 12, -32744(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
## &.branch_lt[2] - .TOC. = .branch_lt - (.got+0x8000) = -32736 ## &.branch_lt[2] - .TOC. = .branch_lt - (.got+0x8000) = -32736
# CHECK: __long_branch_: # CHECK: <__long_branch_>:
# CHECK-NEXT: 2030: addis 12, 2, 0 # CHECK-NEXT: 2030: addis 12, 2, 0
# CHECK-NEXT: ld 12, -32736(12) # CHECK-NEXT: ld 12, -32736(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
.section .text_low, "ax", %progbits .section .text_low, "ax", %progbits
.globl _start .globl _start
_start: _start:
bl .text_high # Need a thunk bl .text_high # Need a thunk
bl .text_high bl .text_high
bl .text_high+8 # Need a thunk bl .text_high+8 # Need a thunk
bl .text_high+0xc # Need a thunk bl .text_high+0xc # Need a thunk
# CHECK: high_target: # CHECK: <high_target>:
# CHECK-NEXT: 2002000: bl .-33554428 # CHECK-NEXT: 2002000: bl .-33554428
# CHECK-NEXT: bl .-33554432 # CHECK-NEXT: bl .-33554432
# CHECK-NEXT: bl .+8 # CHECK-NEXT: bl .+8
## &.branch_lt[3] - .TOC. = .branch_lt - (.got+0x8000) = -32728 ## &.branch_lt[3] - .TOC. = .branch_lt - (.got+0x8000) = -32728
# CHECK: __long_branch_: # CHECK: <__long_branch_>:
# CHECK-NEXT: 2002010: addis 12, 2, 0 # CHECK-NEXT: 2002010: addis 12, 2, 0
# CHECK-NEXT: ld 12, -32728(12) # CHECK-NEXT: ld 12, -32728(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
.section .text_high, "ax", %progbits .section .text_high, "ax", %progbits
high_target: high_target:
bl .text_low+4 bl .text_low+4
bl .text_low+4 bl .text_low+4
bl .text_low # Need a thunk bl .text_low # Need a thunk
blr blr
## Force creation of .got ## Force creation of .got
## The R_PPC64_RELATIVE makes sure .rela.dyn survives removeUnusedSyntheticSections. ## The R_PPC64_RELATIVE makes sure .rela.dyn survives removeUnusedSyntheticSections.
.section .data .section .data
.quad .TOC.@tocbase .quad .TOC.@tocbase

lld/test/ELF/ppc64-long-branch.s

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# SEC: There are no relocations in this file. # SEC: There are no relocations in this file.
## high@localentry (high+8), .text_high+16 and .text_low+8 ## high@localentry (high+8), .text_high+16 and .text_low+8
# BRANCH-LE: 0x02002030 08200002 00000000 10200002 00000000 # BRANCH-LE: 0x02002030 08200002 00000000 10200002 00000000
# BRANCH-LE-NEXT: 0x02002040 08200000 00000000 # BRANCH-LE-NEXT: 0x02002040 08200000 00000000
# BRANCH-BE: 0x02002030 00000000 02002008 00000000 02002010 # BRANCH-BE: 0x02002030 00000000 02002008 00000000 02002010
# BRANCH-BE-NEXT: 0x02002040 00000000 00002008 # BRANCH-BE-NEXT: 0x02002040 00000000 00002008
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: 2000: bl .+24 # CHECK-NEXT: 2000: bl .+24
# CHECK-NEXT: bl .+20 # CHECK-NEXT: bl .+20
# CHECK-NEXT: bl .+16 # CHECK-NEXT: bl .+16
# CHECK-NEXT: bl .+33554428 # CHECK-NEXT: bl .+33554428
## &.branch_lt[0] - .TOC. = .branch_lt - (.got+0x8000) = -32760 ## &.branch_lt[0] - .TOC. = .branch_lt - (.got+0x8000) = -32760
# CHECK: __long_branch_high: # CHECK: <__long_branch_high>:
# CHECK-NEXT: 2018: addis 12, 2, 0 # CHECK-NEXT: 2018: addis 12, 2, 0
# CHECK-NEXT: ld 12, -32760(12) # CHECK-NEXT: ld 12, -32760(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
## &.branch_lt[1] - .TOC. = .branch_lt - (.got+0x8000) = -32752 ## &.branch_lt[1] - .TOC. = .branch_lt - (.got+0x8000) = -32752
# CHECK: __long_branch_: # CHECK: <__long_branch_>:
# CHECK-NEXT: 2028: addis 12, 2, 0 # CHECK-NEXT: 2028: addis 12, 2, 0
# CHECK-NEXT: ld 12, -32752(12) # CHECK-NEXT: ld 12, -32752(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
.section .text_low, "ax", %progbits .section .text_low, "ax", %progbits
.globl _start .globl _start
_start: _start:
bl high # Need a thunk bl high # Need a thunk
bl high # Need a thunk bl high # Need a thunk
bl high # Need a thunk bl high # Need a thunk
bl high bl high
bl .text_high+16 # Need a thunk bl .text_high+16 # Need a thunk
blr blr
# CHECK: Disassembly of section .text_high: # CHECK: Disassembly of section .text_high:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: high: # CHECK-NEXT: <high>:
# CHECK-NEXT: 2002000: addis 2, 12, 1 # CHECK-NEXT: 2002000: addis 2, 12, 1
# CHECK-NEXT: addi 2, 2, -32728 # CHECK-NEXT: addi 2, 2, -32728
# CHECK-NEXT: bl .-33554432 # CHECK-NEXT: bl .-33554432
# CHECK-NEXT: bl .+8 # CHECK-NEXT: bl .+8
# CHECK: __long_branch_: # CHECK: <__long_branch_>:
# CHECK-NEXT: 2002014: addis 12, 2, 0 # CHECK-NEXT: 2002014: addis 12, 2, 0
# CHECK-NEXT: ld 12, -32744(12) # CHECK-NEXT: ld 12, -32744(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
.section .text_high, "ax", %progbits .section .text_high, "ax", %progbits
.globl high .globl high
high: high:
addis 2, 12, .TOC.-high@ha addis 2, 12, .TOC.-high@ha
addi 2, 2, .TOC.-high@l addi 2, 2, .TOC.-high@l
.localentry high, 8 .localentry high, 8
bl .text_low+8 bl .text_low+8
bl .text_low+8 # Need a thunk bl .text_low+8 # Need a thunk
blr blr

lld/test/ELF/ppc64-plt-stub.s

Show All 17 Lines
# SEC: .plt NOBITS 00000000100303e8 0003e8 000018 # SEC: .plt NOBITS 00000000100303e8 0003e8 000018
# SEC: 0x0000000000000003 (PLTGOT) 0x100303e8 # SEC: 0x0000000000000003 (PLTGOT) 0x100303e8
## .plt[0] holds the address of _dl_runtime_resolve. ## .plt[0] holds the address of _dl_runtime_resolve.
## .plt[1] holds the link map. ## .plt[1] holds the link map.
## The JMP_SLOT relocation is stored at .plt[2] ## The JMP_SLOT relocation is stored at .plt[2]
# RELOC: 0x10030010 R_PPC64_JMP_SLOT foo 0x0 # RELOC: 0x10030010 R_PPC64_JMP_SLOT foo 0x0
# CHECK: _start: # CHECK: <_start>:
# CHECK: 10010298: bl .+16 # CHECK: 10010298: bl .+16
# CHECK-LABEL: 00000000100102a8 __plt_foo: # CHECK-LABEL: 00000000100102a8 <__plt_foo>:
# CHECK-NEXT: std 2, 24(1) # CHECK-NEXT: std 2, 24(1)
# CHECK-NEXT: addis 12, 2, 1 # CHECK-NEXT: addis 12, 2, 1
# CHECK-NEXT: ld 12, -32744(12) # CHECK-NEXT: ld 12, -32744(12)
# CHECK-NEXT: mtctr 12 # CHECK-NEXT: mtctr 12
# CHECK-NEXT: bctr # CHECK-NEXT: bctr
.text .text
Show All 16 Lines

lld/test/ELF/ppc64-tls-ie.s

Show All 27 Lines
# IE-REL-NEXT: 0x204B8 R_PPC64_TPREL64 l 0x0 # IE-REL-NEXT: 0x204B8 R_PPC64_TPREL64 l 0x0
# IE-REL-NEXT: 0x204A8 R_PPC64_TPREL64 s 0x0 # IE-REL-NEXT: 0x204A8 R_PPC64_TPREL64 s 0x0
# IE-REL-NEXT: } # IE-REL-NEXT: }
# INPUT-REL: R_PPC64_GOT_TPREL16_HA c 0x0 # INPUT-REL: R_PPC64_GOT_TPREL16_HA c 0x0
# INPUT-REL: R_PPC64_GOT_TPREL16_LO_DS c 0x0 # INPUT-REL: R_PPC64_GOT_TPREL16_LO_DS c 0x0
# INPUT-REL: R_PPC64_TLS c 0x0 # INPUT-REL: R_PPC64_TLS c 0x0
## &.got[0] - .TOC. = -32768 ## &.got[0] - .TOC. = -32768
# IE-LABEL: test1: # IE-LABEL: <test1>:
# IE-NEXT: addis 3, 2, 0 # IE-NEXT: addis 3, 2, 0
# IE-NEXT: ld 3, -32768(3) # IE-NEXT: ld 3, -32768(3)
# IE-NEXT: lbzx 3, 3, 13 # IE-NEXT: lbzx 3, 3, 13
# LE-LABEL: test1: # LE-LABEL: <test1>:
# LE-NEXT: nop # LE-NEXT: nop
# LE-NEXT: addis 3, 13, 0 # LE-NEXT: addis 3, 13, 0
# LE-NEXT: lbz 3, -28672(3) # LE-NEXT: lbz 3, -28672(3)
test1: test1:
addis 3, 2, c@got@tprel@ha addis 3, 2, c@got@tprel@ha
ld 3, c@got@tprel@l(3) ld 3, c@got@tprel@l(3)
lbzx 3, 3, c@tls lbzx 3, 3, c@tls
# INPUT-REL: R_PPC64_GOT_TPREL16_HA s 0x0 # INPUT-REL: R_PPC64_GOT_TPREL16_HA s 0x0
# INPUT-REL: R_PPC64_GOT_TPREL16_LO_DS s 0x0 # INPUT-REL: R_PPC64_GOT_TPREL16_LO_DS s 0x0
# INPUT-REL: R_PPC64_TLS s 0x0 # INPUT-REL: R_PPC64_TLS s 0x0
## &.got[1] - .TOC. = -32760 ## &.got[1] - .TOC. = -32760
# IE-LABEL: test2: # IE-LABEL: <test2>:
# IE-NEXT: addis 3, 2, 0 # IE-NEXT: addis 3, 2, 0
# IE-NEXT: ld 3, -32760(3) # IE-NEXT: ld 3, -32760(3)
# IE-NEXT: lhzx 3, 3, 13 # IE-NEXT: lhzx 3, 3, 13
# LE-LABEL: test2: # LE-LABEL: <test2>:
# LE-NEXT: nop # LE-NEXT: nop
# LE-NEXT: addis 3, 13, 0 # LE-NEXT: addis 3, 13, 0
# LE-NEXT: lhz 3, -28670(3) # LE-NEXT: lhz 3, -28670(3)
test2: test2:
addis 3, 2, s@got@tprel@ha addis 3, 2, s@got@tprel@ha
ld 3, s@got@tprel@l(3) ld 3, s@got@tprel@l(3)
lhzx 3, 3, s@tls lhzx 3, 3, s@tls
# INPUT-REL: R_PPC64_GOT_TPREL16_HA i 0x0 # INPUT-REL: R_PPC64_GOT_TPREL16_HA i 0x0
# INPUT-REL: R_PPC64_GOT_TPREL16_LO_DS i 0x0 # INPUT-REL: R_PPC64_GOT_TPREL16_LO_DS i 0x0
# INPUT-REL: R_PPC64_TLS i 0x0 # INPUT-REL: R_PPC64_TLS i 0x0
## &.got[2] - .TOC. = -32752 ## &.got[2] - .TOC. = -32752
# IE-LABEL: test3: # IE-LABEL: <test3>:
# IE-NEXT: addis 3, 2, 0 # IE-NEXT: addis 3, 2, 0
# IE-NEXT: ld 3, -32752(3) # IE-NEXT: ld 3, -32752(3)
# IE-NEXT: lwzx 3, 3, 13 # IE-NEXT: lwzx 3, 3, 13
# LE-LABEL: test3: # LE-LABEL: <test3>:
# LE-NEXT: nop # LE-NEXT: nop
# LE-NEXT: addis 3, 13, 0 # LE-NEXT: addis 3, 13, 0
# LE-NEXT: lwz 3, -28668(3) # LE-NEXT: lwz 3, -28668(3)
test3: test3:
addis 3, 2, i@got@tprel@ha addis 3, 2, i@got@tprel@ha
ld 3, i@got@tprel@l(3) ld 3, i@got@tprel@l(3)
lwzx 3, 3, i@tls lwzx 3, 3, i@tls
# INPUT-REL: R_PPC64_GOT_TPREL16_HA l 0x0 # INPUT-REL: R_PPC64_GOT_TPREL16_HA l 0x0
# INPUT-REL: R_PPC64_GOT_TPREL16_LO_DS l 0x0 # INPUT-REL: R_PPC64_GOT_TPREL16_LO_DS l 0x0
# INPUT-REL: R_PPC64_TLS l 0x0 # INPUT-REL: R_PPC64_TLS l 0x0
## &.got[3] - .TOC. = -32744 ## &.got[3] - .TOC. = -32744
# IE-LABEL: test4: # IE-LABEL: <test4>:
# IE-NEXT: addis 3, 2, 0 # IE-NEXT: addis 3, 2, 0
# IE-NEXT: ld 3, -32744(3) # IE-NEXT: ld 3, -32744(3)
# IE-NEXT: ldx 3, 3, 13 # IE-NEXT: ldx 3, 3, 13
# LE-LABEL: test4: # LE-LABEL: <test4>:
# LE-NEXT: nop # LE-NEXT: nop
# LE-NEXT: addis 3, 13, 0 # LE-NEXT: addis 3, 13, 0
# LE-NEXT: ld 3, -28664(3) # LE-NEXT: ld 3, -28664(3)
test4: test4:
addis 3, 2, l@got@tprel@ha addis 3, 2, l@got@tprel@ha
ld 3, l@got@tprel@l(3) ld 3, l@got@tprel@l(3)
ldx 3, 3, l@tls ldx 3, 3, l@tls
# LE-LABEL: test5: # LE-LABEL: <test5>:
# LE-NEXT: nop # LE-NEXT: nop
# LE-NEXT: addis 4, 13, 0 # LE-NEXT: addis 4, 13, 0
# LE-NEXT: stb 3, -28672(4) # LE-NEXT: stb 3, -28672(4)
test5: test5:
addis 4, 2, c@got@tprel@ha addis 4, 2, c@got@tprel@ha
ld 4, c@got@tprel@l(4) ld 4, c@got@tprel@l(4)
stbx 3, 4, c@tls stbx 3, 4, c@tls
# LE-LABEL: test6: # LE-LABEL: <test6>:
# LE-NEXT: nop # LE-NEXT: nop
# LE-NEXT: addis 4, 13, 0 # LE-NEXT: addis 4, 13, 0
# LE-NEXT: sth 3, -28670(4) # LE-NEXT: sth 3, -28670(4)
test6: test6:
addis 4, 2, s@got@tprel@ha addis 4, 2, s@got@tprel@ha
ld 4, s@got@tprel@l(4) ld 4, s@got@tprel@l(4)
sthx 3, 4, s@tls sthx 3, 4, s@tls
# LE-LABEL: test7: # LE-LABEL: <test7>:
# LE-NEXT: nop # LE-NEXT: nop
# LE-NEXT: addis 4, 13, 0 # LE-NEXT: addis 4, 13, 0
# LE-NEXT: stw 3, -28668(4) # LE-NEXT: stw 3, -28668(4)
test7: test7:
addis 4, 2, i@got@tprel@ha addis 4, 2, i@got@tprel@ha
ld 4, i@got@tprel@l(4) ld 4, i@got@tprel@l(4)
stwx 3, 4, i@tls stwx 3, 4, i@tls
# LE-LABEL: test8: # LE-LABEL: <test8>:
# LE-NEXT: nop # LE-NEXT: nop
# LE-NEXT: addis 4, 13, 0 # LE-NEXT: addis 4, 13, 0
# LE-NEXT: std 3, -28664(4) # LE-NEXT: std 3, -28664(4)
test8: test8:
addis 4, 2, l@got@tprel@ha addis 4, 2, l@got@tprel@ha
ld 4, l@got@tprel@l(4) ld 4, l@got@tprel@l(4)
stdx 3, 4, l@tls stdx 3, 4, l@tls
# LE-LABEL: test9: # LE-LABEL: <test9>:
# LE-NEXT: nop # LE-NEXT: nop
# LE-NEXT: addis 3, 13, 0 # LE-NEXT: addis 3, 13, 0
# LE-NEXT: addi 3, 3, -28668 # LE-NEXT: addi 3, 3, -28668
test9: test9:
addis 3, 2, i@got@tprel@ha addis 3, 2, i@got@tprel@ha
ld 3, i@got@tprel@l(3) ld 3, i@got@tprel@l(3)
add 3, 3, i@tls add 3, 3, i@tls
# LE-LABEL: test_ds: # LE-LABEL: <test_ds>:
# LE-NEXT: addis 4, 13, 0 # LE-NEXT: addis 4, 13, 0
# LE-NEXT: std 3, -28664(4) # LE-NEXT: std 3, -28664(4)
test_ds: test_ds:
ld 4, l@got@tprel(2) ld 4, l@got@tprel(2)
stdx 3, 4, l@tls stdx 3, 4, l@tls
# NOREL: There are no relocations in this file. # NOREL: There are no relocations in this file.
Show All 16 Lines

lld/test/ELF/ppc64-tls-ld-le.s

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
// Verify that the input has local-dynamic tls relocation types // Verify that the input has local-dynamic tls relocation types
// InputRelocs: Relocation section '.rela.text' // InputRelocs: Relocation section '.rela.text'
// InputRelocs: R_PPC64_GOT_TLSLD16_HA {{0+}} a + 0 // InputRelocs: R_PPC64_GOT_TLSLD16_HA {{0+}} a + 0
// InputRelocs: R_PPC64_GOT_TLSLD16_LO {{0+}} a + 0 // InputRelocs: R_PPC64_GOT_TLSLD16_LO {{0+}} a + 0
// InputRelocs: R_PPC64_TLSLD {{0+}} a + 0 // InputRelocs: R_PPC64_TLSLD {{0+}} a + 0
// Verify that the local-dynamic sequence is relaxed to local exec. // Verify that the local-dynamic sequence is relaxed to local exec.
// Dis: _start: // Dis: <_start>:
// Dis: nop // Dis: nop
// Dis: addis 3, 13, 0 // Dis: addis 3, 13, 0
// Dis: nop // Dis: nop
// Dis: addi 3, 3, 4096 // Dis: addi 3, 3, 4096
// #ha(a@dtprel) --> (0x0 -0x8000 + 0x8000) >> 16 = 0 // #ha(a@dtprel) --> (0x0 -0x8000 + 0x8000) >> 16 = 0
// #lo(a@dtprel) --> (0x0 -0x8000) = -0x8000 = -32768 // #lo(a@dtprel) --> (0x0 -0x8000) = -0x8000 = -32768
// Dis: addis 3, 3, 0 // Dis: addis 3, 3, 0
// Dis: addi 3, 3, -32768 // Dis: addi 3, 3, -32768
// Verify that no local-dynamic relocations exist for the dynamic linker. // Verify that no local-dynamic relocations exist for the dynamic linker.
// OutputRelocs-NOT: R_PPC64_DTPMOD64 // OutputRelocs-NOT: R_PPC64_DTPMOD64

lld/test/ELF/ppc64-toc-addis-nop.s

Show All 32 Lines.Lbytes_gep:
addi 2, 2, .TOC.-.Lbytes_gep@l addi 2, 2, .TOC.-.Lbytes_gep@l
.Lbytes_lep: .Lbytes_lep:
.localentry bytes, .Lbytes_lep-.Lbytes_gep .localentry bytes, .Lbytes_lep-.Lbytes_gep
addis 3, 2, byteLd@toc@ha addis 3, 2, byteLd@toc@ha
lbz 3, byteLd@toc@l(3) lbz 3, byteLd@toc@l(3)
addis 4, 2, byteSt@toc@ha addis 4, 2, byteSt@toc@ha
stb 3, byteSt@toc@l(4) stb 3, byteSt@toc@l(4)
blr blr
# Dis-LABEL: bytes: # Dis-LABEL: <bytes>:
# Dis-NEXT: addis # Dis-NEXT: addis
# Dis-NEXT: addi # Dis-NEXT: addi
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: lbz 3, -32752(2) # Dis-NEXT: lbz 3, -32752(2)
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: stb 3, -32751(2) # Dis-NEXT: stb 3, -32751(2)
# Dis-NEXT: blr # Dis-NEXT: blr
# NoOpt-LABEL: bytes: # NoOpt-LABEL: <bytes>:
# NoOpt-NEXT: addis # NoOpt-NEXT: addis
# NoOpt-NEXT: addi # NoOpt-NEXT: addi
# NoOpt-NEXT: addis 3, 2, 0 # NoOpt-NEXT: addis 3, 2, 0
# NoOpt-NEXT: lbz 3, -32752(3) # NoOpt-NEXT: lbz 3, -32752(3)
# NoOpt-NEXT: addis 4, 2, 0 # NoOpt-NEXT: addis 4, 2, 0
# NoOpt-NEXT: stb 3, -32751(4) # NoOpt-NEXT: stb 3, -32751(4)
# NoOpt-NEXT: blr # NoOpt-NEXT: blr
.global halfs .global halfs
.p2align 4 .p2align 4
.type halfs,@function .type halfs,@function
halfs: halfs:
.Lhalfs_gep: .Lhalfs_gep:
addis 2, 12, .TOC.-.Lhalfs_gep@ha addis 2, 12, .TOC.-.Lhalfs_gep@ha
addi 2, 2, .TOC.-.Lhalfs_gep@l addi 2, 2, .TOC.-.Lhalfs_gep@l
.Lhalfs_lep: .Lhalfs_lep:
.localentry halfs, .Lhalfs_lep-.Lhalfs_gep .localentry halfs, .Lhalfs_lep-.Lhalfs_gep
addis 3, 2, halfLd@toc@ha addis 3, 2, halfLd@toc@ha
lhz 3, halfLd@toc@l(3) lhz 3, halfLd@toc@l(3)
addis 4, 2, halfLd@toc@ha addis 4, 2, halfLd@toc@ha
lha 4, halfLd@toc@l(4) lha 4, halfLd@toc@l(4)
addis 5, 2, halfSt@toc@ha addis 5, 2, halfSt@toc@ha
sth 4, halfSt@toc@l(5) sth 4, halfSt@toc@l(5)
blr blr
# Dis-LABEL: halfs: # Dis-LABEL: <halfs>:
# Dis-NEXT: addis # Dis-NEXT: addis
# Dis-NEXT: addi # Dis-NEXT: addi
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: lhz 3, -32750(2) # Dis-NEXT: lhz 3, -32750(2)
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: lha 4, -32750(2) # Dis-NEXT: lha 4, -32750(2)
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: sth 4, -32748(2) # Dis-NEXT: sth 4, -32748(2)
# Dis-NEXT: blr # Dis-NEXT: blr
# NoOpt-LABEL: halfs: # NoOpt-LABEL: <halfs>:
# NoOpt-NEXT: addis # NoOpt-NEXT: addis
# NoOpt-NEXT: addi # NoOpt-NEXT: addi
# NoOpt-NEXT: addis 3, 2, 0 # NoOpt-NEXT: addis 3, 2, 0
# NoOpt-NEXT: lhz 3, -32750(3) # NoOpt-NEXT: lhz 3, -32750(3)
# NoOpt-NEXT: addis 4, 2, 0 # NoOpt-NEXT: addis 4, 2, 0
# NoOpt-NEXT: lha 4, -32750(4) # NoOpt-NEXT: lha 4, -32750(4)
# NoOpt-NEXT: addis 5, 2, 0 # NoOpt-NEXT: addis 5, 2, 0
# NoOpt-NEXT: sth 4, -32748(5) # NoOpt-NEXT: sth 4, -32748(5)
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
.Lvec_dq_lep: .Lvec_dq_lep:
.localentry vec_dq, .Lvec_dq_lep-.Lvec_dq_gep .localentry vec_dq, .Lvec_dq_lep-.Lvec_dq_gep
addis 3, 2, vecLd@toc@ha addis 3, 2, vecLd@toc@ha
lxv 3, vecLd@toc@l(3) lxv 3, vecLd@toc@l(3)
addis 3, 2, vecSt@toc@ha addis 3, 2, vecSt@toc@ha
stxv 3, vecSt@toc@l(3) stxv 3, vecSt@toc@l(3)
blr blr
# Dis-LABEL: vec_dq: # Dis-LABEL: <vec_dq>:
# Dis-NEXT: addis # Dis-NEXT: addis
# Dis-NEXT: addi # Dis-NEXT: addi
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: lxv 3, -32720(2) # Dis-NEXT: lxv 3, -32720(2)
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: stxv 3, -32704(2) # Dis-NEXT: stxv 3, -32704(2)
# Dis-NEXT: blr # Dis-NEXT: blr
# NoOpt-LABEL: vec_dq: # NoOpt-LABEL: <vec_dq>:
# NoOpt-NEXT: addis # NoOpt-NEXT: addis
# NoOpt-NEXT: addi # NoOpt-NEXT: addi
# NoOpt-NEXT: addis 3, 2, 0 # NoOpt-NEXT: addis 3, 2, 0
# NoOpt-NEXT: lxv 3, -32720(3) # NoOpt-NEXT: lxv 3, -32720(3)
# NoOpt-NEXT: addis 3, 2, 0 # NoOpt-NEXT: addis 3, 2, 0
# NoOpt-NEXT: stxv 3, -32704(3) # NoOpt-NEXT: stxv 3, -32704(3)
# NoOpt-NEXT: blr # NoOpt-NEXT: blr
Show All 10 Lines.Lvec_ds_lep:
lxsd 3, vecLd@toc@l(3) lxsd 3, vecLd@toc@l(3)
addis 3, 2, vecSt@toc@ha addis 3, 2, vecSt@toc@ha
stxsd 3, vecSt@toc@l(3) stxsd 3, vecSt@toc@l(3)
addis 3, 2, vecLd@toc@ha addis 3, 2, vecLd@toc@ha
lxssp 3, vecLd@toc@l(3) lxssp 3, vecLd@toc@l(3)
addis 3, 2, vecSt@toc@ha addis 3, 2, vecSt@toc@ha
stxssp 3, vecSt@toc@l(3) stxssp 3, vecSt@toc@l(3)
blr blr
# Dis-LABEL: vec_ds: # Dis-LABEL: <vec_ds>:
# Dis-NEXT: addis # Dis-NEXT: addis
# Dis-NEXT: addi # Dis-NEXT: addi
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: lxsd 3, -32720(2) # Dis-NEXT: lxsd 3, -32720(2)
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: stxsd 3, -32704(2) # Dis-NEXT: stxsd 3, -32704(2)
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: lxssp 3, -32720(2) # Dis-NEXT: lxssp 3, -32720(2)
# Dis-NEXT: nop # Dis-NEXT: nop
# Dis-NEXT: stxssp 3, -32704(2) # Dis-NEXT: stxssp 3, -32704(2)
# Dis-NEXT: blr # Dis-NEXT: blr
# NoOpt-LABEL: vec_ds: # NoOpt-LABEL: <vec_ds>:
# NoOpt-NEXT: addis # NoOpt-NEXT: addis
# NoOpt-NEXT: addi # NoOpt-NEXT: addi
# NoOpt-NEXT: addis 3, 2, 0 # NoOpt-NEXT: addis 3, 2, 0
# NoOpt-NEXT: lxsd 3, -32720(3) # NoOpt-NEXT: lxsd 3, -32720(3)
# NoOpt-NEXT: addis 3, 2, 0 # NoOpt-NEXT: addis 3, 2, 0
# NoOpt-NEXT: stxsd 3, -32704(3) # NoOpt-NEXT: stxsd 3, -32704(3)
# NoOpt-NEXT: addis 3, 2, 0 # NoOpt-NEXT: addis 3, 2, 0
# NoOpt-NEXT: lxssp 3, -32720(3) # NoOpt-NEXT: lxssp 3, -32720(3)
Show All 34 Lines

lld/test/ELF/ppc64-toc-rel.s

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
# HEX-LE: section '.got': # HEX-LE: section '.got':
# HEX-LE-NEXT: 0x100201e8 e8810210 00000000 # HEX-LE-NEXT: 0x100201e8 e8810210 00000000
# HEX-BE: section '.got': # HEX-BE: section '.got':
# HEX-BE-NEXT: 0x100201e8 00000000 100281e8 # HEX-BE-NEXT: 0x100201e8 00000000 100281e8
# r2 stores the TOC base address. To access global_a with r3, it # r2 stores the TOC base address. To access global_a with r3, it
# computes the address with TOC plus an offset. # computes the address with TOC plus an offset.
# global_a - .TOC. = 0x100301f0 - 0x100281e8 = (1 << 16) - 32760 # global_a - .TOC. = 0x100301f0 - 0x100281e8 = (1 << 16) - 32760
# CHECK: _start: # CHECK: <_start>:
# CHECK: 100101d0: addis 3, 2, 1 # CHECK: 100101d0: addis 3, 2, 1
# CHECK-NEXT: 100101d4: addi 3, 3, -32760 # CHECK-NEXT: 100101d4: addi 3, 3, -32760

lld/test/ELF/ppc64-toc-restore-recursive-call.s

# REQUIRES: ppc # REQUIRES: ppc
# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
# RUN: ld.lld -shared %t.o -o %t.so # RUN: ld.lld -shared %t.o -o %t.so
# RUN: llvm-objdump -d --no-show-raw-insn -r %t.so | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn -r %t.so | FileCheck %s
# For a recursive call that is interposable the linker calls the plt-stub rather # For a recursive call that is interposable the linker calls the plt-stub rather
# then calling the function directly. Since the call is through a plt stub and # then calling the function directly. Since the call is through a plt stub and
# might be interposed with a different definition at runtime, a toc-restore is # might be interposed with a different definition at runtime, a toc-restore is
# required to follow the call. # required to follow the call.
# The decision to use a plt-stub for the recursive call is not one I feel # The decision to use a plt-stub for the recursive call is not one I feel
# strongly about either way. It was done because it matches what bfd and gold do # strongly about either way. It was done because it matches what bfd and gold do
# for recursive calls as well as keeps the logic for recursive calls consistent # for recursive calls as well as keeps the logic for recursive calls consistent
# with non-recursive calls. # with non-recursive calls.
# CHECK-LABEL: 0000000000010290 recursive_func: # CHECK-LABEL: 0000000000010290 <recursive_func>:
# CHECK: 102b8: bl .+32 # CHECK: 102b8: bl .+32
# CHECK-NEXT: ld 2, 24(1) # CHECK-NEXT: ld 2, 24(1)
# CHECK-LABEL: 00000000000102d8 __plt_recursive_func: # CHECK-LABEL: 00000000000102d8 <__plt_recursive_func>:
.abiversion 2 .abiversion 2
.section ".text" .section ".text"
.p2align 2 .p2align 2
.global recursive_func .global recursive_func
.type recursive_func, @function .type recursive_func, @function
recursive_func: recursive_func:
.Lrf_gep: .Lrf_gep:
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lld/test/ELF/ppc64-toc-restore.s

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# Calling external function foo in a shared object needs a nop. # Calling external function foo in a shared object needs a nop.
# Calling local function bar_local doe not need a nop. # Calling local function bar_local doe not need a nop.
.global _start .global _start
_start: _start:
bl foo bl foo
nop nop
bl bar_local bl bar_local
// CHECK-LABEL: _start: // CHECK-LABEL: <_start>:
// CHECK-NEXT: 100102c8: bl .+60 // CHECK-NEXT: 100102c8: bl .+60
// CHECK-NEXT: 100102cc: ld 2, 24(1) // CHECK-NEXT: 100102cc: ld 2, 24(1)
// CHECK-NEXT: 100102d0: bl .-16 // CHECK-NEXT: 100102d0: bl .-16
// CHECK-EMPTY: // CHECK-EMPTY:
# Calling a function in another object file which will have same # Calling a function in another object file which will have same
# TOC base does not need a nop. If nop present, do not rewrite to # TOC base does not need a nop. If nop present, do not rewrite to
# a toc restore # a toc restore
.global diff_object .global diff_object
_diff_object: _diff_object:
bl foo_not_shared bl foo_not_shared
bl foo_not_shared bl foo_not_shared
nop nop
// CHECK-LABEL: _diff_object: // CHECK-LABEL: <_diff_object>:
// CHECK-NEXT: 100102d4: bl .+28 // CHECK-NEXT: 100102d4: bl .+28
// CHECK-NEXT: 100102d8: bl .+24 // CHECK-NEXT: 100102d8: bl .+24
// CHECK-NEXT: 100102dc: nop // CHECK-NEXT: 100102dc: nop
# Branching to a local function does not need a nop # Branching to a local function does not need a nop
.global noretbranch .global noretbranch
noretbranch: noretbranch:
b bar_local b bar_local
// CHECK-LABEL: noretbranch: // CHECK-LABEL: <noretbranch>:
// CHECK: 100102e0: b .+67108832 // CHECK: 100102e0: b .+67108832
// CHECK-EMPTY: // CHECK-EMPTY:
// This should come last to check the end-of-buffer condition. // This should come last to check the end-of-buffer condition.
.global last .global last
last: last:
bl foo bl foo
nop nop
// CHECK-LABEL: last: // CHECK-LABEL: <last>:
// CHECK-NEXT: 100102e4: bl .+32 // CHECK-NEXT: 100102e4: bl .+32
// CHECK-NEXT: 100102e8: ld 2, 24(1) // CHECK-NEXT: 100102e8: ld 2, 24(1)

lld/test/ELF/pr34660.s

# REQUIRES: aarch64 # REQUIRES: aarch64
# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-none %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=aarch64-linux-none %s -o %t.o
# RUN: ld.lld --hash-style=sysv -shared %t.o -o %t # RUN: ld.lld --hash-style=sysv -shared %t.o -o %t
# RUN: llvm-objdump %t -d --no-show-raw-insn | FileCheck %s --check-prefix=DISASM # RUN: llvm-objdump %t -d --no-show-raw-insn | FileCheck %s --check-prefix=DISASM
# RUN: llvm-readelf %t --symbols | FileCheck %s --check-prefix=SYM # RUN: llvm-readelf %t --symbols | FileCheck %s --check-prefix=SYM
# It would be much easier to understand/read this test if llvm-objdump would print # It would be much easier to understand/read this test if llvm-objdump would print
# the immediates in hex. # the immediates in hex.
# IMM = hex(65540) = 0x10004 # IMM = hex(65540) = 0x10004
# PC = 0x10000 # PC = 0x10000
# As the relocation is PC-relative, IMM + PC = 0x20004 which is the VA of the # As the relocation is PC-relative, IMM + PC = 0x20004 which is the VA of the
# correct symbol. # correct symbol.
# DISASM: Disassembly of section .text: # DISASM: Disassembly of section .text:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: $x.0: # DISASM-NEXT: <$x.0>:
# DISASM-NEXT: 1022c: ldr x8, #131176 # DISASM-NEXT: 1022c: ldr x8, #131176
# SYM: Symbol table '.symtab' # SYM: Symbol table '.symtab'
# SYM: 0000000000030294 0 NOTYPE LOCAL DEFAULT 6 patatino # SYM: 0000000000030294 0 NOTYPE LOCAL DEFAULT 6 patatino
ldr x8, patatino ldr x8, patatino
.data .data
.zero 4 .zero 4
patatino: patatino:

lld/test/ELF/pre_init_fini_array.s

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// CHECK-NEXT: Binding: Local // CHECK-NEXT: Binding: Local
// CHECK-NEXT: Type: None // CHECK-NEXT: Type: None
// CHECK-NEXT: Other [ // CHECK-NEXT: Other [
// CHECK-NEXT: STV_HIDDEN // CHECK-NEXT: STV_HIDDEN
// CHECK-NEXT: ] // CHECK-NEXT: ]
// CHECK-NEXT: Section: .preinit_array // CHECK-NEXT: Section: .preinit_array
// CHECK-NEXT: } // CHECK-NEXT: }
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: callq {{.*}} <__preinit_array_start> // DISASM-NEXT: callq {{.*}} <__preinit_array_start>
// DISASM-NEXT: callq {{.*}} <__fini_array_start> // DISASM-NEXT: callq {{.*}} <__fini_array_start>
// DISASM-NEXT: callq {{.*}} <__init_array_start> // DISASM-NEXT: callq {{.*}} <__init_array_start>
// DISASM-NEXT: callq {{.*}} <__preinit_array_start> // DISASM-NEXT: callq {{.*}} <__preinit_array_start>
// DISASM-NEXT: callq {{.*}} <__fini_array_start> // DISASM-NEXT: callq {{.*}} <__fini_array_start>
// DISASM-NEXT: callq {{.*}} <__fini_array_end> // DISASM-NEXT: callq {{.*}} <__fini_array_end>

lld/test/ELF/pre_init_fini_array_missing.s

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// With no .init_array section the symbols resolve to .text. // With no .init_array section the symbols resolve to .text.
// 0x201120 - (0x201120 + 5) = -5 // 0x201120 - (0x201120 + 5) = -5
// 0x201120 - (0x201125 + 5) = -10 // 0x201120 - (0x201125 + 5) = -10
// ... // ...
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 201120: callq -5 // CHECK-NEXT: 201120: callq -5
// CHECK-NEXT: callq -10 // CHECK-NEXT: callq -10
// CHECK-NEXT: callq -15 // CHECK-NEXT: callq -15
// CHECK-NEXT: callq -20 // CHECK-NEXT: callq -20
// CHECK-NEXT: callq -25 // CHECK-NEXT: callq -25
// CHECK-NEXT: callq -30 // CHECK-NEXT: callq -30
// In position-independent binaries, they resolve to .text too. // In position-independent binaries, they resolve to .text too.
// PIE: Disassembly of section .text: // PIE: Disassembly of section .text:
// PIE-EMPTY: // PIE-EMPTY:
// PIE-NEXT: _start: // PIE-NEXT: <_start>:
// PIE-NEXT: 1210: callq -5 // PIE-NEXT: 1210: callq -5
// PIE-NEXT: callq -10 // PIE-NEXT: callq -10
// PIE-NEXT: callq -15 // PIE-NEXT: callq -15
// PIE-NEXT: callq -20 // PIE-NEXT: callq -20
// PIE-NEXT: callq -25 // PIE-NEXT: callq -25
// PIE-NEXT: callq -30 // PIE-NEXT: callq -30

lld/test/ELF/relocatable-symbols.s

# REQUIRES: x86 # REQUIRES: x86
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
# RUN: ld.lld -r %t -o %tout # RUN: ld.lld -r %t -o %tout
# RUN: llvm-objdump -d %tout | FileCheck -check-prefix=DISASM %s # RUN: llvm-objdump -d %tout | FileCheck -check-prefix=DISASM %s
# RUN: llvm-readobj -r %t | FileCheck -check-prefix=RELOC %s # RUN: llvm-readobj -r %t | FileCheck -check-prefix=RELOC %s
# RUN: llvm-readobj --symbols -r %tout | FileCheck -check-prefix=SYMBOL %s # RUN: llvm-readobj --symbols -r %tout | FileCheck -check-prefix=SYMBOL %s
# DISASM: _start: # DISASM: <_start>:
# DISASM-NEXT: 0: {{.*}} callq 0 # DISASM-NEXT: 0: {{.*}} callq 0
# DISASM-NEXT: 5: {{.*}} callq 0 # DISASM-NEXT: 5: {{.*}} callq 0
# DISASM-NEXT: a: {{.*}} callq 0 # DISASM-NEXT: a: {{.*}} callq 0
# DISASM-NEXT: f: {{.*}} callq 0 # DISASM-NEXT: f: {{.*}} callq 0
# DISASM-NEXT: 14: {{.*}} callq 0 # DISASM-NEXT: 14: {{.*}} callq 0
# DISASM-NEXT: 19: {{.*}} callq 0 # DISASM-NEXT: 19: {{.*}} callq 0
# DISASM-NEXT: 1e: {{.*}} callq 0 # DISASM-NEXT: 1e: {{.*}} callq 0
# DISASM-NEXT: 23: {{.*}} callq 0 # DISASM-NEXT: 23: {{.*}} callq 0
# DISASM-NEXT: 28: {{.*}} callq 0 # DISASM-NEXT: 28: {{.*}} callq 0
# DISASM-NEXT: 2d: {{.*}} callq 0 # DISASM-NEXT: 2d: {{.*}} callq 0
# DISASM-NEXT: 32: {{.*}} callq 0 # DISASM-NEXT: 32: {{.*}} callq 0
# DISASM-NEXT: 37: {{.*}} callq 0 # DISASM-NEXT: 37: {{.*}} callq 0
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: Disassembly of section foo: # DISASM-NEXT: Disassembly of section foo:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: foo: # DISASM-NEXT: <foo>:
# DISASM-NEXT: 0: 90 nop # DISASM-NEXT: 0: 90 nop
# DISASM-NEXT: 1: 90 nop # DISASM-NEXT: 1: 90 nop
# DISASM-NEXT: 2: 90 nop # DISASM-NEXT: 2: 90 nop
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: Disassembly of section bar: # DISASM-NEXT: Disassembly of section bar:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: bar: # DISASM-NEXT: <bar>:
# DISASM-NEXT: 0: 90 nop # DISASM-NEXT: 0: 90 nop
# DISASM-NEXT: 1: 90 nop # DISASM-NEXT: 1: 90 nop
# DISASM-NEXT: 2: 90 nop # DISASM-NEXT: 2: 90 nop
# RELOC: Relocations [ # RELOC: Relocations [
# RELOC-NEXT: Section ({{.*}}) .rela.text { # RELOC-NEXT: Section ({{.*}}) .rela.text {
# RELOC-NEXT: 0x1 R_X86_64_PC32 __start_foo 0xFFFFFFFFFFFFFFFC # RELOC-NEXT: 0x1 R_X86_64_PC32 __start_foo 0xFFFFFFFFFFFFFFFC
# RELOC-NEXT: 0x6 R_X86_64_PC32 __stop_foo 0xFFFFFFFFFFFFFFFC # RELOC-NEXT: 0x6 R_X86_64_PC32 __stop_foo 0xFFFFFFFFFFFFFFFC
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lld/test/ELF/relocatable.s

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# SECTION: 3 .bss 00000018 0000000000000000 BSS # SECTION: 3 .bss 00000018 0000000000000000 BSS
# SECTION: 4 .note.GNU-stack 00000000 0000000000000000 # SECTION: 4 .note.GNU-stack 00000000 0000000000000000
# SECTION: 5 .symtab 00000168 0000000000000000 # SECTION: 5 .symtab 00000168 0000000000000000
# SECTION: 6 .shstrtab 00000041 0000000000000000 # SECTION: 6 .shstrtab 00000041 0000000000000000
# SECTION: 7 .strtab 0000002d 0000000000000000 # SECTION: 7 .strtab 0000002d 0000000000000000
# CHECKTEXT: Disassembly of section .text: # CHECKTEXT: Disassembly of section .text:
# CHECKTEXT-EMPTY: # CHECKTEXT-EMPTY:
# CHECKTEXT-NEXT: main: # CHECKTEXT-NEXT: <main>:
# CHECKTEXT-NEXT: 0: c7 04 25 00 00 00 00 05 00 00 00 movl $5, 0 # CHECKTEXT-NEXT: 0: c7 04 25 00 00 00 00 05 00 00 00 movl $5, 0
# CHECKTEXT-NEXT: b: c7 04 25 00 00 00 00 07 00 00 00 movl $7, 0 # CHECKTEXT-NEXT: b: c7 04 25 00 00 00 00 07 00 00 00 movl $7, 0
# CHECKTEXT: foo: # CHECKTEXT: <foo>:
# CHECKTEXT-NEXT: 20: c7 04 25 00 00 00 00 01 00 00 00 movl $1, 0 # CHECKTEXT-NEXT: 20: c7 04 25 00 00 00 00 01 00 00 00 movl $1, 0
# CHECKTEXT-NEXT: 2b: c7 04 25 00 00 00 00 02 00 00 00 movl $2, 0 # CHECKTEXT-NEXT: 2b: c7 04 25 00 00 00 00 02 00 00 00 movl $2, 0
# CHECKTEXT: bar: # CHECKTEXT: <bar>:
# CHECKTEXT-NEXT: 40: c7 04 25 00 00 00 00 08 00 00 00 movl $8, 0 # CHECKTEXT-NEXT: 40: c7 04 25 00 00 00 00 08 00 00 00 movl $8, 0
# CHECKTEXT-NEXT: 4b: c7 04 25 00 00 00 00 09 00 00 00 movl $9, 0 # CHECKTEXT-NEXT: 4b: c7 04 25 00 00 00 00 09 00 00 00 movl $9, 0
# CHECKEXE: Format: ELF64-x86-64 # CHECKEXE: Format: ELF64-x86-64
# CHECKEXE-NEXT: Arch: x86_64 # CHECKEXE-NEXT: Arch: x86_64
# CHECKEXE-NEXT: AddressSize: 64bit # CHECKEXE-NEXT: AddressSize: 64bit
# CHECKEXE-NEXT: LoadName: # CHECKEXE-NEXT: LoadName:
# CHECKEXE-NEXT: ElfHeader { # CHECKEXE-NEXT: ElfHeader {
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lld/test/ELF/relocation-absolute.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %S/Inputs/abs.s -o %tabs // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %S/Inputs/abs.s -o %tabs
// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t
// RUN: ld.lld %tabs %t -o %tout // RUN: ld.lld %tabs %t -o %tout
// RUN: llvm-objdump -d %tout | FileCheck %s // RUN: llvm-objdump -d %tout | FileCheck %s
.global _start .global _start
_start: _start:
movl $abs, %edx movl $abs, %edx
//CHECK: start: //CHECK: <_start>:
//CHECK-NEXT: movl $66, %edx //CHECK-NEXT: movl $66, %edx

lld/test/ELF/relocation-b-aarch64.test

# REQUIRES: aarch64 # REQUIRES: aarch64
# RUN: yaml2obj %s -o %t.o # RUN: yaml2obj %s -o %t.o
# RUN: ld.lld %t.o -o %t.out # RUN: ld.lld %t.o -o %t.out
# RUN: llvm-objdump -d --no-show-raw-insn %t.out | FileCheck %s # RUN: llvm-objdump -d --no-show-raw-insn %t.out | FileCheck %s
# Check that the R_AARCH64_JUMP26 writes the branch opcode as well as the # Check that the R_AARCH64_JUMP26 writes the branch opcode as well as the
# immediate. We use this property to overwrite instructions with a branch. # immediate. We use this property to overwrite instructions with a branch.
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: foo: # CHECK-NEXT: <foo>:
# CHECK-NEXT: 210120: b #4 # CHECK-NEXT: 210120: b #4
# CHECK: bar: # CHECK: <bar>:
# CHECK-NEXT: 210124: b #-4 # CHECK-NEXT: 210124: b #-4
!ELF !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_REL Type: ET_REL
Machine: EM_AARCH64 Machine: EM_AARCH64
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lld/test/ELF/relocation-copy-i686.s

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// CHECK-NEXT: Addend: 0x0 // CHECK-NEXT: Addend: 0x0
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: ] // CHECK-NEXT: ]
// 16 is alignment here // 16 is alignment here
// CODE: Disassembly of section .text: // CODE: Disassembly of section .text:
// CODE-EMPTY: // CODE-EMPTY:
// CODE-NEXT: main: // CODE-NEXT: <main>:
/// .bss + 0 = 0x403270 /// .bss + 0 = 0x403270
// CODE-NEXT: 4011f0: movl $0x5, 0x403270 // CODE-NEXT: 4011f0: movl $0x5, 0x403270
/// .bss + 16 = 0x403270 + 16 = 0x403280 /// .bss + 16 = 0x403270 + 16 = 0x403280
// CODE-NEXT: 4011fa: movl $0x7, 0x403280 // CODE-NEXT: 4011fa: movl $0x7, 0x403280
/// .bss + 20 = 0x403270 + 20 = 0x403284 /// .bss + 20 = 0x403270 + 20 = 0x403284
// CODE-NEXT: 401204: movl $0x9, 0x403284 // CODE-NEXT: 401204: movl $0x9, 0x403284

lld/test/ELF/relocation-copy.s

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// CHECK-NEXT: Addend: 0x0 // CHECK-NEXT: Addend: 0x0
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: ] // CHECK-NEXT: ]
// 16 is alignment here // 16 is alignment here
// CODE: Disassembly of section .text: // CODE: Disassembly of section .text:
// CODE-EMPTY: // CODE-EMPTY:
// CODE-NEXT: _start: // CODE-NEXT: <_start>:
// CODE-NEXT: movl $0x5, 0x203400 // CODE-NEXT: movl $0x5, 0x203400
// CODE-NEXT: movl $0x7, 0x203410 // CODE-NEXT: movl $0x7, 0x203410
// CODE-NEXT: movl $0x9, 0x203414 // CODE-NEXT: movl $0x9, 0x203414
// CODE-NEXT: movl $0x203400, %edx // CODE-NEXT: movl $0x203400, %edx
// CODE-NEXT: movl $0x203410, %edx // CODE-NEXT: movl $0x203410, %edx
// CODE-NEXT: movl $0x203414, %edx // CODE-NEXT: movl $0x203414, %edx

lld/test/ELF/relocation-i686.s

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.section .R_386_PC32,"ax",@progbits,unique,2 .section .R_386_PC32,"ax",@progbits,unique,2
.zero 4 .zero 4
R_386_PC32_2: R_386_PC32_2:
nop nop
// CHECK: Disassembly of section .R_386_32: // CHECK: Disassembly of section .R_386_32:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: R_386_32: // CHECK-NEXT: <R_386_32>:
// CHECK-NEXT: movl $4198829, %edx // CHECK-NEXT: movl $4198829, %edx
// CHECK: Disassembly of section .R_386_PC32: // CHECK: Disassembly of section .R_386_PC32:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: R_386_PC32: // CHECK-NEXT: <R_386_PC32>:
// CHECK-NEXT: calll 4 // CHECK-NEXT: calll 4
// CHECK: R_386_PC32_2: // CHECK: <R_386_PC32_2>:
// CHECK-NEXT: nop // CHECK-NEXT: nop
// Create a .got // Create a .got
movl bar@GOT, %eax movl bar@GOT, %eax
// ADDR: Name: .plt // ADDR: Name: .plt
// ADDR-NEXT: Type: SHT_PROGBITS // ADDR-NEXT: Type: SHT_PROGBITS
// ADDR-NEXT: Flags [ // ADDR-NEXT: Flags [
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.section .R_386_GOTPC,"ax",@progbits .section .R_386_GOTPC,"ax",@progbits
R_386_GOTPC: R_386_GOTPC:
movl $_GLOBAL_OFFSET_TABLE_, %eax movl $_GLOBAL_OFFSET_TABLE_, %eax
// .got.plt - 0x4011c0 = 0x403280 - 0x4011c0 = 8384 // .got.plt - 0x4011c0 = 0x403280 - 0x4011c0 = 8384
// CHECK: Disassembly of section .R_386_GOTPC: // CHECK: Disassembly of section .R_386_GOTPC:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: R_386_GOTPC: // CHECK-NEXT: <R_386_GOTPC>:
// CHECK-NEXT: 4011c0: movl $8384, %eax // CHECK-NEXT: 4011c0: movl $8384, %eax
.section .dynamic_reloc, "ax",@progbits .section .dynamic_reloc, "ax",@progbits
call bar call bar
// .plt + 16 - (0x4011c5 + 5) = 0x4011e0 + 16 - 0x4011ca = 38 // .plt + 16 - (0x4011c5 + 5) = 0x4011e0 + 16 - 0x4011ca = 38
// CHECK: Disassembly of section .dynamic_reloc: // CHECK: Disassembly of section .dynamic_reloc:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: .dynamic_reloc: // CHECK-NEXT: <.dynamic_reloc>:
// CHECK-NEXT: 4011c5: calll 38 <bar@plt> // CHECK-NEXT: 4011c5: calll 38 <bar@plt>
.section .R_386_GOT32,"ax",@progbits .section .R_386_GOT32,"ax",@progbits
.global R_386_GOT32 .global R_386_GOT32
R_386_GOT32: R_386_GOT32:
movl bar@GOT, %eax movl bar@GOT, %eax
movl zed@GOT, %eax movl zed@GOT, %eax
movl bar+8@GOT, %eax movl bar+8@GOT, %eax
movl zed+4@GOT, %eax movl zed+4@GOT, %eax
// &.got[0] - .got.plt = 0x402278 - 0x403280 = 4294963192 // &.got[0] - .got.plt = 0x402278 - 0x403280 = 4294963192
// &.got[1] - .got.plt = 0x402278 + 4 - 0x403280 = 4294963196 // &.got[1] - .got.plt = 0x402278 + 4 - 0x403280 = 4294963196
// &.got[2] - .got.plt = 0x402278 + 8 - 0x403280 = 4294963200 // &.got[2] - .got.plt = 0x402278 + 8 - 0x403280 = 4294963200
// CHECK: Disassembly of section .R_386_GOT32: // CHECK: Disassembly of section .R_386_GOT32:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: R_386_GOT32: // CHECK-NEXT: <R_386_GOT32>:
// CHECK-NEXT: 4011ca: movl 4294963192, %eax // CHECK-NEXT: 4011ca: movl 4294963192, %eax
// CHECK-NEXT: movl 4294963196, %eax // CHECK-NEXT: movl 4294963196, %eax
// CHECK-NEXT: movl 4294963200, %eax // CHECK-NEXT: movl 4294963200, %eax
// CHECK-NEXT: movl 4294963200, %eax // CHECK-NEXT: movl 4294963200, %eax

lld/test/ELF/relocation.s

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.section .text,"ax",@progbits,unique,2 .section .text,"ax",@progbits,unique,2
.zero 4 .zero 4
.global lulz .global lulz
lulz: lulz:
nop nop
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: _start: // CHECK-NEXT: <_start>:
// CHECK-NEXT: 201310: e8 04 00 00 00 callq 4 // CHECK-NEXT: 201310: e8 04 00 00 00 callq 4
// CHECK-NEXT: 201315: // CHECK-NEXT: 201315:
// CHECK: lulz: // CHECK: <lulz>:
// CHECK-NEXT: 201319: 90 nop // CHECK-NEXT: 201319: 90 nop
.section .text2,"ax",@progbits .section .text2,"ax",@progbits
.global R_X86_64_32 .global R_X86_64_32
R_X86_64_32: R_X86_64_32:
movl $R_X86_64_32, %edx movl $R_X86_64_32, %edx
// FIXME: this would be far more self evident if llvm-objdump printed // FIXME: this would be far more self evident if llvm-objdump printed
// constants in hex. // constants in hex.
// CHECK: Disassembly of section .text2: // CHECK: Disassembly of section .text2:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: R_X86_64_32: // CHECK-NEXT: <R_X86_64_32>:
// CHECK-NEXT: 20131a: {{.*}} movl $2102042, %edx // CHECK-NEXT: 20131a: {{.*}} movl $2102042, %edx
.section .R_X86_64_32S,"ax",@progbits .section .R_X86_64_32S,"ax",@progbits
.global R_X86_64_32S .global R_X86_64_32S
R_X86_64_32S: R_X86_64_32S:
movq lulz - 0x100000, %rdx movq lulz - 0x100000, %rdx
// CHECK: Disassembly of section .R_X86_64_32S: // CHECK: Disassembly of section .R_X86_64_32S:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: R_X86_64_32S: // CHECK-NEXT: <R_X86_64_32S>:
// CHECK-NEXT: {{.*}}: {{.*}} movq 1053465, %rdx // CHECK-NEXT: {{.*}}: {{.*}} movq 1053465, %rdx
.section .R_X86_64_PC32,"ax",@progbits .section .R_X86_64_PC32,"ax",@progbits
.global R_X86_64_PC32 .global R_X86_64_PC32
R_X86_64_PC32: R_X86_64_PC32:
call bar call bar
movl $bar, %eax movl $bar, %eax
//16 is a size of PLT[0] //16 is a size of PLT[0]
// 0x201340 + 16 - (0x201327 + 5) = 36 // 0x201340 + 16 - (0x201327 + 5) = 36
// CHECK: Disassembly of section .R_X86_64_PC32: // CHECK: Disassembly of section .R_X86_64_PC32:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: R_X86_64_PC32: // CHECK-NEXT: <R_X86_64_PC32>:
// CHECK-NEXT: 201327: {{.*}} callq 36 // CHECK-NEXT: 201327: {{.*}} callq 36
// CHECK-NEXT: 20132c: {{.*}} movl $2102096, %eax // CHECK-NEXT: 20132c: {{.*}} movl $2102096, %eax
.section .R_X86_64_32S_2,"ax",@progbits .section .R_X86_64_32S_2,"ax",@progbits
.global R_X86_64_32S_2 .global R_X86_64_32S_2
R_X86_64_32S_2: R_X86_64_32S_2:
mov bar2, %eax mov bar2, %eax
// plt is at 0x201340. The second plt entry is at 0x201360 == 2102112 // plt is at 0x201340. The second plt entry is at 0x201360 == 2102112
// CHECK: Disassembly of section .R_X86_64_32S_2: // CHECK: Disassembly of section .R_X86_64_32S_2:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: R_X86_64_32S_2: // CHECK-NEXT: <R_X86_64_32S_2>:
// CHECK-NEXT: 201331: {{.*}} movl 2102112, %eax // CHECK-NEXT: 201331: {{.*}} movl 2102112, %eax

lld/test/ELF/riscv-ifunc-nonpreemptible.s

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# RUN: llvm-objdump -d --no-show-raw-insn %t.64 | FileCheck --check-prefix=DIS64 %s # RUN: llvm-objdump -d --no-show-raw-insn %t.64 | FileCheck --check-prefix=DIS64 %s
# RELOC32: .rela.dyn { # RELOC32: .rela.dyn {
# RELOC32-NEXT: 0x3218 R_RISCV_IRELATIVE - 0x117C # RELOC32-NEXT: 0x3218 R_RISCV_IRELATIVE - 0x117C
# RELOC32-NEXT: } # RELOC32-NEXT: }
# SYM32: 0001190 0 FUNC GLOBAL DEFAULT {{.*}} func # SYM32: 0001190 0 FUNC GLOBAL DEFAULT {{.*}} func
# DIS32: _start: # DIS32: <_start>:
# DIS32-NEXT: 1180: auipc a0, 0 # DIS32-NEXT: 1180: auipc a0, 0
# DIS32-NEXT: addi a0, a0, 16 # DIS32-NEXT: addi a0, a0, 16
# DIS32: Disassembly of section .iplt: # DIS32: Disassembly of section .iplt:
# DIS32: func: # DIS32: <func>:
## 32-bit: &.got.plt[func]-. = 0x3218-0x1190 = 4096*2+136 ## 32-bit: &.got.plt[func]-. = 0x3218-0x1190 = 4096*2+136
# DIS32-NEXT: 1190: auipc t3, 2 # DIS32-NEXT: 1190: auipc t3, 2
# DIS32-NEXT: lw t3, 136(t3) # DIS32-NEXT: lw t3, 136(t3)
# DIS32-NEXT: jalr t1, t3 # DIS32-NEXT: jalr t1, t3
# DIS32-NEXT: nop # DIS32-NEXT: nop
# RELOC64: .rela.dyn { # RELOC64: .rela.dyn {
# RELOC64-NEXT: 0x3370 R_RISCV_IRELATIVE - 0x1260 # RELOC64-NEXT: 0x3370 R_RISCV_IRELATIVE - 0x1260
# RELOC64-NEXT: } # RELOC64-NEXT: }
# SYM64: 000000000001270 0 FUNC GLOBAL DEFAULT {{.*}} func # SYM64: 000000000001270 0 FUNC GLOBAL DEFAULT {{.*}} func
# DIS64: _start: # DIS64: <_start>:
# DIS64-NEXT: 1264: auipc a0, 0 # DIS64-NEXT: 1264: auipc a0, 0
# DIS64-NEXT: addi a0, a0, 12 # DIS64-NEXT: addi a0, a0, 12
# DIS64: Disassembly of section .iplt: # DIS64: Disassembly of section .iplt:
# DIS64: func: # DIS64: <func>:
## 64-bit: &.got.plt[func]-. = 0x3370-0x1270 = 4096*2+256 ## 64-bit: &.got.plt[func]-. = 0x3370-0x1270 = 4096*2+256
# DIS64-NEXT: 1270: auipc t3, 2 # DIS64-NEXT: 1270: auipc t3, 2
# DIS64-NEXT: ld t3, 256(t3) # DIS64-NEXT: ld t3, 256(t3)
# DIS64-NEXT: jalr t1, t3 # DIS64-NEXT: jalr t1, t3
# DIS64-NEXT: nop # DIS64-NEXT: nop
.text .text
.globl func .globl func
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lld/test/ELF/riscv-plt.s

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# RELOC64: .rela.plt { # RELOC64: .rela.plt {
# RELOC64-NEXT: 0x130E0 R_RISCV_JUMP_SLOT bar 0x0 # RELOC64-NEXT: 0x130E0 R_RISCV_JUMP_SLOT bar 0x0
# RELOC64-NEXT: 0x130E8 R_RISCV_JUMP_SLOT weak 0x0 # RELOC64-NEXT: 0x130E8 R_RISCV_JUMP_SLOT weak 0x0
# RELOC64-NEXT: } # RELOC64-NEXT: }
# GOTPLT64: section '.got.plt' # GOTPLT64: section '.got.plt'
# GOTPLT64-NEXT: 0x000130d0 00000000 00000000 00000000 00000000 # GOTPLT64-NEXT: 0x000130d0 00000000 00000000 00000000 00000000
# GOTPLT64-NEXT: 0x000130e0 30100100 00000000 30100100 00000000 # GOTPLT64-NEXT: 0x000130e0 30100100 00000000 30100100 00000000
# DIS: _start: # DIS: <_start>:
## Direct call ## Direct call
## foo - . = 0x11020-0x11000 = 32 ## foo - . = 0x11020-0x11000 = 32
# DIS-NEXT: 11000: auipc ra, 0 # DIS-NEXT: 11000: auipc ra, 0
# DIS-NEXT: jalr 32(ra) # DIS-NEXT: jalr 32(ra)
## bar@plt - . = 0x11050-0x11008 = 72 ## bar@plt - . = 0x11050-0x11008 = 72
# DIS-NEXT: 11008: auipc ra, 0 # DIS-NEXT: 11008: auipc ra, 0
# DIS-NEXT: jalr 72(ra) # DIS-NEXT: jalr 72(ra)
## bar@plt - . = 0x11050-0x11010 = 64 ## bar@plt - . = 0x11050-0x11010 = 64
# DIS-NEXT: 11010: auipc ra, 0 # DIS-NEXT: 11010: auipc ra, 0
# DIS-NEXT: jalr 64(ra) # DIS-NEXT: jalr 64(ra)
## weak@plt - . = 0x11060-0x11018 = 72 ## weak@plt - . = 0x11060-0x11018 = 72
# DIS-NEXT: 11018: auipc ra, 0 # DIS-NEXT: 11018: auipc ra, 0
# DIS-NEXT: jalr 72(ra) # DIS-NEXT: jalr 72(ra)
# DIS: foo: # DIS: <foo>:
# DIS-NEXT: 11020: # DIS-NEXT: 11020:
# DIS: Disassembly of section .plt: # DIS: Disassembly of section .plt:
# DIS: .plt: # DIS: <.plt>:
# DIS-NEXT: auipc t2, 2 # DIS-NEXT: auipc t2, 2
# DIS-NEXT: sub t1, t1, t3 # DIS-NEXT: sub t1, t1, t3
## .got.plt - .plt = 0x13068 - 0x11030 = 4096*2+56 ## .got.plt - .plt = 0x13068 - 0x11030 = 4096*2+56
# DIS32-NEXT: lw t3, 56(t2) # DIS32-NEXT: lw t3, 56(t2)
# DIS64-NEXT: ld t3, 160(t2) # DIS64-NEXT: ld t3, 160(t2)
# DIS-NEXT: addi t1, t1, -44 # DIS-NEXT: addi t1, t1, -44
# DIS32-NEXT: addi t0, t2, 56 # DIS32-NEXT: addi t0, t2, 56
# DIS64-NEXT: addi t0, t2, 160 # DIS64-NEXT: addi t0, t2, 160
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lld/test/ELF/riscv-undefined-weak.s

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.weak target .weak target
.global absolute, relative, branch .global absolute, relative, branch
## Absolute relocations are resolved to 0. ## Absolute relocations are resolved to 0.
# RELOC: 0x0 R_RISCV_HI20 target 0x1 # RELOC: 0x0 R_RISCV_HI20 target 0x1
# RELOC-NEXT: 0x4 R_RISCV_LO12_I target 0x1 # RELOC-NEXT: 0x4 R_RISCV_LO12_I target 0x1
# CHECK-LABEL: absolute: # CHECK-LABEL: <absolute>:
# CHECK-NEXT: lui t0, 0 # CHECK-NEXT: lui t0, 0
# CHECK-NEXT: addi t0, t0, 1 # CHECK-NEXT: addi t0, t0, 1
absolute: absolute:
lui t0, %hi(target+1) lui t0, %hi(target+1)
addi t0, t0, %lo(target+1) addi t0, t0, %lo(target+1)
## Currently, PC-relative relocations are resolved to 0. ## Currently, PC-relative relocations are resolved to 0.
# RELOC-NEXT: 0x8 R_RISCV_PCREL_HI20 target 0x0 # RELOC-NEXT: 0x8 R_RISCV_PCREL_HI20 target 0x0
# RELOC-NEXT: 0xC R_RISCV_PCREL_LO12_I .Lpcrel_hi0 0x0 # RELOC-NEXT: 0xC R_RISCV_PCREL_LO12_I .Lpcrel_hi0 0x0
# RELOC-NEXT: 0x10 R_RISCV_PCREL_HI20 target 0x2 # RELOC-NEXT: 0x10 R_RISCV_PCREL_HI20 target 0x2
# RELOC-NEXT: 0x14 R_RISCV_PCREL_LO12_S .Lpcrel_hi1 0x0 # RELOC-NEXT: 0x14 R_RISCV_PCREL_LO12_S .Lpcrel_hi1 0x0
## 1048559 should be -0x11. ## 1048559 should be -0x11.
# CHECK-LABEL: relative: # CHECK-LABEL: <relative>:
# CHECK-NEXT: 11{{...}}: auipc a1, 1048559 # CHECK-NEXT: 11{{...}}: auipc a1, 1048559
# PC-NEXT: addi a1, a1, -352 # PC-NEXT: addi a1, a1, -352
# PLT-NEXT: addi a1, a1, -792 # PLT-NEXT: addi a1, a1, -792
# CHECK-LABEL: .Lpcrel_hi1: # CHECK-LABEL: <.Lpcrel_hi1>:
# CHECK-NEXT: 11{{...}}: auipc t1, 1048559 # CHECK-NEXT: 11{{...}}: auipc t1, 1048559
# PC-NEXT: sd a2, -358(t1) # PC-NEXT: sd a2, -358(t1)
# PLT-NEXT: sd a2, -798(t1) # PLT-NEXT: sd a2, -798(t1)
relative: relative:
la a1, target la a1, target
sd a2, target+2, t1 sd a2, target+2, t1
## Branch relocations ## Branch relocations
## If .dynsym does not exist, an undefined weak symbol is non-preemptible. ## If .dynsym does not exist, an undefined weak symbol is non-preemptible.
## Treat them as PC relative relocations. ## Treat them as PC relative relocations.
# RELOC: 0x18 R_RISCV_CALL target 0x0 # RELOC: 0x18 R_RISCV_CALL target 0x0
# RELOC-NEXT: 0x20 R_RISCV_JAL target 0x0 # RELOC-NEXT: 0x20 R_RISCV_JAL target 0x0
# PC-LABEL: branch: # PC-LABEL: <branch>:
# PC-NEXT: auipc ra, 1048559 # PC-NEXT: auipc ra, 1048559
# PC-NEXT: jalr -368(ra) # PC-NEXT: jalr -368(ra)
## FIXME: llvm-objdump -d should print the address, instead of the offset. ## FIXME: llvm-objdump -d should print the address, instead of the offset.
# PC-NEXT: j -70008 # PC-NEXT: j -70008
## If .dynsym exists, an undefined weak symbol is preemptible. ## If .dynsym exists, an undefined weak symbol is preemptible.
## We create a PLT entry and redirect the reference to it. ## We create a PLT entry and redirect the reference to it.
# PLT-LABEL: branch: # PLT-LABEL: <branch>:
# PLT-NEXT: auipc ra, 0 # PLT-NEXT: auipc ra, 0
# PLT-NEXT: jalr 56(ra) # PLT-NEXT: jalr 56(ra)
# PLT-NEXT: j -70448 # PLT-NEXT: j -70448
branch: branch:
call target call target
jal x0, target jal x0, target
## Absolute relocations are resolved to 0. ## Absolute relocations are resolved to 0.
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lld/test/ELF/startstop-gccollect.s

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# RUN: llvm-objdump -d %tout | FileCheck -check-prefix=DISASM %s # RUN: llvm-objdump -d %tout | FileCheck -check-prefix=DISASM %s
# RUN: echo ".global __start_foo; __start_foo:" > %t2.s # RUN: echo ".global __start_foo; __start_foo:" > %t2.s
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %t2.s -o %t2.o # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %t2.s -o %t2.o
# RUN: ld.lld -shared %t2.o -o %t2.so # RUN: ld.lld -shared %t2.o -o %t2.so
# RUN: ld.lld %t --gc-sections -o %tout %t2.so # RUN: ld.lld %t --gc-sections -o %tout %t2.so
# RUN: llvm-objdump -d %tout | FileCheck -check-prefix=DISASM %s # RUN: llvm-objdump -d %tout | FileCheck -check-prefix=DISASM %s
# DISASM: _start: # DISASM: <_start>:
# DISASM-NEXT: callq {{.*}} <__start_foo> # DISASM-NEXT: callq {{.*}} <__start_foo>
# DISASM-NEXT: callq {{.*}} <__stop_bar> # DISASM-NEXT: callq {{.*}} <__stop_bar>
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: Disassembly of section foo: # DISASM-NEXT: Disassembly of section foo:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: __start_foo: # DISASM-NEXT: <__start_foo>:
# DISASM-NEXT: nop # DISASM-NEXT: nop
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: Disassembly of section bar: # DISASM-NEXT: Disassembly of section bar:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: bar: # DISASM-NEXT: <bar>:
# DISASM-NEXT: nop # DISASM-NEXT: nop
.global _start .global _start
.text .text
_start: _start:
callq __start_foo callq __start_foo
callq __stop_bar callq __stop_bar
.section foo,"ax" .section foo,"ax"
nop nop
.section bar,"ax" .section bar,"ax"
nop nop

lld/test/ELF/startstop.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
// RUN: ld.lld %t -o %t.so -shared // RUN: ld.lld %t -o %t.so -shared
// RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck -check-prefix=DISASM %s // RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck -check-prefix=DISASM %s
// RUN: llvm-readobj --symbols -r %t.so | FileCheck -check-prefix=SYMBOL %s // RUN: llvm-readobj --symbols -r %t.so | FileCheck -check-prefix=SYMBOL %s
// DISASM: _start: // DISASM: <_start>:
// DISASM: 1330: callq 10 <__start_foo> // DISASM: 1330: callq 10 <__start_foo>
// DISASM: 1335: callq 8 <__start_bar> // DISASM: 1335: callq 8 <__start_bar>
// DISASM: 133a: callq 3 <__start_bar> // DISASM: 133a: callq 3 <__start_bar>
// DISASM: Disassembly of section foo: // DISASM: Disassembly of section foo:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM: __start_foo: // DISASM: <__start_foo>:
// DISASM: 133f: nop // DISASM: 133f: nop
// DISASM: nop // DISASM: nop
// DISASM: nop // DISASM: nop
// DISASM: Disassembly of section bar: // DISASM: Disassembly of section bar:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM: __start_bar: // DISASM: <__start_bar>:
// DISASM: 1342: nop // DISASM: 1342: nop
// DISASM: nop // DISASM: nop
// DISASM: nop // DISASM: nop
// SYMBOL: Relocations [ // SYMBOL: Relocations [
// SYMBOL-NEXT: Section ({{.*}}) .rela.dyn { // SYMBOL-NEXT: Section ({{.*}}) .rela.dyn {
// SYMBOL-NEXT: R_X86_64_RELATIVE // SYMBOL-NEXT: R_X86_64_RELATIVE
// SYMBOL-NEXT: R_X86_64_RELATIVE // SYMBOL-NEXT: R_X86_64_RELATIVE
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lld/test/ELF/tls-opt.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
// RUN: ld.lld %t.o -o %t1 // RUN: ld.lld %t.o -o %t1
// RUN: llvm-readobj -r %t1 | FileCheck --check-prefix=NORELOC %s // RUN: llvm-readobj -r %t1 | FileCheck --check-prefix=NORELOC %s
// RUN: llvm-objdump -d --no-show-raw-insn %t1 | FileCheck --check-prefix=DISASM %s // RUN: llvm-objdump -d --no-show-raw-insn %t1 | FileCheck --check-prefix=DISASM %s
// NORELOC: Relocations [ // NORELOC: Relocations [
// NORELOC-NEXT: ] // NORELOC-NEXT: ]
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: movq $-8, %rax // DISASM-NEXT: movq $-8, %rax
// DISASM-NEXT: movq $-8, %r15 // DISASM-NEXT: movq $-8, %r15
// DISASM-NEXT: leaq -8(%rax), %rax // DISASM-NEXT: leaq -8(%rax), %rax
// DISASM-NEXT: leaq -8(%r15), %r15 // DISASM-NEXT: leaq -8(%r15), %r15
// DISASM-NEXT: addq $-8, %rsp // DISASM-NEXT: addq $-8, %rsp
// DISASM-NEXT: addq $-8, %r12 // DISASM-NEXT: addq $-8, %r12
// DISASM-NEXT: movq $-4, %rax // DISASM-NEXT: movq $-4, %rax
// DISASM-NEXT: movq $-4, %r15 // DISASM-NEXT: movq $-4, %r15
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// GD to LE: // GD to LE:
// DISASM-NEXT: movq %fs:0, %rax // DISASM-NEXT: movq %fs:0, %rax
// DISASM-NEXT: leaq -8(%rax), %rax // DISASM-NEXT: leaq -8(%rax), %rax
// DISASM-NEXT: movq %fs:0, %rax // DISASM-NEXT: movq %fs:0, %rax
// DISASM-NEXT: leaq -4(%rax), %rax // DISASM-NEXT: leaq -4(%rax), %rax
// LD to LE: // LD to LE:
// DISASM: _DTPOFF64_1: // DISASM: <_DTPOFF64_1>:
// DISASM-NEXT: clc // DISASM-NEXT: clc
// DISASM: _DTPOFF64_2: // DISASM: <_DTPOFF64_2>:
// DISASM-NEXT: cld // DISASM-NEXT: cld
.type tls0,@object .type tls0,@object
.section .tbss,"awT",@nobits .section .tbss,"awT",@nobits
.globl tls0 .globl tls0
.align 4 .align 4
tls0: tls0:
.long 0 .long 0
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lld/test/ELF/tls.s

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// CHECK-NEXT: Binding: Global // CHECK-NEXT: Binding: Global
// CHECK-NEXT: Type: TLS // CHECK-NEXT: Type: TLS
// CHECK-NEXT: Other: 0 // CHECK-NEXT: Other: 0
// CHECK-NEXT: Section: .thread_data // CHECK-NEXT: Section: .thread_data
// CHECK-NEXT: } // CHECK-NEXT: }
// DIS: Disassembly of section .text: // DIS: Disassembly of section .text:
// DIS-EMPTY: // DIS-EMPTY:
// DIS-NEXT: _start: // DIS-NEXT: <_start>:
// DIS-NEXT: movl %fs:-8, %eax // DIS-NEXT: movl %fs:-8, %eax
// DIS-NEXT: movl %fs:-16, %eax // DIS-NEXT: movl %fs:-16, %eax
// DIS-NEXT: movl %fs:-4, %eax // DIS-NEXT: movl %fs:-4, %eax
// DIS-NEXT: movl %fs:-12, %eax // DIS-NEXT: movl %fs:-12, %eax

lld/test/ELF/weak-undef-got-pie.s

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# RELOCS-NEXT: R_X86_64_GLOB_DAT foo 0x0 # RELOCS-NEXT: R_X86_64_GLOB_DAT foo 0x0
# RELOCS-NEXT: } # RELOCS-NEXT: }
# RELOCS-NEXT: ] # RELOCS-NEXT: ]
.weak foo .weak foo
.globl _start .globl _start
_start: _start:
# DISASM: _start: # DISASM: <_start>:
# DISASM-NEXT: movq {{.*}}(%rip), %rax # DISASM-NEXT: movq {{.*}}(%rip), %rax
mov foo@gotpcrel(%rip), %rax mov foo@gotpcrel(%rip), %rax

lld/test/ELF/wrap-no-real.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t1.o
// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/wrap-no-real.s -o %t2.o // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/wrap-no-real.s -o %t2.o
// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/wrap-no-real2.s -o %t3.o // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/wrap-no-real2.s -o %t3.o
// RUN: ld.lld -o %t3.so -shared %t3.o // RUN: ld.lld -o %t3.so -shared %t3.o
// RUN: ld.lld -o %t %t1.o %t2.o -wrap foo // RUN: ld.lld -o %t %t1.o %t2.o -wrap foo
// RUN: llvm-objdump -d -print-imm-hex %t | FileCheck %s // RUN: llvm-objdump -d -print-imm-hex %t | FileCheck %s
// RUN: ld.lld -o %t %t1.o %t2.o %t3.so -wrap foo // RUN: ld.lld -o %t %t1.o %t2.o %t3.so -wrap foo
// RUN: llvm-objdump -d -print-imm-hex %t | FileCheck %s // RUN: llvm-objdump -d -print-imm-hex %t | FileCheck %s
// CHECK: _start: // CHECK: <_start>:
// CHECK-NEXT: movl $0x11010, %edx // CHECK-NEXT: movl $0x11010, %edx
// CHECK-NEXT: movl $0x11010, %edx // CHECK-NEXT: movl $0x11010, %edx
// CHECK-NEXT: movl $0x11000, %edx // CHECK-NEXT: movl $0x11000, %edx
// RUN: llvm-objdump -t %t | FileCheck -check-prefix=SYM %s // RUN: llvm-objdump -t %t | FileCheck -check-prefix=SYM %s
// SYM: {{.*}} l .dynamic 0000000000000000 .hidden _DYNAMIC // SYM: {{.*}} l .dynamic 0000000000000000 .hidden _DYNAMIC
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lld/test/ELF/wrap-plt.s

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// CHECK: Relocations [ // CHECK: Relocations [
// CHECK-NEXT: Section ({{.*}}) .rela.plt { // CHECK-NEXT: Section ({{.*}}) .rela.plt {
// CHECK-NEXT: R_X86_64_JUMP_SLOT __wrap_foo 0x0 // CHECK-NEXT: R_X86_64_JUMP_SLOT __wrap_foo 0x0
// CHECK-NEXT: R_X86_64_JUMP_SLOT _start 0x0 // CHECK-NEXT: R_X86_64_JUMP_SLOT _start 0x0
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: ] // CHECK-NEXT: ]
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: jmp {{.*}} <__wrap_foo@plt> // DISASM-NEXT: jmp {{.*}} <__wrap_foo@plt>
// DISASM-NEXT: jmp {{.*}} <__wrap_foo@plt> // DISASM-NEXT: jmp {{.*}} <__wrap_foo@plt>
// DISASM-NEXT: jmp {{.*}} <_start@plt> // DISASM-NEXT: jmp {{.*}} <_start@plt>
.global foo .global foo
foo: foo:
nop nop
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lld/test/ELF/wrap.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t
// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/wrap.s -o %t2 // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/wrap.s -o %t2
// RUN: ld.lld -o %t3 %t %t2 -wrap foo -wrap nosuchsym // RUN: ld.lld -o %t3 %t %t2 -wrap foo -wrap nosuchsym
// RUN: llvm-objdump -d -print-imm-hex %t3 | FileCheck %s // RUN: llvm-objdump -d -print-imm-hex %t3 | FileCheck %s
// RUN: ld.lld -o %t3 %t %t2 --wrap foo -wrap=nosuchsym // RUN: ld.lld -o %t3 %t %t2 --wrap foo -wrap=nosuchsym
// RUN: llvm-objdump -d -print-imm-hex %t3 | FileCheck %s // RUN: llvm-objdump -d -print-imm-hex %t3 | FileCheck %s
// RUN: ld.lld -o %t3 %t %t2 --wrap foo --wrap foo -wrap=nosuchsym // RUN: ld.lld -o %t3 %t %t2 --wrap foo --wrap foo -wrap=nosuchsym
// RUN: llvm-objdump -d -print-imm-hex %t3 | FileCheck %s // RUN: llvm-objdump -d -print-imm-hex %t3 | FileCheck %s
// CHECK: _start: // CHECK: <_start>:
// CHECK-NEXT: movl $0x11010, %edx // CHECK-NEXT: movl $0x11010, %edx
// CHECK-NEXT: movl $0x11010, %edx // CHECK-NEXT: movl $0x11010, %edx
// CHECK-NEXT: movl $0x11000, %edx // CHECK-NEXT: movl $0x11000, %edx
// RUN: llvm-readobj --symbols %t3 > %t4.dump // RUN: llvm-readobj --symbols %t3 > %t4.dump
// RUN: FileCheck --check-prefix=SYM1 %s < %t4.dump // RUN: FileCheck --check-prefix=SYM1 %s < %t4.dump
// RUN: FileCheck --check-prefix=SYM2 %s < %t4.dump // RUN: FileCheck --check-prefix=SYM2 %s < %t4.dump
// RUN: FileCheck --check-prefix=SYM3 %s < %t4.dump // RUN: FileCheck --check-prefix=SYM3 %s < %t4.dump
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lld/test/ELF/x86-64-feature-cet.s

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# RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t | FileCheck --check-prefix=DISASM %s # RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t | FileCheck --check-prefix=DISASM %s
# GOTPLT: Hex dump of section '.got.plt': # GOTPLT: Hex dump of section '.got.plt':
# GOTPLT-NEXT: 203480 80232000 00000000 00000000 00000000 # GOTPLT-NEXT: 203480 80232000 00000000 00000000 00000000
# GOTPLT-NEXT: 203490 00000000 00000000 50132000 00000000 # GOTPLT-NEXT: 203490 00000000 00000000 50132000 00000000
# GOTPLT-NEXT: 2034a0 00000000 00000000 # GOTPLT-NEXT: 2034a0 00000000 00000000
# DISASM: Disassembly of section .text: # DISASM: Disassembly of section .text:
# DISASM: 0000000000201330 func1: # DISASM: 0000000000201330 <func1>:
# DISASM-NEXT: 201330: callq 0x2b <func2+0x201360> # DISASM-NEXT: 201330: callq 0x2b <func2+0x201360>
# DISASM-NEXT: 201335: callq 0x36 <func2+0x201370> # DISASM-NEXT: 201335: callq 0x36 <func2+0x201370>
# DISASM-NEXT: retq # DISASM-NEXT: retq
# DISASM: Disassembly of section .plt: # DISASM: Disassembly of section .plt:
# DISASM: 0000000000201340 .plt: # DISASM: 0000000000201340 <.plt>:
# DISASM-NEXT: 201340: pushq 0x2142(%rip) # DISASM-NEXT: 201340: pushq 0x2142(%rip)
# DISASM-NEXT: jmpq *0x2144(%rip) # DISASM-NEXT: jmpq *0x2144(%rip)
# DISASM-NEXT: nopl (%rax) # DISASM-NEXT: nopl (%rax)
# DISASM-NEXT: endbr64 # DISASM-NEXT: endbr64
# DISASM-NEXT: pushq $0x0 # DISASM-NEXT: pushq $0x0
# DISASM-NEXT: jmp -0x1e <.plt> # DISASM-NEXT: jmp -0x1e <.plt>
# DISASM-NEXT: nop # DISASM-NEXT: nop
# DISASM: Disassembly of section .plt.sec: # DISASM: Disassembly of section .plt.sec:
# DISASM: 0000000000201360 .plt.sec: # DISASM: 0000000000201360 <.plt.sec>:
# DISASM-NEXT: 201360: endbr64 # DISASM-NEXT: 201360: endbr64
# DISASM-NEXT: jmpq *0x212e(%rip) # DISASM-NEXT: jmpq *0x212e(%rip)
# DISASM-NEXT: nopw (%rax,%rax) # DISASM-NEXT: nopw (%rax,%rax)
# DISASM: Disassembly of section .iplt: # DISASM: Disassembly of section .iplt:
# DISASM: 0000000000201370 .iplt: # DISASM: 0000000000201370 <.iplt>:
# DISASM-NEXT: 201370: endbr64 # DISASM-NEXT: 201370: endbr64
# DISASM-NEXT: jmpq *0x2126(%rip) # DISASM-NEXT: jmpq *0x2126(%rip)
# DISASM-NEXT: nopw (%rax,%rax) # DISASM-NEXT: nopw (%rax,%rax)
.section ".note.gnu.property", "a" .section ".note.gnu.property", "a"
.long 4 .long 4
.long 0x10 .long 0x10
.long 0x5 .long 0x5
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lld/test/ELF/x86-64-gotpc-relax-nopic.s

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# SYMRELOC: Symbols [ # SYMRELOC: Symbols [
# SYMRELOC: Symbol { # SYMRELOC: Symbol {
# SYMRELOC: Name: bar # SYMRELOC: Name: bar
# SYMRELOC-NEXT: Value: 0x202197 # SYMRELOC-NEXT: Value: 0x202197
## 2105751 = 0x202197 (bar) ## 2105751 = 0x202197 (bar)
# DISASM: Disassembly of section .text: # DISASM: Disassembly of section .text:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: _start: # DISASM-NEXT: <_start>:
# DISASM-NEXT: 201158: adcq $2105751, %rax # DISASM-NEXT: 201158: adcq $2105751, %rax
# DISASM-NEXT: addq $2105751, %rbx # DISASM-NEXT: addq $2105751, %rbx
# DISASM-NEXT: andq $2105751, %rcx # DISASM-NEXT: andq $2105751, %rcx
# DISASM-NEXT: cmpq $2105751, %rdx # DISASM-NEXT: cmpq $2105751, %rdx
# DISASM-NEXT: orq $2105751, %rdi # DISASM-NEXT: orq $2105751, %rdi
# DISASM-NEXT: sbbq $2105751, %rsi # DISASM-NEXT: sbbq $2105751, %rsi
# DISASM-NEXT: subq $2105751, %rbp # DISASM-NEXT: subq $2105751, %rbp
# DISASM-NEXT: xorq $2105751, %r8 # DISASM-NEXT: xorq $2105751, %r8
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# SEC-PIC-NEXT: } # SEC-PIC-NEXT: }
# SEC-PIC-NEXT: ] # SEC-PIC-NEXT: ]
## Check that there was no relaxation performed. All values refer to got entry. ## Check that there was no relaxation performed. All values refer to got entry.
## Ex: 0x1000 + 4249 + 7 = 0x20A0 ## Ex: 0x1000 + 4249 + 7 = 0x20A0
## 0x102a + 4207 + 7 = 0x20A0 ## 0x102a + 4207 + 7 = 0x20A0
# DISASM-PIC: Disassembly of section .text: # DISASM-PIC: Disassembly of section .text:
# DISASM-PIC-EMPTY: # DISASM-PIC-EMPTY:
# DISASM-PIC-NEXT: _start: # DISASM-PIC-NEXT: <_start>:
# DISASM-PIC-NEXT: 1268: adcq 4313(%rip), %rax # DISASM-PIC-NEXT: 1268: adcq 4313(%rip), %rax
# DISASM-PIC-NEXT: addq 4306(%rip), %rbx # DISASM-PIC-NEXT: addq 4306(%rip), %rbx
# DISASM-PIC-NEXT: andq 4299(%rip), %rcx # DISASM-PIC-NEXT: andq 4299(%rip), %rcx
# DISASM-PIC-NEXT: cmpq 4292(%rip), %rdx # DISASM-PIC-NEXT: cmpq 4292(%rip), %rdx
# DISASM-PIC-NEXT: orq 4285(%rip), %rdi # DISASM-PIC-NEXT: orq 4285(%rip), %rdi
# DISASM-PIC-NEXT: sbbq 4278(%rip), %rsi # DISASM-PIC-NEXT: sbbq 4278(%rip), %rsi
# DISASM-PIC-NEXT: subq 4271(%rip), %rbp # DISASM-PIC-NEXT: subq 4271(%rip), %rbp
# DISASM-PIC-NEXT: xorq 4264(%rip), %r8 # DISASM-PIC-NEXT: xorq 4264(%rip), %r8
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lld/test/ELF/x86-64-gotpc-relax-und-dso.s

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# RELOC-NEXT: R_X86_64_GLOB_DAT und 0x0 # RELOC-NEXT: R_X86_64_GLOB_DAT und 0x0
# RELOC-NEXT: } # RELOC-NEXT: }
# RELOC-NEXT: ] # RELOC-NEXT: ]
# 0x101e + 7 - 36 = 0x1001 # 0x101e + 7 - 36 = 0x1001
# 0x1025 + 7 - 43 = 0x1001 # 0x1025 + 7 - 43 = 0x1001
# DISASM: Disassembly of section .text: # DISASM: Disassembly of section .text:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: foo: # DISASM-NEXT: <foo>:
# DISASM-NEXT: nop # DISASM-NEXT: nop
# DISASM: hid: # DISASM: <hid>:
# DISASM-NEXT: nop # DISASM-NEXT: nop
# DISASM: _start: # DISASM: <_start>:
# DISASM-NEXT: movq 4367(%rip), %rax # DISASM-NEXT: movq 4367(%rip), %rax
# DISASM-NEXT: movq 4360(%rip), %rax # DISASM-NEXT: movq 4360(%rip), %rax
# DISASM-NEXT: movq 4361(%rip), %rax # DISASM-NEXT: movq 4361(%rip), %rax
# DISASM-NEXT: movq 4354(%rip), %rax # DISASM-NEXT: movq 4354(%rip), %rax
# DISASM-NEXT: leaq -36(%rip), %rax # DISASM-NEXT: leaq -36(%rip), %rax
# DISASM-NEXT: leaq -43(%rip), %rax # DISASM-NEXT: leaq -43(%rip), %rax
# DISASM-NEXT: movq 4341(%rip), %rax # DISASM-NEXT: movq 4341(%rip), %rax
# DISASM-NEXT: movq 4334(%rip), %rax # DISASM-NEXT: movq 4334(%rip), %rax
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lld/test/ELF/x86-64-gotpc-relax.s

# REQUIRES: x86 # REQUIRES: x86
# RUN: llvm-mc -filetype=obj -relax-relocations -triple=x86_64-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -relax-relocations -triple=x86_64-unknown-linux %s -o %t.o
# RUN: ld.lld %t.o -o %t1 # RUN: ld.lld %t.o -o %t1
# RUN: llvm-readobj -r %t1 | FileCheck --check-prefix=RELOC %s # RUN: llvm-readobj -r %t1 | FileCheck --check-prefix=RELOC %s
# RUN: llvm-objdump -d %t1 | FileCheck --check-prefix=DISASM %s # RUN: llvm-objdump -d %t1 | FileCheck --check-prefix=DISASM %s
## There is no relocations. ## There is no relocations.
# RELOC: Relocations [ # RELOC: Relocations [
# RELOC: ] # RELOC: ]
# 0x201173 + 7 - 10 = 0x201170 # 0x201173 + 7 - 10 = 0x201170
# 0x20117a + 7 - 17 = 0x201170 # 0x20117a + 7 - 17 = 0x201170
# 0x201181 + 7 - 23 = 0x201171 # 0x201181 + 7 - 23 = 0x201171
# 0x201188 + 7 - 30 = 0x201171 # 0x201188 + 7 - 30 = 0x201171
# DISASM: Disassembly of section .text: # DISASM: Disassembly of section .text:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: foo: # DISASM-NEXT: <foo>:
# DISASM-NEXT: 201170: 90 nop # DISASM-NEXT: 201170: 90 nop
# DISASM: hid: # DISASM: <hid>:
# DISASM-NEXT: 201171: 90 nop # DISASM-NEXT: 201171: 90 nop
# DISASM: ifunc: # DISASM: <ifunc>:
# DISASM-NEXT: 201172: c3 retq # DISASM-NEXT: 201172: c3 retq
# DISASM: _start: # DISASM: <_start>:
# DISASM-NEXT: leaq -10(%rip), %rax # DISASM-NEXT: leaq -10(%rip), %rax
# DISASM-NEXT: leaq -17(%rip), %rax # DISASM-NEXT: leaq -17(%rip), %rax
# DISASM-NEXT: leaq -23(%rip), %rax # DISASM-NEXT: leaq -23(%rip), %rax
# DISASM-NEXT: leaq -30(%rip), %rax # DISASM-NEXT: leaq -30(%rip), %rax
# DISASM-NEXT: movq 4234(%rip), %rax # DISASM-NEXT: movq 4234(%rip), %rax
# DISASM-NEXT: movq 4227(%rip), %rax # DISASM-NEXT: movq 4227(%rip), %rax
# DISASM-NEXT: leaq -52(%rip), %rax # DISASM-NEXT: leaq -52(%rip), %rax
# DISASM-NEXT: leaq -59(%rip), %rax # DISASM-NEXT: leaq -59(%rip), %rax
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lld/test/ELF/x86-64-plt.s

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
// CHECK2: Relocations [ // CHECK2: Relocations [
// CHECK2-NEXT: Section ({{.*}}) .rela.plt { // CHECK2-NEXT: Section ({{.*}}) .rela.plt {
// CHECK2-NEXT: 0x2033F8 R_X86_64_JUMP_SLOT bar 0x0 // CHECK2-NEXT: 0x2033F8 R_X86_64_JUMP_SLOT bar 0x0
// CHECK2-NEXT: 0x203400 R_X86_64_JUMP_SLOT zed 0x0 // CHECK2-NEXT: 0x203400 R_X86_64_JUMP_SLOT zed 0x0
// CHECK2-NEXT: } // CHECK2-NEXT: }
// CHECK2-NEXT: ] // CHECK2-NEXT: ]
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: jmp {{.*}} <bar@plt> // DISASM-NEXT: jmp {{.*}} <bar@plt>
// DISASM-NEXT: jmp {{.*}} <bar@plt> // DISASM-NEXT: jmp {{.*}} <bar@plt>
// DISASM-NEXT: jmp {{.*}} <zed@plt> // DISASM-NEXT: jmp {{.*}} <zed@plt>
// DISASM-NEXT: jmp {{.*}} <_start@plt> // DISASM-NEXT: jmp {{.*}} <_start@plt>
// 0x3018 - 0x1036 = 8162 // 0x3018 - 0x1036 = 8162
// 0x3020 - 0x1046 = 8154 // 0x3020 - 0x1046 = 8154
// 0x3028 - 0x1056 = 8146 // 0x3028 - 0x1056 = 8146
// DISASM: Disassembly of section .plt: // DISASM: Disassembly of section .plt:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: .plt: // DISASM-NEXT: <.plt>:
// DISASM-NEXT: 1320: pushq 8450(%rip) // DISASM-NEXT: 1320: pushq 8450(%rip)
// DISASM-NEXT: jmpq *8452(%rip) // DISASM-NEXT: jmpq *8452(%rip)
// DISASM-NEXT: nopl (%rax) // DISASM-NEXT: nopl (%rax)
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: bar@plt: // DISASM-NEXT: <bar@plt>:
// DISASM-NEXT: 1330: jmpq *8450(%rip) // DISASM-NEXT: 1330: jmpq *8450(%rip)
// DISASM-NEXT: pushq $0 // DISASM-NEXT: pushq $0
// DISASM-NEXT: jmp -32 <.plt> // DISASM-NEXT: jmp -32 <.plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: zed@plt: // DISASM-NEXT: <zed@plt>:
// DISASM-NEXT: 1340: jmpq *8442(%rip) // DISASM-NEXT: 1340: jmpq *8442(%rip)
// DISASM-NEXT: pushq $1 // DISASM-NEXT: pushq $1
// DISASM-NEXT: jmp -48 <.plt> // DISASM-NEXT: jmp -48 <.plt>
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: _start@plt: // DISASM-NEXT: <_start@plt>:
// DISASM-NEXT: 1350: jmpq *8434(%rip) // DISASM-NEXT: 1350: jmpq *8434(%rip)
// DISASM-NEXT: pushq $2 // DISASM-NEXT: pushq $2
// DISASM-NEXT: jmp -64 <.plt> // DISASM-NEXT: jmp -64 <.plt>
// 0x201030 - (0x201000 + 1) - 4 = 43 // 0x201030 - (0x201000 + 1) - 4 = 43
// 0x201030 - (0x201005 + 1) - 4 = 38 // 0x201030 - (0x201005 + 1) - 4 = 38
// 0x201040 - (0x20100a + 1) - 4 = 49 // 0x201040 - (0x20100a + 1) - 4 = 49
// 0x201000 - (0x20100f + 1) - 4 = -20 // 0x201000 - (0x20100f + 1) - 4 = -20
// DISASM2: _start: // DISASM2: <_start>:
// DISASM2-NEXT: jmp 43 <bar@plt> // DISASM2-NEXT: jmp 43 <bar@plt>
// DISASM2-NEXT: jmp 38 <bar@plt> // DISASM2-NEXT: jmp 38 <bar@plt>
// DISASM2-NEXT: jmp 49 <zed@plt> // DISASM2-NEXT: jmp 49 <zed@plt>
// DISASM2-NEXT: jmp -20 <_start> // DISASM2-NEXT: jmp -20 <_start>
// 0x202018 - 0x201036 = 4066 // 0x202018 - 0x201036 = 4066
// 0x202020 - 0x201046 = 4058 // 0x202020 - 0x201046 = 4058
// DISASM2: Disassembly of section .plt: // DISASM2: Disassembly of section .plt:
// DISASM2-EMPTY: // DISASM2-EMPTY:
// DISASM2-NEXT: .plt: // DISASM2-NEXT: <.plt>:
// DISASM2-NEXT: 2012e0: pushq 8450(%rip) // DISASM2-NEXT: 2012e0: pushq 8450(%rip)
// DISASM2-NEXT: jmpq *8452(%rip) // DISASM2-NEXT: jmpq *8452(%rip)
// DISASM2-NEXT: nopl (%rax) // DISASM2-NEXT: nopl (%rax)
// DISASM2-EMPTY: // DISASM2-EMPTY:
// DISASM2-NEXT: bar@plt: // DISASM2-NEXT: <bar@plt>:
// DISASM2-NEXT: 2012f0: jmpq *8450(%rip) // DISASM2-NEXT: 2012f0: jmpq *8450(%rip)
// DISASM2-NEXT: pushq $0 // DISASM2-NEXT: pushq $0
// DISASM2-NEXT: jmp -32 <.plt> // DISASM2-NEXT: jmp -32 <.plt>
// DISASM2-EMPTY: // DISASM2-EMPTY:
// DISASM2-NEXT: zed@plt: // DISASM2-NEXT: <zed@plt>:
// DISASM2-NEXT: 201300: jmpq *8442(%rip) // DISASM2-NEXT: 201300: jmpq *8442(%rip)
// DISASM2-NEXT: pushq $1 // DISASM2-NEXT: pushq $1
// DISASM2-NEXT: jmp -48 <.plt> // DISASM2-NEXT: jmp -48 <.plt>
// DISASM2-NOT: {{.}} // DISASM2-NOT: {{.}}
.global _start .global _start
_start: _start:
jmp bar@PLT jmp bar@PLT
jmp bar@PLT jmp bar@PLT
jmp zed@PLT jmp zed@PLT
jmp _start@plt jmp _start@plt

lld/test/ELF/x86-64-reloc-gotpc64.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
// RUN: ld.lld %t.o -shared -o %t.so // RUN: ld.lld %t.o -shared -o %t.so
// RUN: llvm-readelf -S %t.so | FileCheck %s -check-prefix=SECTION // RUN: llvm-readelf -S %t.so | FileCheck %s -check-prefix=SECTION
// RUN: llvm-objdump -d %t.so | FileCheck %s // RUN: llvm-objdump -d %t.so | FileCheck %s
// SECTION: .got.plt PROGBITS 00000000000032f0 0002f0 000018 // SECTION: .got.plt PROGBITS 00000000000032f0 0002f0 000018
// 0x3300 (.got.plt) - 0x1274 = 8316 // 0x3300 (.got.plt) - 0x1274 = 8316
// CHECK: gotpc64: // CHECK: <gotpc64>:
// CHECK-NEXT: 1274: {{.*}} movabsq $8316, %r11 // CHECK-NEXT: 1274: {{.*}} movabsq $8316, %r11
.global gotpc64 .global gotpc64
gotpc64: gotpc64:
movabsq $_GLOBAL_OFFSET_TABLE_-., %r11 movabsq $_GLOBAL_OFFSET_TABLE_-., %r11

lld/test/ELF/x86-64-reloc-size-shared.s

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// DATA: section '.data': // DATA: section '.data':
// DATA-NEXT: 00000000 00000000 00000000 00000000 // DATA-NEXT: 00000000 00000000 00000000 00000000
// DATA-NEXT: 00000000 00000000 00001900 00000000 // DATA-NEXT: 00000000 00000000 00001900 00000000
// DATA-NEXT: 00001a00 00000000 00001b00 00000000 // DATA-NEXT: 00001a00 00000000 00001b00 00000000
// DATA-NEXT: 00000000 00000000 00000000 00000000 // DATA-NEXT: 00000000 00000000 00000000 00000000
// DATA-NEXT: 00000000 00000000 0000 // DATA-NEXT: 00000000 00000000 0000
// DISASM: _start: // DISASM: <_start>:
// DISASM-NEXT: movl 25, %eax // DISASM-NEXT: movl 25, %eax
// DISASM-NEXT: movl 26, %eax // DISASM-NEXT: movl 26, %eax
// DISASM-NEXT: movl 27, %eax // DISASM-NEXT: movl 27, %eax
// DISASM-NEXT: movl 0, %eax // DISASM-NEXT: movl 0, %eax
// DISASM-NEXT: movl 0, %eax // DISASM-NEXT: movl 0, %eax
// DISASM-NEXT: movl 0, %eax // DISASM-NEXT: movl 0, %eax
.data .data
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lld/test/ELF/x86-64-reloc-size.s

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# NORELOC-NEXT: ] # NORELOC-NEXT: ]
# DATA: section '.data': # DATA: section '.data':
# DATA-NEXT: 0x002031ac 00000000 00000000 00000000 00000000 # DATA-NEXT: 0x002031ac 00000000 00000000 00000000 00000000
# DATA-NEXT: 0x002031bc 00000000 00000000 00001900 00000000 # DATA-NEXT: 0x002031bc 00000000 00000000 00001900 00000000
# DATA-NEXT: 0x002031cc 00001b00 00000000 00001900 00000000 # DATA-NEXT: 0x002031cc 00001b00 00000000 00001900 00000000
# DATA-NEXT: 0x002031dc 00001b00 00000000 0000 # DATA-NEXT: 0x002031dc 00001b00 00000000 0000
# DISASM: _start: # DISASM: <_start>:
# DISASM-NEXT: movl 25, %eax # DISASM-NEXT: movl 25, %eax
# DISASM-NEXT: movl 27, %eax # DISASM-NEXT: movl 27, %eax
# DISASM-NEXT: movl 25, %eax # DISASM-NEXT: movl 25, %eax
# DISASM-NEXT: movl 27, %eax # DISASM-NEXT: movl 27, %eax
# RELOC2: Relocations [ # RELOC2: Relocations [
# RELOC2-NEXT: Section ({{.*}}) .rela.dyn { # RELOC2-NEXT: Section ({{.*}}) .rela.dyn {
# RELOC2-NEXT: 0x2333 R_X86_64_SIZE32 foo 0xFFFFFFFFFFFFFFFF # RELOC2-NEXT: 0x2333 R_X86_64_SIZE32 foo 0xFFFFFFFFFFFFFFFF
# RELOC2-NEXT: 0x233A R_X86_64_SIZE32 foo 0x1 # RELOC2-NEXT: 0x233A R_X86_64_SIZE32 foo 0x1
# RELOC2-NEXT: 0x440A R_X86_64_SIZE64 foo 0xFFFFFFFFFFFFFFFF # RELOC2-NEXT: 0x440A R_X86_64_SIZE64 foo 0xFFFFFFFFFFFFFFFF
# RELOC2-NEXT: 0x4412 R_X86_64_SIZE64 foo 0x1 # RELOC2-NEXT: 0x4412 R_X86_64_SIZE64 foo 0x1
# RELOC2-NEXT: } # RELOC2-NEXT: }
# RELOC2-NEXT: ] # RELOC2-NEXT: ]
# DATA2: section '.data': # DATA2: section '.data':
# DATA2-NEXT: 00000000 00000000 00000000 00000000 # DATA2-NEXT: 00000000 00000000 00000000 00000000
# DATA2-NEXT: 00000000 00000000 00000000 00000000 # DATA2-NEXT: 00000000 00000000 00000000 00000000
# DATA2-NEXT: 00000000 00000000 00001900 00000000 # DATA2-NEXT: 00000000 00000000 00001900 00000000
# DATA2-NEXT: 00001b00 00000000 0000 # DATA2-NEXT: 00001b00 00000000 0000
# DISASM2: _start: # DISASM2: <_start>:
# DISASM2-NEXT: movl 0, %eax # DISASM2-NEXT: movl 0, %eax
# DISASM2-NEXT: movl 0, %eax # DISASM2-NEXT: movl 0, %eax
# DISASM2-NEXT: movl 25, %eax # DISASM2-NEXT: movl 25, %eax
# DISASM2-NEXT: movl 27, %eax # DISASM2-NEXT: movl 27, %eax
.data .data
.global foo, foohidden .global foo, foohidden
.hidden foohidden .hidden foohidden
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lld/test/ELF/x86-64-retpoline-linkerscript.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o
// RUN: ld.lld -shared %t2.o -o %t2.so // RUN: ld.lld -shared %t2.o -o %t2.so
// RUN: echo "SECTIONS { \ // RUN: echo "SECTIONS { \
// RUN: .text : { *(.text) } \ // RUN: .text : { *(.text) } \
// RUN: .plt : { *(.plt) } \ // RUN: .plt : { *(.plt) } \
// RUN: .got.plt : { *(.got.plt) } \ // RUN: .got.plt : { *(.got.plt) } \
// RUN: .dynstr : { *(.dynstr) } \ // RUN: .dynstr : { *(.dynstr) } \
// RUN: }" > %t.script // RUN: }" > %t.script
// RUN: ld.lld -shared %t1.o %t2.so -o %t.exe -z retpolineplt --script %t.script // RUN: ld.lld -shared %t1.o %t2.so -o %t.exe -z retpolineplt --script %t.script
// RUN: llvm-objdump -d -s %t.exe | FileCheck %s // RUN: llvm-objdump -d -s %t.exe | FileCheck %s
// CHECK: Disassembly of section .plt: // CHECK: Disassembly of section .plt:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: .plt: // CHECK-NEXT: <.plt>:
// CHECK-NEXT: 10: ff 35 32 01 00 00 pushq 306(%rip) // CHECK-NEXT: 10: ff 35 32 01 00 00 pushq 306(%rip)
// CHECK-NEXT: 16: 4c 8b 1d 33 01 00 00 movq 307(%rip), %r11 // CHECK-NEXT: 16: 4c 8b 1d 33 01 00 00 movq 307(%rip), %r11
// CHECK-NEXT: 1d: e8 0e 00 00 00 callq 14 <.plt+0x20> // CHECK-NEXT: 1d: e8 0e 00 00 00 callq 14 <.plt+0x20>
// CHECK-NEXT: 22: f3 90 pause // CHECK-NEXT: 22: f3 90 pause
// CHECK-NEXT: 24: 0f ae e8 lfence // CHECK-NEXT: 24: 0f ae e8 lfence
// CHECK-NEXT: 27: eb f9 jmp -7 <.plt+0x12> // CHECK-NEXT: 27: eb f9 jmp -7 <.plt+0x12>
// CHECK-NEXT: 29: cc int3 // CHECK-NEXT: 29: cc int3
// CHECK-NEXT: 2a: cc int3 // CHECK-NEXT: 2a: cc int3
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

lld/test/ELF/x86-64-retpoline-znow-linkerscript.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o
// RUN: ld.lld -shared %t2.o -o %t2.so // RUN: ld.lld -shared %t2.o -o %t2.so
// RUN: echo "SECTIONS { \ // RUN: echo "SECTIONS { \
// RUN: .text : { *(.text) } \ // RUN: .text : { *(.text) } \
// RUN: .plt : { *(.plt) } \ // RUN: .plt : { *(.plt) } \
// RUN: .got.plt : { *(.got.plt) } \ // RUN: .got.plt : { *(.got.plt) } \
// RUN: .dynstr : { *(.dynstr) } \ // RUN: .dynstr : { *(.dynstr) } \
// RUN: }" > %t.script // RUN: }" > %t.script
// RUN: ld.lld -shared %t1.o %t2.so -o %t.exe -z retpolineplt -z now --script %t.script // RUN: ld.lld -shared %t1.o %t2.so -o %t.exe -z retpolineplt -z now --script %t.script
// RUN: llvm-objdump -d -s %t.exe | FileCheck %s // RUN: llvm-objdump -d -s %t.exe | FileCheck %s
// CHECK: Disassembly of section .plt: // CHECK: Disassembly of section .plt:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: .plt: // CHECK-NEXT: <.plt>:
// CHECK-NEXT: 10: e8 0b 00 00 00 callq 11 <.plt+0x10> // CHECK-NEXT: 10: e8 0b 00 00 00 callq 11 <.plt+0x10>
// CHECK-NEXT: 15: f3 90 pause // CHECK-NEXT: 15: f3 90 pause
// CHECK-NEXT: 17: 0f ae e8 lfence // CHECK-NEXT: 17: 0f ae e8 lfence
// CHECK-NEXT: 1a: eb f9 jmp -7 <.plt+0x5> // CHECK-NEXT: 1a: eb f9 jmp -7 <.plt+0x5>
// CHECK-NEXT: 1c: cc int3 // CHECK-NEXT: 1c: cc int3
// CHECK-NEXT: 1d: cc int3 // CHECK-NEXT: 1d: cc int3
// CHECK-NEXT: 1e: cc int3 // CHECK-NEXT: 1e: cc int3
// CHECK-NEXT: 1f: cc int3 // CHECK-NEXT: 1f: cc int3
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lld/test/ELF/x86-64-retpoline-znow-static-iplt.s

# REQUIRES: x86 # REQUIRES: x86
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
# RUN: ld.lld -z retpolineplt -z now %t.o -o %t # RUN: ld.lld -z retpolineplt -z now %t.o -o %t
# RUN: llvm-objdump -d -no-show-raw-insn %t | FileCheck %s # RUN: llvm-objdump -d -no-show-raw-insn %t | FileCheck %s
#0x2011a9+5 + 34 = 0x2011d0 (foo@plt) #0x2011a9+5 + 34 = 0x2011d0 (foo@plt)
# CHECK: _start: # CHECK: <_start>:
# CHECK-NEXT: 2011a9: callq 34 # CHECK-NEXT: 2011a9: callq 34
#Static IPLT header due to -z retpolineplt #Static IPLT header due to -z retpolineplt
# CHECK: 00000000002011b0 .plt: # CHECK: 00000000002011b0 <.plt>:
# CHECK-NEXT: 2011b0: callq 11 <.plt+0x10> # CHECK-NEXT: 2011b0: callq 11 <.plt+0x10>
# CHECK-NEXT: 2011b5: pause # CHECK-NEXT: 2011b5: pause
# CHECK-NEXT: 2011b7: lfence # CHECK-NEXT: 2011b7: lfence
#foo@plt #foo@plt
# CHECK: 2011d0: movq 4105(%rip), %r11 # CHECK: 2011d0: movq 4105(%rip), %r11
# CHECK-NEXT: 2011d7: jmp -44 <.plt> # CHECK-NEXT: 2011d7: jmp -44 <.plt>
.type foo STT_GNU_IFUNC .type foo STT_GNU_IFUNC
.globl foo .globl foo
foo: foo:
ret ret
.globl _start .globl _start
_start: _start:
call foo call foo

lld/test/ELF/x86-64-retpoline-znow.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o
// RUN: ld.lld -shared %t2.o -soname=so -o %t2.so // RUN: ld.lld -shared %t2.o -soname=so -o %t2.so
// RUN: ld.lld -shared %t1.o %t2.so -o %t.exe -z retpolineplt -z now // RUN: ld.lld -shared %t1.o %t2.so -o %t.exe -z retpolineplt -z now
// RUN: llvm-objdump -d -s --no-show-raw-insn %t.exe | FileCheck %s // RUN: llvm-objdump -d -s --no-show-raw-insn %t.exe | FileCheck %s
// CHECK: Contents of section .got.plt: // CHECK: Contents of section .got.plt:
// CHECK-NEXT: 23f0 10230000 00000000 00000000 00000000 // CHECK-NEXT: 23f0 10230000 00000000 00000000 00000000
// CHECK-NEXT: 2400 00000000 00000000 00000000 00000000 // CHECK-NEXT: 2400 00000000 00000000 00000000 00000000
// CHECK-NEXT: 2410 00000000 00000000 // CHECK-NEXT: 2410 00000000 00000000
// CHECK: Disassembly of section .plt: // CHECK: Disassembly of section .plt:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: .plt: // CHECK-NEXT: <.plt>:
// CHECK-NEXT: 12d0: callq 11 <.plt+0x10> // CHECK-NEXT: 12d0: callq 11 <.plt+0x10>
// CHECK-NEXT: pause // CHECK-NEXT: pause
// CHECK-NEXT: lfence // CHECK-NEXT: lfence
// CHECK-NEXT: jmp -7 <.plt+0x5> // CHECK-NEXT: jmp -7 <.plt+0x5>
// CHECK-NEXT: int3 // CHECK-NEXT: int3
// CHECK-NEXT: int3 // CHECK-NEXT: int3
// CHECK-NEXT: int3 // CHECK-NEXT: int3
// CHECK-NEXT: int3 // CHECK-NEXT: int3
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lld/test/ELF/x86-64-retpoline.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o
// RUN: ld.lld -shared %t2.o -soname=so -o %t2.so // RUN: ld.lld -shared %t2.o -soname=so -o %t2.so
// RUN: ld.lld -shared %t1.o %t2.so -o %t.exe -z retpolineplt // RUN: ld.lld -shared %t1.o %t2.so -o %t.exe -z retpolineplt
// RUN: llvm-objdump -d -s --no-show-raw-insn %t.exe | FileCheck %s // RUN: llvm-objdump -d -s --no-show-raw-insn %t.exe | FileCheck %s
// CHECK: Contents of section .got.plt: // CHECK: Contents of section .got.plt:
// CHECK-NEXT: 3430 70230000 00000000 00000000 00000000 // CHECK-NEXT: 3430 70230000 00000000 00000000 00000000
// CHECK-NEXT: 3440 00000000 00000000 41130000 00000000 // CHECK-NEXT: 3440 00000000 00000000 41130000 00000000
// CHECK-NEXT: 3450 61130000 00000000 // CHECK-NEXT: 3450 61130000 00000000
// CHECK: Disassembly of section .plt: // CHECK: Disassembly of section .plt:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: .plt: // CHECK-NEXT: <.plt>:
// CHECK-NEXT: 1300: pushq 8498(%rip) // CHECK-NEXT: 1300: pushq 8498(%rip)
// CHECK-NEXT: movq 8499(%rip), %r11 // CHECK-NEXT: movq 8499(%rip), %r11
// CHECK-NEXT: callq 14 <.plt+0x20> // CHECK-NEXT: callq 14 <.plt+0x20>
// CHECK-NEXT: pause // CHECK-NEXT: pause
// CHECK-NEXT: lfence // CHECK-NEXT: lfence
// CHECK-NEXT: jmp -7 <.plt+0x12> // CHECK-NEXT: jmp -7 <.plt+0x12>
// CHECK-NEXT: int3 // CHECK-NEXT: int3
// CHECK-NEXT: int3 // CHECK-NEXT: int3
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

lld/test/ELF/x86-64-split-stack-prologue-adjust-shared.s

# REQUIRES: x86 # REQUIRES: x86
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/x86-64-split-stack-extra.s -o %t2.o # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/x86-64-split-stack-extra.s -o %t2.o
# RUN: ld.lld --defsym __morestack=0x100 --defsym __morestack_non_split=0x200 %t2.o -o %t4.so -shared # RUN: ld.lld --defsym __morestack=0x100 --defsym __morestack_non_split=0x200 %t2.o -o %t4.so -shared
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o
# RUN: ld.lld --defsym __morestack=0x100 --defsym __morestack_non_split=0x200 %t1.o %t4.so -o %t # RUN: ld.lld --defsym __morestack=0x100 --defsym __morestack_non_split=0x200 %t1.o %t4.so -o %t
# RUN: llvm-objdump -d %t | FileCheck %s # RUN: llvm-objdump -d %t | FileCheck %s
# For a cross .so call, make sure lld produced the conservative call to __morestack_non_split. # For a cross .so call, make sure lld produced the conservative call to __morestack_non_split.
# CHECK: prologue1_cross_so_call: # CHECK: <prologue1_cross_so_call>:
# CHECK-NEXT: stc{{.*$}} # CHECK-NEXT: stc{{.*$}}
# CHECK-NEXT: nopl{{.*$}} # CHECK-NEXT: nopl{{.*$}}
# CHECK: jae{{.*$}} # CHECK: jae{{.*$}}
# CHECK-NEXT: callq{{.*}}<__morestack_non_split> # CHECK-NEXT: callq{{.*}}<__morestack_non_split>
.text .text
.global prologue1_cross_so_call .global prologue1_cross_so_call
Show All 13 Lines

lld/test/ELF/x86-64-split-stack-prologue-adjust-success.s

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesfoo:
.section .text,"ax",@progbits .section .text,"ax",@progbits
.quad foo .quad foo
.text .text
# For split-stack code calling split-stack code, ensure prologue v1 still # For split-stack code calling split-stack code, ensure prologue v1 still
# calls plain __morestack, and that any raw bytes written to the prologue # calls plain __morestack, and that any raw bytes written to the prologue
# make sense. # make sense.
# CHECK: prologue1_calls_split: # CHECK: <prologue1_calls_split>:
# CHECK-NEXT: cmp{{.*}}%fs:{{[^,]*}},{{.*}}%rsp # CHECK-NEXT: cmp{{.*}}%fs:{{[^,]*}},{{.*}}%rsp
# CHECK: jae{{.*$}} # CHECK: jae{{.*$}}
# CHECK-NEXT: callq{{.*}}<__morestack> # CHECK-NEXT: callq{{.*}}<__morestack>
prologue1 split prologue1 split
# For split-stack code calling split-stack code, ensure prologue v2 still # For split-stack code calling split-stack code, ensure prologue v2 still
# calls plain __morestack, that any raw bytes written to the prologue # calls plain __morestack, that any raw bytes written to the prologue
# make sense, and that the register number is preserved. # make sense, and that the register number is preserved.
# CHECK: prologue2_calls_splitr10: # CHECK: <prologue2_calls_splitr10>:
# CHECK-NEXT: lea{{.*}} -512(%rsp),{{.*}}%r10 # CHECK-NEXT: lea{{.*}} -512(%rsp),{{.*}}%r10
# CHECK: cmp{{.*}}%fs:{{[^,]*}},{{.*}}%r{{[0-9]+}} # CHECK: cmp{{.*}}%fs:{{[^,]*}},{{.*}}%r{{[0-9]+}}
# CHECK: jae{{.*}} # CHECK: jae{{.*}}
# CHECK-NEXT: callq{{.*}}<__morestack> # CHECK-NEXT: callq{{.*}}<__morestack>
prologue2 split r10 0x200 prologue2 split r10 0x200
# CHECK: prologue2_calls_splitr11: # CHECK: <prologue2_calls_splitr11>:
# CHECK-NEXT: lea{{.*}} -256(%rsp),{{.*}}%r11 # CHECK-NEXT: lea{{.*}} -256(%rsp),{{.*}}%r11
# CHECK: cmp{{.*}}%fs:{{[^,]*}},{{.*}}%r{{[0-9]+}} # CHECK: cmp{{.*}}%fs:{{[^,]*}},{{.*}}%r{{[0-9]+}}
# CHECK: jae{{.*}} # CHECK: jae{{.*}}
# CHECK-NEXT: callq{{.*}}<__morestack> # CHECK-NEXT: callq{{.*}}<__morestack>
prologue2 split r11 0x100 prologue2 split r11 0x100
# For split-stack code calling non-split-stack code, ensure prologue v1 # For split-stack code calling non-split-stack code, ensure prologue v1
# calls __morestack_non_split, and that any raw bytes written to the prologue # calls __morestack_non_split, and that any raw bytes written to the prologue
# make sense. # make sense.
# CHECK: prologue1_calls_non_split: # CHECK: <prologue1_calls_non_split>:
# CHECK-NEXT: stc{{.*$}} # CHECK-NEXT: stc{{.*$}}
# CHECK-NEXT: nopl{{.*$}} # CHECK-NEXT: nopl{{.*$}}
# CHECK: jae{{.*$}} # CHECK: jae{{.*$}}
# CHECK-NEXT: callq{{.*}}<__morestack_non_split> # CHECK-NEXT: callq{{.*}}<__morestack_non_split>
prologue1 non_split prologue1 non_split
# For split-stack code calling non-split-stack code, ensure prologue v2 # For split-stack code calling non-split-stack code, ensure prologue v2
# calls __morestack_non_split, that any raw bytes written to the prologue # calls __morestack_non_split, that any raw bytes written to the prologue
# make sense, and that the register number is preserved # make sense, and that the register number is preserved
# CHECK: prologue2_calls_non_splitr10: # CHECK: <prologue2_calls_non_splitr10>:
# CHECK-NEXT: lea{{.*}} -16640(%rsp),{{.*}}%r10 # CHECK-NEXT: lea{{.*}} -16640(%rsp),{{.*}}%r10
# CHECK: cmp{{.*}}%fs:{{[^,]*}},{{.*}}%r10 # CHECK: cmp{{.*}}%fs:{{[^,]*}},{{.*}}%r10
# CHECK: jae{{.*$}} # CHECK: jae{{.*$}}
# CHECK-NEXT: callq{{.*}}<__morestack_non_split> # CHECK-NEXT: callq{{.*}}<__morestack_non_split>
prologue2 non_split r10 0x100 prologue2 non_split r10 0x100
# CHECK: prologue2_calls_non_splitr11: # CHECK: <prologue2_calls_non_splitr11>:
# CHECK-NEXT: lea{{.*}} -16896(%rsp),{{.*}}%r11 # CHECK-NEXT: lea{{.*}} -16896(%rsp),{{.*}}%r11
# CHECK: cmp{{.*}}%fs:{{[^,]*}},{{.*}}%r11 # CHECK: cmp{{.*}}%fs:{{[^,]*}},{{.*}}%r11
# CHECK: jae{{.*$}} # CHECK: jae{{.*$}}
# CHECK-NEXT: callq{{.*}}<__morestack_non_split> # CHECK-NEXT: callq{{.*}}<__morestack_non_split>
prologue2 non_split r11 0x200 prologue2 non_split r11 0x200
.section .note.GNU-stack,"",@progbits .section .note.GNU-stack,"",@progbits
.section .note.GNU-split-stack,"",@progbits .section .note.GNU-split-stack,"",@progbits

lld/test/ELF/x86-64-tls-dynamic.s

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
// 4457 = (0x24A0 + -4) - (0x1330 + 3) // PC relative offset to got entry. // 4457 = (0x24A0 + -4) - (0x1330 + 3) // PC relative offset to got entry.
// 4445 = (0x24B0 + -4) - (0x133c + 3) // PC relative offset to got entry. // 4445 = (0x24B0 + -4) - (0x133c + 3) // PC relative offset to got entry.
// 4427 = (0x24B8 + -4) - (0x135e + 3) // PC relative offset to got entry. // 4427 = (0x24B8 + -4) - (0x135e + 3) // PC relative offset to got entry.
// 4423 = (0x24C0 + -4) - (0x1372 + 3) // PC relative offset to got entry. // 4423 = (0x24C0 + -4) - (0x1372 + 3) // PC relative offset to got entry.
// DIS: Disassembly of section .text: // DIS: Disassembly of section .text:
// DIS-EMPTY: // DIS-EMPTY:
// DIS-NEXT: .text: // DIS-NEXT: <.text>:
// DIS-NEXT: 1330: {{.+}} leaq 4457(%rip), %rdi // DIS-NEXT: 1330: {{.+}} leaq 4457(%rip), %rdi
// DIS-NEXT: {{.+}} callq // DIS-NEXT: {{.+}} callq
// DIS-NEXT: 133c: {{.+}} leaq 4445(%rip), %rdi // DIS-NEXT: 133c: {{.+}} leaq 4445(%rip), %rdi
// DIS-NEXT: {{.+}} callq // DIS-NEXT: {{.+}} callq
// DIS-NEXT: {{.+}} leaq (%rax), %rcx // DIS-NEXT: {{.+}} leaq (%rax), %rcx
// DIS-NEXT: {{.+}} leaq 4(%rax), %rcx // DIS-NEXT: {{.+}} leaq 4(%rax), %rcx
// DIS-NEXT: 04 00 // DIS-NEXT: 04 00
// DIS-NEXT: 00 00 // DIS-NEXT: 00 00
Show All 10 Lines

lld/test/ELF/x86-64-tls-gd-got.s

# REQUIRES: x86 # REQUIRES: x86
# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t1.o # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t1.o
# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/x86-64-tls-gd-got.s -o %t2.o # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/x86-64-tls-gd-got.s -o %t2.o
# RUN: ld.lld %t1.o %t2.o -o %t # RUN: ld.lld %t1.o %t2.o -o %t
# RUN: llvm-objdump -d %t | FileCheck %s # RUN: llvm-objdump -d %t | FileCheck %s
.globl _start .globl _start
_start: _start:
.byte 0x66 .byte 0x66
leaq bar@tlsgd(%rip), %rdi leaq bar@tlsgd(%rip), %rdi
.byte 0x66 .byte 0x66
rex64 rex64
call *__tls_get_addr@GOTPCREL(%rip) call *__tls_get_addr@GOTPCREL(%rip)
ret ret
// CHECK: _start: // CHECK: <_start>:
// CHECK-NEXT: movq %fs:0, %rax // CHECK-NEXT: movq %fs:0, %rax
// CHECK-NEXT: leaq -4(%rax), %rax // CHECK-NEXT: leaq -4(%rax), %rax
// CHECK-NEXT: retq // CHECK-NEXT: retq

lld/test/ELF/x86-64-tls-gdie.s

Show All 14 Lines
//RELOC-NEXT: 0x2023B0 R_X86_64_TPOFF64 tlsshared1 0x0 //RELOC-NEXT: 0x2023B0 R_X86_64_TPOFF64 tlsshared1 0x0
//RELOC-NEXT: } //RELOC-NEXT: }
//RELOC-NEXT: ] //RELOC-NEXT: ]
// 0x2023A8 - (2012d1+7) = 4304 // 0x2023A8 - (2012d1+7) = 4304
// 0x2023B0 - (2012e1+7) = 4296 // 0x2023B0 - (2012e1+7) = 4296
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: _start: // DISASM-NEXT: <_start>:
// DISASM-NEXT: movq %fs:0, %rax // DISASM-NEXT: movq %fs:0, %rax
// DISASM-NEXT: 2012d1: addq 4304(%rip), %rax // DISASM-NEXT: 2012d1: addq 4304(%rip), %rax
// DISASM-NEXT: movq %fs:0, %rax // DISASM-NEXT: movq %fs:0, %rax
// DISASM-NEXT: 2012e1: addq 4296(%rip), %rax // DISASM-NEXT: 2012e1: addq 4296(%rip), %rax
.section .text .section .text
.globl _start .globl _start
_start: _start:
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lld/test/ELF/x86-64-tls-ie-opt-local.s

// REQUIRES: x86 // REQUIRES: x86
// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
// RUN: ld.lld %t.o -o %t1 // RUN: ld.lld %t.o -o %t1
// RUN: llvm-readobj -r %t1 | FileCheck --check-prefix=NORELOC %s // RUN: llvm-readobj -r %t1 | FileCheck --check-prefix=NORELOC %s
// RUN: llvm-objdump -d %t1 | FileCheck --check-prefix=DISASM %s // RUN: llvm-objdump -d %t1 | FileCheck --check-prefix=DISASM %s
// NORELOC: Relocations [ // NORELOC: Relocations [
// NORELOC-NEXT: ] // NORELOC-NEXT: ]
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: _start: // DISASM-NEXT: <_start>:
// DISASM-NEXT: movq $-8, %rax // DISASM-NEXT: movq $-8, %rax
// DISASM-NEXT: movq $-8, %r15 // DISASM-NEXT: movq $-8, %r15
// DISASM-NEXT: leaq -8(%rax), %rax // DISASM-NEXT: leaq -8(%rax), %rax
// DISASM-NEXT: leaq -8(%r15), %r15 // DISASM-NEXT: leaq -8(%r15), %r15
// DISASM-NEXT: addq $-8, %rsp // DISASM-NEXT: addq $-8, %rsp
// DISASM-NEXT: addq $-8, %r12 // DISASM-NEXT: addq $-8, %r12
// DISASM-NEXT: movq $-4, %rax // DISASM-NEXT: movq $-4, %rax
// DISASM-NEXT: movq $-4, %r15 // DISASM-NEXT: movq $-4, %r15
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lld/test/ELF/x86-64-tls-ie.s

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// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK-NEXT: ] // CHECK-NEXT: ]
// 0x2012d0 + 4329 + 7 = 0x2023C0 // 0x2012d0 + 4329 + 7 = 0x2023C0
// 0x2012dA + 4327 + 7 = 0x2023C8 // 0x2012dA + 4327 + 7 = 0x2023C8
// 0x2012e4 + 4317 + 7 = 0x2023C8 // 0x2012e4 + 4317 + 7 = 0x2023C8
// DISASM: Disassembly of section .text: // DISASM: Disassembly of section .text:
// DISASM-EMPTY: // DISASM-EMPTY:
// DISASM-NEXT: main: // DISASM-NEXT: <main>:
// DISASM-NEXT: 2012d0: {{.*}} movq 4329(%rip), %rax // DISASM-NEXT: 2012d0: {{.*}} movq 4329(%rip), %rax
// DISASM-NEXT: 2012d7: {{.*}} movl %fs:(%rax), %eax // DISASM-NEXT: 2012d7: {{.*}} movl %fs:(%rax), %eax
// DISASM-NEXT: 2012da: {{.*}} movq 4327(%rip), %rax // DISASM-NEXT: 2012da: {{.*}} movq 4327(%rip), %rax
// DISASM-NEXT: 2012e1: {{.*}} movl %fs:(%rax), %eax // DISASM-NEXT: 2012e1: {{.*}} movl %fs:(%rax), %eax
// DISASM-NEXT: 2012e4: {{.*}} movq 4317(%rip), %rax // DISASM-NEXT: 2012e4: {{.*}} movq 4317(%rip), %rax
// DISASM-NEXT: 2012eb: {{.*}} movl %fs:(%rax), %eax // DISASM-NEXT: 2012eb: {{.*}} movl %fs:(%rax), %eax
// DISASM-NEXT: 2012ee: {{.*}} retq // DISASM-NEXT: 2012ee: {{.*}} retq
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lld/test/ELF/x86-64-tls-opt-noplt.s

Show All 11 Lines
// RELOC: Relocations [ // RELOC: Relocations [
// RELOC-NEXT: Section {{.*}} .rela.dyn { // RELOC-NEXT: Section {{.*}} .rela.dyn {
// RELOC-NEXT: 0x202420 R_X86_64_TPOFF64 tlsshared0 0x0 // RELOC-NEXT: 0x202420 R_X86_64_TPOFF64 tlsshared0 0x0
// RELOC-NEXT: 0x202428 R_X86_64_TPOFF64 tlsshared1 0x0 // RELOC-NEXT: 0x202428 R_X86_64_TPOFF64 tlsshared1 0x0
// RELOC-NEXT: } // RELOC-NEXT: }
// RELOC-NEXT: ] // RELOC-NEXT: ]
// DISASM: _start: // DISASM: <_start>:
// Table 11.5: GD -> IE Code Transition (LP64) // Table 11.5: GD -> IE Code Transition (LP64)
// DISASM-NEXT: movq %fs:0, %rax // DISASM-NEXT: movq %fs:0, %rax
// DISASM-NEXT: 201309: addq 4368(%rip), %rax // DISASM-NEXT: 201309: addq 4368(%rip), %rax
// DISASM-NEXT: movq %fs:0, %rax // DISASM-NEXT: movq %fs:0, %rax
// DISASM-NEXT: 201319: addq 4360(%rip), %rax // DISASM-NEXT: 201319: addq 4360(%rip), %rax
// Table 11.7: GD -> LE Code Transition (LP64) // Table 11.7: GD -> LE Code Transition (LP64)
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llvm/test/CodeGen/AArch64/arm64-simplest-elf.ll

; RUN: llc -mtriple=arm64-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=arm64-linux-gnu < %s | FileCheck %s
; RUN: llc -mtriple=arm64-linux-gnu -filetype=obj < %s | llvm-objdump - -r -d --triple=arm64-linux-gnu | FileCheck --check-prefix=CHECK-ELF %s ; RUN: llc -mtriple=arm64-linux-gnu -filetype=obj < %s | llvm-objdump - -r -d --triple=arm64-linux-gnu | FileCheck --check-prefix=CHECK-ELF %s
define void @foo() nounwind { define void @foo() nounwind {
ret void ret void
} }
; Check source looks ELF-like: no leading underscore, comments with // ; Check source looks ELF-like: no leading underscore, comments with //
; CHECK: foo: // @foo ; CHECK: foo: // @foo
; CHECK: ret ; CHECK: ret
; Similarly make sure ELF output works and is vaguely sane: aarch64 target ; Similarly make sure ELF output works and is vaguely sane: aarch64 target
; machine with correct section & symbol names. ; machine with correct section & symbol names.
; CHECK-ELF: file format elf64-aarch64 ; CHECK-ELF: file format elf64-aarch64
; CHECK-ELF: Disassembly of section .text ; CHECK-ELF: Disassembly of section .text
; CHECK-ELF-LABEL: foo: ; CHECK-ELF-LABEL: <foo>:
; CHECK-ELF: ret ; CHECK-ELF: ret

llvm/test/CodeGen/AArch64/callbr-asm-obj-file.ll

; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -filetype=obj -o - \ ; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -filetype=obj -o - \
; RUN: | llvm-objdump -triple aarch64-unknown-linux-gnu -d - \ ; RUN: | llvm-objdump -triple aarch64-unknown-linux-gnu -d - \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
%struct.c = type { i1 (...)* } %struct.c = type { i1 (...)* }
@l = common hidden local_unnamed_addr global i32 0, align 4 @l = common hidden local_unnamed_addr global i32 0, align 4
; CHECK-LABEL: test1: ; CHECK-LABEL: <test1>:
; CHECK-LABEL: $d.1: ; CHECK-LABEL: <$d.1>:
; CHECK-LABEL: $x.2: ; CHECK-LABEL: <$x.2>:
; CHECK-NEXT: b #16 <$x.4+0x4> ; CHECK-NEXT: b #16 <$x.4+0x4>
; CHECK-LABEL: $x.4: ; CHECK-LABEL: <$x.4>:
; CHECK-NEXT: b #4 <$x.4+0x4> ; CHECK-NEXT: b #4 <$x.4+0x4>
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: ldr x30, [sp], #16 ; CHECK-NEXT: ldr x30, [sp], #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define hidden i32 @test1() { define hidden i32 @test1() {
%1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)() %1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
%2 = icmp eq i32 %1, 0 %2 = icmp eq i32 %1, 0
br i1 %2, label %3, label %5 br i1 %2, label %3, label %5
Show All 13 Lines7: ; preds = %3, %4, %5
%8 = phi i32 [ %6, %5 ], [ 0, %4 ], [ 0, %3 ] %8 = phi i32 [ %6, %5 ], [ 0, %4 ], [ 0, %3 ]
ret i32 %8 ret i32 %8
} }
declare dso_local i32 @g(...) local_unnamed_addr declare dso_local i32 @g(...) local_unnamed_addr
declare dso_local i32 @i(...) local_unnamed_addr declare dso_local i32 @i(...) local_unnamed_addr
; CHECK-LABEL: test2: ; CHECK-LABEL: <test2>:
; CHECK: bl #0 <test2+0x10> ; CHECK: bl #0 <test2+0x10>
; CHECK-LABEL: $d.5: ; CHECK-LABEL: <$d.5>:
; CHECK-LABEL: $x.6: ; CHECK-LABEL: <$x.6>:
; CHECK-NEXT: b #16 <$x.8+0x4> ; CHECK-NEXT: b #16 <$x.8+0x4>
define hidden i32 @test2() local_unnamed_addr { define hidden i32 @test2() local_unnamed_addr {
%1 = load i32, i32* @l, align 4 %1 = load i32, i32* @l, align 4
%2 = icmp eq i32 %1, 0 %2 = icmp eq i32 %1, 0
br i1 %2, label %10, label %3 br i1 %2, label %10, label %3
3: ; preds = %0 3: ; preds = %0
%4 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)() %4 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
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9: ; preds = %6 9: ; preds = %6
br label %10 br label %10
10: ; preds = %7, %0, %6, %9 10: ; preds = %7, %0, %6, %9
ret i32 undef ret i32 undef
} }
; CHECK-LABEL: test3: ; CHECK-LABEL: <test3>:
; CHECK-LABEL: $d.9: ; CHECK-LABEL: <$d.9>:
; CHECK-LABEL: $x.10: ; CHECK-LABEL: <$x.10>:
; CHECK-NEXT: b #-20 <test3+0x18> ; CHECK-NEXT: b #-20 <test3+0x18>
; CHECK-LABEL: $x.12: ; CHECK-LABEL: <$x.12>:
; CHECK-NEXT: b #4 <$x.12+0x4> ; CHECK-NEXT: b #4 <$x.12+0x4>
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: ldr x30, [sp], #16 ; CHECK-NEXT: ldr x30, [sp], #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define internal i1 @test3() { define internal i1 @test3() {
%1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)() %1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
%2 = icmp eq i32 %1, 0 %2 = icmp eq i32 %1, 0
br i1 %2, label %3, label %5 br i1 %2, label %3, label %5
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llvm/test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll

; We actually need to use -filetype=obj in this test because if we output ; We actually need to use -filetype=obj in this test because if we output
; assembly, the current code path will bypass the parser and just write the ; assembly, the current code path will bypass the parser and just write the
; raw text out to the Streamer. We need to actually parse the inlineasm to ; raw text out to the Streamer. We need to actually parse the inlineasm to
; demonstrate the bug. Going the asm->obj route does not show the issue. ; demonstrate the bug. Going the asm->obj route does not show the issue.
; RUN: llc -mtriple=aarch64 < %s -filetype=obj | llvm-objdump -arch=aarch64 -d - | FileCheck %s ; RUN: llc -mtriple=aarch64 < %s -filetype=obj | llvm-objdump -arch=aarch64 -d - | FileCheck %s
; CHECK-LABEL: foo: ; CHECK-LABEL: <foo>:
; CHECK: a0 79 95 d2 mov x0, #43981 ; CHECK: a0 79 95 d2 mov x0, #43981
; CHECK: c0 03 5f d6 ret ; CHECK: c0 03 5f d6 ret
define i32 @foo() nounwind { define i32 @foo() nounwind {
entry: entry:
%0 = tail call i32 asm sideeffect "ldr $0,=0xabcd", "=r"() nounwind %0 = tail call i32 asm sideeffect "ldr $0,=0xabcd", "=r"() nounwind
ret i32 %0 ret i32 %0
} }
; CHECK-LABEL: bar: ; CHECK-LABEL: <bar>:
; CHECK: 40 00 00 58 ldr x0, #8 ; CHECK: 40 00 00 58 ldr x0, #8
; CHECK: c0 03 5f d6 ret ; CHECK: c0 03 5f d6 ret
; Make sure the constant pool entry comes after the return ; Make sure the constant pool entry comes after the return
; CHECK-LABEL: $d.1: ; CHECK-LABEL: <$d.1>:
define i32 @bar() nounwind { define i32 @bar() nounwind {
entry: entry:
%0 = tail call i32 asm sideeffect "ldr $0,=0x10001", "=r"() nounwind %0 = tail call i32 asm sideeffect "ldr $0,=0x10001", "=r"() nounwind
ret i32 %0 ret i32 %0
} }

llvm/test/CodeGen/AArch64/space.ll

; RUN: llc -mtriple aarch64 %s -o - | FileCheck %s ; RUN: llc -mtriple aarch64 %s -o - | FileCheck %s
; RUN: llc -mtriple aarch64 -filetype=obj %s -o - | llvm-objdump --arch=aarch64 -d - | FileCheck %s --check-prefix=DUMP ; RUN: llc -mtriple aarch64 -filetype=obj %s -o - | llvm-objdump --arch=aarch64 -d - | FileCheck %s --check-prefix=DUMP
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
define dso_local void @f(i64 %v) { define dso_local void @f(i64 %v) {
entry: entry:
%dummy = tail call i64 @llvm.aarch64.space(i32 32684, i64 %v) %dummy = tail call i64 @llvm.aarch64.space(i32 32684, i64 %v)
ret void ret void
} }
; CHECK: // SPACE ; CHECK: // SPACE
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; DUMP-LABEL: f: ; DUMP-LABEL: <f>:
; DUMP-NEXT: ret ; DUMP-NEXT: ret
declare dso_local i64 @llvm.aarch64.space(i32, i64) local_unnamed_addr #0 declare dso_local i64 @llvm.aarch64.space(i32, i64) local_unnamed_addr #0

llvm/test/CodeGen/AMDGPU/nop-data.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=fiji -filetype=obj < %s | llvm-objdump -d - -mcpu=fiji | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=fiji -filetype=obj < %s | llvm-objdump -d - -mcpu=fiji | FileCheck %s
; CHECK: kernel0: ; CHECK: <kernel0>:
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
define amdgpu_kernel void @kernel0() align 256 { define amdgpu_kernel void @kernel0() align 256 {
entry: entry:
ret void ret void
} }
; CHECK-NEXT: s_nop 0 ; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_nop 0 ; CHECK-NEXT: s_nop 0
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; CHECK-NEXT: s_nop 0 ; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_nop 0 ; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_nop 0 ; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_nop 0 ; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_nop 0 ; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_nop 0 // 0000000001FC: BF800000 ; CHECK-NEXT: s_nop 0 // 0000000001FC: BF800000
; CHECK-EMPTY: ; CHECK-EMPTY:
; CHECK-NEXT: kernel1: ; CHECK-NEXT: <kernel1>:
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
define amdgpu_kernel void @kernel1(i32 addrspace(1)* addrspace(4)* %ptr.out) align 256 { define amdgpu_kernel void @kernel1(i32 addrspace(1)* addrspace(4)* %ptr.out) align 256 {
entry: entry:
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/s_code_end.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10END,GFX10END-ASM %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10END,GFX10END-ASM %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj < %s | llvm-objdump -arch=amdgcn -mcpu=gfx1010 -disassemble - | FileCheck -check-prefixes=GCN,GCN-OBJ,GFX10END,GFX10END-OBJ %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj < %s | llvm-objdump -arch=amdgcn -mcpu=gfx1010 -disassemble - | FileCheck -check-prefixes=GCN,GCN-OBJ,GFX10END,GFX10END-OBJ %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10END,GFX10END-ASM %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10END,GFX10END-ASM %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10NOEND,GFX10NOEND-ASM %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10NOEND,GFX10NOEND-ASM %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -filetype=obj < %s | llvm-objdump -arch=amdgcn -mcpu=gfx1010 -disassemble - | FileCheck -check-prefixes=GCN,GCN-OBJ,GFX10NOEND,GFX10NOEND-OBJ %s ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -filetype=obj < %s | llvm-objdump -arch=amdgcn -mcpu=gfx1010 -disassemble - | FileCheck -check-prefixes=GCN,GCN-OBJ,GFX10NOEND,GFX10NOEND-OBJ %s
; GCN: a_kernel1: ; GCN: a_kernel1{{>?}}:
; GCN: s_endpgm ; GCN: s_endpgm
; GCN-ASM: [[END_LABEL1:\.Lfunc_end.*]]: ; GCN-ASM: [[END_LABEL1:\.Lfunc_end.*]]:
; GCN-ASM-NEXT: .size a_kernel1, [[END_LABEL1]]-a_kernel1 ; GCN-ASM-NEXT: .size a_kernel1, [[END_LABEL1]]-a_kernel1
; GCN-OBJ-NEXT: s_nop 0 ; GCN-OBJ-NEXT: s_nop 0
define amdgpu_kernel void @a_kernel1() { define amdgpu_kernel void @a_kernel1() {
ret void ret void
} }
; GCN: a_kernel2: ; GCN: a_kernel2{{>?}}:
; GCN: s_endpgm ; GCN: s_endpgm
; GCN-ASM: [[END_LABEL2:\.Lfunc_end.*]]: ; GCN-ASM: [[END_LABEL2:\.Lfunc_end.*]]:
; GCN-ASM-NEXT: .size a_kernel2, [[END_LABEL2]]-a_kernel2 ; GCN-ASM-NEXT: .size a_kernel2, [[END_LABEL2]]-a_kernel2
; GCN-OBJ: {{^$}} ; GCN-OBJ: {{^$}}
define amdgpu_kernel void @a_kernel2() { define amdgpu_kernel void @a_kernel2() {
ret void ret void
} }
; GCN-ASM: .globl a_function ; GCN-ASM: .globl a_function
; GCN-ASM-NEXT: .p2align 2 ; GCN-ASM-NEXT: .p2align 2
; GCN-ASM-NEXT: .type a_function,@function ; GCN-ASM-NEXT: .type a_function,@function
; GCN-NEXT: a_function: ; GCN-NEXT: a_function{{>?}}:
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
; GCN-ASM-NEXT: [[END_LABEL3:\.Lfunc_end.*]]: ; GCN-ASM-NEXT: [[END_LABEL3:\.Lfunc_end.*]]:
; GCN-ASM-NEXT: .size a_function, [[END_LABEL3]]-a_function ; GCN-ASM-NEXT: .size a_function, [[END_LABEL3]]-a_function
; GFX10END-ASM: .p2alignl 6, 3214868480 ; GFX10END-ASM: .p2alignl 6, 3214868480
; GFX10END-ASM-NEXT: .fill 48, 4, 3214868480 ; GFX10END-ASM-NEXT: .fill 48, 4, 3214868480
; GFX10NOEND-NOT: .fill ; GFX10NOEND-NOT: .fill
; GFX10NOEND-OBJ-NOT: s_code_end ; GFX10NOEND-OBJ-NOT: s_code_end
; GFX10END-OBJ-NEXT: s_code_end ; GFX10END-OBJ-NEXT: s_code_end
; GFX10END-OBJ: s_code_end // 000000000140: ; GFX10END-OBJ: s_code_end // 000000000140:
; GFX10END-OBJ-COUNT-47: s_code_end ; GFX10END-OBJ-COUNT-47: s_code_end
define void @a_function() { define void @a_function() {
ret void ret void
} }

llvm/test/CodeGen/ARM/Windows/trivial-gnu-object.ll

; RUN: llc -mtriple=thumbv7-windows-itanium -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s ; RUN: llc -mtriple=thumbv7-windows-itanium -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
; RUN: llc -mtriple=thumbv7-windows-gnu -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s ; RUN: llc -mtriple=thumbv7-windows-gnu -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
define void @foo() { define void @foo() {
; CHECK: file format coff-arm ; CHECK: file format coff-arm
; CHECK-LABEL: foo: ; CHECK-LABEL: <foo>:
; CHECK: bx lr ; CHECK: bx lr
ret void ret void
} }

llvm/test/CodeGen/ARM/inlineasm-ldr-pseudo.ll

; PR18354 ; PR18354
; We actually need to use -filetype=obj in this test because if we output ; We actually need to use -filetype=obj in this test because if we output
; assembly, the current code path will bypass the parser and just write the ; assembly, the current code path will bypass the parser and just write the
; raw text out to the Streamer. We need to actually parse the inlineasm to ; raw text out to the Streamer. We need to actually parse the inlineasm to
; demonstrate the bug. Going the asm->obj route does not show the issue. ; demonstrate the bug. Going the asm->obj route does not show the issue.
; RUN: llc -mtriple=arm-none-linux < %s -filetype=obj | llvm-objdump -d - | FileCheck %s ; RUN: llc -mtriple=arm-none-linux < %s -filetype=obj | llvm-objdump -d - | FileCheck %s
; RUN: llc -mtriple=arm-apple-darwin < %s -filetype=obj | llvm-objdump -d - | FileCheck %s ; RUN: llc -mtriple=arm-apple-darwin < %s -filetype=obj | llvm-objdump -d - | FileCheck %s
; CHECK-LABEL: foo: ; CHECK-LABEL: <{{_?}}foo>:
; CHECK: 0: 00 00 9f e5 ldr r0, [pc] ; CHECK: 0: 00 00 9f e5 ldr r0, [pc]
; CHECK: 4: 0e f0 a0 e1 mov pc, lr ; CHECK: 4: 0e f0 a0 e1 mov pc, lr
; Make sure the constant pool entry comes after the return ; Make sure the constant pool entry comes after the return
; CHECK: 8: 78 56 34 12 ; CHECK: 8: 78 56 34 12
define i32 @foo() nounwind { define i32 @foo() nounwind {
entry: entry:
%0 = tail call i32 asm sideeffect "ldr $0,=0x12345678", "=r"() nounwind %0 = tail call i32 asm sideeffect "ldr $0,=0x12345678", "=r"() nounwind
ret i32 %0 ret i32 %0
} }

llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
declare void @use_K(%struct.K* byval) declare void @use_K(%struct.K* byval)
%struct.L = type { [ 100 x i32 ], [ 3 x i8 ] } ; 403 bytes %struct.L = type { [ 100 x i32 ], [ 3 x i8 ] } ; 403 bytes
declare void @use_L(%struct.L* byval) declare void @use_L(%struct.L* byval)
%struct.M = type { [ 64 x i8 ] } ; 64 bytes %struct.M = type { [ 64 x i8 ] } ; 64 bytes
declare void @use_M(%struct.M* byval) declare void @use_M(%struct.M* byval)
%struct.N = type { [ 128 x i8 ] } ; 128 bytes %struct.N = type { [ 128 x i8 ] } ; 128 bytes
declare void @use_N(%struct.N* byval) declare void @use_N(%struct.N* byval)
;ARM-LABEL: test_A_1: ;ARM-LABEL: <test_A_1>:
;THUMB2-LABEL: test_A_1: ;THUMB2-LABEL: <test_A_1>:
;NO_NEON-LABEL:test_A_1: ;NO_NEON-LABEL:<test_A_1>:
;THUMB1-LABEL: test_A_1: ;THUMB1-LABEL: <test_A_1>:
;T1POST-LABEL: test_A_1: ;T1POST-LABEL: <test_A_1>:
define void @test_A_1() { define void @test_A_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.A, align 1 %a = alloca %struct.A, align 1
call void @use_A(%struct.A* byval align 1 %a) call void @use_A(%struct.A* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_A_2: ;ARM-LABEL: <test_A_2>:
;THUMB2-LABEL: test_A_2: ;THUMB2-LABEL: <test_A_2>:
;NO_NEON-LABEL:test_A_2: ;NO_NEON-LABEL:<test_A_2>:
;THUMB1-LABEL: test_A_2: ;THUMB1-LABEL: <test_A_2>:
;T1POST-LABEL: test_A_2: ;T1POST-LABEL: <test_A_2>:
define void @test_A_2() { define void @test_A_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.A, align 2 %a = alloca %struct.A, align 2
call void @use_A(%struct.A* byval align 2 %a) call void @use_A(%struct.A* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_A_4: ;ARM-LABEL: <test_A_4>:
;THUMB2-LABEL: test_A_4: ;THUMB2-LABEL: <test_A_4>:
;NO_NEON-LABEL:test_A_4: ;NO_NEON-LABEL:<test_A_4>:
;THUMB1-LABEL: test_A_4: ;THUMB1-LABEL: <test_A_4>:
;T1POST-LABEL: test_A_4: ;T1POST-LABEL: <test_A_4>:
define void @test_A_4() { define void @test_A_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.A, align 4 %a = alloca %struct.A, align 4
call void @use_A(%struct.A* byval align 4 %a) call void @use_A(%struct.A* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_A_8: ;ARM-LABEL: <test_A_8>:
;THUMB2-LABEL: test_A_8: ;THUMB2-LABEL: <test_A_8>:
;NO_NEON-LABEL:test_A_8: ;NO_NEON-LABEL:<test_A_8>:
;THUMB1-LABEL: test_A_8: ;THUMB1-LABEL: <test_A_8>:
;T1POST-LABEL: test_A_8: ;T1POST-LABEL: <test_A_8>:
define void @test_A_8() { define void @test_A_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.A, align 8 %a = alloca %struct.A, align 8
call void @use_A(%struct.A* byval align 8 %a) call void @use_A(%struct.A* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_A_16: ;ARM-LABEL: <test_A_16>:
;THUMB2-LABEL: test_A_16: ;THUMB2-LABEL: <test_A_16>:
;NO_NEON-LABEL:test_A_16: ;NO_NEON-LABEL:<test_A_16>:
;THUMB1-LABEL: test_A_16: ;THUMB1-LABEL: <test_A_16>:
;T1POST-LABEL: test_A_16: ;T1POST-LABEL: <test_A_16>:
define void @test_A_16() { define void @test_A_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.A, align 16 %a = alloca %struct.A, align 16
call void @use_A(%struct.A* byval align 16 %a) call void @use_A(%struct.A* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_B_1: ;ARM-LABEL: <test_B_1>:
;THUMB2-LABEL: test_B_1: ;THUMB2-LABEL: <test_B_1>:
;NO_NEON-LABEL:test_B_1: ;NO_NEON-LABEL:<test_B_1>:
;THUMB1-LABEL: test_B_1: ;THUMB1-LABEL: <test_B_1>:
;T1POST-LABEL: test_B_1: ;T1POST-LABEL: <test_B_1>:
define void @test_B_1() { define void @test_B_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.B, align 1 %a = alloca %struct.B, align 1
call void @use_B(%struct.B* byval align 1 %a) call void @use_B(%struct.B* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_B_2: ;ARM-LABEL: <test_B_2>:
;THUMB2-LABEL: test_B_2: ;THUMB2-LABEL: <test_B_2>:
;NO_NEON-LABEL:test_B_2: ;NO_NEON-LABEL:<test_B_2>:
;THUMB1-LABEL: test_B_2: ;THUMB1-LABEL: <test_B_2>:
;T1POST-LABEL: test_B_2: ;T1POST-LABEL: <test_B_2>:
define void @test_B_2() { define void @test_B_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.B, align 2 %a = alloca %struct.B, align 2
call void @use_B(%struct.B* byval align 2 %a) call void @use_B(%struct.B* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_B_4: ;ARM-LABEL: <test_B_4>:
;THUMB2-LABEL: test_B_4: ;THUMB2-LABEL: <test_B_4>:
;NO_NEON-LABEL:test_B_4: ;NO_NEON-LABEL:<test_B_4>:
;THUMB1-LABEL: test_B_4: ;THUMB1-LABEL: <test_B_4>:
;T1POST-LABEL: test_B_4: ;T1POST-LABEL: <test_B_4>:
define void @test_B_4() { define void @test_B_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.B, align 4 %a = alloca %struct.B, align 4
call void @use_B(%struct.B* byval align 4 %a) call void @use_B(%struct.B* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_B_8: ;ARM-LABEL: <test_B_8>:
;THUMB2-LABEL: test_B_8: ;THUMB2-LABEL: <test_B_8>:
;NO_NEON-LABEL:test_B_8: ;NO_NEON-LABEL:<test_B_8>:
;THUMB1-LABEL: test_B_8: ;THUMB1-LABEL: <test_B_8>:
;T1POST-LABEL: test_B_8: ;T1POST-LABEL: <test_B_8>:
define void @test_B_8() { define void @test_B_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.B, align 8 %a = alloca %struct.B, align 8
call void @use_B(%struct.B* byval align 8 %a) call void @use_B(%struct.B* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_B_16: ;ARM-LABEL: <test_B_16>:
;THUMB2-LABEL: test_B_16: ;THUMB2-LABEL: <test_B_16>:
;NO_NEON-LABEL:test_B_16: ;NO_NEON-LABEL:<test_B_16>:
;THUMB1-LABEL: test_B_16: ;THUMB1-LABEL: <test_B_16>:
;T1POST-LABEL: test_B_16: ;T1POST-LABEL: <test_B_16>:
define void @test_B_16() { define void @test_B_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.B, align 16 %a = alloca %struct.B, align 16
call void @use_B(%struct.B* byval align 16 %a) call void @use_B(%struct.B* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_C_1: ;ARM-LABEL: <test_C_1>:
;THUMB2-LABEL: test_C_1: ;THUMB2-LABEL: <test_C_1>:
;NO_NEON-LABEL:test_C_1: ;NO_NEON-LABEL:<test_C_1>:
;THUMB1-LABEL: test_C_1: ;THUMB1-LABEL: <test_C_1>:
;T1POST-LABEL: test_C_1: ;T1POST-LABEL: <test_C_1>:
define void @test_C_1() { define void @test_C_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.C, align 1 %a = alloca %struct.C, align 1
call void @use_C(%struct.C* byval align 1 %a) call void @use_C(%struct.C* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_C_2: ;ARM-LABEL: <test_C_2>:
;THUMB2-LABEL: test_C_2: ;THUMB2-LABEL: <test_C_2>:
;NO_NEON-LABEL:test_C_2: ;NO_NEON-LABEL:<test_C_2>:
;THUMB1-LABEL: test_C_2: ;THUMB1-LABEL: <test_C_2>:
;T1POST-LABEL: test_C_2: ;T1POST-LABEL: <test_C_2>:
define void @test_C_2() { define void @test_C_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.C, align 2 %a = alloca %struct.C, align 2
call void @use_C(%struct.C* byval align 2 %a) call void @use_C(%struct.C* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_C_4: ;ARM-LABEL: <test_C_4>:
;THUMB2-LABEL: test_C_4: ;THUMB2-LABEL: <test_C_4>:
;NO_NEON-LABEL:test_C_4: ;NO_NEON-LABEL:<test_C_4>:
;THUMB1-LABEL: test_C_4: ;THUMB1-LABEL: <test_C_4>:
;T1POST-LABEL: test_C_4: ;T1POST-LABEL: <test_C_4>:
define void @test_C_4() { define void @test_C_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.C, align 4 %a = alloca %struct.C, align 4
call void @use_C(%struct.C* byval align 4 %a) call void @use_C(%struct.C* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_C_8: ;ARM-LABEL: <test_C_8>:
;THUMB2-LABEL: test_C_8: ;THUMB2-LABEL: <test_C_8>:
;NO_NEON-LABEL:test_C_8: ;NO_NEON-LABEL:<test_C_8>:
;THUMB1-LABEL: test_C_8: ;THUMB1-LABEL: <test_C_8>:
;T1POST-LABEL: test_C_8: ;T1POST-LABEL: <test_C_8>:
define void @test_C_8() { define void @test_C_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.C, align 8 %a = alloca %struct.C, align 8
call void @use_C(%struct.C* byval align 8 %a) call void @use_C(%struct.C* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_C_16: ;ARM-LABEL: <test_C_16>:
;THUMB2-LABEL: test_C_16: ;THUMB2-LABEL: <test_C_16>:
;NO_NEON-LABEL:test_C_16: ;NO_NEON-LABEL:<test_C_16>:
;THUMB1-LABEL: test_C_16: ;THUMB1-LABEL: <test_C_16>:
;T1POST-LABEL: test_C_16: ;T1POST-LABEL: <test_C_16>:
define void @test_C_16() { define void @test_C_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.C, align 16 %a = alloca %struct.C, align 16
call void @use_C(%struct.C* byval align 16 %a) call void @use_C(%struct.C* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_D_1: ;ARM-LABEL: <test_D_1>:
;THUMB2-LABEL: test_D_1: ;THUMB2-LABEL: <test_D_1>:
;NO_NEON-LABEL:test_D_1: ;NO_NEON-LABEL:<test_D_1>:
;THUMB1-LABEL: test_D_1: ;THUMB1-LABEL: <test_D_1>:
;T1POST-LABEL: test_D_1: ;T1POST-LABEL: <test_D_1>:
define void @test_D_1() { define void @test_D_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.D, align 1 %a = alloca %struct.D, align 1
call void @use_D(%struct.D* byval align 1 %a) call void @use_D(%struct.D* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_D_2: ;ARM-LABEL: <test_D_2>:
;THUMB2-LABEL: test_D_2: ;THUMB2-LABEL: <test_D_2>:
;NO_NEON-LABEL:test_D_2: ;NO_NEON-LABEL:<test_D_2>:
;THUMB1-LABEL: test_D_2: ;THUMB1-LABEL: <test_D_2>:
;T1POST-LABEL: test_D_2: ;T1POST-LABEL: <test_D_2>:
define void @test_D_2() { define void @test_D_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: bne ;ARM: bne
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.D, align 2 %a = alloca %struct.D, align 2
call void @use_D(%struct.D* byval align 2 %a) call void @use_D(%struct.D* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_D_4: ;ARM-LABEL: <test_D_4>:
;THUMB2-LABEL: test_D_4: ;THUMB2-LABEL: <test_D_4>:
;NO_NEON-LABEL:test_D_4: ;NO_NEON-LABEL:<test_D_4>:
;THUMB1-LABEL: test_D_4: ;THUMB1-LABEL: <test_D_4>:
;T1POST-LABEL: test_D_4: ;T1POST-LABEL: <test_D_4>:
define void @test_D_4() { define void @test_D_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: bne ;ARM: bne
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.D, align 4 %a = alloca %struct.D, align 4
call void @use_D(%struct.D* byval align 4 %a) call void @use_D(%struct.D* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_D_8: ;ARM-LABEL: <test_D_8>:
;THUMB2-LABEL: test_D_8: ;THUMB2-LABEL: <test_D_8>:
;NO_NEON-LABEL:test_D_8: ;NO_NEON-LABEL:<test_D_8>:
;THUMB1-LABEL: test_D_8: ;THUMB1-LABEL: <test_D_8>:
;T1POST-LABEL: test_D_8: ;T1POST-LABEL: <test_D_8>:
define void @test_D_8() { define void @test_D_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.D, align 8 %a = alloca %struct.D, align 8
call void @use_D(%struct.D* byval align 8 %a) call void @use_D(%struct.D* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_D_16: ;ARM-LABEL: <test_D_16>:
;THUMB2-LABEL: test_D_16: ;THUMB2-LABEL: <test_D_16>:
;NO_NEON-LABEL:test_D_16: ;NO_NEON-LABEL:<test_D_16>:
;THUMB1-LABEL: test_D_16: ;THUMB1-LABEL: <test_D_16>:
;T1POST-LABEL: test_D_16: ;T1POST-LABEL: <test_D_16>:
define void @test_D_16() { define void @test_D_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.D, align 16 %a = alloca %struct.D, align 16
call void @use_D(%struct.D* byval align 16 %a) call void @use_D(%struct.D* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_E_1: ;ARM-LABEL: <test_E_1>:
;THUMB2-LABEL: test_E_1: ;THUMB2-LABEL: <test_E_1>:
;NO_NEON-LABEL:test_E_1: ;NO_NEON-LABEL:<test_E_1>:
;THUMB1-LABEL: test_E_1: ;THUMB1-LABEL: <test_E_1>:
;T1POST-LABEL: test_E_1: ;T1POST-LABEL: <test_E_1>:
define void @test_E_1() { define void @test_E_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.E, align 1 %a = alloca %struct.E, align 1
call void @use_E(%struct.E* byval align 1 %a) call void @use_E(%struct.E* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_E_2: ;ARM-LABEL: <test_E_2>:
;THUMB2-LABEL: test_E_2: ;THUMB2-LABEL: <test_E_2>:
;NO_NEON-LABEL:test_E_2: ;NO_NEON-LABEL:<test_E_2>:
;THUMB1-LABEL: test_E_2: ;THUMB1-LABEL: <test_E_2>:
;T1POST-LABEL: test_E_2: ;T1POST-LABEL: <test_E_2>:
define void @test_E_2() { define void @test_E_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: bne ;ARM: bne
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.E, align 2 %a = alloca %struct.E, align 2
call void @use_E(%struct.E* byval align 2 %a) call void @use_E(%struct.E* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_E_4: ;ARM-LABEL: <test_E_4>:
;THUMB2-LABEL: test_E_4: ;THUMB2-LABEL: <test_E_4>:
;NO_NEON-LABEL:test_E_4: ;NO_NEON-LABEL:<test_E_4>:
;THUMB1-LABEL: test_E_4: ;THUMB1-LABEL: <test_E_4>:
;T1POST-LABEL: test_E_4: ;T1POST-LABEL: <test_E_4>:
define void @test_E_4() { define void @test_E_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: bne ;ARM: bne
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.E, align 4 %a = alloca %struct.E, align 4
call void @use_E(%struct.E* byval align 4 %a) call void @use_E(%struct.E* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_E_8: ;ARM-LABEL: <test_E_8>:
;THUMB2-LABEL: test_E_8: ;THUMB2-LABEL: <test_E_8>:
;NO_NEON-LABEL:test_E_8: ;NO_NEON-LABEL:<test_E_8>:
;THUMB1-LABEL: test_E_8: ;THUMB1-LABEL: <test_E_8>:
;T1POST-LABEL: test_E_8: ;T1POST-LABEL: <test_E_8>:
define void @test_E_8() { define void @test_E_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
Show All 9 Lines
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.E, align 8 %a = alloca %struct.E, align 8
call void @use_E(%struct.E* byval align 8 %a) call void @use_E(%struct.E* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_E_16: ;ARM-LABEL: <test_E_16>:
;THUMB2-LABEL: test_E_16: ;THUMB2-LABEL: <test_E_16>:
;NO_NEON-LABEL:test_E_16: ;NO_NEON-LABEL:<test_E_16>:
;THUMB1-LABEL: test_E_16: ;THUMB1-LABEL: <test_E_16>:
;T1POST-LABEL: test_E_16: ;T1POST-LABEL: <test_E_16>:
define void @test_E_16() { define void @test_E_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
Show All 9 Lines
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.E, align 16 %a = alloca %struct.E, align 16
call void @use_E(%struct.E* byval align 16 %a) call void @use_E(%struct.E* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_F_1: ;ARM-LABEL: <test_F_1>:
;THUMB2-LABEL: test_F_1: ;THUMB2-LABEL: <test_F_1>:
;NO_NEON-LABEL:test_F_1: ;NO_NEON-LABEL:<test_F_1>:
;THUMB1-LABEL: test_F_1: ;THUMB1-LABEL: <test_F_1>:
;T1POST-LABEL: test_F_1: ;T1POST-LABEL: <test_F_1>:
define void @test_F_1() { define void @test_F_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.F, align 1 %a = alloca %struct.F, align 1
call void @use_F(%struct.F* byval align 1 %a) call void @use_F(%struct.F* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_F_2: ;ARM-LABEL: <test_F_2>:
;THUMB2-LABEL: test_F_2: ;THUMB2-LABEL: <test_F_2>:
;NO_NEON-LABEL:test_F_2: ;NO_NEON-LABEL:<test_F_2>:
;THUMB1-LABEL: test_F_2: ;THUMB1-LABEL: <test_F_2>:
;T1POST-LABEL: test_F_2: ;T1POST-LABEL: <test_F_2>:
define void @test_F_2() { define void @test_F_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: bne ;ARM: bne
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.F, align 2 %a = alloca %struct.F, align 2
call void @use_F(%struct.F* byval align 2 %a) call void @use_F(%struct.F* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_F_4: ;ARM-LABEL: <test_F_4>:
;THUMB2-LABEL: test_F_4: ;THUMB2-LABEL: <test_F_4>:
;NO_NEON-LABEL:test_F_4: ;NO_NEON-LABEL:<test_F_4>:
;THUMB1-LABEL: test_F_4: ;THUMB1-LABEL: <test_F_4>:
;T1POST-LABEL: test_F_4: ;T1POST-LABEL: <test_F_4>:
define void @test_F_4() { define void @test_F_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: bne ;ARM: bne
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
Show All 9 Lines
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.F, align 4 %a = alloca %struct.F, align 4
call void @use_F(%struct.F* byval align 4 %a) call void @use_F(%struct.F* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_F_8: ;ARM-LABEL: <test_F_8>:
;THUMB2-LABEL: test_F_8: ;THUMB2-LABEL: <test_F_8>:
;NO_NEON-LABEL:test_F_8: ;NO_NEON-LABEL:<test_F_8>:
;THUMB1-LABEL: test_F_8: ;THUMB1-LABEL: <test_F_8>:
;T1POST-LABEL: test_F_8: ;T1POST-LABEL: <test_F_8>:
define void @test_F_8() { define void @test_F_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
Show All 10 Lines
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.F, align 8 %a = alloca %struct.F, align 8
call void @use_F(%struct.F* byval align 8 %a) call void @use_F(%struct.F* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_F_16: ;ARM-LABEL: <test_F_16>:
;THUMB2-LABEL: test_F_16: ;THUMB2-LABEL: <test_F_16>:
;NO_NEON-LABEL:test_F_16: ;NO_NEON-LABEL:<test_F_16>:
;THUMB1-LABEL: test_F_16: ;THUMB1-LABEL: <test_F_16>:
;T1POST-LABEL: test_F_16: ;T1POST-LABEL: <test_F_16>:
define void @test_F_16() { define void @test_F_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
Show All 10 Lines
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.F, align 16 %a = alloca %struct.F, align 16
call void @use_F(%struct.F* byval align 16 %a) call void @use_F(%struct.F* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_G_1: ;ARM-LABEL: <test_G_1>:
;THUMB2-LABEL: test_G_1: ;THUMB2-LABEL: <test_G_1>:
;NO_NEON-LABEL:test_G_1: ;NO_NEON-LABEL:<test_G_1>:
;THUMB1-LABEL: test_G_1: ;THUMB1-LABEL: <test_G_1>:
;T1POST-LABEL: test_G_1: ;T1POST-LABEL: <test_G_1>:
define void @test_G_1() { define void @test_G_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.G, align 1 %a = alloca %struct.G, align 1
call void @use_G(%struct.G* byval align 1 %a) call void @use_G(%struct.G* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_G_2: ;ARM-LABEL: <test_G_2>:
;THUMB2-LABEL: test_G_2: ;THUMB2-LABEL: <test_G_2>:
;NO_NEON-LABEL:test_G_2: ;NO_NEON-LABEL:<test_G_2>:
;THUMB1-LABEL: test_G_2: ;THUMB1-LABEL: <test_G_2>:
;T1POST-LABEL: test_G_2: ;T1POST-LABEL: <test_G_2>:
define void @test_G_2() { define void @test_G_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.G, align 2 %a = alloca %struct.G, align 2
call void @use_G(%struct.G* byval align 2 %a) call void @use_G(%struct.G* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_G_4: ;ARM-LABEL: <test_G_4>:
;THUMB2-LABEL: test_G_4: ;THUMB2-LABEL: <test_G_4>:
;NO_NEON-LABEL:test_G_4: ;NO_NEON-LABEL:<test_G_4>:
;THUMB1-LABEL: test_G_4: ;THUMB1-LABEL: <test_G_4>:
;T1POST-LABEL: test_G_4: ;T1POST-LABEL: <test_G_4>:
define void @test_G_4() { define void @test_G_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.G, align 4 %a = alloca %struct.G, align 4
call void @use_G(%struct.G* byval align 4 %a) call void @use_G(%struct.G* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_G_8: ;ARM-LABEL: <test_G_8>:
;THUMB2-LABEL: test_G_8: ;THUMB2-LABEL: <test_G_8>:
;NO_NEON-LABEL:test_G_8: ;NO_NEON-LABEL:<test_G_8>:
;THUMB1-LABEL: test_G_8: ;THUMB1-LABEL: <test_G_8>:
;T1POST-LABEL: test_G_8: ;T1POST-LABEL: <test_G_8>:
define void @test_G_8() { define void @test_G_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.G, align 8 %a = alloca %struct.G, align 8
call void @use_G(%struct.G* byval align 8 %a) call void @use_G(%struct.G* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_G_16: ;ARM-LABEL: <test_G_16>:
;THUMB2-LABEL: test_G_16: ;THUMB2-LABEL: <test_G_16>:
;NO_NEON-LABEL:test_G_16: ;NO_NEON-LABEL:<test_G_16>:
;THUMB1-LABEL: test_G_16: ;THUMB1-LABEL: <test_G_16>:
;T1POST-LABEL: test_G_16: ;T1POST-LABEL: <test_G_16>:
define void @test_G_16() { define void @test_G_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.G, align 16 %a = alloca %struct.G, align 16
call void @use_G(%struct.G* byval align 16 %a) call void @use_G(%struct.G* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_H_1: ;ARM-LABEL: <test_H_1>:
;THUMB2-LABEL: test_H_1: ;THUMB2-LABEL: <test_H_1>:
;NO_NEON-LABEL:test_H_1: ;NO_NEON-LABEL:<test_H_1>:
;THUMB1-LABEL: test_H_1: ;THUMB1-LABEL: <test_H_1>:
;T1POST-LABEL: test_H_1: ;T1POST-LABEL: <test_H_1>:
define void @test_H_1() { define void @test_H_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.H, align 1 %a = alloca %struct.H, align 1
call void @use_H(%struct.H* byval align 1 %a) call void @use_H(%struct.H* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_H_2: ;ARM-LABEL: <test_H_2>:
;THUMB2-LABEL: test_H_2: ;THUMB2-LABEL: <test_H_2>:
;NO_NEON-LABEL:test_H_2: ;NO_NEON-LABEL:<test_H_2>:
;THUMB1-LABEL: test_H_2: ;THUMB1-LABEL: <test_H_2>:
;T1POST-LABEL: test_H_2: ;T1POST-LABEL: <test_H_2>:
define void @test_H_2() { define void @test_H_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.H, align 2 %a = alloca %struct.H, align 2
call void @use_H(%struct.H* byval align 2 %a) call void @use_H(%struct.H* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_H_4: ;ARM-LABEL: <test_H_4>:
;THUMB2-LABEL: test_H_4: ;THUMB2-LABEL: <test_H_4>:
;NO_NEON-LABEL:test_H_4: ;NO_NEON-LABEL:<test_H_4>:
;THUMB1-LABEL: test_H_4: ;THUMB1-LABEL: <test_H_4>:
;T1POST-LABEL: test_H_4: ;T1POST-LABEL: <test_H_4>:
define void @test_H_4() { define void @test_H_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.H, align 4 %a = alloca %struct.H, align 4
call void @use_H(%struct.H* byval align 4 %a) call void @use_H(%struct.H* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_H_8: ;ARM-LABEL: <test_H_8>:
;THUMB2-LABEL: test_H_8: ;THUMB2-LABEL: <test_H_8>:
;NO_NEON-LABEL:test_H_8: ;NO_NEON-LABEL:<test_H_8>:
;THUMB1-LABEL: test_H_8: ;THUMB1-LABEL: <test_H_8>:
;T1POST-LABEL: test_H_8: ;T1POST-LABEL: <test_H_8>:
define void @test_H_8() { define void @test_H_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.H, align 8 %a = alloca %struct.H, align 8
call void @use_H(%struct.H* byval align 8 %a) call void @use_H(%struct.H* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_H_16: ;ARM-LABEL: <test_H_16>:
;THUMB2-LABEL: test_H_16: ;THUMB2-LABEL: <test_H_16>:
;NO_NEON-LABEL:test_H_16: ;NO_NEON-LABEL:<test_H_16>:
;THUMB1-LABEL: test_H_16: ;THUMB1-LABEL: <test_H_16>:
;T1POST-LABEL: test_H_16: ;T1POST-LABEL: <test_H_16>:
define void @test_H_16() { define void @test_H_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.H, align 16 %a = alloca %struct.H, align 16
call void @use_H(%struct.H* byval align 16 %a) call void @use_H(%struct.H* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_I_1: ;ARM-LABEL: <test_I_1>:
;THUMB2-LABEL: test_I_1: ;THUMB2-LABEL: <test_I_1>:
;NO_NEON-LABEL:test_I_1: ;NO_NEON-LABEL:<test_I_1>:
;THUMB1-LABEL: test_I_1: ;THUMB1-LABEL: <test_I_1>:
;T1POST-LABEL: test_I_1: ;T1POST-LABEL: <test_I_1>:
define void @test_I_1() { define void @test_I_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.I, align 1 %a = alloca %struct.I, align 1
call void @use_I(%struct.I* byval align 1 %a) call void @use_I(%struct.I* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_I_2: ;ARM-LABEL: <test_I_2>:
;THUMB2-LABEL: test_I_2: ;THUMB2-LABEL: <test_I_2>:
;NO_NEON-LABEL:test_I_2: ;NO_NEON-LABEL:<test_I_2>:
;THUMB1-LABEL: test_I_2: ;THUMB1-LABEL: <test_I_2>:
;T1POST-LABEL: test_I_2: ;T1POST-LABEL: <test_I_2>:
define void @test_I_2() { define void @test_I_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.I, align 2 %a = alloca %struct.I, align 2
call void @use_I(%struct.I* byval align 2 %a) call void @use_I(%struct.I* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_I_4: ;ARM-LABEL: <test_I_4>:
;THUMB2-LABEL: test_I_4: ;THUMB2-LABEL: <test_I_4>:
;NO_NEON-LABEL:test_I_4: ;NO_NEON-LABEL:<test_I_4>:
;THUMB1-LABEL: test_I_4: ;THUMB1-LABEL: <test_I_4>:
;T1POST-LABEL: test_I_4: ;T1POST-LABEL: <test_I_4>:
define void @test_I_4() { define void @test_I_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.I, align 4 %a = alloca %struct.I, align 4
call void @use_I(%struct.I* byval align 4 %a) call void @use_I(%struct.I* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_I_8: ;ARM-LABEL: <test_I_8>:
;THUMB2-LABEL: test_I_8: ;THUMB2-LABEL: <test_I_8>:
;NO_NEON-LABEL:test_I_8: ;NO_NEON-LABEL:<test_I_8>:
;THUMB1-LABEL: test_I_8: ;THUMB1-LABEL: <test_I_8>:
;T1POST-LABEL: test_I_8: ;T1POST-LABEL: <test_I_8>:
define void @test_I_8() { define void @test_I_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.I, align 8 %a = alloca %struct.I, align 8
call void @use_I(%struct.I* byval align 8 %a) call void @use_I(%struct.I* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_I_16: ;ARM-LABEL: <test_I_16>:
;THUMB2-LABEL: test_I_16: ;THUMB2-LABEL: <test_I_16>:
;NO_NEON-LABEL:test_I_16: ;NO_NEON-LABEL:<test_I_16>:
;THUMB1-LABEL: test_I_16: ;THUMB1-LABEL: <test_I_16>:
;T1POST-LABEL: test_I_16: ;T1POST-LABEL: <test_I_16>:
define void @test_I_16() { define void @test_I_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.I, align 16 %a = alloca %struct.I, align 16
call void @use_I(%struct.I* byval align 16 %a) call void @use_I(%struct.I* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_J_1: ;ARM-LABEL: <test_J_1>:
;THUMB2-LABEL: test_J_1: ;THUMB2-LABEL: <test_J_1>:
;NO_NEON-LABEL:test_J_1: ;NO_NEON-LABEL:<test_J_1>:
;THUMB1-LABEL: test_J_1: ;THUMB1-LABEL: <test_J_1>:
;T1POST-LABEL: test_J_1: ;T1POST-LABEL: <test_J_1>:
define void @test_J_1() { define void @test_J_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.J, align 1 %a = alloca %struct.J, align 1
call void @use_J(%struct.J* byval align 1 %a) call void @use_J(%struct.J* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_J_2: ;ARM-LABEL: <test_J_2>:
;THUMB2-LABEL: test_J_2: ;THUMB2-LABEL: <test_J_2>:
;NO_NEON-LABEL:test_J_2: ;NO_NEON-LABEL:<test_J_2>:
;THUMB1-LABEL: test_J_2: ;THUMB1-LABEL: <test_J_2>:
;T1POST-LABEL: test_J_2: ;T1POST-LABEL: <test_J_2>:
define void @test_J_2() { define void @test_J_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: bne ;ARM: bne
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.J, align 2 %a = alloca %struct.J, align 2
call void @use_J(%struct.J* byval align 2 %a) call void @use_J(%struct.J* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_J_4: ;ARM-LABEL: <test_J_4>:
;THUMB2-LABEL: test_J_4: ;THUMB2-LABEL: <test_J_4>:
;NO_NEON-LABEL:test_J_4: ;NO_NEON-LABEL:<test_J_4>:
;THUMB1-LABEL: test_J_4: ;THUMB1-LABEL: <test_J_4>:
;T1POST-LABEL: test_J_4: ;T1POST-LABEL: <test_J_4>:
define void @test_J_4() { define void @test_J_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: bne ;ARM: bne
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.J, align 4 %a = alloca %struct.J, align 4
call void @use_J(%struct.J* byval align 4 %a) call void @use_J(%struct.J* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_J_8: ;ARM-LABEL: <test_J_8>:
;THUMB2-LABEL: test_J_8: ;THUMB2-LABEL: <test_J_8>:
;NO_NEON-LABEL:test_J_8: ;NO_NEON-LABEL:<test_J_8>:
;THUMB1-LABEL: test_J_8: ;THUMB1-LABEL: <test_J_8>:
;T1POST-LABEL: test_J_8: ;T1POST-LABEL: <test_J_8>:
define void @test_J_8() { define void @test_J_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.J, align 8 %a = alloca %struct.J, align 8
call void @use_J(%struct.J* byval align 8 %a) call void @use_J(%struct.J* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_J_16: ;ARM-LABEL: <test_J_16>:
;THUMB2-LABEL: test_J_16: ;THUMB2-LABEL: <test_J_16>:
;NO_NEON-LABEL:test_J_16: ;NO_NEON-LABEL:<test_J_16>:
;THUMB1-LABEL: test_J_16: ;THUMB1-LABEL: <test_J_16>:
;T1POST-LABEL: test_J_16: ;T1POST-LABEL: <test_J_16>:
define void @test_J_16() { define void @test_J_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.J, align 16 %a = alloca %struct.J, align 16
call void @use_J(%struct.J* byval align 16 %a) call void @use_J(%struct.J* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_K_1: ;ARM-LABEL: <test_K_1>:
;THUMB2-LABEL: test_K_1: ;THUMB2-LABEL: <test_K_1>:
;NO_NEON-LABEL:test_K_1: ;NO_NEON-LABEL:<test_K_1>:
;THUMB1-LABEL: test_K_1: ;THUMB1-LABEL: <test_K_1>:
;T1POST-LABEL: test_K_1: ;T1POST-LABEL: <test_K_1>:
define void @test_K_1() { define void @test_K_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.K, align 1 %a = alloca %struct.K, align 1
call void @use_K(%struct.K* byval align 1 %a) call void @use_K(%struct.K* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_K_2: ;ARM-LABEL: <test_K_2>:
;THUMB2-LABEL: test_K_2: ;THUMB2-LABEL: <test_K_2>:
;NO_NEON-LABEL:test_K_2: ;NO_NEON-LABEL:<test_K_2>:
;THUMB1-LABEL: test_K_2: ;THUMB1-LABEL: <test_K_2>:
;T1POST-LABEL: test_K_2: ;T1POST-LABEL: <test_K_2>:
define void @test_K_2() { define void @test_K_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: bne ;ARM: bne
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.K, align 2 %a = alloca %struct.K, align 2
call void @use_K(%struct.K* byval align 2 %a) call void @use_K(%struct.K* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_K_4: ;ARM-LABEL: <test_K_4>:
;THUMB2-LABEL: test_K_4: ;THUMB2-LABEL: <test_K_4>:
;NO_NEON-LABEL:test_K_4: ;NO_NEON-LABEL:<test_K_4>:
;THUMB1-LABEL: test_K_4: ;THUMB1-LABEL: <test_K_4>:
;T1POST-LABEL: test_K_4: ;T1POST-LABEL: <test_K_4>:
define void @test_K_4() { define void @test_K_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: bne ;ARM: bne
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.K, align 4 %a = alloca %struct.K, align 4
call void @use_K(%struct.K* byval align 4 %a) call void @use_K(%struct.K* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_K_8: ;ARM-LABEL: <test_K_8>:
;THUMB2-LABEL: test_K_8: ;THUMB2-LABEL: <test_K_8>:
;NO_NEON-LABEL:test_K_8: ;NO_NEON-LABEL:<test_K_8>:
;THUMB1-LABEL: test_K_8: ;THUMB1-LABEL: <test_K_8>:
;T1POST-LABEL: test_K_8: ;T1POST-LABEL: <test_K_8>:
define void @test_K_8() { define void @test_K_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.K, align 8 %a = alloca %struct.K, align 8
call void @use_K(%struct.K* byval align 8 %a) call void @use_K(%struct.K* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_K_16: ;ARM-LABEL: <test_K_16>:
;THUMB2-LABEL: test_K_16: ;THUMB2-LABEL: <test_K_16>:
;NO_NEON-LABEL:test_K_16: ;NO_NEON-LABEL:<test_K_16>:
;THUMB1-LABEL: test_K_16: ;THUMB1-LABEL: <test_K_16>:
;T1POST-LABEL: test_K_16: ;T1POST-LABEL: <test_K_16>:
define void @test_K_16() { define void @test_K_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.K, align 16 %a = alloca %struct.K, align 16
call void @use_K(%struct.K* byval align 16 %a) call void @use_K(%struct.K* byval align 16 %a)
ret void ret void
} }
;ARM-LABEL: test_L_1: ;ARM-LABEL: <test_L_1>:
;THUMB2-LABEL: test_L_1: ;THUMB2-LABEL: <test_L_1>:
;NO_NEON-LABEL:test_L_1: ;NO_NEON-LABEL:<test_L_1>:
;THUMB1-LABEL: test_L_1: ;THUMB1-LABEL: <test_L_1>:
;T1POST-LABEL: test_L_1: ;T1POST-LABEL: <test_L_1>:
define void @test_L_1() { define void @test_L_1() {
;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
;ARM: bne ;ARM: bne
;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #1 ;THUMB1: adds [[BASE]], #1
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry: entry:
%a = alloca %struct.L, align 1 %a = alloca %struct.L, align 1
call void @use_L(%struct.L* byval align 1 %a) call void @use_L(%struct.L* byval align 1 %a)
ret void ret void
} }
;ARM-LABEL: test_L_2: ;ARM-LABEL: <test_L_2>:
;THUMB2-LABEL: test_L_2: ;THUMB2-LABEL: <test_L_2>:
;NO_NEON-LABEL:test_L_2: ;NO_NEON-LABEL:<test_L_2>:
;THUMB1-LABEL: test_L_2: ;THUMB1-LABEL: <test_L_2>:
;T1POST-LABEL: test_L_2: ;T1POST-LABEL: <test_L_2>:
define void @test_L_2() { define void @test_L_2() {
;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
;ARM: bne ;ARM: bne
;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #2 ;THUMB1: adds [[BASE]], #2
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry: entry:
%a = alloca %struct.L, align 2 %a = alloca %struct.L, align 2
call void @use_L(%struct.L* byval align 2 %a) call void @use_L(%struct.L* byval align 2 %a)
ret void ret void
} }
;ARM-LABEL: test_L_4: ;ARM-LABEL: <test_L_4>:
;THUMB2-LABEL: test_L_4: ;THUMB2-LABEL: <test_L_4>:
;NO_NEON-LABEL:test_L_4: ;NO_NEON-LABEL:<test_L_4>:
;THUMB1-LABEL: test_L_4: ;THUMB1-LABEL: <test_L_4>:
;T1POST-LABEL: test_L_4: ;T1POST-LABEL: <test_L_4>:
define void @test_L_4() { define void @test_L_4() {
;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 ;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4
;ARM: bne ;ARM: bne
;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 ;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry: entry:
%a = alloca %struct.L, align 4 %a = alloca %struct.L, align 4
call void @use_L(%struct.L* byval align 4 %a) call void @use_L(%struct.L* byval align 4 %a)
ret void ret void
} }
;ARM-LABEL: test_L_8: ;ARM-LABEL: <test_L_8>:
;THUMB2-LABEL: test_L_8: ;THUMB2-LABEL: <test_L_8>:
;NO_NEON-LABEL:test_L_8: ;NO_NEON-LABEL:<test_L_8>:
;THUMB1-LABEL: test_L_8: ;THUMB1-LABEL: <test_L_8>:
;T1POST-LABEL: test_L_8: ;T1POST-LABEL: <test_L_8>:
define void @test_L_8() { define void @test_L_8() {
;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.L, align 8 %a = alloca %struct.L, align 8
call void @use_L(%struct.L* byval align 8 %a) call void @use_L(%struct.L* byval align 8 %a)
ret void ret void
} }
;ARM-LABEL: test_L_16: ;ARM-LABEL: <test_L_16>:
;THUMB2-LABEL: test_L_16: ;THUMB2-LABEL: <test_L_16>:
;NO_NEON-LABEL:test_L_16: ;NO_NEON-LABEL:<test_L_16>:
;THUMB1-LABEL: test_L_16: ;THUMB1-LABEL: <test_L_16>:
;T1POST-LABEL: test_L_16: ;T1POST-LABEL: <test_L_16>:
define void @test_L_16() { define void @test_L_16() {
;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;ARM: bne ;ARM: bne
;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB2: bne ;THUMB2: bne
;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 ;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4
;NO_NEON: bne ;NO_NEON: bne
;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;THUMB1: adds [[BASE]], #4 ;THUMB1: adds [[BASE]], #4
;THUMB1: bne ;THUMB1: bne
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry: entry:
%a = alloca %struct.L, align 16 %a = alloca %struct.L, align 16
call void @use_L(%struct.L* byval align 16 %a) call void @use_L(%struct.L* byval align 16 %a)
ret void ret void
} }
;V8MBASE-LABEL: test_M: ;V8MBASE-LABEL: <test_M>:
define void @test_M() { define void @test_M() {
;V8MBASE: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} ;V8MBASE: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
;V8MBASE: adds [[BASE]], #1 ;V8MBASE: adds [[BASE]], #1
;V8MBASE-NOT: movw ;V8MBASE-NOT: movw
entry: entry:
%a = alloca %struct.M, align 1 %a = alloca %struct.M, align 1
call void @use_M(%struct.M* byval align 1 %a) call void @use_M(%struct.M* byval align 1 %a)
ret void ret void
} }
;V8MBASE-LABEL: test_N: ;V8MBASE-LABEL: <test_N>:
define void @test_N() { define void @test_N() {
;V8MBASE: movw r{{[0-9]+}}, #{{[0-9]+}} ;V8MBASE: movw r{{[0-9]+}}, #{{[0-9]+}}
;V8MBASE-NOT: b #{{[0-9]+}} ;V8MBASE-NOT: b #{{[0-9]+}}
entry: entry:
%a = alloca %struct.N, align 1 %a = alloca %struct.N, align 1
call void @use_N(%struct.N* byval align 1 %a) call void @use_N(%struct.N* byval align 1 %a)
ret void ret void
} }

llvm/test/CodeGen/ARM/thumb1-varalloc.ll

; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s ; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s
; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-apple-darwin ; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-apple-darwin
; RUN: llvm-objdump -triple=thumbv6-apple-darwin -d %t | FileCheck %s ; RUN: llvm-objdump -triple=thumbv6-apple-darwin -d %t | FileCheck %s
@__bar = external hidden global i8* @__bar = external hidden global i8*
@__baz = external hidden global i8* @__baz = external hidden global i8*
; rdar://8819685 ; rdar://8819685
define i8* @_foo() { define i8* @_foo() {
entry: entry:
; CHECK-LABEL: foo: ; CHECK-LABEL: __foo{{>?}}:
%size = alloca i32, align 4 %size = alloca i32, align 4
%0 = load i8*, i8** @__bar, align 4 %0 = load i8*, i8** @__bar, align 4
%1 = icmp eq i8* %0, null %1 = icmp eq i8* %0, null
br i1 %1, label %bb1, label %bb3 br i1 %1, label %bb1, label %bb3
; CHECK: bne ; CHECK: bne
bb1: bb1:
Show All 20 Lines; CHECK-NEXT: pop {r4, r6, r7, pc}
ret i8* %.0 ret i8* %.0
} }
declare noalias i8* @strdup(i8* nocapture) nounwind declare noalias i8* @strdup(i8* nocapture) nounwind
declare i32 @_called_func(i8*, i32*) nounwind declare i32 @_called_func(i8*, i32*) nounwind
; Simple variable ending up *at* sp. ; Simple variable ending up *at* sp.
define void @test_simple_var() { define void @test_simple_var() {
; CHECK-LABEL: test_simple_var: ; CHECK-LABEL: test_simple_var{{>?}}:
%addr32 = alloca i32 %addr32 = alloca i32
%addr8 = bitcast i32* %addr32 to i8* %addr8 = bitcast i32* %addr32 to i8*
; CHECK: mov r0, sp ; CHECK: mov r0, sp
; CHECK-NOT: adds r0 ; CHECK-NOT: adds r0
; CHECK: bl ; CHECK: bl
call void @take_ptr(i8* %addr8) call void @take_ptr(i8* %addr8)
ret void ret void
} }
; Simple variable ending up at aligned offset from sp. ; Simple variable ending up at aligned offset from sp.
define void @test_local_var_addr_aligned() { define void @test_local_var_addr_aligned() {
; CHECK-LABEL: test_local_var_addr_aligned: ; CHECK-LABEL: test_local_var_addr_aligned{{>?}}:
%addr1.32 = alloca i32 %addr1.32 = alloca i32
%addr1 = bitcast i32* %addr1.32 to i8* %addr1 = bitcast i32* %addr1.32 to i8*
%addr2.32 = alloca i32 %addr2.32 = alloca i32
%addr2 = bitcast i32* %addr2.32 to i8* %addr2 = bitcast i32* %addr2.32 to i8*
; CHECK: add r0, sp, #{{[0-9]+}} ; CHECK: add r0, sp, #{{[0-9]+}}
; CHECK: bl ; CHECK: bl
call void @take_ptr(i8* %addr1) call void @take_ptr(i8* %addr1)
; CHECK: mov r0, sp ; CHECK: mov r0, sp
; CHECK-NOT: add r0 ; CHECK-NOT: add r0
; CHECK: bl ; CHECK: bl
call void @take_ptr(i8* %addr2) call void @take_ptr(i8* %addr2)
ret void ret void
} }
; Simple variable ending up at aligned offset from sp. ; Simple variable ending up at aligned offset from sp.
define void @test_local_var_big_offset() { define void @test_local_var_big_offset() {
; CHECK-LABEL: test_local_var_big_offset: ; CHECK-LABEL: test_local_var_big_offset{{>?}}:
%addr1.32 = alloca i32, i32 257 %addr1.32 = alloca i32, i32 257
%addr1 = bitcast i32* %addr1.32 to i8* %addr1 = bitcast i32* %addr1.32 to i8*
%addr2.32 = alloca i32, i32 257 %addr2.32 = alloca i32, i32 257
; CHECK: add [[RTMP:r[0-9]+]], sp, #1020 ; CHECK: add [[RTMP:r[0-9]+]], sp, #1020
; CHECK: adds [[RTMP]], #8 ; CHECK: adds [[RTMP]], #8
; CHECK: bl ; CHECK: bl
call void @take_ptr(i8* %addr1) call void @take_ptr(i8* %addr1)
Show All 34 Lines

llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll

Show All 14 Linesdefine i32* @wrong-t2stmia-size-reduction(i32* %addr, i32 %val0, i32 %val1) minsize {
store i32 %lr32, i32* %addr2 store i32 %lr32, i32* %addr2
%addr3 = getelementptr i32, i32* %addr, i32 3 %addr3 = getelementptr i32, i32* %addr, i32 3
ret i32* %addr3 ret i32* %addr3
} }
; Check that stm writes three registers. The bug caused one of registers (LR, ; Check that stm writes three registers. The bug caused one of registers (LR,
; which invalid for Thumb1 form of STMIA instruction) to be dropped. ; which invalid for Thumb1 form of STMIA instruction) to be dropped.
; CHECK-LABEL: wrong-t2stmia-size-reduction: ; CHECK-LABEL: <wrong-t2stmia-size-reduction>:
; CHECK: stm{{[^,]*}}, {{{.*,.*,.*}}} ; CHECK: stm{{[^,]*}}, {{{.*,.*,.*}}}

llvm/test/CodeGen/BPF/objdump_cond_op.ll

Show All 38 Lines
; CHECK: r0 *= r0 ; CHECK: r0 *= r0
; CHECK: r0 <<= 1 ; CHECK: r0 <<= 1
; CHECK: goto +7 <LBB0_4> ; CHECK: goto +7 <LBB0_4>
; <label>:11: ; preds = %8 ; <label>:11: ; preds = %8
%12 = shl nsw i32 %10, 2 %12 = shl nsw i32 %10, 2
br label %13 br label %13
; CHECK-LABEL: LBB0_2: ; CHECK-LABEL: <LBB0_2>:
; CHECK: r3 = 0 ll ; CHECK: r3 = 0 ll
; CHECK: r0 = *(u32 *)(r3 + 0) ; CHECK: r0 = *(u32 *)(r3 + 0)
; CHECK: r2 <<= 32 ; CHECK: r2 <<= 32
; CHECK: r2 >>= 32 ; CHECK: r2 >>= 32
; CHECK: if r1 == r2 goto +4 <LBB0_5> ; CHECK: if r1 == r2 goto +4 <LBB0_5>
; CHECK: r0 <<= 2 ; CHECK: r0 <<= 2
; <label>:13: ; preds = %4, %11 ; <label>:13: ; preds = %4, %11
%14 = phi i32 [ %12, %11 ], [ %7, %4 ] %14 = phi i32 [ %12, %11 ], [ %7, %4 ]
store i32 %14, i32* @gbl, align 4 store i32 %14, i32* @gbl, align 4
br label %15 br label %15
; CHECK-LABEL: LBB0_4: ; CHECK-LABEL: <LBB0_4>:
; CHECK: r1 = 0 ll ; CHECK: r1 = 0 ll
; CHECK: *(u32 *)(r1 + 0) = r0 ; CHECK: *(u32 *)(r1 + 0) = r0
; <label>:15: ; preds = %8, %13 ; <label>:15: ; preds = %8, %13
%16 = phi i32 [ %14, %13 ], [ %10, %8 ] %16 = phi i32 [ %14, %13 ], [ %10, %8 ]
ret i32 %16 ret i32 %16
; CHECK-LABEL: LBB0_5: ; CHECK-LABEL: <LBB0_5>:
; CHECK: exit ; CHECK: exit
} }
attributes #0 = { norecurse nounwind } attributes #0 = { norecurse nounwind }

llvm/test/CodeGen/BPF/objdump_cond_op_2.ll

; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s ; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
; Source Code: ; Source Code:
; int test(int a, int b) { ; int test(int a, int b) {
; int s = 0; ; int s = 0;
; while (a < b) { s++; a += s; b -= s; } ; while (a < b) { s++; a += s; b -= s; }
; return s; ; return s;
; } ; }
define i32 @test(i32, i32) local_unnamed_addr #0 { define i32 @test(i32, i32) local_unnamed_addr #0 {
; CHECK-LABEL: test: ; CHECK-LABEL: <test>:
%3 = icmp slt i32 %0, %1 %3 = icmp slt i32 %0, %1
br i1 %3, label %4, label %13 br i1 %3, label %4, label %13
; <label>:4: ; preds = %2 ; <label>:4: ; preds = %2
br label %5 br label %5
; CHECK: if r4 s>= r3 goto +11 <LBB0_3> ; CHECK: if r4 s>= r3 goto +11 <LBB0_3>
; CHECK: r0 = 0 ; CHECK: r0 = 0
; CHECK-LABEL: LBB0_2: ; CHECK-LABEL: <LBB0_2>:
; <label>:5: ; preds = %4, %5 ; <label>:5: ; preds = %4, %5
%6 = phi i32 [ %9, %5 ], [ 0, %4 ] %6 = phi i32 [ %9, %5 ], [ 0, %4 ]
%7 = phi i32 [ %11, %5 ], [ %1, %4 ] %7 = phi i32 [ %11, %5 ], [ %1, %4 ]
%8 = phi i32 [ %10, %5 ], [ %0, %4 ] %8 = phi i32 [ %10, %5 ], [ %0, %4 ]
%9 = add nuw nsw i32 %6, 1 %9 = add nuw nsw i32 %6, 1
%10 = add nsw i32 %9, %8 %10 = add nsw i32 %9, %8
%11 = sub nsw i32 %7, %9 %11 = sub nsw i32 %7, %9
%12 = icmp slt i32 %10, %11 %12 = icmp slt i32 %10, %11
br i1 %12, label %5, label %13 br i1 %12, label %5, label %13
; CHECK: r1 = r3 ; CHECK: r1 = r3
; CHECK: if r2 s> r3 goto -10 <LBB0_2> ; CHECK: if r2 s> r3 goto -10 <LBB0_2>
; <label>:13: ; preds = %5, %2 ; <label>:13: ; preds = %5, %2
%14 = phi i32 [ 0, %2 ], [ %9, %5 ] %14 = phi i32 [ 0, %2 ], [ %9, %5 ]
ret i32 %14 ret i32 %14
; CHECK-LABEL: LBB0_3: ; CHECK-LABEL: <LBB0_3>:
; CHECK: exit ; CHECK: exit
} }
attributes #0 = { norecurse nounwind readnone } attributes #0 = { norecurse nounwind readnone }

llvm/test/CodeGen/BPF/objdump_two_funcs.ll

Show All 10 Lines
; return a * a * a; ; return a * a * a;
; } ; }
; Compiler flag to generate IR: ; Compiler flag to generate IR:
; clang -target bpf -S -gdwarf-5 -gembed-source -emit-llvm -g -O2 bug.c ; clang -target bpf -S -gdwarf-5 -gembed-source -emit-llvm -g -O2 bug.c
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define dso_local i32 @func1(i32 %a) local_unnamed_addr #0 section "s1" !dbg !7 { define dso_local i32 @func1(i32 %a) local_unnamed_addr #0 section "s1" !dbg !7 {
entry: entry:
; CHECK: func1: ; CHECK: <func1>:
call void @llvm.dbg.value(metadata i32 %a, metadata !12, metadata !DIExpression()), !dbg !13 call void @llvm.dbg.value(metadata i32 %a, metadata !12, metadata !DIExpression()), !dbg !13
%mul = mul nsw i32 %a, %a, !dbg !14 %mul = mul nsw i32 %a, %a, !dbg !14
ret i32 %mul, !dbg !15 ret i32 %mul, !dbg !15
; CHECK: ; return a * a; ; CHECK: ; return a * a;
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define dso_local i32 @func2(i32 %a) local_unnamed_addr #0 section "s2" !dbg !16 { define dso_local i32 @func2(i32 %a) local_unnamed_addr #0 section "s2" !dbg !16 {
entry: entry:
; CHECK: func2: ; CHECK: <func2>:
call void @llvm.dbg.value(metadata i32 %a, metadata !18, metadata !DIExpression()), !dbg !19 call void @llvm.dbg.value(metadata i32 %a, metadata !18, metadata !DIExpression()), !dbg !19
%mul = mul nsw i32 %a, %a, !dbg !20 %mul = mul nsw i32 %a, %a, !dbg !20
%mul1 = mul nsw i32 %mul, %a, !dbg !21 %mul1 = mul nsw i32 %mul, %a, !dbg !21
ret i32 %mul1, !dbg !22 ret i32 %mul1, !dbg !22
; CHECK: ; return a * a * a; ; CHECK: ; return a * a * a;
} }
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
Show All 32 Lines

llvm/test/CodeGen/Hexagon/S3_2op.ll

; RUN: llc -march=hexagon -filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s ; RUN: llc -march=hexagon -filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s
; CHECK-LABEL: f0: ; CHECK-LABEL: <f0>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = abs(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = abs(r{{[1-9]}}:{{[0-9]}})
define double @f0(double %a0) #0 { define double @f0(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.A2.absp(i64 %v2) %v3 = call i64 @llvm.hexagon.A2.absp(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.A2.absp(i64) #1 declare i64 @llvm.hexagon.A2.absp(i64) #1
; CHECK-LABEL: f1: ; CHECK-LABEL: <f1>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = neg(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = neg(r{{[1-9]}}:{{[0-9]}})
define double @f1(double %a0) #0 { define double @f1(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.A2.negp(i64 %v2) %v3 = call i64 @llvm.hexagon.A2.negp(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.A2.negp(i64) #1 declare i64 @llvm.hexagon.A2.negp(i64) #1
; CHECK-LABEL: f2: ; CHECK-LABEL: <f2>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = not(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = not(r{{[1-9]}}:{{[0-9]}})
define double @f2(double %a0) #0 { define double @f2(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.A2.notp(i64 %v2) %v3 = call i64 @llvm.hexagon.A2.notp(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.A2.notp(i64) #1 declare i64 @llvm.hexagon.A2.notp(i64) #1
; CHECK-LABEL: f3: ; CHECK-LABEL: <f3>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = interleave(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = interleave(r{{[1-9]}}:{{[0-9]}})
define double @f3(double %a0) #0 { define double @f3(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.interleave(i64 %v2) %v3 = call i64 @llvm.hexagon.S2.interleave(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.interleave(i64) #1 declare i64 @llvm.hexagon.S2.interleave(i64) #1
; CHECK-LABEL: f4: ; CHECK-LABEL: <f4>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = deinterleave(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = deinterleave(r{{[1-9]}}:{{[0-9]}})
define double @f4(double %a0) #0 { define double @f4(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.deinterleave(i64 %v2) %v3 = call i64 @llvm.hexagon.S2.deinterleave(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.deinterleave(i64) #1 declare i64 @llvm.hexagon.S2.deinterleave(i64) #1
; CHECK-LABEL: f5: ; CHECK-LABEL: <f5>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vconj(r{{[1-9]}}:{{[0-9]}}):sat ; CHECK: r{{[1-9]}}:{{[0-9]}} = vconj(r{{[1-9]}}:{{[0-9]}}):sat
define double @f5(double %a0) #0 { define double @f5(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.A2.vconj(i64 %v2) %v3 = call i64 @llvm.hexagon.A2.vconj(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.A2.vconj(i64) #1 declare i64 @llvm.hexagon.A2.vconj(i64) #1
; CHECK-LABEL: f6: ; CHECK-LABEL: <f6>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vsathb(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vsathb(r{{[1-9]}}:{{[0-9]}})
define double @f6(double %a0) #0 { define double @f6(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.vsathb.nopack(i64 %v2) %v3 = call i64 @llvm.hexagon.S2.vsathb.nopack(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.vsathb.nopack(i64) #1 declare i64 @llvm.hexagon.S2.vsathb.nopack(i64) #1
; CHECK-LABEL: f7: ; CHECK-LABEL: <f7>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vsathub(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vsathub(r{{[1-9]}}:{{[0-9]}})
define double @f7(double %a0) #0 { define double @f7(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.vsathub.nopack(i64 %v2) %v3 = call i64 @llvm.hexagon.S2.vsathub.nopack(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.vsathub.nopack(i64) #1 declare i64 @llvm.hexagon.S2.vsathub.nopack(i64) #1
; CHECK-LABEL: f8: ; CHECK-LABEL: <f8>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vsatwh(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vsatwh(r{{[1-9]}}:{{[0-9]}})
define double @f8(double %a0) #0 { define double @f8(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.vsatwh.nopack(i64 %v2) %v3 = call i64 @llvm.hexagon.S2.vsatwh.nopack(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.vsatwh.nopack(i64) #1 declare i64 @llvm.hexagon.S2.vsatwh.nopack(i64) #1
; CHECK-LABEL: f9: ; CHECK-LABEL: <f9>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vsatwuh(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vsatwuh(r{{[1-9]}}:{{[0-9]}})
define double @f9(double %a0) #0 { define double @f9(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.vsatwuh.nopack(i64 %v2) %v3 = call i64 @llvm.hexagon.S2.vsatwuh.nopack(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.vsatwuh.nopack(i64) #1 declare i64 @llvm.hexagon.S2.vsatwuh.nopack(i64) #1
; CHECK-LABEL: f10: ; CHECK-LABEL: <f10>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = asr(r{{[1-9]}}:{{[0-9]}},#1) ; CHECK: r{{[1-9]}}:{{[0-9]}} = asr(r{{[1-9]}}:{{[0-9]}},#1)
define double @f10(double %a0) #0 { define double @f10(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v2, i32 1) %v3 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v2, i32 1)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32) #1 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32) #1
; CHECK-LABEL: f11: ; CHECK-LABEL: <f11>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = lsr(r{{[1-9]}}:{{[0-9]}},#1) ; CHECK: r{{[1-9]}}:{{[0-9]}} = lsr(r{{[1-9]}}:{{[0-9]}},#1)
define double @f11(double %a0) #0 { define double @f11(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %v2, i32 1) %v3 = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %v2, i32 1)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32) #1 declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32) #1
; CHECK-LABEL: f12: ; CHECK-LABEL: <f12>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = asl(r{{[1-9]}}:{{[0-9]}},#1) ; CHECK: r{{[1-9]}}:{{[0-9]}} = asl(r{{[1-9]}}:{{[0-9]}},#1)
define double @f12(double %a0) #0 { define double @f12(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.asl.i.p(i64 %v2, i32 1) %v3 = call i64 @llvm.hexagon.S2.asl.i.p(i64 %v2, i32 1)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32) #1 declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32) #1
; CHECK-LABEL: f13: ; CHECK-LABEL: <f13>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsh(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsh(r{{[1-9]}}:{{[0-9]}})
define double @f13(double %a0) #0 { define double @f13(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.A2.vabsh(i64 %v2) %v3 = call i64 @llvm.hexagon.A2.vabsh(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.A2.vabsh(i64) #1 declare i64 @llvm.hexagon.A2.vabsh(i64) #1
; CHECK-LABEL: f14: ; CHECK-LABEL: <f14>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsh(r{{[1-9]}}:{{[0-9]}}):sat ; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsh(r{{[1-9]}}:{{[0-9]}}):sat
define double @f14(double %a0) #0 { define double @f14(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.A2.vabshsat(i64 %v2) %v3 = call i64 @llvm.hexagon.A2.vabshsat(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.A2.vabshsat(i64) #1 declare i64 @llvm.hexagon.A2.vabshsat(i64) #1
; CHECK-LABEL: f15: ; CHECK-LABEL: <f15>:
; CHECK: r{{[0-9]}}:{{[0-9]}} = vasrh(r{{[1-9]}}:{{[0-9]}},#1) ; CHECK: r{{[0-9]}}:{{[0-9]}} = vasrh(r{{[1-9]}}:{{[0-9]}},#1)
define double @f15(double %a0) #0 { define double @f15(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.asr.i.vh(i64 %v2, i32 1) %v3 = call i64 @llvm.hexagon.S2.asr.i.vh(i64 %v2, i32 1)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) #1 declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) #1
; CHECK-LABEL: f16: ; CHECK-LABEL: <f16>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vlsrh(r{{[1-9]}}:{{[0-9]}},#1) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vlsrh(r{{[1-9]}}:{{[0-9]}},#1)
define double @f16(double %a0) #0 { define double @f16(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %v2, i32 1) %v3 = call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %v2, i32 1)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) #1 declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) #1
; CHECK-LABEL: f17: ; CHECK-LABEL: <f17>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vaslh(r{{[1-9]}}:{{[0-9]}},#1) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vaslh(r{{[1-9]}}:{{[0-9]}},#1)
define double @f17(double %a0) #0 { define double @f17(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.asl.i.vh(i64 %v2, i32 1) %v3 = call i64 @llvm.hexagon.S2.asl.i.vh(i64 %v2, i32 1)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) #1 declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) #1
; CHECK-LABEL: f18: ; CHECK-LABEL: <f18>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsw(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsw(r{{[1-9]}}:{{[0-9]}})
define double @f18(double %a0) #0 { define double @f18(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.A2.vabsw(i64 %v2) %v3 = call i64 @llvm.hexagon.A2.vabsw(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.A2.vabsw(i64) #1 declare i64 @llvm.hexagon.A2.vabsw(i64) #1
; CHECK-LABEL: f19: ; CHECK-LABEL: <f19>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsw(r{{[1-9]}}:{{[0-9]}}):sat ; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsw(r{{[1-9]}}:{{[0-9]}}):sat
define double @f19(double %a0) #0 { define double @f19(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.A2.vabswsat(i64 %v2) %v3 = call i64 @llvm.hexagon.A2.vabswsat(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.A2.vabswsat(i64) #1 declare i64 @llvm.hexagon.A2.vabswsat(i64) #1
; CHECK-LABEL: f20: ; CHECK-LABEL: <f20>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vasrw(r{{[1-9]}}:{{[0-9]}},#1) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vasrw(r{{[1-9]}}:{{[0-9]}},#1)
define double @f20(double %a0) #0 { define double @f20(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.asr.i.vw(i64 %v2, i32 1) %v3 = call i64 @llvm.hexagon.S2.asr.i.vw(i64 %v2, i32 1)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) #1 declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) #1
; CHECK-LABEL: f21: ; CHECK-LABEL: <f21>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vlsrw(r{{[1-9]}}:{{[0-9]}},#1) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vlsrw(r{{[1-9]}}:{{[0-9]}},#1)
define double @f21(double %a0) #0 { define double @f21(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %v2, i32 1) %v3 = call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %v2, i32 1)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) #1 declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) #1
; CHECK-LABEL: f22: ; CHECK-LABEL: <f22>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = vaslw(r{{[1-9]}}:{{[0-9]}},#1) ; CHECK: r{{[1-9]}}:{{[0-9]}} = vaslw(r{{[1-9]}}:{{[0-9]}},#1)
define double @f22(double %a0) #0 { define double @f22(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.asl.i.vw(i64 %v2, i32 1) %v3 = call i64 @llvm.hexagon.S2.asl.i.vw(i64 %v2, i32 1)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) #1 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) #1
; CHECK-LABEL: f23: ; CHECK-LABEL: <f23>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = brev(r{{[1-9]}}:{{[0-9]}}) ; CHECK: r{{[1-9]}}:{{[0-9]}} = brev(r{{[1-9]}}:{{[0-9]}})
define double @f23(double %a0) #0 { define double @f23(double %a0) #0 {
b0: b0:
%v0 = alloca double, align 8 %v0 = alloca double, align 8
store double %a0, double* %v0, align 8 store double %a0, double* %v0, align 8
%v1 = load double, double* %v0, align 8 %v1 = load double, double* %v0, align 8
%v2 = fptosi double %v1 to i64 %v2 = fptosi double %v1 to i64
%v3 = call i64 @llvm.hexagon.S2.brevp(i64 %v2) %v3 = call i64 @llvm.hexagon.S2.brevp(i64 %v2)
%v4 = sitofp i64 %v3 to double %v4 = sitofp i64 %v3 to double
ret double %v4 ret double %v4
} }
declare i64 @llvm.hexagon.S2.brevp(i64) #1 declare i64 @llvm.hexagon.S2.brevp(i64) #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/Hexagon/vrcmpys.ll

; RUN: llc -march=hexagon --filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s ; RUN: llc -march=hexagon --filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s
@g0 = common global double 0.000000e+00, align 8 @g0 = common global double 0.000000e+00, align 8
@g1 = common global double 0.000000e+00, align 8 @g1 = common global double 0.000000e+00, align 8
; CHECK-LABEL: f0: ; CHECK-LABEL: <f0>:
; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo ; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo
define double @f0(i32 %a0, i32 %a1) { define double @f0(i32 %a0, i32 %a1) {
b0: b0:
%v0 = load double, double* @g0, align 8, !tbaa !0 %v0 = load double, double* @g0, align 8, !tbaa !0
%v1 = fptosi double %v0 to i64 %v1 = fptosi double %v0 to i64
%v2 = load double, double* @g1, align 8, !tbaa !0 %v2 = load double, double* @g1, align 8, !tbaa !0
%v3 = fptosi double %v2 to i64 %v3 = fptosi double %v2 to i64
%v4 = tail call i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64 %v1, i64 %v3, i32 %a0) %v4 = tail call i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64 %v1, i64 %v3, i32 %a0)
%v5 = sitofp i64 %v4 to double %v5 = sitofp i64 %v4 to double
ret double %v5 ret double %v5
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64, i64, i32) #0 declare i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64, i64, i32) #0
; CHECK-LABEL: f1: ; CHECK-LABEL: <f1>:
; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi ; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi
define double @f1(i32 %a0, i32 %a1) { define double @f1(i32 %a0, i32 %a1) {
b0: b0:
%v0 = load double, double* @g0, align 8, !tbaa !0 %v0 = load double, double* @g0, align 8, !tbaa !0
%v1 = fptosi double %v0 to i64 %v1 = fptosi double %v0 to i64
%v2 = load double, double* @g1, align 8, !tbaa !0 %v2 = load double, double* @g1, align 8, !tbaa !0
%v3 = fptosi double %v2 to i64 %v3 = fptosi double %v2 to i64
%v4 = tail call i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64 %v1, i64 %v3, i32 %a1) %v4 = tail call i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64 %v1, i64 %v3, i32 %a1)
%v5 = sitofp i64 %v4 to double %v5 = sitofp i64 %v4 to double
ret double %v5 ret double %v5
} }
; CHECK-LABEL: f2: ; CHECK-LABEL: <f2>:
; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo ; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo
define double @f2(i32 %a0, i32 %a1) { define double @f2(i32 %a0, i32 %a1) {
b0: b0:
%v0 = load double, double* @g1, align 8, !tbaa !0 %v0 = load double, double* @g1, align 8, !tbaa !0
%v1 = fptosi double %v0 to i64 %v1 = fptosi double %v0 to i64
%v2 = tail call i64 @llvm.hexagon.M2.vrcmpys.s1(i64 %v1, i32 %a0) %v2 = tail call i64 @llvm.hexagon.M2.vrcmpys.s1(i64 %v1, i32 %a0)
%v3 = sitofp i64 %v2 to double %v3 = sitofp i64 %v2 to double
ret double %v3 ret double %v3
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i64 @llvm.hexagon.M2.vrcmpys.s1(i64, i32) #0 declare i64 @llvm.hexagon.M2.vrcmpys.s1(i64, i32) #0
; CHECK-LABEL: f3: ; CHECK-LABEL: <f3>:
; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi ; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi
define double @f3(i32 %a0, i32 %a1) { define double @f3(i32 %a0, i32 %a1) {
b0: b0:
%v0 = load double, double* @g1, align 8, !tbaa !0 %v0 = load double, double* @g1, align 8, !tbaa !0
%v1 = fptosi double %v0 to i64 %v1 = fptosi double %v0 to i64
%v2 = tail call i64 @llvm.hexagon.M2.vrcmpys.s1(i64 %v1, i32 %a1) %v2 = tail call i64 @llvm.hexagon.M2.vrcmpys.s1(i64 %v1, i32 %a1)
%v3 = sitofp i64 %v2 to double %v3 = sitofp i64 %v2 to double
ret double %v3 ret double %v3
} }
; CHECK-LABEL: f4: ; CHECK-LABEL: <f4>:
; CHECK: e9a4c2e0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:lo } ; CHECK: e9a4c2e0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:lo }
; CHECK: e9a4c2c0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:hi } ; CHECK: e9a4c2c0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:hi }
define void @f4() { define void @f4() {
b0: b0:
call void asm sideeffect "r0=vrcmpys(r5:4,r2):<<1:rnd:sat", ""(), !srcloc !4 call void asm sideeffect "r0=vrcmpys(r5:4,r2):<<1:rnd:sat", ""(), !srcloc !4
call void asm sideeffect "r0=vrcmpys(r5:4,r3):<<1:rnd:sat", ""(), !srcloc !5 call void asm sideeffect "r0=vrcmpys(r5:4,r3):<<1:rnd:sat", ""(), !srcloc !5
ret void ret void
} }
Show All 9 Lines

llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll

Show All 34 Lines if.end:
ret i32 0 ret i32 0
} }
; We silently fixup cases where the register allocator or user has given us ; We silently fixup cases where the register allocator or user has given us
; an instruction with incorrect operands that is trivially acceptable. ; an instruction with incorrect operands that is trivially acceptable.
; beqc and bnec have the restriction that $rs < $rt. ; beqc and bnec have the restriction that $rs < $rt.
define i32 @f2(i32 %a, i32 %b) { define i32 @f2(i32 %a, i32 %b) {
; ENCODING-LABEL: f2: ; ENCODING-LABEL: <f2>:
; ENCODING-NOT: beqc $5, $4 ; ENCODING-NOT: beqc $5, $4
; ENCODING-NOT: bnec $5, $4 ; ENCODING-NOT: bnec $5, $4
%cmp = icmp eq i32 %b, %a %cmp = icmp eq i32 %b, %a
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
ret i32 1 ret i32 1
Show All 30 Lines if.end:
ret i64 0 ret i64 0
} }
; We silently fixup cases where the register allocator or user has given us ; We silently fixup cases where the register allocator or user has given us
; an instruction with incorrect operands that is trivially acceptable. ; an instruction with incorrect operands that is trivially acceptable.
; beqc and bnec have the restriction that $rs < $rt. ; beqc and bnec have the restriction that $rs < $rt.
define i64 @f5(i64 %a, i64 %b) { define i64 @f5(i64 %a, i64 %b) {
; ENCODING-LABEL: f5: ; ENCODING-LABEL: <f5>:
; ENCODING-NOT: beqc $5, $4 ; ENCODING-NOT: beqc $5, $4
; ENCODING-NOT: bnec $5, $4 ; ENCODING-NOT: bnec $5, $4
%cmp = icmp eq i64 %b, %a %cmp = icmp eq i64 %b, %a
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
ret i64 1 ret i64 1
Show All 32 Lines

llvm/test/CodeGen/Mips/dsp-spill-reload.ll

; RUN: llc -march=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \ ; RUN: llc -march=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \
; RUN: --check-prefixes=ASM,ALL ; RUN: --check-prefixes=ASM,ALL
; RUN: llc -march=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \ ; RUN: llc -march=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \
; RUN: llvm-objdump -d - | FileCheck %s --check-prefixes=MM-OBJ,ALL ; RUN: llvm-objdump -d - | FileCheck %s --check-prefixes=MM-OBJ,ALL
; Test that spill and reloads use the dsp "variant" instructions. We use -O0 ; Test that spill and reloads use the dsp "variant" instructions. We use -O0
; to use the simple register allocator. ; to use the simple register allocator.
; To test the micromips output, we have to take a round trip through the ; To test the micromips output, we have to take a round trip through the
; object file encoder/decoder as the instruction mapping tables are used to ; object file encoder/decoder as the instruction mapping tables are used to
; support micromips. ; support micromips.
; FIXME: We should be able to get rid of those instructions with the variable ; FIXME: We should be able to get rid of those instructions with the variable
; value registers. ; value registers.
; ALL-LABEL: spill_reload: ; ALL-LABEL: spill_reload{{>?}}:
define <4 x i8> @spill_reload(<4 x i8> %a, <4 x i8> %b, i32 %g) { define <4 x i8> @spill_reload(<4 x i8> %a, <4 x i8> %b, i32 %g) {
entry: entry:
%c = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %a, <4 x i8> %b) %c = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %a, <4 x i8> %b)
%cond = icmp eq i32 %g, 0 %cond = icmp eq i32 %g, 0
br i1 %cond, label %true, label %end br i1 %cond, label %true, label %end
; ASM: SWDSP ; ASM: SWDSP
Show All 25 Lines

llvm/test/CodeGen/Mips/micromips-b-range.ll

; RUN: llc -march=mips -relocation-model=pic -mattr=+micromips \ ; RUN: llc -march=mips -relocation-model=pic -mattr=+micromips \
; RUN: -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s ; RUN: -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
; CHECK-LABEL: foo: ; CHECK-LABEL: <foo>:
; CHECK-NEXT: 0: 41 a2 00 00 lui $2, 0 ; CHECK-NEXT: 0: 41 a2 00 00 lui $2, 0
; CHECK-NEXT: 4: 30 42 00 00 addiu $2, $2, 0 ; CHECK-NEXT: 4: 30 42 00 00 addiu $2, $2, 0
; CHECK-NEXT: 8: 03 22 11 50 addu $2, $2, $25 ; CHECK-NEXT: 8: 03 22 11 50 addu $2, $2, $25
; CHECK-NEXT: c: fc 42 00 00 lw $2, 0($2) ; CHECK-NEXT: c: fc 42 00 00 lw $2, 0($2)
; CHECK-NEXT: 10: 69 20 lw16 $2, 0($2) ; CHECK-NEXT: 10: 69 20 lw16 $2, 0($2)
; CHECK-NEXT: 12: 40 c2 00 14 bgtz $2, 44 <foo+0x3e> ; CHECK-NEXT: 12: 40 c2 00 14 bgtz $2, 44 <foo+0x3e>
; CHECK-NEXT: 16: 00 00 00 00 nop ; CHECK-NEXT: 16: 00 00 00 00 nop
; CHECK-NEXT: 1a: 33 bd ff f8 addiu $sp, $sp, -8 ; CHECK-NEXT: 1a: 33 bd ff f8 addiu $sp, $sp, -8
▲ Show 20 Lines • Show All 85 Lines • Show Last 20 Lines

llvm/test/CodeGen/Mips/micromips-sw.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips \ ; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips \
; RUN: -filetype=obj -o - %s | llvm-objdump -d - \ ; RUN: -filetype=obj -o - %s | llvm-objdump -d - \
; RUN: | FileCheck --check-prefix=MM2 %s ; RUN: | FileCheck --check-prefix=MM2 %s
; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs \ ; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs \
; RUN: -filetype=obj -o - %s | llvm-objdump -d - \ ; RUN: -filetype=obj -o - %s | llvm-objdump -d - \
; RUN: | FileCheck --check-prefix=MM6 %s ; RUN: | FileCheck --check-prefix=MM6 %s
define void @fun(i32 %val) { define void @fun(i32 %val) {
; MM2-LABEL: fun: ; MM2-LABEL: <fun>:
; MM2: cb e5 sw $ra, 20($sp) ; MM2: cb e5 sw $ra, 20($sp)
; MM6-LABEL: fun: ; MM6-LABEL: <fun>:
; MM6: fb fd 00 14 sw $ra, 20($sp) ; MM6: fb fd 00 14 sw $ra, 20($sp)
entry: entry:
call i32* @fun1() call i32* @fun1()
ret void ret void
} }
declare i32* @fun1() declare i32* @fun1()

llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines bb.0.entry:
%2:gpr32 = LWLE %0, 0, %3 :: (load 4 from %ir.a, align 1) %2:gpr32 = LWLE %0, 0, %3 :: (load 4 from %ir.a, align 1)
%4:gpr32 = LWRE %0, 3, %2 :: (load 4 from %ir.a, align 1) %4:gpr32 = LWRE %0, 3, %2 :: (load 4 from %ir.a, align 1)
SWLE %4, %1, 0 :: (store 4 into %ir.b, align 1) SWLE %4, %1, 0 :: (store 4 into %ir.b, align 1)
SWRE %4, %1, 3 :: (store 4 into %ir.b, align 1) SWRE %4, %1, 3 :: (store 4 into %ir.b, align 1)
RetRA RetRA
... ...
# CHECK-LABEL: g: # CHECK-LABEL: <g>:
# CHECK: 0: 60 24 00 00 lwl $1, 0($4) # CHECK: 0: 60 24 00 00 lwl $1, 0($4)
# CHECK: 4: 60 24 10 03 lwr $1, 3($4) # CHECK: 4: 60 24 10 03 lwr $1, 3($4)
# CHECK: 8: 60 25 80 00 swl $1, 0($5) # CHECK: 8: 60 25 80 00 swl $1, 0($5)
# CHECK: c: 60 25 90 03 swr $1, 3($5) # CHECK: c: 60 25 90 03 swr $1, 3($5)
# CHECK-LABEL: g2: # CHECK-LABEL: <g2>:
# CHECK: 14: 60 24 64 00 lwle $1, 0($4) # CHECK: 14: 60 24 64 00 lwle $1, 0($4)
# CHECK: 18: 60 24 66 03 lwre $1, 3($4) # CHECK: 18: 60 24 66 03 lwre $1, 3($4)
# CHECK: 1c: 60 25 a0 00 swle $1, 0($5) # CHECK: 1c: 60 25 a0 00 swle $1, 0($5)
# CHECK: 20: 60 25 a2 03 swre $1, 3($5) # CHECK: 20: 60 25 a2 03 swre $1, 3($5)

llvm/test/CodeGen/PowerPC/aix-indirect-call.ll

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
; MIR64-DAG: $x2 = LD 8, killed renamable $x3 :: (dereferenceable invariant load 8 from %ir.0 + 8) ; MIR64-DAG: $x2 = LD 8, killed renamable $x3 :: (dereferenceable invariant load 8 from %ir.0 + 8)
; MIR64-DAG: $x3 = LI8 1 ; MIR64-DAG: $x3 = LI8 1
; MIR64-DAG: $x4 = LI8 2 ; MIR64-DAG: $x4 = LI8 2
; MIR64-DAG: $x5 = LI8 3 ; MIR64-DAG: $x5 = LI8 3
; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_aix64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1 ; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_aix64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1
; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .callThroughPtrWithArgs: ; CHECKASM-LABEL: .callThroughPtrWithArgs:
; CHECKOBJ-LABEL: .callThroughPtrWithArgs: ; CHECKOBJ-LABEL: <.callThroughPtrWithArgs>:
; ASMOBJ32: stwu 1, -64(1) ; ASMOBJ32: stwu 1, -64(1)
; ASMOBJ32-DAG: lwz [[REG:[0-9]+]], 0(3) ; ASMOBJ32-DAG: lwz [[REG:[0-9]+]], 0(3)
; ASMOBJ32-DAG: li 5, 0 ; ASMOBJ32-DAG: li 5, 0
; ASMOBJ32-DAG: li 6, 3 ; ASMOBJ32-DAG: li 6, 3
; ASMOBJ32-DAG: stw 2, 20(1) ; ASMOBJ32-DAG: stw 2, 20(1)
; ASMOBJ32-DAG: mtctr [[REG]] ; ASMOBJ32-DAG: mtctr [[REG]]
; ASMOBJ32-DAG: li 4, 2 ; ASMOBJ32-DAG: li 4, 2
Show All 19 Lines

llvm/test/CodeGen/PowerPC/aix-return55.ll

Show All 13 Lines
define dso_local signext i32 @foo() { define dso_local signext i32 @foo() {
entry: entry:
ret i32 55 ret i32 55
; CHECK-LABEL: .foo: ; CHECK-LABEL: .foo:
; CHECK: li 3, 55 ; CHECK: li 3, 55
; CHECK: blr ; CHECK: blr
} }
;CHECKOBJ: 00000000 .text: ;CHECKOBJ: 00000000 <.text>:
;CHECKOBJ-NEXT: 0: 38 60 00 37 li 3, 55 ;CHECKOBJ-NEXT: 0: 38 60 00 37 li 3, 55
;CHECKOBJ-NEXT: 4: 4e 80 00 20 blr{{[[:space:]] *}} ;CHECKOBJ-NEXT: 4: 4e 80 00 20 blr{{[[:space:]] *}}
;CHECKOBJ-NEXT: 00000008 .rodata.str1.1: ;CHECKOBJ-NEXT: 00000008 <.rodata.str1.1>:
;CHECKOBJ-NEXT: 8: 68 65 6c 6c xori 5, 3, 27756 ;CHECKOBJ-NEXT: 8: 68 65 6c 6c xori 5, 3, 27756
;CHECKOBJ-NEXT: c: 6f 77 6f 72 xoris 23, 27, 28530 ;CHECKOBJ-NEXT: c: 6f 77 6f 72 xoris 23, 27, 28530
;CHECKOBJ-NEXT: 10: 0a 00 00 00 tdlti 0, 0{{[[:space:]] *}} ;CHECKOBJ-NEXT: 10: 0a 00 00 00 tdlti 0, 0{{[[:space:]] *}}
;CHECKOBJ-NEXT: Disassembly of section .data:{{[[:space:]] *}} ;CHECKOBJ-NEXT: Disassembly of section .data:{{[[:space:]] *}}
;CHECKOBJ-NEXT: 00000018 a: ;CHECKOBJ-NEXT: 00000018 <a>:
;CHECKOBJ-NEXT: 18: 00 01 23 45 <unknown> ;CHECKOBJ-NEXT: 18: 00 01 23 45 <unknown>
;CHECKOBJ-NEXT: 1c: 67 8a bc de oris 10, 28, 48350{{[[:space:]] *}} ;CHECKOBJ-NEXT: 1c: 67 8a bc de oris 10, 28, 48350{{[[:space:]] *}}
;CHECKOBJ-NEXT: 00000020 d: ;CHECKOBJ-NEXT: 00000020 <d>:
;CHECKOBJ-NEXT: 20: 40 14 00 00 bdnzf 20, .+0 ;CHECKOBJ-NEXT: 20: 40 14 00 00 bdnzf 20, .+0
;CHECKOBJ-NEXT: 24: 00 00 00 00 <unknown>{{[[:space:]] *}} ;CHECKOBJ-NEXT: 24: 00 00 00 00 <unknown>{{[[:space:]] *}}
;CHECKOBJ-NEXT: 00000028 foo: ;CHECKOBJ-NEXT: 00000028 <foo>:
;CHECKOBJ-NEXT: 28: 00 00 00 00 <unknown> ;CHECKOBJ-NEXT: 28: 00 00 00 00 <unknown>
;CHECKOBJ-NEXT: 2c: 00 00 00 34 <unknown> ;CHECKOBJ-NEXT: 2c: 00 00 00 34 <unknown>
;CHECKOBJ-NEXT: 30: 00 00 00 00 <unknown> ;CHECKOBJ-NEXT: 30: 00 00 00 00 <unknown>
;CHECKSECT: Sections [ ;CHECKSECT: Sections [
;CHECKSECT-NEXT: Section { ;CHECKSECT-NEXT: Section {
;CHECKSECT-NEXT: Index: 1 ;CHECKSECT-NEXT: Index: 1
;CHECKSECT-NEXT: Name: .text ;CHECKSECT-NEXT: Name: .text
Show All 24 Lines

llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; 32-REL-NEXT: Type: R_POS (0x0) ; 32-REL-NEXT: Type: R_POS (0x0)
; 32-REL-NEXT: } ; 32-REL-NEXT: }
; 32-REL-NEXT: } ; 32-REL-NEXT: }
; 32-REL-NEXT: ] ; 32-REL-NEXT: ]
; 32-REL-NOT: Type: R_RBR (0x1A) ; 32-REL-NOT: Type: R_RBR (0x1A)
; 32-DIS: Disassembly of section .text: ; 32-DIS: Disassembly of section .text:
; 32-DIS: 00000000 .text: ; 32-DIS: 00000000 <.text>:
; 32-DIS-NEXT: 0: 38 60 00 03 li 3, 3 ; 32-DIS-NEXT: 0: 38 60 00 03 li 3, 3
; 32-DIS-NEXT: 4: 4e 80 00 20 blr ; 32-DIS-NEXT: 4: 4e 80 00 20 blr
; 32-DIS-NEXT: 8: 60 00 00 00 nop ; 32-DIS-NEXT: 8: 60 00 00 00 nop
; 32-DIS-NEXT: c: 60 00 00 00 nop ; 32-DIS-NEXT: c: 60 00 00 00 nop
; 32-DIS: 00000010 .call_memcpy: ; 32-DIS: 00000010 <.call_memcpy>:
; 32-DIS-NEXT: 10: 7c 08 02 a6 mflr 0 ; 32-DIS-NEXT: 10: 7c 08 02 a6 mflr 0
; 32-DIS-NEXT: 14: 90 01 00 08 stw 0, 8(1) ; 32-DIS-NEXT: 14: 90 01 00 08 stw 0, 8(1)
; 32-DIS-NEXT: 18: 94 21 ff c0 stwu 1, -64(1) ; 32-DIS-NEXT: 18: 94 21 ff c0 stwu 1, -64(1)
; 32-DIS-NEXT: 1c: 4b ff ff e5 bl .-28 ; 32-DIS-NEXT: 1c: 4b ff ff e5 bl .-28
; 32-DIS-NEXT: 20: 60 00 00 00 nop ; 32-DIS-NEXT: 20: 60 00 00 00 nop
; 32-DIS-NEXT: 24: 38 21 00 40 addi 1, 1, 64 ; 32-DIS-NEXT: 24: 38 21 00 40 addi 1, 1, 64
; 32-DIS-NEXT: 28: 80 01 00 08 lwz 0, 8(1) ; 32-DIS-NEXT: 28: 80 01 00 08 lwz 0, 8(1)
; 32-DIS-NEXT: 2c: 7c 08 03 a6 mtlr 0 ; 32-DIS-NEXT: 2c: 7c 08 03 a6 mtlr 0
; 32-DIS-NEXT: 30: 4e 80 00 20 blr ; 32-DIS-NEXT: 30: 4e 80 00 20 blr
; 64-CHECK: LLVM ERROR: 64-bit XCOFF object files are not supported yet. ; 64-CHECK: LLVM ERROR: 64-bit XCOFF object files are not supported yet.

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
;CHECK-NEXT: .long 0 # 0x0 ;CHECK-NEXT: .long 0 # 0x0
;CHECK-NEXT: .align 3 ;CHECK-NEXT: .align 3
;CHECK-NEXT: .L__const.main.cnst4: ;CHECK-NEXT: .L__const.main.cnst4:
;CHECK-NEXT: .short 16392 # 0x4008 ;CHECK-NEXT: .short 16392 # 0x4008
;CHECK-NEXT: .byte 0 # 0x0 ;CHECK-NEXT: .byte 0 # 0x0
;CHECK-NEXT: .space 1 ;CHECK-NEXT: .space 1
;CHECKOBJ: 00000000 .text: ;CHECKOBJ: 00000000 <.text>:
;CHECKOBJ-NEXT: 0: 38 60 00 00 li 3, 0 ;CHECKOBJ-NEXT: 0: 38 60 00 00 li 3, 0
;CHECKOBJ-NEXT: 4: 4e 80 00 20 blr ;CHECKOBJ-NEXT: 4: 4e 80 00 20 blr
;CHECKOBJ-NEXT: ...{{[[:space:]] *}} ;CHECKOBJ-NEXT: ...{{[[:space:]] *}}
;CHECKOBJ-NEXT: 00000010 .rodata: ;CHECKOBJ-NEXT: 00000010 <.rodata>:
;CHECKOBJ-NEXT: 10: 40 00 00 00 ;CHECKOBJ-NEXT: 10: 40 00 00 00
;CHECKOBJ-NEXT: 14: 00 00 00 32 ;CHECKOBJ-NEXT: 14: 00 00 00 32
;CHECKOBJ-NEXT: ...{{[[:space:]] *}} ;CHECKOBJ-NEXT: ...{{[[:space:]] *}}
;CHECKOBJ-SAME: 30: 40 00 00 00 ;CHECKOBJ-SAME: 30: 40 00 00 00
;CHECKOBJ-NEXT: 34: 00 00 00 16 ;CHECKOBJ-NEXT: 34: 00 00 00 16
;CHECKOBJ-NEXT: ...{{[[:space:]] *}} ;CHECKOBJ-NEXT: ...{{[[:space:]] *}}
;CHECKOBJ-SAME: 40: 40 00 00 08 ;CHECKOBJ-SAME: 40: 40 00 00 08
;CHECKOBJ-NEXT: 44: 00 00 00 00 ;CHECKOBJ-NEXT: 44: 00 00 00 00
Show All 21 Lines

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .byte 99 ; CHECK-NEXT: .byte 99
; CHECK-NEXT: .byte 100 ; CHECK-NEXT: .byte 100
; CHECK-NEXT: .byte 101 ; CHECK-NEXT: .byte 101
; CHECK-NEXT: .byte 102 ; CHECK-NEXT: .byte 102
; CHECK-NEXT: .byte 103 ; CHECK-NEXT: .byte 103
; CHECK-NEXT: .byte 104 ; CHECK-NEXT: .byte 104
; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .byte 0
; CHECKOBJ: 00000010 .rodata.str2.2: ; CHECKOBJ: 00000010 <.rodata.str2.2>:
; CHECKOBJ-NEXT: 10: 01 08 01 10 ; CHECKOBJ-NEXT: 10: 01 08 01 10
; CHECKOBJ-NEXT: 14: 00 d5 00 00 {{.*}}{{[[:space:]] *}} ; CHECKOBJ-NEXT: 14: 00 d5 00 00 {{.*}}{{[[:space:]] *}}
; CHECKOBJ-NEXT: 00000018 .rodata.str4.4: ; CHECKOBJ-NEXT: 00000018 <.rodata.str4.4>:
; CHECKOBJ-NEXT: 18: 00 00 01 d0 ; CHECKOBJ-NEXT: 18: 00 00 01 d0
; CHECKOBJ-NEXT: 1c: 00 00 01 d8 ; CHECKOBJ-NEXT: 1c: 00 00 01 d8
; CHECKOBJ-NEXT: 20: 00 00 01 9d ; CHECKOBJ-NEXT: 20: 00 00 01 9d
; CHECKOBJ-NEXT: 24: 00 00 00 00 {{.*}}{{[[:space:]] *}} ; CHECKOBJ-NEXT: 24: 00 00 00 00 {{.*}}{{[[:space:]] *}}
; CHECKOBJ-NEXT: 00000028 .rodata.str1.1: ; CHECKOBJ-NEXT: 00000028 <.rodata.str1.1>:
; CHECKOBJ-NEXT: 28: 68 65 6c 6c ; CHECKOBJ-NEXT: 28: 68 65 6c 6c
; CHECKOBJ-NEXT: 2c: 6f 20 77 6f ; CHECKOBJ-NEXT: 2c: 6f 20 77 6f
; CHECKOBJ-NEXT: 30: 72 6c 64 21 ; CHECKOBJ-NEXT: 30: 72 6c 64 21
; CHECKOBJ-NEXT: 34: 0a 00 61 62 ; CHECKOBJ-NEXT: 34: 0a 00 61 62
; CHECKOBJ-NEXT: 38: 63 64 65 66 ; CHECKOBJ-NEXT: 38: 63 64 65 66
; CHECKOBJ-NEXT: 3c: 67 68 00 00 ; CHECKOBJ-NEXT: 3c: 67 68 00 00

llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Show First 20 Lines • Show All 404 Lines • ▼ Show 20 Lines
; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: StabSectNum: 0x0
; SYM-NEXT: } ; SYM-NEXT: }
; SYM-NEXT: } ; SYM-NEXT: }
; SYM-NEXT: ] ; SYM-NEXT: ]
; DIS: {{.*}}aix-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000 ; DIS: {{.*}}aix-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000
; DIS: Disassembly of section .text: ; DIS: Disassembly of section .text:
; DIS: 00000000 .text: ; DIS: 00000000 <.text>:
; DIS-NEXT: 0: 7c 08 02 a6 mflr 0 ; DIS-NEXT: 0: 7c 08 02 a6 mflr 0
; DIS-NEXT: 4: 90 01 00 08 stw 0, 8(1) ; DIS-NEXT: 4: 90 01 00 08 stw 0, 8(1)
; DIS-NEXT: 8: 94 21 ff c0 stwu 1, -64(1) ; DIS-NEXT: 8: 94 21 ff c0 stwu 1, -64(1)
; DIS-NEXT: c: 38 60 00 01 li 3, 1 ; DIS-NEXT: c: 38 60 00 01 li 3, 1
; DIS-NEXT: 10: 4b ff ff f1 bl .-16 ; DIS-NEXT: 10: 4b ff ff f1 bl .-16
; DIS-NEXT: 14: 60 00 00 00 nop ; DIS-NEXT: 14: 60 00 00 00 nop
; DIS-NEXT: 18: 80 82 00 00 lwz 4, 0(2) ; DIS-NEXT: 18: 80 82 00 00 lwz 4, 0(2)
; DIS-NEXT: 1c: 80 a2 00 04 lwz 5, 4(2) ; DIS-NEXT: 1c: 80 a2 00 04 lwz 5, 4(2)
; DIS-NEXT: 20: 80 84 00 00 lwz 4, 0(4) ; DIS-NEXT: 20: 80 84 00 00 lwz 4, 0(4)
; DIS-NEXT: 24: 80 a5 00 00 lwz 5, 0(5) ; DIS-NEXT: 24: 80 a5 00 00 lwz 5, 0(5)
; DIS-NEXT: 28: 7c 63 22 14 add 3, 3, 4 ; DIS-NEXT: 28: 7c 63 22 14 add 3, 3, 4
; DIS-NEXT: 2c: 7c 63 2a 14 add 3, 3, 5 ; DIS-NEXT: 2c: 7c 63 2a 14 add 3, 3, 5
; DIS-NEXT: 30: 38 21 00 40 addi 1, 1, 64 ; DIS-NEXT: 30: 38 21 00 40 addi 1, 1, 64
; DIS-NEXT: 34: 80 01 00 08 lwz 0, 8(1) ; DIS-NEXT: 34: 80 01 00 08 lwz 0, 8(1)
; DIS-NEXT: 38: 7c 08 03 a6 mtlr 0 ; DIS-NEXT: 38: 7c 08 03 a6 mtlr 0
; DIS-NEXT: 3c: 4e 80 00 20 blr ; DIS-NEXT: 3c: 4e 80 00 20 blr
; DIS: Disassembly of section .data: ; DIS: Disassembly of section .data:
; DIS: 00000040 globalA: ; DIS: 00000040 <globalA>:
; DIS-NEXT: 40: 00 00 00 01 <unknown> ; DIS-NEXT: 40: 00 00 00 01 <unknown>
; DIS: 00000044 globalB: ; DIS: 00000044 <globalB>:
; DIS-NEXT: 44: 00 00 00 02 <unknown> ; DIS-NEXT: 44: 00 00 00 02 <unknown>
; DIS: 00000048 arr: ; DIS: 00000048 <arr>:
; DIS-NEXT: 48: 00 00 00 03 <unknown> ; DIS-NEXT: 48: 00 00 00 03 <unknown>
; DIS-NEXT: ... ; DIS-NEXT: ...
; DIS: 00000070 p: ; DIS: 00000070 <p>:
; DIS-NEXT: 70: 00 00 00 58 <unknown> ; DIS-NEXT: 70: 00 00 00 58 <unknown>
; DIS: 00000074 foo: ; DIS: 00000074 <foo>:
; DIS-NEXT: 74: 00 00 00 00 <unknown> ; DIS-NEXT: 74: 00 00 00 00 <unknown>
; DIS-NEXT: 78: 00 00 00 80 <unknown> ; DIS-NEXT: 78: 00 00 00 80 <unknown>
; DIS-NEXT: 7c: 00 00 00 00 <unknown> ; DIS-NEXT: 7c: 00 00 00 00 <unknown>
; DIS: 00000080 globalA: ; DIS: 00000080 <globalA>:
; DIS-NEXT: 80: 00 00 00 40 <unknown> ; DIS-NEXT: 80: 00 00 00 40 <unknown>
; DIS: 00000084 globalB: ; DIS: 00000084 <globalB>:
; DIS-NEXT: 84: 00 00 00 44 <unknown> ; DIS-NEXT: 84: 00 00 00 44 <unknown>

llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll

Show First 20 Lines • Show All 279 Lines • ▼ Show 20 Lines
; SYMS-NEXT: StorageMappingClass: XMC_RO (0x1) ; SYMS-NEXT: StorageMappingClass: XMC_RO (0x1)
; SYMS-NEXT: StabInfoIndex: 0x0 ; SYMS-NEXT: StabInfoIndex: 0x0
; SYMS-NEXT: StabSectNum: 0x0 ; SYMS-NEXT: StabSectNum: 0x0
; SYMS-NEXT: } ; SYMS-NEXT: }
; SYMS-NEXT: } ; SYMS-NEXT: }
; SYMS: ] ; SYMS: ]
; DIS: Disassembly of section .text: ; DIS: Disassembly of section .text:
; DIS: 00000000 const_ivar: ; DIS: 00000000 <const_ivar>:
; DIS-NEXT: 0: 00 00 00 23 ; DIS-NEXT: 0: 00 00 00 23
; DIS-NEXT: 4: 00 00 00 00 ; DIS-NEXT: 4: 00 00 00 00
; DIS: 00000008 const_llvar: ; DIS: 00000008 <const_llvar>:
; DIS-NEXT: 8: 00 00 00 00 ; DIS-NEXT: 8: 00 00 00 00
; DIS-NEXT: c: 00 00 00 24 ; DIS-NEXT: c: 00 00 00 24
; DIS: 00000010 const_svar: ; DIS: 00000010 <const_svar>:
; DIS-NEXT: 10: 00 25 00 00 ; DIS-NEXT: 10: 00 25 00 00
; DIS: 00000014 const_fvar: ; DIS: 00000014 <const_fvar>:
; DIS-NEXT: 14: 44 48 00 00 ; DIS-NEXT: 14: 44 48 00 00
; DIS: 00000018 const_dvar: ; DIS: 00000018 <const_dvar>:
; DIS-NEXT: 18: 40 8c 20 00 ; DIS-NEXT: 18: 40 8c 20 00
; DIS-NEXT: 1c: 00 00 00 00 ; DIS-NEXT: 1c: 00 00 00 00
; DIS: 00000020 const_over_aligned: ; DIS: 00000020 <const_over_aligned>:
; DIS-NEXT: 20: 40 8c 20 00 ; DIS-NEXT: 20: 40 8c 20 00
; DIS-NEXT: 24: 00 00 00 00 ; DIS-NEXT: 24: 00 00 00 00
; DIS: 00000028 const_chrarray: ; DIS: 00000028 <const_chrarray>:
; DIS-NEXT: 28: 61 62 63 64 ; DIS-NEXT: 28: 61 62 63 64
; DIS-NEXT: 2c: 00 00 00 00 ; DIS-NEXT: 2c: 00 00 00 00
; DIS: 00000030 const_dblarr: ; DIS: 00000030 <const_dblarr>:
; DIS-NEXT: 30: 3f f0 00 00 ; DIS-NEXT: 30: 3f f0 00 00
; DIS-NEXT: 34: 00 00 00 00 ; DIS-NEXT: 34: 00 00 00 00
; DIS-NEXT: 38: 40 00 00 00 ; DIS-NEXT: 38: 40 00 00 00
; DIS-NEXT: 3c: 00 00 00 00 ; DIS-NEXT: 3c: 00 00 00 00
; DIS-NEXT: 40: 40 08 00 00 ; DIS-NEXT: 40: 40 08 00 00
; DIS-NEXT: 44: 00 00 00 00 ; DIS-NEXT: 44: 00 00 00 00
; DIS-NEXT: 48: 40 10 00 00 ; DIS-NEXT: 48: 40 10 00 00
; DIS-NEXT: 4c: 00 00 00 00 ; DIS-NEXT: 4c: 00 00 00 00

llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECK %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECK %s
define i32 @foo() #0 { define i32 @foo() #0 {
entry: entry:
ret i32 0 ret i32 0
} }
define i32 @foo1() #0 { define i32 @foo1() #0 {
entry: entry:
ret i32 1 ret i32 1
} }
; CHECK: Disassembly of section .text:{{[[:space:]] *}} ; CHECK: Disassembly of section .text:{{[[:space:]] *}}
; CHECK-NEXT: 00000000 .text: ; CHECK-NEXT: 00000000 <.text>:
; CHECK-NEXT: 0: 38 60 00 00 li 3, 0 ; CHECK-NEXT: 0: 38 60 00 00 li 3, 0
; CHECK-NEXT: 4: 4e 80 00 20 blr ; CHECK-NEXT: 4: 4e 80 00 20 blr
; CHECK-NEXT: 8: 60 00 00 00 nop ; CHECK-NEXT: 8: 60 00 00 00 nop
; CHECK-NEXT: c: 60 00 00 00 nop ; CHECK-NEXT: c: 60 00 00 00 nop
; CHECK: 00000010 .foo1: ; CHECK: 00000010 <.foo1>:
; CHECK-NEXT: 10: 38 60 00 01 li 3, 1 ; CHECK-NEXT: 10: 38 60 00 01 li 3, 1
; CHECK-NEXT: 14: 4e 80 00 20 blr ; CHECK-NEXT: 14: 4e 80 00 20 blr

llvm/test/CodeGen/RISCV/compress-float.ll

Show All 26 Lines
; This acts as a sanity check for the codegen instruction compression path, ; This acts as a sanity check for the codegen instruction compression path,
; verifying that the assembled file contains compressed instructions when ; verifying that the assembled file contains compressed instructions when
; expected. Handling of the compressed ISA is implemented so the same ; expected. Handling of the compressed ISA is implemented so the same
; transformation patterns should be used whether compressing an input .s file or ; transformation patterns should be used whether compressing an input .s file or
; compressing codegen output. This file contains sanity checks using ; compressing codegen output. This file contains sanity checks using
; instructions which also require one of the floating point extensions. ; instructions which also require one of the floating point extensions.
define float @float_load(float *%a) #0 { define float @float_load(float *%a) #0 {
; RV32IFDC-LABEL: float_load: ; RV32IFDC-LABEL: <float_load>:
; RV32IFDC: c.flw fa0, 0(a0) ; RV32IFDC: c.flw fa0, 0(a0)
; RV32IFDC-NEXT: c.jr ra ; RV32IFDC-NEXT: c.jr ra
%1 = load volatile float, float* %a %1 = load volatile float, float* %a
ret float %1 ret float %1
} }
define double @double_load(double *%a) #0 { define double @double_load(double *%a) #0 {
; RV32IFDC-LABEL: double_load: ; RV32IFDC-LABEL: <double_load>:
; RV32IFDC: c.fld fa0, 0(a0) ; RV32IFDC: c.fld fa0, 0(a0)
; RV32IFDC-NEXT: c.jr ra ; RV32IFDC-NEXT: c.jr ra
%1 = load volatile double, double* %a %1 = load volatile double, double* %a
ret double %1 ret double %1
} }

llvm/test/CodeGen/RISCV/compress-inline-asm.ll

; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s\ ; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s\
; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -M no-aliases -\ ; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -M no-aliases -\
; RUN: | FileCheck -check-prefix=CHECK %s ; RUN: | FileCheck -check-prefix=CHECK %s
@ext = external global i32 @ext = external global i32
define i32 @compress_test(i32 %a) { define i32 @compress_test(i32 %a) {
; CHECK-LABEL: compress_test: ; CHECK-LABEL: <compress_test>:
; CHECK: c.add a0, a1 ; CHECK: c.add a0, a1
; CHECK-NEXT: c.jr ra ; CHECK-NEXT: c.jr ra
%1 = load i32, i32* @ext %1 = load i32, i32* @ext
%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1) %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
ret i32 %2 ret i32 %2
} }

llvm/test/CodeGen/RISCV/compress.ll

Show All 24 Lines
; Note: TODOs in this file are only appropriate if they highlight a case where ; Note: TODOs in this file are only appropriate if they highlight a case where
; a generated instruction that can be compressed by an existing pattern isn't. ; a generated instruction that can be compressed by an existing pattern isn't.
; It may be useful to have tests that indicate where better compression would be ; It may be useful to have tests that indicate where better compression would be
; possible if alternative codegen choices were made, but they belong in a ; possible if alternative codegen choices were made, but they belong in a
; different test file. ; different test file.
define i32 @simple_arith(i32 %a, i32 %b) #0 { define i32 @simple_arith(i32 %a, i32 %b) #0 {
; RV32IC-LABEL: simple_arith: ; RV32IC-LABEL: <simple_arith>:
; RV32IC: addi a2, a0, 1 ; RV32IC: addi a2, a0, 1
; RV32IC-NEXT: c.andi a2, 11 ; RV32IC-NEXT: c.andi a2, 11
; RV32IC-NEXT: c.slli a2, 7 ; RV32IC-NEXT: c.slli a2, 7
; RV32IC-NEXT: c.srai a1, 9 ; RV32IC-NEXT: c.srai a1, 9
; RV32IC-NEXT: c.add a1, a2 ; RV32IC-NEXT: c.add a1, a2
; RV32IC-NEXT: sub a0, a1, a0 ; RV32IC-NEXT: sub a0, a1, a0
; RV32IC-NEXT: c.jr ra ; RV32IC-NEXT: c.jr ra
%1 = add i32 %a, 1 %1 = add i32 %a, 1
%2 = and i32 %1, 11 %2 = and i32 %1, 11
%3 = shl i32 %2, 7 %3 = shl i32 %2, 7
%4 = ashr i32 %b, 9 %4 = ashr i32 %b, 9
%5 = add i32 %3, %4 %5 = add i32 %3, %4
%6 = sub i32 %5, %a %6 = sub i32 %5, %a
ret i32 %6 ret i32 %6
} }
define i32 @select(i32 %a, i32 *%b) #0 { define i32 @select(i32 %a, i32 *%b) #0 {
; RV32IC-LABEL: select: ; RV32IC-LABEL: <select>:
; RV32IC: c.lw a2, 0(a1) ; RV32IC: c.lw a2, 0(a1)
; RV32IC-NEXT: c.beqz a2, 4 ; RV32IC-NEXT: c.beqz a2, 4
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: c.lw a2, 0(a1)
; RV32IC-NEXT: c.bnez a2, 4 ; RV32IC-NEXT: c.bnez a2, 4
; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0(a1) ; RV32IC-NEXT: c.lw a2, 0(a1)
; RV32IC-NEXT: bltu a2, a0, 6 ; RV32IC-NEXT: bltu a2, a0, 6
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines; RV32IC-NEXT: c.jr ra
%val19 = load volatile i32, i32* %b %val19 = load volatile i32, i32* %b
%tst10 = icmp sle i32 %val18, %val19 %tst10 = icmp sle i32 %val18, %val19
%val20 = select i1 %tst10, i32 %val18, i32 %val19 %val20 = select i1 %tst10, i32 %val18, i32 %val19
ret i32 %val20 ret i32 %val20
} }
define i32 @pos_tiny() #0 { define i32 @pos_tiny() #0 {
; RV32IC-LABEL: pos_tiny: ; RV32IC-LABEL: <pos_tiny>:
; RV32IC: c.li a0, 18 ; RV32IC: c.li a0, 18
; RV32IC-NEXT: c.jr ra ; RV32IC-NEXT: c.jr ra
ret i32 18 ret i32 18
} }
define i32 @pos_i32() #0 { define i32 @pos_i32() #0 {
; RV32IC-LABEL: pos_i32: ; RV32IC-LABEL: <pos_i32>:
; RV32IC: lui a0, 423811 ; RV32IC: lui a0, 423811
; RV32IC-NEXT: addi a0, a0, -1297 ; RV32IC-NEXT: addi a0, a0, -1297
; RV32IC-NEXT: c.jr ra ; RV32IC-NEXT: c.jr ra
ret i32 1735928559 ret i32 1735928559
} }
define i32 @pos_i32_half_compressible() #0 { define i32 @pos_i32_half_compressible() #0 {
; RV32IC-LABEL: pos_i32_half_compressible: ; RV32IC-LABEL: <pos_i32_half_compressible>:
; RV32IC: lui a0, 423810 ; RV32IC: lui a0, 423810
; RV32IC-NEXT: c.addi a0, 28 ; RV32IC-NEXT: c.addi a0, 28
; RV32IC-NEXT: c.jr ra ; RV32IC-NEXT: c.jr ra
ret i32 1735925788 ret i32 1735925788
} }
define i32 @neg_tiny() #0 { define i32 @neg_tiny() #0 {
; RV32IC-LABEL: neg_tiny: ; RV32IC-LABEL: <neg_tiny>:
; RV32IC: c.li a0, -19 ; RV32IC: c.li a0, -19
; RV32IC-NEXT: c.jr ra ; RV32IC-NEXT: c.jr ra
ret i32 -19 ret i32 -19
} }
define i32 @neg_i32() #0 { define i32 @neg_i32() #0 {
; RV32IC-LABEL: neg_i32: ; RV32IC-LABEL: <neg_i32>:
; RV32IC: lui a0, 912092 ; RV32IC: lui a0, 912092
; RV32IC-NEXT: addi a0, a0, -273 ; RV32IC-NEXT: addi a0, a0, -273
; RV32IC-NEXT: c.jr ra ; RV32IC-NEXT: c.jr ra
ret i32 -559038737 ret i32 -559038737
} }
define i32 @pos_i32_hi20_only() #0 { define i32 @pos_i32_hi20_only() #0 {
; RV32IC-LABEL: pos_i32_hi20_only: ; RV32IC-LABEL: <pos_i32_hi20_only>:
; RV32IC: c.lui a0, 16 ; RV32IC: c.lui a0, 16
; RV32IC-NEXT: c.jr ra ; RV32IC-NEXT: c.jr ra
ret i32 65536 ret i32 65536
} }
define i32 @neg_i32_hi20_only() #0 { define i32 @neg_i32_hi20_only() #0 {
; RV32IC-LABEL: neg_i32_hi20_only: ; RV32IC-LABEL: <neg_i32_hi20_only>:
; RV32IC: c.lui a0, 1048560 ; RV32IC: c.lui a0, 1048560
; RV32IC-NEXT: c.jr ra ; RV32IC-NEXT: c.jr ra
ret i32 -65536 ret i32 -65536
} }

llvm/test/CodeGen/RISCV/option-norelax.ll

; RUN: llc -mtriple=riscv32 -mattr=+relax -filetype=obj < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+relax -filetype=obj < %s \
; RUN: | llvm-objdump -d -r - | FileCheck %s ; RUN: | llvm-objdump -d -r - | FileCheck %s
; This test demonstrates that .option norelax has no effect on codegen ; This test demonstrates that .option norelax has no effect on codegen
; when emitting an ELF directly. ; when emitting an ELF directly.
declare i32 @foo(i32) declare i32 @foo(i32)
define i32 @bar(i32 %a) nounwind { define i32 @bar(i32 %a) nounwind {
; CHECK-LABEL: bar: ; CHECK-LABEL: <bar>:
; CHECK: R_RISCV_CALL ; CHECK: R_RISCV_CALL
; CHECK: R_RISCV_RELAX ; CHECK: R_RISCV_RELAX
tail call void asm sideeffect ".option norelax", ""() tail call void asm sideeffect ".option norelax", ""()
%1 = call i32 @foo(i32 %a) %1 = call i32 @foo(i32 %a)
ret i32 %1 ret i32 %1
} }

llvm/test/CodeGen/RISCV/option-norvc.ll

; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s\ ; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s\
; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -M no-aliases -\ ; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -M no-aliases -\
; RUN: | FileCheck -check-prefix=CHECK %s ; RUN: | FileCheck -check-prefix=CHECK %s
; This test demonstrates that .option norvc has no effect on codegen when ; This test demonstrates that .option norvc has no effect on codegen when
; emitting an ELF directly. ; emitting an ELF directly.
define i32 @add(i32 %a, i32 %b) nounwind { define i32 @add(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: add: ; CHECK-LABEL: <add>:
; CHECK: c.add a0, a1 ; CHECK: c.add a0, a1
; CHECK-NEXT: c.jr ra ; CHECK-NEXT: c.jr ra
tail call void asm sideeffect ".option norvc", ""() tail call void asm sideeffect ".option norvc", ""()
%add = add nsw i32 %b, %a %add = add nsw i32 %b, %a
ret i32 %add ret i32 %add
} }

llvm/test/CodeGen/RISCV/option-relax.ll

; RUN: llc -mtriple=riscv32 -mattr=-relax -filetype=obj < %s \ ; RUN: llc -mtriple=riscv32 -mattr=-relax -filetype=obj < %s \
; RUN: | llvm-objdump -d -r - | FileCheck %s ; RUN: | llvm-objdump -d -r - | FileCheck %s
; This test demonstrates that .option relax has no effect on codegen ; This test demonstrates that .option relax has no effect on codegen
; when emitting an ELF directly. ; when emitting an ELF directly.
declare i32 @foo(i32) declare i32 @foo(i32)
define i32 @bar(i32 %a) nounwind { define i32 @bar(i32 %a) nounwind {
; CHECK-LABEL: bar: ; CHECK-LABEL: <bar>:
; CHECK: R_RISCV_CALL ; CHECK: R_RISCV_CALL
; CHECK-NOT: R_RISCV_RELAX ; CHECK-NOT: R_RISCV_RELAX
tail call void asm sideeffect ".option relax", ""() tail call void asm sideeffect ".option relax", ""()
%1 = call i32 @foo(i32 %a) %1 = call i32 @foo(i32 %a)
ret i32 %1 ret i32 %1
} }

llvm/test/CodeGen/RISCV/option-rvc.ll

; RUN: llc -mtriple=riscv32 -filetype=obj < %s\ ; RUN: llc -mtriple=riscv32 -filetype=obj < %s\
; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -M no-aliases -\ ; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -M no-aliases -\
; RUN: | FileCheck -check-prefix=CHECK %s ; RUN: | FileCheck -check-prefix=CHECK %s
; This test demonstrates that .option norvc has no effect on codegen when ; This test demonstrates that .option norvc has no effect on codegen when
; emitting an ELF directly. ; emitting an ELF directly.
define i32 @add(i32 %a, i32 %b) nounwind { define i32 @add(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: add: ; CHECK-LABEL: <add>:
; CHECK: add a0, a1, a0 ; CHECK: add a0, a1, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
tail call void asm sideeffect ".option rvc", ""() tail call void asm sideeffect ".option rvc", ""()
%add = add nsw i32 %b, %a %add = add nsw i32 %b, %a
ret i32 %add ret i32 %add
} }

llvm/test/CodeGen/Thumb/large-stack.ll

; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN4 ; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN4
; RUN: llc < %s -mtriple=thumb-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN8 ; RUN: llc < %s -mtriple=thumb-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN8
; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-apple-ios ; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-apple-ios
; RUN: llvm-objdump -triple=thumbv6-apple-ios -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN4 ; RUN: llvm-objdump -triple=thumbv6-apple-ios -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN4
; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-none-eabi ; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-none-eabi
; RUN: llvm-objdump -triple=thumbv6-none-eabi -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN8 ; RUN: llvm-objdump -triple=thumbv6-none-eabi -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN8
; Largest stack for which a single tADDspi/tSUBspi is enough ; Largest stack for which a single tADDspi/tSUBspi is enough
define void @test1() { define void @test1() {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1{{>?}}:
; CHECK: sub sp, #508 ; CHECK: sub sp, #508
; CHECK: add sp, #508 ; CHECK: add sp, #508
%tmp = alloca [ 508 x i8 ] , align 4 %tmp = alloca [ 508 x i8 ] , align 4
ret void ret void
} }
; Largest stack for which three tADDspi/tSUBspis are enough ; Largest stack for which three tADDspi/tSUBspis are enough
define void @test100() { define void @test100() {
; CHECK-LABEL: test100: ; CHECK-LABEL: test100{{>?}}:
; CHECK: sub sp, #508 ; CHECK: sub sp, #508
; CHECK: sub sp, #508 ; CHECK: sub sp, #508
; CHECK: sub sp, #508 ; CHECK: sub sp, #508
; CHECK: add sp, #508 ; CHECK: add sp, #508
; CHECK: add sp, #508 ; CHECK: add sp, #508
; CHECK: add sp, #508 ; CHECK: add sp, #508
%tmp = alloca [ 1524 x i8 ] , align 4 %tmp = alloca [ 1524 x i8 ] , align 4
ret void ret void
} }
; Largest stack for which three tADDspi/tSUBspis are enough ; Largest stack for which three tADDspi/tSUBspis are enough
define void @test100_nofpelim() "frame-pointer"="all" { define void @test100_nofpelim() "frame-pointer"="all" {
; CHECK-LABEL: test100_nofpelim: ; CHECK-LABEL: test100_nofpelim{{>?}}:
; CHECK: sub sp, #508 ; CHECK: sub sp, #508
; CHECK: sub sp, #508 ; CHECK: sub sp, #508
; CHECK: sub sp, #508 ; CHECK: sub sp, #508
; CHECK: subs r4, r7, #7 ; CHECK: subs r4, r7, #7
; CHECK: subs r4, #1 ; CHECK: subs r4, #1
; CHECK: mov sp, r4 ; CHECK: mov sp, r4
%tmp = alloca [ 1524 x i8 ] , align 4 %tmp = alloca [ 1524 x i8 ] , align 4
ret void ret void
} }
; Smallest stack for which we use a constant pool ; Smallest stack for which we use a constant pool
define void @test2() { define void @test2() {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2{{>?}}:
; CHECK: ldr [[TEMP:r[0-7]]], ; CHECK: ldr [[TEMP:r[0-7]]],
; CHECK: add sp, [[TEMP]] ; CHECK: add sp, [[TEMP]]
; CHECK: ldr [[TEMP:r[0-7]]], ; CHECK: ldr [[TEMP:r[0-7]]],
; CHECK: add sp, [[TEMP]] ; CHECK: add sp, [[TEMP]]
%tmp = alloca [ 1528 x i8 ] , align 4 %tmp = alloca [ 1528 x i8 ] , align 4
ret void ret void
} }
; Smallest stack for which we use a constant pool ; Smallest stack for which we use a constant pool
define void @test2_nofpelim() "frame-pointer"="all" { define void @test2_nofpelim() "frame-pointer"="all" {
; CHECK-LABEL: test2_nofpelim: ; CHECK-LABEL: test2_nofpelim{{>?}}:
; CHECK: ldr [[TEMP:r[0-7]]], ; CHECK: ldr [[TEMP:r[0-7]]],
; CHECK: add sp, [[TEMP]] ; CHECK: add sp, [[TEMP]]
; CHECK: subs r4, r7, #7 ; CHECK: subs r4, r7, #7
; CHECK: subs r4, #1 ; CHECK: subs r4, #1
; CHECK: mov sp, r4 ; CHECK: mov sp, r4
%tmp = alloca [ 1528 x i8 ] , align 4 %tmp = alloca [ 1528 x i8 ] , align 4
ret void ret void
} }
define i32 @test3() { define i32 @test3() {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3{{>?}}:
; CHECK: ldr [[TEMP:r[0-7]]], ; CHECK: ldr [[TEMP:r[0-7]]],
; CHECK: add sp, [[TEMP]] ; CHECK: add sp, [[TEMP]]
; CHECK: ldr [[TEMP2:r[0-7]]], ; CHECK: ldr [[TEMP2:r[0-7]]],
; CHECK: add [[TEMP2]], sp ; CHECK: add [[TEMP2]], sp
; CHECK: ldr [[TEMP3:r[0-7]]], ; CHECK: ldr [[TEMP3:r[0-7]]],
; CHECK: add sp, [[TEMP3]] ; CHECK: add sp, [[TEMP3]]
%retval = alloca i32, align 4 %retval = alloca i32, align 4
%tmp = alloca i32, align 4 %tmp = alloca i32, align 4
%a = alloca [805306369 x i8], align 4 %a = alloca [805306369 x i8], align 4
store i32 0, i32* %tmp store i32 0, i32* %tmp
%tmp1 = load i32, i32* %tmp %tmp1 = load i32, i32* %tmp
ret i32 %tmp1 ret i32 %tmp1
} }
define i32 @test3_nofpelim() "frame-pointer"="all" { define i32 @test3_nofpelim() "frame-pointer"="all" {
; CHECK-LABEL: test3_nofpelim: ; CHECK-LABEL: test3_nofpelim{{>?}}:
; CHECK: ldr [[TEMP:r[0-7]]], ; CHECK: ldr [[TEMP:r[0-7]]],
; CHECK: add sp, [[TEMP]] ; CHECK: add sp, [[TEMP]]
; CHECK: ldr [[TEMP2:r[0-7]]], ; CHECK: ldr [[TEMP2:r[0-7]]],
; CHECK: add [[TEMP2]], sp ; CHECK: add [[TEMP2]], sp
; CHECK: subs r4, r7, ; CHECK: subs r4, r7,
; CHECK: mov sp, r4 ; CHECK: mov sp, r4
%retval = alloca i32, align 4 %retval = alloca i32, align 4
%tmp = alloca i32, align 4 %tmp = alloca i32, align 4
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llvm/test/CodeGen/X86/2014-08-29-CompactUnwind.ll

; RUN: llc < %s -mtriple x86_64-apple-darwin11 -mcpu corei7 -filetype=obj -o - | llvm-objdump -d -unwind-info -s - | FileCheck %s ; RUN: llc < %s -mtriple x86_64-apple-darwin11 -mcpu corei7 -filetype=obj -o - | llvm-objdump -d -unwind-info -s - | FileCheck %s
; Regression test for http://llvm.org/bugs/show_bug.cgi?id=20800. ; Regression test for http://llvm.org/bugs/show_bug.cgi?id=20800.
; ModuleID = 'asan_report.ii' ; ModuleID = 'asan_report.ii'
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.9.0" target triple = "x86_64-apple-macosx10.9.0"
@.str = private unnamed_addr constant [3 x i8] c"=>\00", align 1 @.str = private unnamed_addr constant [3 x i8] c"=>\00", align 1
@.str1 = private unnamed_addr constant [3 x i8] c" \00", align 1 @.str1 = private unnamed_addr constant [3 x i8] c" \00", align 1
@.str2 = private unnamed_addr constant [6 x i8] c"%s%p:\00", align 1 @.str2 = private unnamed_addr constant [6 x i8] c"%s%p:\00", align 1
; CHECK: ___asan_report_error: ; CHECK: <___asan_report_error>:
; subq instruction starts at 0x0a, so the second byte of the compact encoding ; subq instruction starts at 0x0a, so the second byte of the compact encoding
; (UNWIND_X86_64_FRAMELESS_STACK_SIZE in mach-o/compact_unwind_encoding.h) ; (UNWIND_X86_64_FRAMELESS_STACK_SIZE in mach-o/compact_unwind_encoding.h)
; must be 0x0d. ; must be 0x0d.
; CHECK: {{a:.*subq.*%rsp}} ; CHECK: {{a:.*subq.*%rsp}}
; CHECK: Contents of __compact_unwind section ; CHECK: Contents of __compact_unwind section
; CHECK: ___asan_report_error ; CHECK: ___asan_report_error
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llvm/test/CodeGen/X86/callbr-asm-obj-file.ll

; RUN: llc < %s -mtriple=x86_64-linux-gnu -filetype=obj -o - \ ; RUN: llc < %s -mtriple=x86_64-linux-gnu -filetype=obj -o - \
; RUN: | llvm-objdump -triple x86_64-linux-gnu -d - \ ; RUN: | llvm-objdump -triple x86_64-linux-gnu -d - \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
; CHECK: 0000000000000000 test1: ; CHECK: 0000000000000000 <test1>:
; CHECK-NEXT: 0: 74 00 je 0 <test1+0x2> ; CHECK-NEXT: 0: 74 00 je 0 <test1+0x2>
; CHECK-NEXT: 2: c3 retq ; CHECK-NEXT: 2: c3 retq
define void @test1() { define void @test1() {
entry: entry:
callbr void asm sideeffect "je ${0:l}", "X,~{dirflag},~{fpsr},~{flags}"(i8* blockaddress(@test1, %a.b.normal.jump)) callbr void asm sideeffect "je ${0:l}", "X,~{dirflag},~{fpsr},~{flags}"(i8* blockaddress(@test1, %a.b.normal.jump))
to label %asm.fallthrough [label %a.b.normal.jump] to label %asm.fallthrough [label %a.b.normal.jump]
asm.fallthrough: asm.fallthrough:
ret void ret void
a.b.normal.jump: a.b.normal.jump:
ret void ret void
} }

llvm/test/CodeGen/X86/patchable-prologue.ll

; RUN: llc -verify-machineinstrs -filetype=obj -o - -mtriple=x86_64-apple-macosx < %s | llvm-objdump -triple x86_64-apple-macosx -disassemble - | FileCheck %s ; RUN: llc -verify-machineinstrs -filetype=obj -o - -mtriple=x86_64-apple-macosx < %s | llvm-objdump -triple x86_64-apple-macosx -disassemble - | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=x86_64-apple-macosx < %s | FileCheck %s --check-prefix=CHECK-ALIGN ; RUN: llc -verify-machineinstrs -mtriple=x86_64-apple-macosx < %s | FileCheck %s --check-prefix=CHECK-ALIGN
declare void @callee(i64*) declare void @callee(i64*)
define void @f0() "patchable-function"="prologue-short-redirect" { define void @f0() "patchable-function"="prologue-short-redirect" {
; CHECK-LABEL: _f0: ; CHECK-LABEL: _f0{{>?}}:
; CHECK-NEXT: 66 90 nop ; CHECK-NEXT: 66 90 nop
; CHECK-ALIGN: .p2align 4, 0x90 ; CHECK-ALIGN: .p2align 4, 0x90
; CHECK-ALIGN: _f0: ; CHECK-ALIGN: _f0:
ret void ret void
} }
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; CHECK-ALIGN: .p2align 4, 0x90 ; CHECK-ALIGN: .p2align 4, 0x90
; CHECK-ALIGN: _f3: ; CHECK-ALIGN: _f3:
ret void ret void
} }
; This testcase happens to produce a KILL instruction at the beginning of the ; This testcase happens to produce a KILL instruction at the beginning of the
; first basic block. In this case the 2nd instruction should be turned into a ; first basic block. In this case the 2nd instruction should be turned into a
; patchable one. ; patchable one.
; CHECK-LABEL: f4: ; CHECK-LABEL: f4{{>?}}:
; CHECK-NEXT: 8b 0c 37 movl (%rdi,%rsi), %ecx ; CHECK-NEXT: 8b 0c 37 movl (%rdi,%rsi), %ecx
define i32 @f4(i8* %arg1, i64 %arg2, i32 %arg3) "patchable-function"="prologue-short-redirect" { define i32 @f4(i8* %arg1, i64 %arg2, i32 %arg3) "patchable-function"="prologue-short-redirect" {
bb: bb:
%tmp10 = getelementptr i8, i8* %arg1, i64 %arg2 %tmp10 = getelementptr i8, i8* %arg1, i64 %arg2
%tmp11 = bitcast i8* %tmp10 to i32* %tmp11 = bitcast i8* %tmp10 to i32*
%tmp12 = load i32, i32* %tmp11, align 4 %tmp12 = load i32, i32* %tmp11, align 4
fence acquire fence acquire
%tmp13 = add i32 %tmp12, %arg3 %tmp13 = add i32 %tmp12, %arg3
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llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll

Show All 12 Lines
; READOBJ-RELOCS-NEXT: 0x20 R_RISCV_SUB32 - 0x0 ; READOBJ-RELOCS-NEXT: 0x20 R_RISCV_SUB32 - 0x0
; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_line { ; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_line {
; READOBJ-RELOCS: 0x5A R_RISCV_ADD16 - 0x0 ; READOBJ-RELOCS: 0x5A R_RISCV_ADD16 - 0x0
; READOBJ-RELOCS-NEXT: 0x5A R_RISCV_SUB16 - 0x0 ; READOBJ-RELOCS-NEXT: 0x5A R_RISCV_SUB16 - 0x0
; Check that we can print the source, even with relocations. ; Check that we can print the source, even with relocations.
; OBJDUMP-SOURCE: Disassembly of section .text: ; OBJDUMP-SOURCE: Disassembly of section .text:
; OBJDUMP-SOURCE-EMPTY: ; OBJDUMP-SOURCE-EMPTY:
; OBJDUMP-SOURCE-NEXT: 00000000 main: ; OBJDUMP-SOURCE-NEXT: 00000000 <main>:
; OBJDUMP-SOURCE: ; { ; OBJDUMP-SOURCE: ; {
; OBJDUMP-SOURCE: ; return 0; ; OBJDUMP-SOURCE: ; return 0;
; Check that we correctly dump the DWARF info, even with relocations. ; Check that we correctly dump the DWARF info, even with relocations.
; DWARF-DUMP: DW_AT_name ("dwarf-riscv-relocs.c") ; DWARF-DUMP: DW_AT_name ("dwarf-riscv-relocs.c")
; DWARF-DUMP: DW_AT_comp_dir (".") ; DWARF-DUMP: DW_AT_comp_dir (".")
; DWARF-DUMP: DW_AT_name ("main") ; DWARF-DUMP: DW_AT_name ("main")
; DWARF-DUMP: DW_AT_decl_file ("{{.*}}dwarf-riscv-relocs.c") ; DWARF-DUMP: DW_AT_decl_file ("{{.*}}dwarf-riscv-relocs.c")
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llvm/test/LTO/Resolution/X86/asm-output.ll

; Test the ability to emit assembly code from the resolution-based LTO API ; Test the ability to emit assembly code from the resolution-based LTO API
; ;
; RUN: llvm-as < %s > %t1.bc ; RUN: llvm-as < %s > %t1.bc
; ;
; RUN: llvm-lto2 run -filetype=asm -r %t1.bc,main,px -o %t2 %t1.bc ; RUN: llvm-lto2 run -filetype=asm -r %t1.bc,main,px -o %t2 %t1.bc
; RUN: FileCheck --check-prefix=ASM %s < %t2.0 ; RUN: FileCheck --check-prefix=ASM %s < %t2.0
; RUN: llvm-lto2 run -filetype=obj -r %t1.bc,main,px -o %t2 %t1.bc ; RUN: llvm-lto2 run -filetype=obj -r %t1.bc,main,px -o %t2 %t1.bc
; RUN: llvm-objdump -d %t2.0 | FileCheck --check-prefix=ASM %s ; RUN: llvm-objdump -d %t2.0 | FileCheck --check-prefix=ASM %s
; ;
; ASM: main: ; ASM: main
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define i32 @main() { define i32 @main() {
entry: entry:
ret i32 23 ret i32 23
} }

llvm/test/LTO/Resolution/X86/not-prevailing-alias.ll

; Test to ensure that dead alias are dropped by converting to a declaration ; Test to ensure that dead alias are dropped by converting to a declaration
; RUN: opt -module-summary %s -o %t1.bc ; RUN: opt -module-summary %s -o %t1.bc
; RUN: llvm-lto2 run %t1.bc -r %t1.bc,barAlias,x \ ; RUN: llvm-lto2 run %t1.bc -r %t1.bc,barAlias,x \
; RUN: -r %t1.bc,bar,x -r %t1.bc,zed,px \ ; RUN: -r %t1.bc,bar,x -r %t1.bc,zed,px \
; RUN: -r %t1.bc,var,x -r %t1.bc,varAlias,x \ ; RUN: -r %t1.bc,var,x -r %t1.bc,varAlias,x \
; RUN: -o %t2.o -save-temps ; RUN: -o %t2.o -save-temps
; Check that bar and barAlias were dropped to declarations ; Check that bar and barAlias were dropped to declarations
; RUN: llvm-dis %t2.o.1.1.promote.bc -o - | FileCheck %s --check-prefix=DROP ; RUN: llvm-dis %t2.o.1.1.promote.bc -o - | FileCheck %s --check-prefix=DROP
; DROP-DAG: declare void @bar() ; DROP-DAG: declare void @bar()
; DROP-DAG: declare void @barAlias() ; DROP-DAG: declare void @barAlias()
; DROP-DAG: @var = external global i32 ; DROP-DAG: @var = external global i32
; DROP-DAG: @varAlias = external global i32 ; DROP-DAG: @varAlias = external global i32
; Check that 'barAlias' and 'varAlias' were not inlined. ; Check that 'barAlias' and 'varAlias' were not inlined.
; RUN: llvm-objdump -d %t2.o.1 | FileCheck %s ; RUN: llvm-objdump -d %t2.o.1 | FileCheck %s
; CHECK: zed: ; CHECK: <zed>:
; CHECK-NEXT: {{.*}} pushq ; CHECK-NEXT: {{.*}} pushq
; CHECK-NEXT: {{.*}} callq 0 ; CHECK-NEXT: {{.*}} callq 0
; CHECK-NEXT: movq (%rip), %rax ; CHECK-NEXT: movq (%rip), %rax
; Check that 'barAlias' and 'varAlias' produced as undefined. ; Check that 'barAlias' and 'varAlias' produced as undefined.
; RUN: llvm-readelf --symbols %t2.o.1 | FileCheck %s --check-prefix=SYMBOLS ; RUN: llvm-readelf --symbols %t2.o.1 | FileCheck %s --check-prefix=SYMBOLS
; SYMBOLS: NOTYPE GLOBAL DEFAULT UND barAlias ; SYMBOLS: NOTYPE GLOBAL DEFAULT UND barAlias
; SYMBOLS: NOTYPE GLOBAL DEFAULT UND varAlias ; SYMBOLS: NOTYPE GLOBAL DEFAULT UND varAlias
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llvm/test/LTO/Resolution/X86/not-prevailing-variables.ll

; RUN: opt -module-summary %s -o %t1.o ; RUN: opt -module-summary %s -o %t1.o
; RUN: llvm-lto2 run -save-temps -o %t2.o %t1.o \ ; RUN: llvm-lto2 run -save-temps -o %t2.o %t1.o \
; RUN: -r %t1.o,testVar1,plx -r %t1.o,testVar2,plx \ ; RUN: -r %t1.o,testVar1,plx -r %t1.o,testVar2,plx \
; RUN: -r %t1.o,var1,pl -r %t1.o,var2,lx ; RUN: -r %t1.o,var1,pl -r %t1.o,var2,lx
; Test contains two retainedNodes: var1 and var2. ; Test contains two retainedNodes: var1 and var2.
; var2 is not prevailing and here we check it is not inlined. ; var2 is not prevailing and here we check it is not inlined.
; Check 'var2' was not inlined. ; Check 'var2' was not inlined.
; RUN: llvm-objdump -d %t2.o.1 | FileCheck %s ; RUN: llvm-objdump -d %t2.o.1 | FileCheck %s
; CHECK: testVar1: ; CHECK: <testVar1>:
; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: movl $10, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK: testVar2: ; CHECK: <testVar2>:
; CHECK-NEXT: movl (%rip), %eax ; CHECK-NEXT: movl (%rip), %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; Check 'var2' is undefined. ; Check 'var2' is undefined.
; RUN: llvm-readelf --symbols %t2.o.1 | FileCheck %s --check-prefix=UND ; RUN: llvm-readelf --symbols %t2.o.1 | FileCheck %s --check-prefix=UND
; UND: NOTYPE GLOBAL DEFAULT UND var2 ; UND: NOTYPE GLOBAL DEFAULT UND var2
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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llvm/test/LTO/Resolution/X86/not-prevailing.ll

; RUN: opt -module-summary %s -o %t1.o ; RUN: opt -module-summary %s -o %t1.o
; RUN: opt -module-summary -o %t2.o %S/Inputs/not-prevailing.ll ; RUN: opt -module-summary -o %t2.o %S/Inputs/not-prevailing.ll
; RUN: llvm-lto2 run -o %t3.o %t1.o %t2.o -r %t1.o,foo,x -r %t1.o,zed,px -r %t1.o,bar,x \ ; RUN: llvm-lto2 run -o %t3.o %t1.o %t2.o -r %t1.o,foo,x -r %t1.o,zed,px -r %t1.o,bar,x \
; RUN: -r %t2.o,bar,x -save-temps ; RUN: -r %t2.o,bar,x -save-temps
; Check that 'foo' and 'bar' were not inlined. ; Check that 'foo' and 'bar' were not inlined.
; CHECK: zed: ; CHECK: <zed>:
; CHECK-NEXT: {{.*}} pushq %rbx ; CHECK-NEXT: {{.*}} pushq %rbx
; CHECK-NEXT: {{.*}} callq 0 <zed+0x6> ; CHECK-NEXT: {{.*}} callq 0 <zed+0x6>
; CHECK-NEXT: {{.*}} movl %eax, %ebx ; CHECK-NEXT: {{.*}} movl %eax, %ebx
; CHECK-NEXT: {{.*}} callq 0 <zed+0xd> ; CHECK-NEXT: {{.*}} callq 0 <zed+0xd>
; CHECK-NEXT: {{.*}} movl %ebx, %eax ; CHECK-NEXT: {{.*}} movl %ebx, %eax
; CHECK-NEXT: {{.*}} popq %rbx ; CHECK-NEXT: {{.*}} popq %rbx
; CHECK-NEXT: {{.*}} retq ; CHECK-NEXT: {{.*}} retq
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llvm/test/LTO/X86/codemodel-1.ll

; RUN: llvm-as %s -o %t.o ; RUN: llvm-as %s -o %t.o
; RUN: llvm-lto2 run -r %t.o,_start,px %t.o -o %t.s ; RUN: llvm-lto2 run -r %t.o,_start,px %t.o -o %t.s
; RUN: llvm-objdump -d %t.s.0 | FileCheck %s --check-prefix=CHECK-SMALL ; RUN: llvm-objdump -d %t.s.0 | FileCheck %s --check-prefix=CHECK-SMALL
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
!llvm.module.flags = !{!0, !1} !llvm.module.flags = !{!0, !1}
!0 = !{i32 1, !"wchar_size", i32 4} !0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"Code Model", i32 1} !1 = !{i32 1, !"Code Model", i32 1}
@data = internal constant [0 x i32] [] @data = internal constant [0 x i32] []
define i32* @_start() nounwind readonly { define i32* @_start() nounwind readonly {
entry: entry:
; CHECK-SMALL-LABEL: _start: ; CHECK-SMALL-LABEL: <_start>:
; CHECK-SMALL: leaq (%rip), %rax ; CHECK-SMALL: leaq (%rip), %rax
ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0) ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0)
} }

llvm/test/LTO/X86/codemodel-2.ll

; RUN: llvm-as %s -o %t.o ; RUN: llvm-as %s -o %t.o
; RUN: llvm-lto2 run -r %t.o,_start,px %t.o -o %t.s ; RUN: llvm-lto2 run -r %t.o,_start,px %t.o -o %t.s
; RUN: llvm-objdump -d %t.s.0 | FileCheck %s --check-prefix=CHECK-LARGE ; RUN: llvm-objdump -d %t.s.0 | FileCheck %s --check-prefix=CHECK-LARGE
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
!llvm.module.flags = !{!0, !1} !llvm.module.flags = !{!0, !1}
!0 = !{i32 1, !"wchar_size", i32 4} !0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"Code Model", i32 4} !1 = !{i32 1, !"Code Model", i32 4}
@data = internal constant [0 x i32] [] @data = internal constant [0 x i32] []
define i32* @_start() nounwind readonly { define i32* @_start() nounwind readonly {
entry: entry:
; CHECK-LARGE-LABEL: _start: ; CHECK-LARGE-LABEL: <_start>:
; CHECK-LARGE: movabsq $0, %rax ; CHECK-LARGE: movabsq $0, %rax
ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0) ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0)
} }

llvm/test/LTO/X86/llvm-lto-output.ll

; Test the various output formats of the llvm-lto utility ; Test the various output formats of the llvm-lto utility
; ;
; RUN: llvm-as < %s > %t1 ; RUN: llvm-as < %s > %t1
; ;
; RUN: llvm-lto -exported-symbol=main -save-merged-module -filetype=asm -o %t2 %t1 ; RUN: llvm-lto -exported-symbol=main -save-merged-module -filetype=asm -o %t2 %t1
; RUN: llvm-dis -o - %t2.merged.bc | FileCheck %s ; RUN: llvm-dis -o - %t2.merged.bc | FileCheck %s
; CHECK: @main() ; CHECK: @main()
; RUN: FileCheck --check-prefix=ASM %s < %t2 ; RUN: FileCheck --check-prefix=ASM %s < %t2
; RUN: llvm-lto -exported-symbol=main -filetype=obj -o %t2 %t1 ; RUN: llvm-lto -exported-symbol=main -filetype=obj -o %t2 %t1
; RUN: llvm-objdump -d %t2 | FileCheck --check-prefix=ASM %s ; RUN: llvm-objdump -d %t2 | FileCheck --check-prefix=ASM %s
; ASM: main: ; ASM: main{{>?}}:
; ;
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define i32 @main() { define i32 @main() {
entry: entry:
ret i32 23 ret i32 23
} }

llvm/test/MC/AArch64/label-arithmetic-elf.s

// RUN: llvm-mc -triple aarch64-elf -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s // RUN: llvm-mc -triple aarch64-elf -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s
start: start:
.space 8 .space 8
end: end:
// CHECK-LABEL: end: // CHECK-LABEL: <end>:
adds w0, w1, #(end - start) adds w0, w1, #(end - start)
adds x0, x1, #(end - start) adds x0, x1, #(end - start)
add w0, w1, #(end - start) add w0, w1, #(end - start)
add x0, x1, #(end - start) add x0, x1, #(end - start)
cmp w0, #(end - start) cmp w0, #(end - start)
cmp x0, #(end - start) cmp x0, #(end - start)
sub w0, w1, #(end - start) sub w0, w1, #(end - start)
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
.Lprivate2: .Lprivate2:
add w0, w1, #(.Lprivate2 - .Lprivate1) add w0, w1, #(.Lprivate2 - .Lprivate1)
cmp w0, #(.Lprivate2 - .Lprivate1) cmp w0, #(.Lprivate2 - .Lprivate1)
// CHECK: add w0, w1, #16 // CHECK: add w0, w1, #16
// CHECK: cmp w0, #16 // CHECK: cmp w0, #16
.type foo, @function .type foo, @function
foo: foo:
// CHECK-LABEL: foo: // CHECK-LABEL: <foo>:
add w0, w1, #(foo - .Lprivate2) add w0, w1, #(foo - .Lprivate2)
cmp w0, #(foo - .Lprivate2) cmp w0, #(foo - .Lprivate2)
// CHECK: add w0, w1, #8 // CHECK: add w0, w1, #8
// CHECK: cmp w0, #8 // CHECK: cmp w0, #8
ret ret
.type goo, @function .type goo, @function
goo: goo:
// CHECK-LABEL: goo: // CHECK-LABEL: <goo>:
add w0, w1, #(goo - foo) add w0, w1, #(goo - foo)
cmp w0, #(goo - foo) cmp w0, #(goo - foo)
// CHECK: add w0, w1, #12 // CHECK: add w0, w1, #12
// CHECK: cmp w0, #12 // CHECK: cmp w0, #12
add w0, w1, #(. - goo) add w0, w1, #(. - goo)
cmp w0, #(. - goo) cmp w0, #(. - goo)
// CHECK: add w0, w1, #8 // CHECK: add w0, w1, #8
// CHECK: cmp w0, #12 // CHECK: cmp w0, #12
ret ret

llvm/test/MC/AMDGPU/labels-branch-gfx9.s

// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s --check-prefix=BIN // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
loop_start: loop_start:
s_call_b64 s[10:11], loop_end s_call_b64 s[10:11], loop_end
// GFX9: s_call_b64 s[10:11], loop_end ; encoding: [A,A,0x8a,0xba] // GFX9: s_call_b64 s[10:11], loop_end ; encoding: [A,A,0x8a,0xba]
// GFX9-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br // GFX9-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
// BIN: loop_start: // BIN: <loop_start>:
// BIN-NEXT: s_call_b64 s[10:11], loop_end // 000000000000: BA8A0001 // BIN-NEXT: s_call_b64 s[10:11], loop_end // 000000000000: BA8A0001
s_call_b64 s[10:11], loop_start s_call_b64 s[10:11], loop_start
// GFX9: s_call_b64 s[10:11], loop_start ; encoding: [A,A,0x8a,0xba] // GFX9: s_call_b64 s[10:11], loop_start ; encoding: [A,A,0x8a,0xba]
// GFX9-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br // GFX9-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
// BIN: s_call_b64 s[10:11], loop_start // 000000000004: BA8AFFFE // BIN: s_call_b64 s[10:11], loop_start // 000000000004: BA8AFFFE
// BIN: loop_end: // BIN: <loop_end>:
loop_end: loop_end:
s_nop 0 s_nop 0

llvm/test/MC/AMDGPU/labels-branch.s

// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI // RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objdump -disassemble -mcpu=fiji - | FileCheck %s --check-prefix=BIN // RUN: llvm-mc -arch=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objdump -disassemble -mcpu=fiji - | FileCheck %s --check-prefix=BIN
loop_start: loop_start:
s_branch loop_start s_branch loop_start
// VI: s_branch loop_start ; encoding: [A,A,0x82,0xbf] // VI: s_branch loop_start ; encoding: [A,A,0x82,0xbf]
// VI-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br // VI-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
// BIN: loop_start: // BIN: <loop_start>:
// BIN-NEXT: s_branch loop_start // 000000000000: BF82FFFF // BIN-NEXT: s_branch loop_start // 000000000000: BF82FFFF
s_branch loop_end s_branch loop_end
// VI: s_branch loop_end ; encoding: [A,A,0x82,0xbf] // VI: s_branch loop_end ; encoding: [A,A,0x82,0xbf]
// VI-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br // VI-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
// BIN: s_branch loop_end // 000000000004: BF820000 // BIN: s_branch loop_end // 000000000004: BF820000
// BIN: loop_end: // BIN: <loop_end>:
loop_end: loop_end:
s_branch gds s_branch gds
// VI: s_branch gds ; encoding: [A,A,0x82,0xbf] // VI: s_branch gds ; encoding: [A,A,0x82,0xbf]
// VI-NEXT: ; fixup A - offset: 0, value: gds, kind: fixup_si_sopp_br // VI-NEXT: ; fixup A - offset: 0, value: gds, kind: fixup_si_sopp_br
// BIN: s_branch gds // 000000000008: BF820000 // BIN: s_branch gds // 000000000008: BF820000
// BIN: gds: // BIN: <gds>:
gds: gds:
s_nop 0 s_nop 0

llvm/test/MC/ARM/arm-macho-calls.s

@ RUN: llvm-mc -triple armv7-apple-ios -filetype=obj -o %t %s @ RUN: llvm-mc -triple armv7-apple-ios -filetype=obj -o %t %s
@ RUN: llvm-objdump -d -r %t | FileCheck %s @ RUN: llvm-objdump -d -r %t | FileCheck %s
@ CHECK: _func: @ CHECK: <_func>:
@ CHECK: bl #0 <_func+0x8> @ CHECK: bl #0 <_func+0x8>
@ CHECK: ARM_RELOC_BR24 __text @ CHECK: ARM_RELOC_BR24 __text
@ CHECK: bl #-12 <_func> @ CHECK: bl #-12 <_func>
@ CHECK: ARM_RELOC_BR24 _elsewhere @ CHECK: ARM_RELOC_BR24 _elsewhere
.global _func .global _func
_func: _func:
bl Llocal_symbol bl Llocal_symbol
bl _elsewhere bl _elsewhere
Llocal_symbol: Llocal_symbol:
bx lr bx lr
.global _elsewhere .global _elsewhere
_elsewhere: _elsewhere:
bx lr bx lr

llvm/test/MC/ARM/coff-relocations.s

@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ @ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \
@ RUN: | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-RELOCATION @ RUN: | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-RELOCATION
@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ @ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \
@ RUN: | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-ENCODING @ RUN: | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-ENCODING
.syntax unified .syntax unified
.text .text
.thumb .thumb
.global target .global target
.thumb_func .thumb_func
branch24t_0: branch24t_0:
b target b target
@ CHECK-ENCODING-LABEL: branch24t_0: @ CHECK-ENCODING-LABEL: <branch24t_0>:
@ CHECK-ENCODING-NEXT: b.w #0 @ CHECK-ENCODING-NEXT: b.w #0
.thumb_func .thumb_func
branch24t_1: branch24t_1:
bl target bl target
@ CHECK-ENCODING-LABEL: branch24t_1: @ CHECK-ENCODING-LABEL: <branch24t_1>:
@ CHECK-ENCODING-NEXR: bl #0 @ CHECK-ENCODING-NEXR: bl #0
.thumb_func .thumb_func
branch20t: branch20t:
bcc target bcc target
@ CHECK-ENCODING-LABEL: branch20t: @ CHECK-ENCODING-LABEL: <branch20t>:
@ CHECK-ENCODING-NEXT: blo.w #0 @ CHECK-ENCODING-NEXT: blo.w #0
.thumb_func .thumb_func
blx23t: blx23t:
blx target blx target
@ CHECK-ENCODING-LABEL: blx23t: @ CHECK-ENCODING-LABEL: <blx23t>:
@ CHECK-ENCODING-NEXT: blx #0 @ CHECK-ENCODING-NEXT: blx #0
.thumb_func .thumb_func
mov32t: mov32t:
movw r0, :lower16:target movw r0, :lower16:target
movt r0, :upper16:target movt r0, :upper16:target
blx r0 blx r0
@ CHECK-ENCODING-LABEL: mov32t: @ CHECK-ENCODING-LABEL: <mov32t>:
@ CHECK-ENCODING-NEXT: movw r0, #0 @ CHECK-ENCODING-NEXT: movw r0, #0
@ CHECK-ENCODING-NEXT: movt r0, #0 @ CHECK-ENCODING-NEXT: movt r0, #0
@ CHECK-ENCODING-NEXT: blx r0 @ CHECK-ENCODING-NEXT: blx r0
.thumb_func .thumb_func
addr32: addr32:
ldr r0, .Laddr32 ldr r0, .Laddr32
bx r0 bx r0
trap trap
.Laddr32: .Laddr32:
.long target .long target
@ CHECK-ENCODING-LABEL: addr32: @ CHECK-ENCODING-LABEL: <addr32>:
@ CHECK-ENCODING-NEXT: ldr r0, [pc, #4] @ CHECK-ENCODING-NEXT: ldr r0, [pc, #4]
@ CHECK-ENCODING-NEXT: bx r0 @ CHECK-ENCODING-NEXT: bx r0
@ CHECK-ENCODING-NEXT: trap @ CHECK-ENCODING-NEXT: trap
@ CHECK-ENCODING-NEXT: movs r0, r0 @ CHECK-ENCODING-NEXT: movs r0, r0
@ CHECK-ENCODING-NEXT: movs r0, r0 @ CHECK-ENCODING-NEXT: movs r0, r0
.thumb_func .thumb_func
addr32nb: addr32nb:
ldr r0, .Laddr32nb ldr r0, .Laddr32nb
bx r0 bx r0
trap trap
.Laddr32nb: .Laddr32nb:
.long target(imgrel) .long target(imgrel)
@ CHECK-ENCODING-LABEL: addr32nb: @ CHECK-ENCODING-LABEL: <addr32nb>:
@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4] @ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]
@ CHECK-ENCODING-NEXT: bx r0 @ CHECK-ENCODING-NEXT: bx r0
@ CHECK-ENCODING-NEXT: trap @ CHECK-ENCODING-NEXT: trap
@ CHECK-ENCODING-NEXT: movs r0, r0 @ CHECK-ENCODING-NEXT: movs r0, r0
@ CHECK-ENCODING-NEXT: movs r0, r0 @ CHECK-ENCODING-NEXT: movs r0, r0
.thumb_func .thumb_func
secrel: secrel:
ldr r0, .Lsecrel ldr r0, .Lsecrel
bx r0 bx r0
trap trap
.Lsecrel: .Lsecrel:
.long target(secrel32) .long target(secrel32)
@ CHECK-ENCODING-LABEL: secrel: @ CHECK-ENCODING-LABEL: <secrel>:
@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4] @ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]
@ CHECK-ENCODING-NEXT: bx r0 @ CHECK-ENCODING-NEXT: bx r0
@ CHECK-ENCODING-NEXT: trap @ CHECK-ENCODING-NEXT: trap
@ CHECK-ENCODING-NEXT: movs r0, r0 @ CHECK-ENCODING-NEXT: movs r0, r0
@ CHECK-ENCODING-NEXT: movs r0, r0 @ CHECK-ENCODING-NEXT: movs r0, r0
@ CHECK-RELOCATION: Relocations [ @ CHECK-RELOCATION: Relocations [
@ CHECK-RELOCATION: Section (1) .text { @ CHECK-RELOCATION: Section (1) .text {
Show All 11 Lines

llvm/test/MC/ARM/elf-movt.s

Show All 25 Lines
@ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+8)) @ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+8))
@ ASM: movw r0, :lower16:(extern_symbol+1234) @ ASM: movw r0, :lower16:(extern_symbol+1234)
@ ASM-NEXT: movt r0, :upper16:(extern_symbol+1234) @ ASM-NEXT: movt r0, :upper16:(extern_symbol+1234)
@ ASM: movw r0, :lower16:((foo-bar)+1234) @ ASM: movw r0, :lower16:((foo-bar)+1234)
@ ASM-NEXT: movt r0, :upper16:((foo-bar)+1234) @ ASM-NEXT: movt r0, :upper16:((foo-bar)+1234)
@OBJ: Disassembly of section .text: @OBJ: Disassembly of section .text:
@OBJ-EMPTY: @OBJ-EMPTY:
@OBJ-NEXT: barf: @OBJ-NEXT: <barf>:
@OBJ-NEXT: 0: f0 0f 0f e3 movw r0, #65520 @OBJ-NEXT: 0: f0 0f 0f e3 movw r0, #65520
@OBJ-NEXT: 00000000: R_ARM_MOVW_PREL_NC GOT @OBJ-NEXT: 00000000: R_ARM_MOVW_PREL_NC GOT
@OBJ-NEXT: 4: f4 0f 4f e3 movt r0, #65524 @OBJ-NEXT: 4: f4 0f 4f e3 movt r0, #65524
@OBJ-NEXT: 00000004: R_ARM_MOVT_PREL GOT @OBJ-NEXT: 00000004: R_ARM_MOVT_PREL GOT
@OBJ-NEXT: 8: d2 04 00 e3 movw r0, #1234 @OBJ-NEXT: 8: d2 04 00 e3 movw r0, #1234
@OBJ-NEXT: 00000008: R_ARM_MOVW_ABS_NC extern_symbol @OBJ-NEXT: 00000008: R_ARM_MOVW_ABS_NC extern_symbol
@OBJ-NEXT: c: d2 04 40 e3 movt r0, #1234 @OBJ-NEXT: c: d2 04 40 e3 movt r0, #1234
@OBJ-NEXT: 0000000c: R_ARM_MOVT_ABS extern_symbol @OBJ-NEXT: 0000000c: R_ARM_MOVT_ABS extern_symbol
@OBJ-NEXT: 10: d2 04 00 e3 movw r0, #1234 @OBJ-NEXT: 10: d2 04 00 e3 movw r0, #1234
@OBJ-NEXT: 14: 00 00 40 e3 movt r0, #0 @OBJ-NEXT: 14: 00 00 40 e3 movt r0, #0
@THUMB: Disassembly of section .text: @THUMB: Disassembly of section .text:
@THUMB-EMPTY: @THUMB-EMPTY:
@THUMB-NEXT: barf: @THUMB-NEXT: <barf>:
@THUMB-NEXT: 0: 4f f6 f0 70 movw r0, #65520 @THUMB-NEXT: 0: 4f f6 f0 70 movw r0, #65520
@THUMB-NEXT: 00000000: R_ARM_THM_MOVW_PREL_NC GOT @THUMB-NEXT: 00000000: R_ARM_THM_MOVW_PREL_NC GOT
@THUMB-NEXT: 4: cf f6 f4 70 movt r0, #65524 @THUMB-NEXT: 4: cf f6 f4 70 movt r0, #65524
@THUMB-NEXT: 00000004: R_ARM_THM_MOVT_PREL GOT @THUMB-NEXT: 00000004: R_ARM_THM_MOVT_PREL GOT
@THUMB-NEXT: 8: 40 f2 d2 40 movw r0, #1234 @THUMB-NEXT: 8: 40 f2 d2 40 movw r0, #1234
@THUMB-NEXT: 00000008: R_ARM_THM_MOVW_ABS_NC extern_symbol @THUMB-NEXT: 00000008: R_ARM_THM_MOVW_ABS_NC extern_symbol
@THUMB-NEXT: c: c0 f2 d2 40 movt r0, #1234 @THUMB-NEXT: c: c0 f2 d2 40 movt r0, #1234
@THUMB-NEXT: 0000000c: R_ARM_THM_MOVT_ABS extern_symbol @THUMB-NEXT: 0000000c: R_ARM_THM_MOVT_ABS extern_symbol
@THUMB-NEXT: 10: 40 f2 d2 40 movw r0, #1234 @THUMB-NEXT: 10: 40 f2 d2 40 movw r0, #1234
@THUMB-NEXT: 14: c0 f2 00 00 movt r0, #0 @THUMB-NEXT: 14: c0 f2 00 00 movt r0, #0

llvm/test/MC/ARM/sub-expr-imm.s

Show All 9 LinesAES_Te:
.word 1,2,3,4,5,6 .word 1,2,3,4,5,6
.word 1,2,3,4,5,6 .word 1,2,3,4,5,6
.word 1,2,3,4,5,6 .word 1,2,3,4,5,6
.word 1,2,3,4,5,6 .word 1,2,3,4,5,6
.word 1,2,3,4,5,6 .word 1,2,3,4,5,6
.word 1,2,3,4,5,6 .word 1,2,3,4,5,6
.word 1,2,3,4,5,6 .word 1,2,3,4,5,6
.word 1,2,3,4,5,6 .word 1,2,3,4,5,6
@ CHECK: AES_encrypt: @ CHECK: <AES_encrypt>:
AES_encrypt: AES_encrypt:
@ CHECK: sub r10, r3, #264 @ CHECK: sub r10, r3, #264
sub r10,r3,#(AES_encrypt-AES_Te) sub r10,r3,#(AES_encrypt-AES_Te)
@ CHECK: sub r10, r3, #264 @ CHECK: sub r10, r3, #264
sub r10,r3,#(6*11*4) sub r10,r3,#(6*11*4)
Data: Data:
@ CHECK: 08 01 00 00 @ CHECK: 08 01 00 00
.word (AES_encrypt-AES_Te) .word (AES_encrypt-AES_Te)
@ CHECK: 08 01 00 00 @ CHECK: 08 01 00 00
.word (6*11*4) .word (6*11*4)

llvm/test/MC/AVR/relocations-abs.s

; RUN: llvm-mc -filetype=obj -triple=avr %s | llvm-objdump -dr - | FileCheck %s ; RUN: llvm-mc -filetype=obj -triple=avr %s | llvm-objdump -dr - | FileCheck %s
; CHECK: bar: ; CHECK: <bar>:
; CHECK-NEXT: 00 00 nop ; CHECK-NEXT: 00 00 nop
; CHECK-NEXT: R_AVR_16 .text+0x2 ; CHECK-NEXT: R_AVR_16 .text+0x2
bar: bar:
.short 1f .short 1f
1: 1:

llvm/test/MC/BPF/insn-unit.s

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 LinesLlabel0 :
r2 = -r2 // BPF_NEG r2 = -r2 // BPF_NEG
r4 |= r5 // BPF_OR | BPF_X r4 |= r5 // BPF_OR | BPF_X
r5 &= r6 // BPF_AND | BPF_X r5 &= r6 // BPF_AND | BPF_X
r6 <<= r7 // BPF_LSH | BPF_X r6 <<= r7 // BPF_LSH | BPF_X
r7 >>= r8 // BPF_RSH | BPF_X r7 >>= r8 // BPF_RSH | BPF_X
r8 ^= r9 // BPF_XOR | BPF_X r8 ^= r9 // BPF_XOR | BPF_X
r9 = r10 // BPF_MOV | BPF_X r9 = r10 // BPF_MOV | BPF_X
r10 s>>= r0 // BPF_ARSH | BPF_X r10 s>>= r0 // BPF_ARSH | BPF_X
// CHECK:Llabel0: // CHECK: <Llabel0>:
// CHECK: 87 02 00 00 00 00 00 00 r2 = -r2 // CHECK: 87 02 00 00 00 00 00 00 r2 = -r2
// CHECK: 4f 54 00 00 00 00 00 00 r4 |= r5 // CHECK: 4f 54 00 00 00 00 00 00 r4 |= r5
// CHECK: 5f 65 00 00 00 00 00 00 r5 &= r6 // CHECK: 5f 65 00 00 00 00 00 00 r5 &= r6
// CHECK: 6f 76 00 00 00 00 00 00 r6 <<= r7 // CHECK: 6f 76 00 00 00 00 00 00 r6 <<= r7
// CHECK: 7f 87 00 00 00 00 00 00 r7 >>= r8 // CHECK: 7f 87 00 00 00 00 00 00 r7 >>= r8
// CHECK: af 98 00 00 00 00 00 00 r8 ^= r9 // CHECK: af 98 00 00 00 00 00 00 r8 ^= r9
// CHECK: bf a9 00 00 00 00 00 00 r9 = r10 // CHECK: bf a9 00 00 00 00 00 00 r9 = r10
// CHECK: cf 0a 00 00 00 00 00 00 r10 s>>= r0 // CHECK: cf 0a 00 00 00 00 00 00 r10 s>>= r0
Show All 33 Lines

llvm/test/MC/COFF/cv-inline-linetable-unlikely.s

Show All 15 Lines
# } # }
# This test is interesting because the inlined instructions are discontiguous. # This test is interesting because the inlined instructions are discontiguous.
# LLVM's block layout algorithms will put the 'abort' call last, as it is # LLVM's block layout algorithms will put the 'abort' call last, as it is
# considered highly unlikely to execute. This is similar to what it does for # considered highly unlikely to execute. This is similar to what it does for
# calls to __asan_report*, for which it is very important to have an accurate # calls to __asan_report*, for which it is very important to have an accurate
# stack trace. # stack trace.
# ASM: 0000000000000000 g: # ASM: 0000000000000000 <g>:
# ASM-NEXT: 0: 48 83 ec 28 subq $40, %rsp # ASM-NEXT: 0: 48 83 ec 28 subq $40, %rsp
# ASM-NEXT: 4: c7 05 fc ff ff ff 00 00 00 00 movl $0, -4(%rip) # ASM-NEXT: 4: c7 05 fc ff ff ff 00 00 00 00 movl $0, -4(%rip)
# Begin inline loc (matches cv_loc below) # Begin inline loc (matches cv_loc below)
# ASM-NEXT: e: 83 3d ff ff ff ff 00 cmpl $0, -1(%rip) # ASM-NEXT: e: 83 3d ff ff ff ff 00 cmpl $0, -1(%rip)
# ASM-NEXT: 15: 75 0f jne 15 <g+0x26> # ASM-NEXT: 15: 75 0f jne 15 <g+0x26>
# End inline loc # End inline loc
# ASM-NEXT: 17: c7 05 fc ff ff ff 00 00 00 00 movl $0, -4(%rip) # ASM-NEXT: 17: c7 05 fc ff ff ff 00 00 00 00 movl $0, -4(%rip)
# ASM-NEXT: 21: 48 83 c4 28 addq $40, %rsp # ASM-NEXT: 21: 48 83 c4 28 addq $40, %rsp
▲ Show 20 Lines • Show All 168 Lines • Show Last 20 Lines

llvm/test/MC/COFF/cv-inline-linetable.s

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines# %bb.0: # %entry
.cv_loc 0 1 16 5 # t.cpp:16:5 .cv_loc 0 1 16 5 # t.cpp:16:5
addl $7, "?x@@3HC" addl $7, "?x@@3HC"
.cv_loc 0 1 17 1 # t.cpp:17:1 .cv_loc 0 1 17 1 # t.cpp:17:1
popl %eax popl %eax
retl retl
Lfunc_end0: Lfunc_end0:
# Check the disassembly so we have accurate instruction offsets in hex. # Check the disassembly so we have accurate instruction offsets in hex.
# ASM-LABEL: ?baz@@YAXXZ: # ASM-LABEL: <?baz@@YAXXZ>:
# ASM-NEXT: 0: {{.*}} pushl %eax # ASM-NEXT: 0: {{.*}} pushl %eax
# ASM-NEXT: 1: {{.*}} addl $6, 0 # ASM-NEXT: 1: {{.*}} addl $6, 0
# ASM-NEXT: 8: {{.*}} addl $4, 0 # ASM-NEXT: 8: {{.*}} addl $4, 0
# ASM-NEXT: f: {{.*}} movl $1, (%esp) # ASM-NEXT: f: {{.*}} movl $1, (%esp)
# ASM-NEXT: 16: {{.*}} leal (%esp), %eax # ASM-NEXT: 16: {{.*}} leal (%esp), %eax
# ASM-NEXT: 19: {{.*}} addl %eax, 0 # ASM-NEXT: 19: {{.*}} addl %eax, 0
# ASM-NEXT: 1f: {{.*}} addl $2, 0 # ASM-NEXT: 1f: {{.*}} addl $2, 0
# ASM-NEXT: 26: {{.*}} addl $3, 0 # ASM-NEXT: 26: {{.*}} addl $3, 0
▲ Show 20 Lines • Show All 144 Lines • Show Last 20 Lines

llvm/test/MC/COFF/cv-loc-unreachable-2.s

# RUN: llvm-mc %s -triple=i686-pc-win32 -filetype=obj -o %t.obj # RUN: llvm-mc %s -triple=i686-pc-win32 -filetype=obj -o %t.obj
# RUN: llvm-objdump -d %t.obj | FileCheck %s --check-prefix=ASM # RUN: llvm-objdump -d %t.obj | FileCheck %s --check-prefix=ASM
# RUN: llvm-pdbutil dump -il -symbols %t.obj | FileCheck %s --check-prefix=CODEVIEW # RUN: llvm-pdbutil dump -il -symbols %t.obj | FileCheck %s --check-prefix=CODEVIEW
# Based on the other cv-loc-unreachable-2.s, but with other code in the same # Based on the other cv-loc-unreachable-2.s, but with other code in the same
# section afterwards. We had negative label difference assertions when .cv_loc # section afterwards. We had negative label difference assertions when .cv_loc
# bound tightly to the next instruction. # bound tightly to the next instruction.
# ASM: 00000000 _callit: # ASM: 00000000 <_callit>:
# begin inline { # begin inline {
# ASM-NEXT: 0: e8 00 00 00 00 calll 0 <_callit+0x5> # ASM-NEXT: 0: e8 00 00 00 00 calll 0 <_callit+0x5>
# ASM-NEXT: 5: 85 c0 testl %eax, %eax # ASM-NEXT: 5: 85 c0 testl %eax, %eax
# ASM-NEXT: 7: 75 01 jne 1 <_callit+0xa> # ASM-NEXT: 7: 75 01 jne 1 <_callit+0xa>
# } end inline # } end inline
# ASM-NEXT: 9: c3 retl # ASM-NEXT: 9: c3 retl
# begin inline { # begin inline {
# ASM-NEXT: a: 6a 20 pushl $32 # ASM-NEXT: a: 6a 20 pushl $32
▲ Show 20 Lines • Show All 165 Lines • Show Last 20 Lines

llvm/test/MC/COFF/cv-loc-unreachable.s

Show All 11 Lines
# exit(32); # exit(32);
# } # }
# } # }
# void callit() { # void callit() {
# do_exit(); # do_exit();
# } # }
# ASM: 00000000 _callit: # ASM: 00000000 <_callit>:
# begin inline { # begin inline {
# ASM-NEXT: 0: e8 00 00 00 00 calll 0 <_callit+0x5> # ASM-NEXT: 0: e8 00 00 00 00 calll 0 <_callit+0x5>
# ASM-NEXT: 5: 85 c0 testl %eax, %eax # ASM-NEXT: 5: 85 c0 testl %eax, %eax
# ASM-NEXT: 7: 75 01 jne 1 <_callit+0xa> # ASM-NEXT: 7: 75 01 jne 1 <_callit+0xa>
# } end inline # } end inline
# ASM-NEXT: 9: c3 retl # ASM-NEXT: 9: c3 retl
# begin inline { # begin inline {
# ASM-NEXT: a: 6a 20 pushl $32 # ASM-NEXT: a: 6a 20 pushl $32
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llvm/test/MC/ELF/relax-arith.s

// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s
// Test that we correctly relax these instructions into versions that use // Test that we correctly relax these instructions into versions that use
// 16 or 32 bit immediate values. // 16 or 32 bit immediate values.
bar: bar:
// CHECK: Disassembly of section imul: // CHECK: Disassembly of section imul:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: imul: // CHECK-NEXT: <imul>:
// CHECK-NEXT: 0: 66 69 db 00 00 imulw $0, %bx, %bx // CHECK-NEXT: 0: 66 69 db 00 00 imulw $0, %bx, %bx
// CHECK-NEXT: 5: 66 69 1c 25 00 00 00 00 00 00 imulw $0, 0, %bx // CHECK-NEXT: 5: 66 69 1c 25 00 00 00 00 00 00 imulw $0, 0, %bx
// CHECK-NEXT: f: 69 db 00 00 00 00 imull $0, %ebx, %ebx // CHECK-NEXT: f: 69 db 00 00 00 00 imull $0, %ebx, %ebx
// CHECK-NEXT: 15: 69 1c 25 00 00 00 00 00 00 00 00 imull $0, 0, %ebx // CHECK-NEXT: 15: 69 1c 25 00 00 00 00 00 00 00 00 imull $0, 0, %ebx
// CHECK-NEXT: 20: 48 69 db 00 00 00 00 imulq $0, %rbx, %rbx // CHECK-NEXT: 20: 48 69 db 00 00 00 00 imulq $0, %rbx, %rbx
// CHECK-NEXT: 27: 48 69 1c 25 00 00 00 00 00 00 00 00 imulq $0, 0, %rbx // CHECK-NEXT: 27: 48 69 1c 25 00 00 00 00 00 00 00 00 imulq $0, 0, %rbx
.section imul,"x" .section imul,"x"
imul $foo, %bx, %bx imul $foo, %bx, %bx
imul $foo, bar, %bx imul $foo, bar, %bx
imul $foo, %ebx, %ebx imul $foo, %ebx, %ebx
imul $foo, bar, %ebx imul $foo, bar, %ebx
imul $foo, %rbx, %rbx imul $foo, %rbx, %rbx
imul $foo, bar, %rbx imul $foo, bar, %rbx
// CHECK: Disassembly of section and: // CHECK: Disassembly of section and:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: and: // CHECK-NEXT: <and>:
// CHECK-NEXT: 0: 66 81 e3 00 00 andw $0, %bx // CHECK-NEXT: 0: 66 81 e3 00 00 andw $0, %bx
// CHECK-NEXT: 5: 66 81 24 25 00 00 00 00 00 00 andw $0, 0 // CHECK-NEXT: 5: 66 81 24 25 00 00 00 00 00 00 andw $0, 0
// CHECK-NEXT: f: 81 e3 00 00 00 00 andl $0, %ebx // CHECK-NEXT: f: 81 e3 00 00 00 00 andl $0, %ebx
// CHECK-NEXT: 15: 81 24 25 00 00 00 00 00 00 00 00 andl $0, 0 // CHECK-NEXT: 15: 81 24 25 00 00 00 00 00 00 00 00 andl $0, 0
// CHECK-NEXT: 20: 48 81 e3 00 00 00 00 andq $0, %rbx // CHECK-NEXT: 20: 48 81 e3 00 00 00 00 andq $0, %rbx
// CHECK-NEXT: 27: 48 81 24 25 00 00 00 00 00 00 00 00 andq $0, 0 // CHECK-NEXT: 27: 48 81 24 25 00 00 00 00 00 00 00 00 andq $0, 0
.section and,"x" .section and,"x"
and $foo, %bx and $foo, %bx
andw $foo, bar andw $foo, bar
and $foo, %ebx and $foo, %ebx
andl $foo, bar andl $foo, bar
and $foo, %rbx and $foo, %rbx
andq $foo, bar andq $foo, bar
// CHECK: Disassembly of section or: // CHECK: <or>:
// CHECK-EMPTY:
// CHECK-NEXT: or:
// CHECK-NEXT: 0: 66 81 cb 00 00 orw $0, %bx // CHECK-NEXT: 0: 66 81 cb 00 00 orw $0, %bx
// CHECK-NEXT: 5: 66 81 0c 25 00 00 00 00 00 00 orw $0, 0 // CHECK-NEXT: 5: 66 81 0c 25 00 00 00 00 00 00 orw $0, 0
// CHECK-NEXT: f: 81 cb 00 00 00 00 orl $0, %ebx // CHECK-NEXT: f: 81 cb 00 00 00 00 orl $0, %ebx
// CHECK-NEXT: 15: 81 0c 25 00 00 00 00 00 00 00 00 orl $0, 0 // CHECK-NEXT: 15: 81 0c 25 00 00 00 00 00 00 00 00 orl $0, 0
// CHECK-NEXT: 20: 48 81 cb 00 00 00 00 orq $0, %rbx // CHECK-NEXT: 20: 48 81 cb 00 00 00 00 orq $0, %rbx
// CHECK-NEXT: 27: 48 81 0c 25 00 00 00 00 00 00 00 00 orq $0, 0 // CHECK-NEXT: 27: 48 81 0c 25 00 00 00 00 00 00 00 00 orq $0, 0
.section or,"x" .section or,"x"
or $foo, %bx or $foo, %bx
orw $foo, bar orw $foo, bar
or $foo, %ebx or $foo, %ebx
orl $foo, bar orl $foo, bar
or $foo, %rbx or $foo, %rbx
orq $foo, bar orq $foo, bar
// CHECK: Disassembly of section xor: // CHECK: Disassembly of section xor:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: xor: // CHECK-NEXT: <xor>:
// CHECK-NEXT: 0: 66 81 f3 00 00 xorw $0, %bx // CHECK-NEXT: 0: 66 81 f3 00 00 xorw $0, %bx
// CHECK-NEXT: 5: 66 81 34 25 00 00 00 00 00 00 xorw $0, 0 // CHECK-NEXT: 5: 66 81 34 25 00 00 00 00 00 00 xorw $0, 0
// CHECK-NEXT: f: 81 f3 00 00 00 00 xorl $0, %ebx // CHECK-NEXT: f: 81 f3 00 00 00 00 xorl $0, %ebx
// CHECK-NEXT: 15: 81 34 25 00 00 00 00 00 00 00 00 xorl $0, 0 // CHECK-NEXT: 15: 81 34 25 00 00 00 00 00 00 00 00 xorl $0, 0
// CHECK-NEXT: 20: 48 81 f3 00 00 00 00 xorq $0, %rbx // CHECK-NEXT: 20: 48 81 f3 00 00 00 00 xorq $0, %rbx
// CHECK-NEXT: 27: 48 81 34 25 00 00 00 00 00 00 00 00 xorq $0, 0 // CHECK-NEXT: 27: 48 81 34 25 00 00 00 00 00 00 00 00 xorq $0, 0
.section xor,"x" .section xor,"x"
xor $foo, %bx xor $foo, %bx
xorw $foo, bar xorw $foo, bar
xor $foo, %ebx xor $foo, %ebx
xorl $foo, bar xorl $foo, bar
xor $foo, %rbx xor $foo, %rbx
xorq $foo, bar xorq $foo, bar
// CHECK: Disassembly of section add: // CHECK: Disassembly of section add:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: add: // CHECK-NEXT: <add>:
// CHECK-NEXT: 0: 66 81 c3 00 00 addw $0, %bx // CHECK-NEXT: 0: 66 81 c3 00 00 addw $0, %bx
// CHECK-NEXT: 5: 66 81 04 25 00 00 00 00 00 00 addw $0, 0 // CHECK-NEXT: 5: 66 81 04 25 00 00 00 00 00 00 addw $0, 0
// CHECK-NEXT: f: 81 c3 00 00 00 00 addl $0, %ebx // CHECK-NEXT: f: 81 c3 00 00 00 00 addl $0, %ebx
// CHECK-NEXT: 15: 81 04 25 00 00 00 00 00 00 00 00 addl $0, 0 // CHECK-NEXT: 15: 81 04 25 00 00 00 00 00 00 00 00 addl $0, 0
// CHECK-NEXT: 20: 48 81 c3 00 00 00 00 addq $0, %rbx // CHECK-NEXT: 20: 48 81 c3 00 00 00 00 addq $0, %rbx
// CHECK-NEXT: 27: 48 81 04 25 00 00 00 00 00 00 00 00 addq $0, 0 // CHECK-NEXT: 27: 48 81 04 25 00 00 00 00 00 00 00 00 addq $0, 0
.section add,"x" .section add,"x"
add $foo, %bx add $foo, %bx
addw $foo, bar addw $foo, bar
add $foo, %ebx add $foo, %ebx
addl $foo, bar addl $foo, bar
add $foo, %rbx add $foo, %rbx
addq $foo, bar addq $foo, bar
// CHECK: Disassembly of section sub: // CHECK: Disassembly of section sub:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: sub: // CHECK-NEXT: <sub>:
// CHECK-NEXT: 0: 66 81 eb 00 00 subw $0, %bx // CHECK-NEXT: 0: 66 81 eb 00 00 subw $0, %bx
// CHECK-NEXT: 5: 66 81 2c 25 00 00 00 00 00 00 subw $0, 0 // CHECK-NEXT: 5: 66 81 2c 25 00 00 00 00 00 00 subw $0, 0
// CHECK-NEXT: f: 81 eb 00 00 00 00 subl $0, %ebx // CHECK-NEXT: f: 81 eb 00 00 00 00 subl $0, %ebx
// CHECK-NEXT: 15: 81 2c 25 00 00 00 00 00 00 00 00 subl $0, 0 // CHECK-NEXT: 15: 81 2c 25 00 00 00 00 00 00 00 00 subl $0, 0
// CHECK-NEXT: 20: 48 81 eb 00 00 00 00 subq $0, %rbx // CHECK-NEXT: 20: 48 81 eb 00 00 00 00 subq $0, %rbx
// CHECK-NEXT: 27: 48 81 2c 25 00 00 00 00 00 00 00 00 subq $0, 0 // CHECK-NEXT: 27: 48 81 2c 25 00 00 00 00 00 00 00 00 subq $0, 0
.section sub,"x" .section sub,"x"
sub $foo, %bx sub $foo, %bx
subw $foo, bar subw $foo, bar
sub $foo, %ebx sub $foo, %ebx
subl $foo, bar subl $foo, bar
sub $foo, %rbx sub $foo, %rbx
subq $foo, bar subq $foo, bar
// CHECK: Disassembly of section cmp: // CHECK: Disassembly of section cmp:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: cmp: // CHECK-NEXT: <cmp>:
// CHECK-NEXT: 0: 66 81 fb 00 00 cmpw $0, %bx // CHECK-NEXT: 0: 66 81 fb 00 00 cmpw $0, %bx
// CHECK-NEXT: 5: 66 81 3c 25 00 00 00 00 00 00 cmpw $0, 0 // CHECK-NEXT: 5: 66 81 3c 25 00 00 00 00 00 00 cmpw $0, 0
// CHECK-NEXT: f: 81 fb 00 00 00 00 cmpl $0, %ebx // CHECK-NEXT: f: 81 fb 00 00 00 00 cmpl $0, %ebx
// CHECK-NEXT: 15: 81 3c 25 00 00 00 00 00 00 00 00 cmpl $0, 0 // CHECK-NEXT: 15: 81 3c 25 00 00 00 00 00 00 00 00 cmpl $0, 0
// CHECK-NEXT: 20: 48 81 fb 00 00 00 00 cmpq $0, %rbx // CHECK-NEXT: 20: 48 81 fb 00 00 00 00 cmpq $0, %rbx
// CHECK-NEXT: 27: 48 81 3c 25 00 00 00 00 00 00 00 00 cmpq $0, 0 // CHECK-NEXT: 27: 48 81 3c 25 00 00 00 00 00 00 00 00 cmpq $0, 0
.section cmp,"x" .section cmp,"x"
cmp $foo, %bx cmp $foo, %bx
cmpw $foo, bar cmpw $foo, bar
cmp $foo, %ebx cmp $foo, %ebx
cmpl $foo, bar cmpl $foo, bar
cmp $foo, %rbx cmp $foo, %rbx
cmpq $foo, bar cmpq $foo, bar
// CHECK: Disassembly of section push: // CHECK: Disassembly of section push:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: push: // CHECK-NEXT: <push>:
// CHECK-NEXT: 0: 66 68 00 00 pushw $0 // CHECK-NEXT: 0: 66 68 00 00 pushw $0
// CHECK-NEXT: 4: 68 00 00 00 00 pushq $0 // CHECK-NEXT: 4: 68 00 00 00 00 pushq $0
.section push,"x" .section push,"x"
pushw $foo pushw $foo
push $foo push $foo
// CHECK: Disassembly of section adc: // CHECK: Disassembly of section adc:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: adc: // CHECK-NEXT: <adc>:
// CHECK-NEXT: 0: 66 81 d3 00 00 adcw $0, %bx // CHECK-NEXT: 0: 66 81 d3 00 00 adcw $0, %bx
// CHECK-NEXT: 5: 66 81 14 25 00 00 00 00 00 00 adcw $0, 0 // CHECK-NEXT: 5: 66 81 14 25 00 00 00 00 00 00 adcw $0, 0
// CHECK-NEXT: f: 81 d3 00 00 00 00 adcl $0, %ebx // CHECK-NEXT: f: 81 d3 00 00 00 00 adcl $0, %ebx
// CHECK-NEXT: 15: 81 14 25 00 00 00 00 00 00 00 00 adcl $0, 0 // CHECK-NEXT: 15: 81 14 25 00 00 00 00 00 00 00 00 adcl $0, 0
// CHECK-NEXT: 20: 48 81 d3 00 00 00 00 adcq $0, %rbx // CHECK-NEXT: 20: 48 81 d3 00 00 00 00 adcq $0, %rbx
// CHECK-NEXT: 27: 48 81 14 25 00 00 00 00 00 00 00 00 adcq $0, 0 // CHECK-NEXT: 27: 48 81 14 25 00 00 00 00 00 00 00 00 adcq $0, 0
.section adc,"x" .section adc,"x"
adc $foo, %bx adc $foo, %bx
adcw $foo, bar adcw $foo, bar
adc $foo, %ebx adc $foo, %ebx
adcl $foo, bar adcl $foo, bar
adc $foo, %rbx adc $foo, %rbx
adcq $foo, bar adcq $foo, bar
// CHECK: Disassembly of section sbb: // CHECK: Disassembly of section sbb:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: sbb: // CHECK-NEXT: <sbb>:
// CHECK-NEXT: 0: 66 81 db 00 00 sbbw $0, %bx // CHECK-NEXT: 0: 66 81 db 00 00 sbbw $0, %bx
// CHECK-NEXT: 5: 66 81 1c 25 00 00 00 00 00 00 sbbw $0, 0 // CHECK-NEXT: 5: 66 81 1c 25 00 00 00 00 00 00 sbbw $0, 0
// CHECK-NEXT: f: 81 db 00 00 00 00 sbbl $0, %ebx // CHECK-NEXT: f: 81 db 00 00 00 00 sbbl $0, %ebx
// CHECK-NEXT: 15: 81 1c 25 00 00 00 00 00 00 00 00 sbbl $0, 0 // CHECK-NEXT: 15: 81 1c 25 00 00 00 00 00 00 00 00 sbbl $0, 0
// CHECK-NEXT: 20: 48 81 db 00 00 00 00 sbbq $0, %rbx // CHECK-NEXT: 20: 48 81 db 00 00 00 00 sbbq $0, %rbx
// CHECK-NEXT: 27: 48 81 1c 25 00 00 00 00 00 00 00 00 sbbq $0, 0 // CHECK-NEXT: 27: 48 81 1c 25 00 00 00 00 00 00 00 00 sbbq $0, 0
.section sbb,"x" .section sbb,"x"
sbb $foo, %bx sbb $foo, %bx
sbbw $foo, bar sbbw $foo, bar
sbb $foo, %ebx sbb $foo, %ebx
sbbl $foo, bar sbbl $foo, bar
sbb $foo, %rbx sbb $foo, %rbx
sbbq $foo, bar sbbq $foo, bar

llvm/test/MC/ELF/relax-arith2.s

// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s
// Test that we avoid relaxing these instructions and instead generate versions // Test that we avoid relaxing these instructions and instead generate versions
// that use 8-bit immediate values. // that use 8-bit immediate values.
bar: bar:
// CHECK: Disassembly of section imul: // CHECK: Disassembly of section imul:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: imul: // CHECK-NEXT: <imul>:
// CHECK-NEXT: 0: 66 6b db 80 imulw $-128, %bx, %bx // CHECK-NEXT: 0: 66 6b db 80 imulw $-128, %bx, %bx
// CHECK-NEXT: 4: 66 6b 1c 25 00 00 00 00 7f imulw $127, 0, %bx // CHECK-NEXT: 4: 66 6b 1c 25 00 00 00 00 7f imulw $127, 0, %bx
// CHECK-NEXT: d: 6b db 00 imull $0, %ebx, %ebx // CHECK-NEXT: d: 6b db 00 imull $0, %ebx, %ebx
// CHECK-NEXT: 10: 6b 1c 25 00 00 00 00 01 imull $1, 0, %ebx // CHECK-NEXT: 10: 6b 1c 25 00 00 00 00 01 imull $1, 0, %ebx
// CHECK-NEXT: 18: 48 6b db ff imulq $-1, %rbx, %rbx // CHECK-NEXT: 18: 48 6b db ff imulq $-1, %rbx, %rbx
// CHECK-NEXT: 1c: 48 6b 1c 25 00 00 00 00 2a imulq $42, 0, %rbx // CHECK-NEXT: 1c: 48 6b 1c 25 00 00 00 00 2a imulq $42, 0, %rbx
.section imul,"x" .section imul,"x"
imul $-128, %bx, %bx imul $-128, %bx, %bx
imul $127, bar, %bx imul $127, bar, %bx
imul $0, %ebx, %ebx imul $0, %ebx, %ebx
imul $1, bar, %ebx imul $1, bar, %ebx
imul $-1, %rbx, %rbx imul $-1, %rbx, %rbx
imul $42, bar, %rbx imul $42, bar, %rbx
// CHECK: Disassembly of section and: // CHECK: <and>:
// CHECK-EMPTY:
// CHECK-NEXT: and:
// CHECK-NEXT: 0: 66 83 e3 7f andw $127, %bx // CHECK-NEXT: 0: 66 83 e3 7f andw $127, %bx
// CHECK-NEXT: 4: 66 83 24 25 00 00 00 00 00 andw $0, 0 // CHECK-NEXT: 4: 66 83 24 25 00 00 00 00 00 andw $0, 0
// CHECK-NEXT: d: 83 e3 01 andl $1, %ebx // CHECK-NEXT: d: 83 e3 01 andl $1, %ebx
// CHECK-NEXT: 10: 83 24 25 00 00 00 00 ff andl $-1, 0 // CHECK-NEXT: 10: 83 24 25 00 00 00 00 ff andl $-1, 0
// CHECK-NEXT: 18: 48 83 e3 2a andq $42, %rbx // CHECK-NEXT: 18: 48 83 e3 2a andq $42, %rbx
// CHECK-NEXT: 1c: 48 83 24 25 00 00 00 00 80 andq $-128, 0 // CHECK-NEXT: 1c: 48 83 24 25 00 00 00 00 80 andq $-128, 0
.section and,"x" .section and,"x"
and $127, %bx and $127, %bx
andw $0, bar andw $0, bar
and $1, %ebx and $1, %ebx
andl $-1, bar andl $-1, bar
and $42, %rbx and $42, %rbx
andq $-128, bar andq $-128, bar
// CHECK: Disassembly of section or: // CHECK: <or>:
// CHECK-EMPTY:
// CHECK-NEXT: or:
// CHECK-NEXT: 0: 66 83 cb 00 orw $0, %bx // CHECK-NEXT: 0: 66 83 cb 00 orw $0, %bx
// CHECK-NEXT: 4: 66 83 0c 25 00 00 00 00 01 orw $1, 0 // CHECK-NEXT: 4: 66 83 0c 25 00 00 00 00 01 orw $1, 0
// CHECK-NEXT: d: 83 cb ff orl $-1, %ebx // CHECK-NEXT: d: 83 cb ff orl $-1, %ebx
// CHECK-NEXT: 10: 83 0c 25 00 00 00 00 2a orl $42, 0 // CHECK-NEXT: 10: 83 0c 25 00 00 00 00 2a orl $42, 0
// CHECK-NEXT: 18: 48 83 cb 80 orq $-128, %rbx // CHECK-NEXT: 18: 48 83 cb 80 orq $-128, %rbx
// CHECK-NEXT: 1c: 48 83 0c 25 00 00 00 00 7f orq $127, 0 // CHECK-NEXT: 1c: 48 83 0c 25 00 00 00 00 7f orq $127, 0
.section or,"x" .section or,"x"
or $0, %bx or $0, %bx
orw $1, bar orw $1, bar
or $-1, %ebx or $-1, %ebx
orl $42, bar orl $42, bar
or $-128, %rbx or $-128, %rbx
orq $127, bar orq $127, bar
// CHECK: Disassembly of section xor: // CHECK: <xor>:
// CHECK-EMPTY:
// CHECK-NEXT: xor:
// CHECK-NEXT: 0: 66 83 f3 01 xorw $1, %bx // CHECK-NEXT: 0: 66 83 f3 01 xorw $1, %bx
// CHECK-NEXT: 4: 66 83 34 25 00 00 00 00 ff xorw $-1, 0 // CHECK-NEXT: 4: 66 83 34 25 00 00 00 00 ff xorw $-1, 0
// CHECK-NEXT: d: 83 f3 2a xorl $42, %ebx // CHECK-NEXT: d: 83 f3 2a xorl $42, %ebx
// CHECK-NEXT: 10: 83 34 25 00 00 00 00 80 xorl $-128, 0 // CHECK-NEXT: 10: 83 34 25 00 00 00 00 80 xorl $-128, 0
// CHECK-NEXT: 18: 48 83 f3 7f xorq $127, %rbx // CHECK-NEXT: 18: 48 83 f3 7f xorq $127, %rbx
// CHECK-NEXT: 1c: 48 83 34 25 00 00 00 00 00 xorq $0, 0 // CHECK-NEXT: 1c: 48 83 34 25 00 00 00 00 00 xorq $0, 0
.section xor,"x" .section xor,"x"
xor $1, %bx xor $1, %bx
xorw $-1, bar xorw $-1, bar
xor $42, %ebx xor $42, %ebx
xorl $-128, bar xorl $-128, bar
xor $127, %rbx xor $127, %rbx
xorq $0, bar xorq $0, bar
// CHECK: Disassembly of section add: // CHECK: <add>:
// CHECK-EMPTY:
// CHECK-NEXT: add:
// CHECK-NEXT: 0: 66 83 c3 ff addw $-1, %bx // CHECK-NEXT: 0: 66 83 c3 ff addw $-1, %bx
// CHECK-NEXT: 4: 66 83 04 25 00 00 00 00 2a addw $42, 0 // CHECK-NEXT: 4: 66 83 04 25 00 00 00 00 2a addw $42, 0
// CHECK-NEXT: d: 83 c3 80 addl $-128, %ebx // CHECK-NEXT: d: 83 c3 80 addl $-128, %ebx
// CHECK-NEXT: 10: 83 04 25 00 00 00 00 7f addl $127, 0 // CHECK-NEXT: 10: 83 04 25 00 00 00 00 7f addl $127, 0
// CHECK-NEXT: 18: 48 83 c3 00 addq $0, %rbx // CHECK-NEXT: 18: 48 83 c3 00 addq $0, %rbx
// CHECK-NEXT: 1c: 48 83 04 25 00 00 00 00 01 addq $1, 0 // CHECK-NEXT: 1c: 48 83 04 25 00 00 00 00 01 addq $1, 0
.section add,"x" .section add,"x"
add $-1, %bx add $-1, %bx
addw $42, bar addw $42, bar
add $-128, %ebx add $-128, %ebx
addl $127, bar addl $127, bar
add $0, %rbx add $0, %rbx
addq $1, bar addq $1, bar
// CHECK: Disassembly of section sub: // CHECK: Disassembly of section sub:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: sub: // CHECK-NEXT: <sub>:
// CHECK-NEXT: 0: 66 83 eb 2a subw $42, %bx // CHECK-NEXT: 0: 66 83 eb 2a subw $42, %bx
// CHECK-NEXT: 4: 66 83 2c 25 00 00 00 00 80 subw $-128, 0 // CHECK-NEXT: 4: 66 83 2c 25 00 00 00 00 80 subw $-128, 0
// CHECK-NEXT: d: 83 eb 7f subl $127, %ebx // CHECK-NEXT: d: 83 eb 7f subl $127, %ebx
// CHECK-NEXT: 10: 83 2c 25 00 00 00 00 00 subl $0, 0 // CHECK-NEXT: 10: 83 2c 25 00 00 00 00 00 subl $0, 0
// CHECK-NEXT: 18: 48 83 eb 01 subq $1, %rbx // CHECK-NEXT: 18: 48 83 eb 01 subq $1, %rbx
// CHECK-NEXT: 1c: 48 83 2c 25 00 00 00 00 ff subq $-1, 0 // CHECK-NEXT: 1c: 48 83 2c 25 00 00 00 00 ff subq $-1, 0
.section sub,"x" .section sub,"x"
sub $42, %bx sub $42, %bx
subw $-128, bar subw $-128, bar
sub $127, %ebx sub $127, %ebx
subl $0, bar subl $0, bar
sub $1, %rbx sub $1, %rbx
subq $-1, bar subq $-1, bar
// CHECK: Disassembly of section cmp: // CHECK: Disassembly of section cmp:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: cmp: // CHECK-NEXT: <cmp>:
// CHECK-NEXT: 0: 66 83 fb 80 cmpw $-128, %bx // CHECK-NEXT: 0: 66 83 fb 80 cmpw $-128, %bx
// CHECK-NEXT: 4: 66 83 3c 25 00 00 00 00 7f cmpw $127, 0 // CHECK-NEXT: 4: 66 83 3c 25 00 00 00 00 7f cmpw $127, 0
// CHECK-NEXT: d: 83 fb 00 cmpl $0, %ebx // CHECK-NEXT: d: 83 fb 00 cmpl $0, %ebx
// CHECK-NEXT: 10: 83 3c 25 00 00 00 00 01 cmpl $1, 0 // CHECK-NEXT: 10: 83 3c 25 00 00 00 00 01 cmpl $1, 0
// CHECK-NEXT: 18: 48 83 fb ff cmpq $-1, %rbx // CHECK-NEXT: 18: 48 83 fb ff cmpq $-1, %rbx
// CHECK-NEXT: 1c: 48 83 3c 25 00 00 00 00 2a cmpq $42, 0 // CHECK-NEXT: 1c: 48 83 3c 25 00 00 00 00 2a cmpq $42, 0
.section cmp,"x" .section cmp,"x"
cmp $-128, %bx cmp $-128, %bx
cmpw $127, bar cmpw $127, bar
cmp $0, %ebx cmp $0, %ebx
cmpl $1, bar cmpl $1, bar
cmp $-1, %rbx cmp $-1, %rbx
cmpq $42, bar cmpq $42, bar
// CHECK: Disassembly of section push: // CHECK: Disassembly of section push:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: push: // CHECK-NEXT: <push>:
// CHECK-NEXT: 0: 66 6a 80 pushw $-128 // CHECK-NEXT: 0: 66 6a 80 pushw $-128
// CHECK-NEXT: 3: 66 6a 7f pushw $127 // CHECK-NEXT: 3: 66 6a 7f pushw $127
// CHECK-NEXT: 6: 6a 80 pushq $-128 // CHECK-NEXT: 6: 6a 80 pushq $-128
// CHECK-NEXT: 8: 6a 7f pushq $127 // CHECK-NEXT: 8: 6a 7f pushq $127
.section push,"x" .section push,"x"
pushw $-128 pushw $-128
pushw $127 pushw $127
push $-128 push $-128
push $127 push $127

llvm/test/MC/ELF/relax-arith3.s

// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s
// Test that we correctly relax these instructions into versions that use // Test that we correctly relax these instructions into versions that use
// 16 or 32 bit immediate values. // 16 or 32 bit immediate values.
bar: bar:
// CHECK: Disassembly of section imul: // CHECK: Disassembly of section imul:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: imul: // CHECK-NEXT: <imul>:
// CHECK-NEXT: 0: 66 69 1d 00 00 00 00 00 00 imulw $0, (%rip), %bx // CHECK-NEXT: 0: 66 69 1d 00 00 00 00 00 00 imulw $0, (%rip), %bx
// CHECK-NEXT: 9: 69 1d 00 00 00 00 00 00 00 00 imull $0, (%rip), %ebx // CHECK-NEXT: 9: 69 1d 00 00 00 00 00 00 00 00 imull $0, (%rip), %ebx
// CHECK-NEXT: 13: 48 69 1d 00 00 00 00 00 00 00 00 imulq $0, (%rip), %rbx // CHECK-NEXT: 13: 48 69 1d 00 00 00 00 00 00 00 00 imulq $0, (%rip), %rbx
.section imul,"x" .section imul,"x"
imul $foo, bar(%rip), %bx imul $foo, bar(%rip), %bx
imul $foo, bar(%rip), %ebx imul $foo, bar(%rip), %ebx
imul $foo, bar(%rip), %rbx imul $foo, bar(%rip), %rbx
// CHECK: Disassembly of section and: // CHECK: <and>:
// CHECK-EMPTY:
// CHECK-NEXT: and:
// CHECK-NEXT: 0: 66 81 25 00 00 00 00 00 00 andw $0, (%rip) // CHECK-NEXT: 0: 66 81 25 00 00 00 00 00 00 andw $0, (%rip)
// CHECK-NEXT: 9: 81 25 00 00 00 00 00 00 00 00 andl $0, (%rip) // CHECK-NEXT: 9: 81 25 00 00 00 00 00 00 00 00 andl $0, (%rip)
// CHECK-NEXT: 13: 48 81 25 00 00 00 00 00 00 00 00 andq $0, (%rip) // CHECK-NEXT: 13: 48 81 25 00 00 00 00 00 00 00 00 andq $0, (%rip)
.section and,"x" .section and,"x"
andw $foo, bar(%rip) andw $foo, bar(%rip)
andl $foo, bar(%rip) andl $foo, bar(%rip)
andq $foo, bar(%rip) andq $foo, bar(%rip)
// CHECK: Disassembly of section or: // CHECK: <or>:
// CHECK-EMPTY:
// CHECK-NEXT: or:
// CHECK-NEXT: 0: 66 81 0d 00 00 00 00 00 00 orw $0, (%rip) // CHECK-NEXT: 0: 66 81 0d 00 00 00 00 00 00 orw $0, (%rip)
// CHECK-NEXT: 9: 81 0d 00 00 00 00 00 00 00 00 orl $0, (%rip) // CHECK-NEXT: 9: 81 0d 00 00 00 00 00 00 00 00 orl $0, (%rip)
// CHECK-NEXT: 13: 48 81 0d 00 00 00 00 00 00 00 00 orq $0, (%rip) // CHECK-NEXT: 13: 48 81 0d 00 00 00 00 00 00 00 00 orq $0, (%rip)
.section or,"x" .section or,"x"
orw $foo, bar(%rip) orw $foo, bar(%rip)
orl $foo, bar(%rip) orl $foo, bar(%rip)
orq $foo, bar(%rip) orq $foo, bar(%rip)
// CHECK: Disassembly of section xor: // CHECK: <xor>:
// CHECK-EMPTY:
// CHECK-NEXT: xor:
// CHECK-NEXT: 0: 66 81 35 00 00 00 00 00 00 xorw $0, (%rip) // CHECK-NEXT: 0: 66 81 35 00 00 00 00 00 00 xorw $0, (%rip)
// CHECK-NEXT: 9: 81 35 00 00 00 00 00 00 00 00 xorl $0, (%rip) // CHECK-NEXT: 9: 81 35 00 00 00 00 00 00 00 00 xorl $0, (%rip)
// CHECK-NEXT: 13: 48 81 35 00 00 00 00 00 00 00 00 xorq $0, (%rip) // CHECK-NEXT: 13: 48 81 35 00 00 00 00 00 00 00 00 xorq $0, (%rip)
.section xor,"x" .section xor,"x"
xorw $foo, bar(%rip) xorw $foo, bar(%rip)
xorl $foo, bar(%rip) xorl $foo, bar(%rip)
xorq $foo, bar(%rip) xorq $foo, bar(%rip)
// CHECK: Disassembly of section add: // CHECK: <add>:
// CHECK-EMPTY:
// CHECK-NEXT: add:
// CHECK-NEXT: 0: 66 81 05 00 00 00 00 00 00 addw $0, (%rip) // CHECK-NEXT: 0: 66 81 05 00 00 00 00 00 00 addw $0, (%rip)
// CHECK-NEXT: 9: 81 05 00 00 00 00 00 00 00 00 addl $0, (%rip) // CHECK-NEXT: 9: 81 05 00 00 00 00 00 00 00 00 addl $0, (%rip)
// CHECK-NEXT: 13: 48 81 05 00 00 00 00 00 00 00 00 addq $0, (%rip) // CHECK-NEXT: 13: 48 81 05 00 00 00 00 00 00 00 00 addq $0, (%rip)
.section add,"x" .section add,"x"
addw $foo, bar(%rip) addw $foo, bar(%rip)
addl $foo, bar(%rip) addl $foo, bar(%rip)
addq $foo, bar(%rip) addq $foo, bar(%rip)
// CHECK: Disassembly of section sub: // CHECK: <sub>:
// CHECK-EMPTY:
// CHECK-NEXT: sub:
// CHECK-NEXT: 0: 66 81 2d 00 00 00 00 00 00 subw $0, (%rip) // CHECK-NEXT: 0: 66 81 2d 00 00 00 00 00 00 subw $0, (%rip)
// CHECK-NEXT: 9: 81 2d 00 00 00 00 00 00 00 00 subl $0, (%rip) // CHECK-NEXT: 9: 81 2d 00 00 00 00 00 00 00 00 subl $0, (%rip)
// CHECK-NEXT: 13: 48 81 2d 00 00 00 00 00 00 00 00 subq $0, (%rip) // CHECK-NEXT: 13: 48 81 2d 00 00 00 00 00 00 00 00 subq $0, (%rip)
.section sub,"x" .section sub,"x"
subw $foo, bar(%rip) subw $foo, bar(%rip)
subl $foo, bar(%rip) subl $foo, bar(%rip)
subq $foo, bar(%rip) subq $foo, bar(%rip)
// CHECK: Disassembly of section cmp: // CHECK: <cmp>:
// CHECK-EMPTY:
// CHECK-NEXT: cmp:
// CHECK-NEXT: 0: 66 81 3d 00 00 00 00 00 00 cmpw $0, (%rip) // CHECK-NEXT: 0: 66 81 3d 00 00 00 00 00 00 cmpw $0, (%rip)
// CHECK-NEXT: 9: 81 3d 00 00 00 00 00 00 00 00 cmpl $0, (%rip) // CHECK-NEXT: 9: 81 3d 00 00 00 00 00 00 00 00 cmpl $0, (%rip)
// CHECK-NEXT: 13: 48 81 3d 00 00 00 00 00 00 00 00 cmpq $0, (%rip) // CHECK-NEXT: 13: 48 81 3d 00 00 00 00 00 00 00 00 cmpq $0, (%rip)
.section cmp,"x" .section cmp,"x"
cmpw $foo, bar(%rip) cmpw $foo, bar(%rip)
cmpl $foo, bar(%rip) cmpl $foo, bar(%rip)
cmpq $foo, bar(%rip) cmpq $foo, bar(%rip)

llvm/test/MC/ELF/relax-arith4.s

// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s // RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s
// Test for proper instruction relaxation behavior for the push $imm // Test for proper instruction relaxation behavior for the push $imm
// instruction forms. This is the 32-bit version of the push $imm tests from // instruction forms. This is the 32-bit version of the push $imm tests from
// relax-arith.s and relax-arith2.s. // relax-arith.s and relax-arith2.s.
// CHECK: Disassembly of section push8: // CHECK: Disassembly of section push8:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: push8: // CHECK-NEXT: <push8>:
// CHECK-NEXT: 0: 66 6a 80 pushw $-128 // CHECK-NEXT: 0: 66 6a 80 pushw $-128
// CHECK-NEXT: 3: 66 6a 7f pushw $127 // CHECK-NEXT: 3: 66 6a 7f pushw $127
// CHECK-NEXT: 6: 6a 80 pushl $-128 // CHECK-NEXT: 6: 6a 80 pushl $-128
// CHECK-NEXT: 8: 6a 7f pushl $127 // CHECK-NEXT: 8: 6a 7f pushl $127
.section push8,"x" .section push8,"x"
pushw $-128 pushw $-128
pushw $127 pushw $127
push $-128 push $-128
push $127 push $127
// CHECK: Disassembly of section push32: // CHECK: Disassembly of section push32:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: push32: // CHECK-NEXT: <push32>:
// CHECK-NEXT: 0: 66 68 00 00 pushw $0 // CHECK-NEXT: 0: 66 68 00 00 pushw $0
// CHECK-NEXT: 4: 68 00 00 00 00 pushl $0 // CHECK-NEXT: 4: 68 00 00 00 00 pushl $0
.section push32,"x" .section push32,"x"
pushw $foo pushw $foo
push $foo push $foo

llvm/test/MC/Hexagon/missing_label.s

# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
# #
.I1: .I1:
nop nop
# CHECK: .I1: # CHECK: <.I1>:
# CHECK: nop # CHECK: nop

llvm/test/MC/Mips/cpsetup.s

# RUN: llvm-mc -triple mips-unknown-linux -target-abi o32 -filetype=obj -o - %s | \ # RUN: llvm-mc -triple mips-unknown-linux -target-abi o32 -filetype=obj -o - %s | \
# RUN: llvm-objdump -d -r -z - | FileCheck -check-prefixes=ALL,O32 %s # RUN: llvm-objdump -d -r -z - | FileCheck -check-prefixes=ALL,O32 %s
# RUN: llvm-mc -triple mips-unknown-linux -target-abi o32 %s | \ # RUN: llvm-mc -triple mips-unknown-linux -target-abi o32 %s | \
# RUN: FileCheck -check-prefixes=ALL,ASM,ASM-O32 %s # RUN: FileCheck -check-prefixes=ASM,ASM-O32 %s
# FIXME: Now we check .cpsetup expansion for `-mno-shared` case only. # FIXME: Now we check .cpsetup expansion for `-mno-shared` case only.
# We also need to implement/check the `-mshared` case. # We also need to implement/check the `-mshared` case.
# RUN: llvm-mc -triple mips64-unknown-linux -target-abi n32 -filetype=obj -o - %s | \ # RUN: llvm-mc -triple mips64-unknown-linux -target-abi n32 -filetype=obj -o - %s | \
# RUN: llvm-objdump -d -r -z - | \ # RUN: llvm-objdump -d -r -z - | \
# RUN: FileCheck -check-prefixes=ALL,NXX,N32 %s # RUN: FileCheck -check-prefixes=ALL,NXX,N32 %s
# RUN: llvm-mc -triple mips64-unknown-linux -target-abi n32 %s | \ # RUN: llvm-mc -triple mips64-unknown-linux -target-abi n32 %s | \
# RUN: FileCheck -check-prefixes=ALL,ASM,ASM-N32 %s # RUN: FileCheck -check-prefixes=ASM,ASM-N32 %s
# RUN: llvm-mc -triple mips64-unknown-linux %s -filetype=obj -o - | \ # RUN: llvm-mc -triple mips64-unknown-linux %s -filetype=obj -o - | \
# RUN: llvm-objdump -d -r -z - | \ # RUN: llvm-objdump -d -r -z - | \
# RUN: FileCheck -check-prefixes=ALL,NXX,N64 %s # RUN: FileCheck -check-prefixes=ALL,NXX,N64 %s
# RUN: llvm-mc -triple mips64-unknown-linux %s | \ # RUN: llvm-mc -triple mips64-unknown-linux %s | \
# RUN: FileCheck -check-prefixes=ALL,ASM,ASM-N64 %s # RUN: FileCheck -check-prefixes=ASM,ASM-N64 %s
.text .text
.option pic2 .option pic2
t1: t1:
.cpsetup $25, 8, __cerror .cpsetup $25, 8, __cerror
nop nop
.cpreturn .cpreturn
nop nop
# ALL-LABEL: t1: # ALL-LABEL: <t1>:
# ASM-LABEL: t1:
# O32-NOT: __cerror # O32-NOT: __cerror
# NXX-NEXT: sd $gp, 8($sp) # NXX-NEXT: sd $gp, 8($sp)
# NXX-NEXT: lui $gp, 0 # NXX-NEXT: lui $gp, 0
# N32-NEXT: R_MIPS_HI16 __gnu_local_gp # N32-NEXT: R_MIPS_HI16 __gnu_local_gp
# N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror
# NXX-NEXT: addiu $gp, $gp, 0 # NXX-NEXT: addiu $gp, $gp, 0
# N32-NEXT: R_MIPS_LO16 __gnu_local_gp # N32-NEXT: R_MIPS_LO16 __gnu_local_gp
# N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror
# N64-NEXT: daddu $gp, $gp, $25 # N64-NEXT: daddu $gp, $gp, $25
# ASM-NEXT: .cpsetup $25, 8, __cerror # ASM-NEXT: .cpsetup $25, 8, __cerror
# ALL-NEXT: nop # ALL-NEXT: nop
# ASM-NEXT: .cpreturn # ASM: .cpreturn
# NXX-NEXT: ld $gp, 8($sp) # NXX-NEXT: ld $gp, 8($sp)
# ALL-NEXT: nop # ALL-NEXT: nop
t2: t2:
.cpsetup $25, $2, __cerror .cpsetup $25, $2, __cerror
nop nop
.cpreturn .cpreturn
nop nop
# ALL-LABEL: t2: # ALL-LABEL: <t2>:
# ASM-LABEL: t2:
# O32-NOT: __cerror # O32-NOT: __cerror
# NXX-NEXT: move $2, $gp # NXX-NEXT: move $2, $gp
# NXX-NEXT: lui $gp, 0 # NXX-NEXT: lui $gp, 0
# N32-NEXT: R_MIPS_HI16 __gnu_local_gp # N32-NEXT: R_MIPS_HI16 __gnu_local_gp
# N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror
# NXX-NEXT: addiu $gp, $gp, 0 # NXX-NEXT: addiu $gp, $gp, 0
# N32-NEXT: R_MIPS_LO16 __gnu_local_gp # N32-NEXT: R_MIPS_LO16 __gnu_local_gp
# N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror
# N64-NEXT: daddu $gp, $gp, $25 # N64-NEXT: daddu $gp, $gp, $25
# ASM-NEXT: .cpsetup $25, $2, __cerror # ASM-NEXT: .cpsetup $25, $2, __cerror
# ALL-NEXT: nop # ALL-NEXT: nop
# ASM-NEXT: .cpreturn # ASM: .cpreturn
# NXX-NEXT: move $gp, $2 # NXX-NEXT: move $gp, $2
# ALL-NEXT: nop # ALL-NEXT: nop
# .cpsetup with local labels (PR22518): # .cpsetup with local labels (PR22518):
# The '1:' label isn't emitted in all cases but we still want a label to match # The '1:' label isn't emitted in all cases but we still want a label to match
# so we force one here. # so we force one here.
t3: t3:
nop nop
1: 1:
.cpsetup $25, $2, 1b .cpsetup $25, $2, 1b
nop nop
sub $3, $3, $2 sub $3, $3, $2
# ALL-LABEL: t3: # ALL-LABEL: <t3>:
# ASM-LABEL: t3:
# ALL-NEXT: nop # ALL-NEXT: nop
# O32-NEXT: nop # O32-NEXT: nop
# O32-NEXT: sub $3, $3, $2 # O32-NEXT: sub $3, $3, $2
# NXX-NEXT: move $2, $gp # NXX-NEXT: move $2, $gp
# NXX-NEXT: lui $gp, 0 # NXX-NEXT: lui $gp, 0
# N32-NEXT: {{^ *0+}}38: R_MIPS_HI16 __gnu_local_gp # N32-NEXT: {{^ *0+}}38: R_MIPS_HI16 __gnu_local_gp
Show All 22 Linest4:
nop nop
.cpreturn .cpreturn
nop nop
# Testing that .cpsetup expands to nothing in this case # Testing that .cpsetup expands to nothing in this case
# by checking that the next instruction after the first # by checking that the next instruction after the first
# nop is also a 'nop'. # nop is also a 'nop'.
# ALL-LABEL: t4: # ALL-LABEL: <t4>:
# ASM-LABEL: t4:
# NXX-NEXT: nop # NXX-NEXT: nop
# NXX-NEXT: nop # NXX-NEXT: nop
# NXX-NEXT: nop # NXX-NEXT: nop
# ASM-NEXT: nop # ASM-NEXT: nop
# ASM-NEXT: .cpsetup $25, 8, __cerror # ASM-NEXT: .cpsetup $25, 8, __cerror
# ASM-NEXT: nop # ASM-NEXT: nop
# ASM-NEXT: .cpreturn # ASM-NEXT: .cpreturn
# ASM-NEXT: nop # ASM-NEXT: nop
# Test that we accept constant expressions. # Test that we accept constant expressions.
.option pic2 .option pic2
t5: t5:
.cpsetup $25, ((8*4) - (3*8)), __cerror .cpsetup $25, ((8*4) - (3*8)), __cerror
nop nop
# ALL-LABEL: t5: # ALL-LABEL: <t5>:
# ASM-LABEL: t5:
# O32-NOT: __cerror # O32-NOT: __cerror
# NXX-NEXT: sd $gp, 8($sp) # NXX-NEXT: sd $gp, 8($sp)
# NXX-NEXT: lui $gp, 0 # NXX-NEXT: lui $gp, 0
# N32-NEXT: R_MIPS_HI16 __gnu_local_gp # N32-NEXT: R_MIPS_HI16 __gnu_local_gp
# N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror
# NXX-NEXT: addiu $gp, $gp, 0 # NXX-NEXT: addiu $gp, $gp, 0
# N32-NEXT: R_MIPS_LO16 __gnu_local_gp # N32-NEXT: R_MIPS_LO16 __gnu_local_gp
# N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror
# N64-NEXT: daddu $gp, $gp, $25 # N64-NEXT: daddu $gp, $gp, $25
# ASM-NEXT: .cpsetup $25, 8, __cerror # ASM-NEXT: .cpsetup $25, 8, __cerror
# ALL-NEXT: nop # ALL-NEXT: nop
t1b: t1b:
IMM_8 = 8 IMM_8 = 8
.cpsetup $25, IMM_8, __cerror .cpsetup $25, IMM_8, __cerror
nop nop
.cpreturn .cpreturn
nop nop
# ALL-LABEL: t1b: # ALL-LABEL: <t1b>:
# ASM-LABEL: t1b:
# ASM-NEXT: .set IMM_8, 8 # ASM-NEXT: .set IMM_8, 8
# O32-NOT: __cerror # O32-NOT: __cerror
# NXX-NEXT: sd $gp, 8($sp) # NXX-NEXT: sd $gp, 8($sp)
# NXX-NEXT: lui $gp, 0 # NXX-NEXT: lui $gp, 0
# N32-NEXT: R_MIPS_HI16 __gnu_local_gp # N32-NEXT: R_MIPS_HI16 __gnu_local_gp
# N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror
# NXX-NEXT: addiu $gp, $gp, 0 # NXX-NEXT: addiu $gp, $gp, 0
# N32-NEXT: R_MIPS_LO16 __gnu_local_gp # N32-NEXT: R_MIPS_LO16 __gnu_local_gp
# N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror # N64-NEXT: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror
# N64-NEXT: daddu $gp, $gp, $25 # N64-NEXT: daddu $gp, $gp, $25
# ASM-NEXT: .cpsetup $25, 8, __cerror # ASM-NEXT: .cpsetup $25, 8, __cerror
# ALL-NEXT: nop # ALL-NEXT: nop
# ASM-NEXT: .cpreturn # ASM: .cpreturn
# NXX-NEXT: ld $gp, 8($sp) # NXX-NEXT: ld $gp, 8($sp)
# ALL-NEXT: nop # ALL-NEXT: nop

llvm/test/MC/Mips/higher-highest-addressing.s

# RUN: llvm-mc -filetype=obj -triple=mips64el-unknown-linux -mcpu=mips64r2 %s \ # RUN: llvm-mc -filetype=obj -triple=mips64el-unknown-linux -mcpu=mips64r2 %s \
# RUN: | llvm-objdump -disassemble - | FileCheck %s # RUN: | llvm-objdump -disassemble - | FileCheck %s
# RUN: llvm-mc -filetype=obj -triple=mips64el-unknown-linux -mcpu=mips64r2 %s \ # RUN: llvm-mc -filetype=obj -triple=mips64el-unknown-linux -mcpu=mips64r2 %s \
# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL # RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
# Test that R_MIPS_HIGHER and R_MIPS_HIGHEST relocations are created. By using # Test that R_MIPS_HIGHER and R_MIPS_HIGHEST relocations are created. By using
# NEXT we also test that none of the expressions from the test2 generates # NEXT we also test that none of the expressions from the test2 generates
# relocations. # relocations.
test1: test1:
# CHECK-LABEL: test1: # CHECK-LABEL: <test1>:
lui $5, %highest(func) lui $5, %highest(func)
daddiu $5, $5, %higher(func) daddiu $5, $5, %higher(func)
# CHECK-REL: Relocations [ # CHECK-REL: Relocations [
# CHECK-REL-NEXT: { # CHECK-REL-NEXT: {
# CHECK-REL-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_HIGHEST # CHECK-REL-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_HIGHEST
# CHECK-REL-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_HIGHER # CHECK-REL-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_HIGHER
# CHECK-REL-NEXT: } # CHECK-REL-NEXT: }
# Test the calculation of %higher and %highest: # Test the calculation of %higher and %highest:
# ((x + 0x80008000) >> 32) & 0xffff (higher) # ((x + 0x80008000) >> 32) & 0xffff (higher)
# ((x + 0x800080008000) >> 48) & 0xffff (highest). # ((x + 0x800080008000) >> 48) & 0xffff (highest).
test2: test2:
# CHECK-LABEL: test2: # CHECK-LABEL: <test2>:
# Check the case where relocations are not modified by adding +1. The constant # Check the case where relocations are not modified by adding +1. The constant
# is chosen so that it is just below the value that triggers the addition of +1 # is chosen so that it is just below the value that triggers the addition of +1
# to %higher. # to %higher.
$L1: $L1:
lui $6, %highest($L2-$L1+0x300047FFF7FF7) lui $6, %highest($L2-$L1+0x300047FFF7FF7)
daddiu $6, $6, %higher($L2-$L1+0x300047FFF7FF7) daddiu $6, $6, %higher($L2-$L1+0x300047FFF7FF7)
$L2: $L2:
Show All 16 Lines

llvm/test/MC/Mips/instr-analysis.s

# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o - \ # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o - \
# RUN: | llvm-objdump -d - | FileCheck %s # RUN: | llvm-objdump -d - | FileCheck %s
# CHECK: foo: # CHECK: <foo>:
# CHECK-NEXT: 0: 0c 00 00 02 jal 8 <loc1> # CHECK-NEXT: 0: 0c 00 00 02 jal 8 <loc1>
# CHECK-NEXT: 4: 00 00 00 00 nop # CHECK-NEXT: 4: 00 00 00 00 nop
# #
# CHECK: loc1: # CHECK: <loc1>:
# CHECK-NEXT: 8: 0c 00 00 06 jal 24 <loc3> # CHECK-NEXT: 8: 0c 00 00 06 jal 24 <loc3>
# CHECK-NEXT: c: 00 00 00 00 nop # CHECK-NEXT: c: 00 00 00 00 nop
# #
# CHECK: loc2: # CHECK: <loc2>:
# CHECK-NEXT: 10: 10 00 ff fd b -8 <loc1> # CHECK-NEXT: 10: 10 00 ff fd b -8 <loc1>
# CHECK-NEXT: 14: 00 00 00 00 nop # CHECK-NEXT: 14: 00 00 00 00 nop
# #
# CHECK: loc3: # CHECK: <loc3>:
# CHECK-NEXT: 18: 10 43 ff fd beq $2, $3, -8 <loc2> # CHECK-NEXT: 18: 10 43 ff fd beq $2, $3, -8 <loc2>
# CHECK-NEXT: 1c: 00 00 00 00 nop # CHECK-NEXT: 1c: 00 00 00 00 nop
# CHECK-NEXT: 20: 04 11 ff f9 bal -24 <loc1> # CHECK-NEXT: 20: 04 11 ff f9 bal -24 <loc1>
# CHECK-NEXT: 24: 00 00 00 00 nop # CHECK-NEXT: 24: 00 00 00 00 nop
# CHECK-NEXT: 28: 08 00 00 04 j 16 <loc2> # CHECK-NEXT: 28: 08 00 00 04 j 16 <loc2>
.text .text
.globl foo .globl foo
Show All 12 Lines

llvm/test/MC/Mips/micromips-jump-pc-region.s

# RUN: llvm-mc -triple=mips -mcpu=mips32 -mattr=+micromips -filetype=obj < %s \ # RUN: llvm-mc -triple=mips -mcpu=mips32 -mattr=+micromips -filetype=obj < %s \
#!RUN: | llvm-objdump -d - | FileCheck %s #!RUN: | llvm-objdump -d - | FileCheck %s
.set noreorder .set noreorder
# Force us into the second 256 MB region with a non-zero instruction index # Force us into the second 256 MB region with a non-zero instruction index
.org 256*1024*1024 + 12 .org 256*1024*1024 + 12
# CHECK-LABEL: 1000000c foo: # CHECK-LABEL: 1000000c <foo>:
# CHECK-NEXT: 1000000c: d4 00 00 06 j 12 <foo> # CHECK-NEXT: 1000000c: d4 00 00 06 j 12 <foo>
# CHECK-NEXT: 10000010: f4 00 00 08 jal 16 <foo+0x4> # CHECK-NEXT: 10000010: f4 00 00 08 jal 16 <foo+0x4>
# CHECK-NEXT: 10000014: f0 00 00 05 jalx 20 <foo+0x8> # CHECK-NEXT: 10000014: f0 00 00 05 jalx 20 <foo+0x8>
# CHECK-NEXT: 10000018: 74 00 00 0c jals 24 <foo+0xc> # CHECK-NEXT: 10000018: 74 00 00 0c jals 24 <foo+0xc>
foo: foo:
j 12 j 12
jal 16 jal 16
jalx 20 jalx 20
jals 24 jals 24

llvm/test/MC/Mips/mips-jump-pc-region.s

# RUN: llvm-mc -triple=mips -mcpu=mips32 -filetype=obj < %s \ # RUN: llvm-mc -triple=mips -mcpu=mips32 -filetype=obj < %s \
#!RUN: | llvm-objdump -d - | FileCheck %s #!RUN: | llvm-objdump -d - | FileCheck %s
# RUN: llvm-mc -triple=mips64 -mcpu=mips64 -filetype=obj < %s \ # RUN: llvm-mc -triple=mips64 -mcpu=mips64 -filetype=obj < %s \
#!RUN: | llvm-objdump -d - | FileCheck %s #!RUN: | llvm-objdump -d - | FileCheck %s
.set noreorder .set noreorder
# Force us into the second 256 MB region with a non-zero instruction index # Force us into the second 256 MB region with a non-zero instruction index
.org 256*1024*1024 + 12 .org 256*1024*1024 + 12
# CHECK-LABEL: 1000000c foo: # CHECK-LABEL: 1000000c <foo>:
# CHECK-NEXT: 1000000c: 08 00 00 03 j 12 <foo> # CHECK-NEXT: 1000000c: 08 00 00 03 j 12 <foo>
# CHECK-NEXT: 10000010: 0c 00 00 04 jal 16 <foo+0x4> # CHECK-NEXT: 10000010: 0c 00 00 04 jal 16 <foo+0x4>
# CHECK-NEXT: 10000014: 74 00 00 05 jalx 20 <foo+0x8> # CHECK-NEXT: 10000014: 74 00 00 05 jalx 20 <foo+0x8>
foo: foo:
j 12 j 12
jal 16 jal 16
jalx 20 jalx 20

llvm/test/MC/Mips/nacl-mask.s

Show All 11 Lines
test1: test1:
.set noreorder .set noreorder
jr $a0 jr $a0
nop nop
jr $ra jr $ra
nop nop
# CHECK-LABEL: test1: # CHECK-LABEL: <test1>:
# CHECK: and $4, $4, $14 # CHECK: and $4, $4, $14
# CHECK-NEXT: jr $4 # CHECK-NEXT: jr $4
# Check that additional nop is inserted, to align mask and jr to the next # Check that additional nop is inserted, to align mask and jr to the next
# bundle. # bundle.
# CHECK-NEXT: nop # CHECK-NEXT: nop
Show All 20 Lines .set noreorder
ldc1 $f2, 0($7) ldc1 $f2, 0($7)
ll $4, 0($8) ll $4, 0($8)
lwl $4, 0($9) lwl $4, 0($9)
lwr $4, 0($10) lwr $4, 0($10)
lw $4, 0($sp) lw $4, 0($sp)
lw $4, 0($t8) lw $4, 0($t8)
# CHECK-LABEL: test2: # CHECK-LABEL: <test2>:
# CHECK: and $1, $1, $15 # CHECK: and $1, $1, $15
# CHECK-NEXT: lb $4, 0($1) # CHECK-NEXT: lb $4, 0($1)
# Check that additional nop is inserted, to align mask and load to the next # Check that additional nop is inserted, to align mask and load to the next
# bundle. # bundle.
# CHECK: nop # CHECK: nop
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines .set noreorder
sdc1 $f2, 0($5) sdc1 $f2, 0($5)
swl $4, 0($6) swl $4, 0($6)
swr $4, 0($7) swr $4, 0($7)
sc $4, 0($8) sc $4, 0($8)
sw $4, 0($sp) sw $4, 0($sp)
sw $4, 0($t8) sw $4, 0($t8)
# CHECK-LABEL: test3: # CHECK-LABEL: <test3>:
# CHECK: and $1, $1, $15 # CHECK: and $1, $1, $15
# CHECK-NEXT: sb $4, 0($1) # CHECK-NEXT: sb $4, 0($1)
# Check that additional nop is inserted, to align mask and store to the next # Check that additional nop is inserted, to align mask and store to the next
# bundle. # bundle.
# CHECK: nop # CHECK: nop
Show All 40 Lines .set noreorder
addiu $sp, $sp, 24 addiu $sp, $sp, 24
nop nop
addu $sp, $sp, $1 addu $sp, $sp, $1
lw $sp, 0($2) lw $sp, 0($2)
lw $sp, 123($sp) lw $sp, 123($sp)
sw $sp, 123($sp) sw $sp, 123($sp)
# CHECK-LABEL: test4: # CHECK-LABEL: <test4>:
# CHECK: addiu $sp, $sp, 24 # CHECK: addiu $sp, $sp, 24
# CHECK-NEXT: and $sp, $sp, $15 # CHECK-NEXT: and $sp, $sp, $15
# Check that additional nop is inserted, to align instruction and mask to the # Check that additional nop is inserted, to align instruction and mask to the
# next bundle. # next bundle.
# CHECK: nop # CHECK: nop
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines .set noreorder
addiu $4, $zero, 4 addiu $4, $zero, 4
jalr $t9 jalr $t9
addiu $4, $zero, 5 addiu $4, $zero, 5
# CHECK: nop # CHECK: nop
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-LABEL: test5: # CHECK-LABEL: <test5>:
# CHECK-NEXT: jal # CHECK-NEXT: jal
# CHECK-NEXT: addiu $4, $zero, 1 # CHECK-NEXT: addiu $4, $zero, 1
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: bal # CHECK-NEXT: bal
# CHECK-NEXT: addiu $4, $zero, 2 # CHECK-NEXT: addiu $4, $zero, 2
Show All 33 Lines .set noreorder
jalr $t9 jalr $t9
sw $sp, 0($sp) sw $sp, 0($sp)
# CHECK: nop # CHECK: nop
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-LABEL: test6: # CHECK-LABEL: <test6>:
# CHECK-NEXT: jal # CHECK-NEXT: jal
# CHECK-NEXT: sw $4, 0($sp) # CHECK-NEXT: sw $4, 0($sp)
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: bal # CHECK-NEXT: bal
# CHECK-NEXT: lw $5, 0($24) # CHECK-NEXT: lw $5, 0($24)
# CHECK-NEXT: nop # CHECK-NEXT: nop
# CHECK-NEXT: and $25, $25, $14 # CHECK-NEXT: and $25, $25, $14
# CHECK-NEXT: jalr # CHECK-NEXT: jalr
# CHECK-NEXT: sw $sp, 0($sp) # CHECK-NEXT: sw $sp, 0($sp)

llvm/test/MC/Mips/set-defined-symbol.s

# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
# RUN: llvm-objdump -d -r - | FileCheck %s # RUN: llvm-objdump -d -r - | FileCheck %s
.global foo .global foo
.weak bar .weak bar
.set bar, b .set bar, b
.set foo, b .set foo, b
.set foo, a .set foo, a
a: a:
nop nop
# CHECK-NOT: a: # CHECK-NOT: a:
# CHECK: foo: # CHECK: <foo>:
b: b:
nop nop
# CHECK-NOT: b: # CHECK-NOT: b:
# CHECK-NOT: foo: # CHECK-NOT: foo:
# CHECK: bar: # CHECK: <bar>:

llvm/test/MC/Mips/sext_64_32.ll

; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \ ; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \
; RUN: llvm-objdump -disassemble - | FileCheck %s ; RUN: llvm-objdump -disassemble - | FileCheck %s
; Sign extend from 32 to 64 was creating nonsense opcodes ; Sign extend from 32 to 64 was creating nonsense opcodes
; CHECK: sll ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0 ; CHECK: sll ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
define i64 @foo(i32 %ival) nounwind readnone { define i64 @foo(i32 %ival) nounwind readnone {
entry: entry:
%conv = sext i32 %ival to i64 %conv = sext i32 %ival to i64
ret i64 %conv ret i64 %conv
} }
; CHECK-LABEL: foo_2: ; CHECK-LABEL: <foo_2>:
; CHECK: dext ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0, 32 ; CHECK: dext ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0, 32
define i64 @foo_2(i32 %ival_2) nounwind readnone { define i64 @foo_2(i32 %ival_2) nounwind readnone {
entry: entry:
%conv_2 = zext i32 %ival_2 to i64 %conv_2 = zext i32 %ival_2 to i64
ret i64 %conv_2 ret i64 %conv_2
} }

llvm/test/MC/PowerPC/ppc64-dq-expr.s

Show All 16 Lines.Llep:
addis 3, 2, vecB@toc@ha addis 3, 2, vecB@toc@ha
stxv 3, vecB@toc@l(3) stxv 3, vecB@toc@l(3)
blr blr
.comm vecA, 16, 16 .comm vecA, 16, 16
.comm vecB, 16, 16 .comm vecB, 16, 16
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-LABEL: test: # CHECK-LABEL: <test>:
# CHECK-NEXT: addis 2, 12, 0 # CHECK-NEXT: addis 2, 12, 0
# CHECK-NEXT: R_PPC64_REL16_HA .TOC. # CHECK-NEXT: R_PPC64_REL16_HA .TOC.
# CHECK-NEXT: addi 2, 2, 0 # CHECK-NEXT: addi 2, 2, 0
# CHECK-NEXT: R_PPC64_REL16_LO .TOC. # CHECK-NEXT: R_PPC64_REL16_LO .TOC.
# CHECK-NEXT: addis 3, 2, 0 # CHECK-NEXT: addis 3, 2, 0
# CHECK-NEXT: R_PPC64_TOC16_HA vecA # CHECK-NEXT: R_PPC64_TOC16_HA vecA
# CHECK-NEXT: lxv 3, 0(3) # CHECK-NEXT: lxv 3, 0(3)
# CHECK-NEXT: R_PPC64_TOC16_LO_DS vecA # CHECK-NEXT: R_PPC64_TOC16_LO_DS vecA
# CHECK-NEXT: addis 3, 2, 0 # CHECK-NEXT: addis 3, 2, 0
# CHECK-NEXT: R_PPC64_TOC16_HA vecB # CHECK-NEXT: R_PPC64_TOC16_HA vecB
# CHECK-NEXT: stxv 3, 0(3) # CHECK-NEXT: stxv 3, 0(3)
# CHECK-NEXT: R_PPC64_TOC16_LO_DS vecB # CHECK-NEXT: R_PPC64_TOC16_LO_DS vecB
# CHECK-NEXT: blr # CHECK-NEXT: blr

llvm/test/MC/PowerPC/ppc64-prefix-align.s

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
addi 2, 3, 15 # 60 addi 2, 3, 15 # 60
# CHECK-BE: b8: 38 43 00 0f # CHECK-BE: b8: 38 43 00 0f
# CHECK-BE-NEXT: bc: 60 00 00 00 nop # CHECK-BE-NEXT: bc: 60 00 00 00 nop
# CHECK-BE: LAB1: # CHECK-BE: <LAB1>:
# CHECK-BE-NEXT: c0: 06 01 ff ff # CHECK-BE-NEXT: c0: 06 01 ff ff
# CHECK-BE-NEXT: c4: 38 22 ff f0 # CHECK-BE-NEXT: c4: 38 22 ff f0
# CHECK-LE: b8: 0f 00 43 38 # CHECK-LE: b8: 0f 00 43 38
# CHECK-LE-NEXT: bc: 00 00 00 60 nop # CHECK-LE-NEXT: bc: 00 00 00 60 nop
# CHECK-LE: LAB1: # CHECK-LE: <LAB1>:
# CHECK-LE-NEXT: c0: ff ff 01 06 # CHECK-LE-NEXT: c0: ff ff 01 06
# CHECK-LE-NEXT: c4: f0 ff 22 38 # CHECK-LE-NEXT: c4: f0 ff 22 38
LAB1: paddi 1, 2, 8589934576, 0 LAB1: paddi 1, 2, 8589934576, 0
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0
addi 2, 3, 15 # 60 addi 2, 3, 15 # 60
# CHECK-BE: f8: 38 43 00 0f # CHECK-BE: f8: 38 43 00 0f
# CHECK-BE: LAB2: # CHECK-BE: <LAB2>:
# CHECK-BE-NEXT: fc: 60 00 00 00 nop # CHECK-BE-NEXT: fc: 60 00 00 00 nop
# CHECK-BE-NEXT: 100: 06 01 ff ff # CHECK-BE-NEXT: 100: 06 01 ff ff
# CHECK-BE-NEXT: 104: 38 22 ff f0 # CHECK-BE-NEXT: 104: 38 22 ff f0
# CHECK-LE: f8: 0f 00 43 38 # CHECK-LE: f8: 0f 00 43 38
# CHECK-LE: LAB2: # CHECK-LE: <LAB2>:
# CHECK-LE-NEXT: fc: 00 00 00 60 nop # CHECK-LE-NEXT: fc: 00 00 00 60 nop
# CHECK-LE-NEXT: 100: ff ff 01 06 # CHECK-LE-NEXT: 100: ff ff 01 06
# CHECK-LE-NEXT: 104: f0 ff 22 38 # CHECK-LE-NEXT: 104: f0 ff 22 38
LAB2: LAB2:
paddi 1, 2, 8589934576, 0 paddi 1, 2, 8589934576, 0

llvm/test/MC/RISCV/option-mix.s

Show All 15 Lines
# evaluate the correct value for local symbols in such a situation. # evaluate the correct value for local symbols in such a situation.
.option push .option push
.option norelax .option norelax
la a0, a_symbol la a0, a_symbol
.option pop .option pop
la a1, another_symbol la a1, another_symbol
# ASM-LABEL: .Lpcrel_hi0: # ASM-LABEL: .Lpcrel_hi0{{>?}}:
# ASM-NEXT: auipc a0, %pcrel_hi(a_symbol) # ASM-NEXT: auipc a0, %pcrel_hi(a_symbol)
# ASM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0) # ASM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
# ASM-LABEL: .Lpcrel_hi1: # ASM-LABEL: .Lpcrel_hi1{{>?}}:
# ASM-NEXT: auipc a1, %pcrel_hi(another_symbol) # ASM-NEXT: auipc a1, %pcrel_hi(another_symbol)
# ASM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1) # ASM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
# DISASM-LABEL: .Lpcrel_hi0: # DISASM-LABEL: <.Lpcrel_hi0>:
# DISASM-NEXT: auipc a0, 0 # DISASM-NEXT: auipc a0, 0
# DISASM-NEXT: addi a0, a0, 0 # DISASM-NEXT: addi a0, a0, 0
# DISASM-LABEL:.Lpcrel_hi1: # DISASM-LABEL: <.Lpcrel_hi1>:
# DISASM-NEXT: auipc a1, 0 # DISASM-NEXT: auipc a1, 0
# DISASM-NEXT: addi a1, a1, 0 # DISASM-NEXT: addi a1, a1, 0
.option push .option push
.option norelax .option norelax
1:auipc a0, %pcrel_hi(a_symbol) 1:auipc a0, %pcrel_hi(a_symbol)
addi a0, a0, %pcrel_lo(1b) addi a0, a0, %pcrel_lo(1b)
.option pop .option pop
2:auipc a1, %pcrel_hi(another_symbol) 2:auipc a1, %pcrel_hi(another_symbol)
addi a1, a1, %pcrel_lo(2b) addi a1, a1, %pcrel_lo(2b)
# ASM-LABEL: .Ltmp0: # ASM-LABEL: .Ltmp0{{>?}}:
# ASM-NEXT: auipc a0, %pcrel_hi(a_symbol) # ASM-NEXT: auipc a0, %pcrel_hi(a_symbol)
# ASM-NEXT: addi a0, a0, %pcrel_lo(.Ltmp0) # ASM-NEXT: addi a0, a0, %pcrel_lo(.Ltmp0)
# ASM-LABEL: .Ltmp1: # ASM-LABEL: .Ltmp1{{>?}}:
# ASM-NEXT: auipc a1, %pcrel_hi(another_symbol) # ASM-NEXT: auipc a1, %pcrel_hi(another_symbol)
# ASM-NEXT: addi a1, a1, %pcrel_lo(.Ltmp1) # ASM-NEXT: addi a1, a1, %pcrel_lo(.Ltmp1)
# DISASM-LABEL: .Ltmp0: # DISASM-LABEL: .Ltmp0{{>?}}:
# DISASM-NEXT: auipc a0, 0 # DISASM-NEXT: auipc a0, 0
# DISASM-NEXT: addi a0, a0, 0 # DISASM-NEXT: addi a0, a0, 0
# DISASM-LABEL: .Ltmp1: # DISASM-LABEL: .Ltmp1{{>?}}:
# DISASM-NEXT: auipc a1, 0 # DISASM-NEXT: auipc a1, 0
# DISASM-NEXT: addi a1, a1, 0 # DISASM-NEXT: addi a1, a1, 0
.option push .option push
.option norelax .option norelax
la a0, a_symbol la a0, a_symbol
.option pop .option pop
la a1, local_symbol1 la a1, local_symbol1
local_symbol1: local_symbol1:
nop nop
# ASM-LABEL: .Lpcrel_hi2: # ASM-LABEL: .Lpcrel_hi2{{>?}}:
# ASM-NEXT: auipc a0, %pcrel_hi(a_symbol) # ASM-NEXT: auipc a0, %pcrel_hi(a_symbol)
# ASM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi2) # ASM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi2)
# ASM-LABEL: .Lpcrel_hi3: # ASM-LABEL: .Lpcrel_hi3{{>?}}:
# ASM-NEXT: auipc a1, %pcrel_hi(local_symbol1) # ASM-NEXT: auipc a1, %pcrel_hi(local_symbol1)
# ASM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi3) # ASM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi3)
# DISASM-LABEL: .Lpcrel_hi2: # DISASM-LABEL: .Lpcrel_hi2{{>?}}:
# DISASM-NEXT: auipc a0, 0 # DISASM-NEXT: auipc a0, 0
# DISASM-NEXT: addi a0, a0, 0 # DISASM-NEXT: addi a0, a0, 0
# DISASM-NORELAX-NEXT: auipc a1, 0 # DISASM-NORELAX-NEXT: auipc a1, 0
# DISASM-NORELAX-NEXT: addi a1, a1, 8 # DISASM-NORELAX-NEXT: addi a1, a1, 8
# DISASM-RELAX-LABEL: .Lpcrel_hi3: # DISASM-RELAX-LABEL: .Lpcrel_hi3{{>?}}:
# DISASM-RELAX-NEXT: auipc a1, 0 # DISASM-RELAX-NEXT: auipc a1, 0
# DISASM-RELAX-NEXT: addi a1, a1, 0 # DISASM-RELAX-NEXT: addi a1, a1, 0
.option push .option push
.option norelax .option norelax
1:auipc a0, %pcrel_hi(a_symbol) 1:auipc a0, %pcrel_hi(a_symbol)
addi a0, a0, %pcrel_lo(1b) addi a0, a0, %pcrel_lo(1b)
.option pop .option pop
2:auipc a1, %pcrel_hi(local_symbol2) 2:auipc a1, %pcrel_hi(local_symbol2)
addi a1, a1, %pcrel_lo(2b) addi a1, a1, %pcrel_lo(2b)
local_symbol2: local_symbol2:
nop nop
# ASM-LABEL: .Ltmp2: # ASM-LABEL: .Ltmp2{{>?}}:
# ASM-NEXT: auipc a0, %pcrel_hi(a_symbol) # ASM-NEXT: auipc a0, %pcrel_hi(a_symbol)
# ASM-NEXT: addi a0, a0, %pcrel_lo(.Ltmp2) # ASM-NEXT: addi a0, a0, %pcrel_lo(.Ltmp2)
# ASM-LABEL: .Ltmp3: # ASM-LABEL: .Ltmp3{{>?}}:
# ASM-NEXT: auipc a1, %pcrel_hi(local_symbol2) # ASM-NEXT: auipc a1, %pcrel_hi(local_symbol2)
# ASM-NEXT: addi a1, a1, %pcrel_lo(.Ltmp3) # ASM-NEXT: addi a1, a1, %pcrel_lo(.Ltmp3)
# DISASM-LABEL: .Ltmp2: # DISASM-LABEL: .Ltmp2{{>?}}:
# DISASM-NEXT: auipc a0, 0 # DISASM-NEXT: auipc a0, 0
# DISASM-NEXT: addi a0, a0, 0 # DISASM-NEXT: addi a0, a0, 0
# DISASM-NORELAX-NEXT: auipc a1, 0 # DISASM-NORELAX-NEXT: auipc a1, 0
# DISASM-NORELAX-NEXT: addi a1, a1, 8 # DISASM-NORELAX-NEXT: addi a1, a1, 8
# DISASM-RELAX-LABEL: .Ltmp3: # DISASM-RELAX-LABEL: .Ltmp3{{>?}}:
# DISASM-RELAX-NEXT: auipc a1, 0 # DISASM-RELAX-NEXT: auipc a1, 0
# DISASM-RELAX-NEXT: addi a1, a1, 0 # DISASM-RELAX-NEXT: addi a1, a1, 0

llvm/test/MC/Sparc/sparc-tls-relocations.s

Show All 13 Lines
! REL: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LE_LOX10 Local 0x0 ! REL: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LE_LOX10 Local 0x0
! REL: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_HIX22 Local 0x0 ! REL: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_HIX22 Local 0x0
! REL: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_HI22 Local 0x0 ! REL: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_HI22 Local 0x0
! REL: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_LO10 Local 0x0 ! REL: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_LO10 Local 0x0
! REL: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_LOX10 Local 0x0 ! REL: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_LOX10 Local 0x0
! REL: ] ! REL: ]
! OBJDUMP: foo: ! OBJDUMP: <foo>:
foo: foo:
! Here we use two different sequences to get the address of a static TLS variable 'Local' ! Here we use two different sequences to get the address of a static TLS variable 'Local'
! (note - there is no intent to have valid assembler function here, ! (note - there is no intent to have valid assembler function here,
! we just check how TLS relocations are emitted) ! we just check how TLS relocations are emitted)
! !
! Sequence for Local Executable model: ! Sequence for Local Executable model:
! LE_HIX22/LE_LOX10 ! LE_HIX22/LE_LOX10
▲ Show 20 Lines • Show All 126 Lines • Show Last 20 Lines

llvm/test/MC/SystemZ/directive-insn.s

Show All 9 Lines
#CHECK: a7 18 12 34 lhi %r1, 4660 #CHECK: a7 18 12 34 lhi %r1, 4660
.insn ri,0xa7080000,%r1,0x1234 .insn ri,0xa7080000,%r1,0x1234
# GAS considers this instruction's immediate operand to be PC relative. # GAS considers this instruction's immediate operand to be PC relative.
#CHECK: ec 12 00 06 00 76 crj %r1, %r2, 0, 0x12 #CHECK: ec 12 00 06 00 76 crj %r1, %r2, 0, 0x12
.insn rie,0xec0000000076,%r1,%r2,12 .insn rie,0xec0000000076,%r1,%r2,12
#CHECK: ec 12 00 03 00 64 cgrj %r1, %r2, 0, 0x12 #CHECK: ec 12 00 03 00 64 cgrj %r1, %r2, 0, 0x12
.insn rie,0xec0000000064,%r1,%r2,label.rie .insn rie,0xec0000000064,%r1,%r2,label.rie
#CHECK: label.rie: #CHECK: <label.rie>:
label.rie: label.rie:
# GAS considers this instruction's immediate operand to be PC relative. # GAS considers this instruction's immediate operand to be PC relative.
#CHECK: c6 1d 00 00 00 06 crl %r1, 0x1e #CHECK: c6 1d 00 00 00 06 crl %r1, 0x1e
.insn ril,0xc60d00000000,%r1,12 .insn ril,0xc60d00000000,%r1,12
#CHECK: c6 18 00 00 00 03 cgrl %r1, 0x1e #CHECK: c6 18 00 00 00 03 cgrl %r1, 0x1e
.insn ril,0xc60800000000,%r1,label.ril .insn ril,0xc60800000000,%r1,label.ril
#CHECK: label.ril: #CHECK: <label.ril>:
label.ril: label.ril:
#CHECK: c2 2b 80 00 00 00 alfi %r2, 2147483648 #CHECK: c2 2b 80 00 00 00 alfi %r2, 2147483648
.insn rilu,0xc20b00000000,%r2,0x80000000 .insn rilu,0xc20b00000000,%r2,0x80000000
#CHECK: ec 1c f0 a0 34 fc cgible %r1, 52, 160(%r15) #CHECK: ec 1c f0 a0 34 fc cgible %r1, 52, 160(%r15)
.insn ris,0xec00000000fc,%r1,0x34,0xc,160(%r15) .insn ris,0xec00000000fc,%r1,0x34,0xc,160(%r15)
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#CHECK: ba 01 f0 a0 cs %r0, %r1, 160(%r15) #CHECK: ba 01 f0 a0 cs %r0, %r1, 160(%r15)
.insn rs,0xba000000,%r0,%r1,160(%r15) .insn rs,0xba000000,%r0,%r1,160(%r15)
# GAS considers this instruction's immediate operand to be PC relative. # GAS considers this instruction's immediate operand to be PC relative.
#CHECK: 84 13 00 04 brxh %r1, %r3, 0x4a #CHECK: 84 13 00 04 brxh %r1, %r3, 0x4a
.insn rsi,0x84000000,%r1,%r3,8 .insn rsi,0x84000000,%r1,%r3,8
#CHECK: 84 13 00 02 brxh %r1, %r3, 0x4a #CHECK: 84 13 00 02 brxh %r1, %r3, 0x4a
.insn rsi,0x84000000,%r1,%r3,label.rsi .insn rsi,0x84000000,%r1,%r3,label.rsi
#CHECK: label.rsi: #CHECK: <label.rsi>:
label.rsi: label.rsi:
# RSE formats are short displacement versions of the RSY formats. # RSE formats are short displacement versions of the RSY formats.
#CHECK: eb 12 f0 a0 00 f8 laa %r1, %r2, 160(%r15) #CHECK: eb 12 f0 a0 00 f8 laa %r1, %r2, 160(%r15)
.insn rse,0xeb00000000f8,%r1,%r2,160(%r15) .insn rse,0xeb00000000f8,%r1,%r2,160(%r15)
#CHECK: eb 12 f3 45 12 30 csg %r1, %r2, 74565(%r15) #CHECK: eb 12 f3 45 12 30 csg %r1, %r2, 74565(%r15)
.insn rsy,0xeb0000000030,%r1,%r2,74565(%r15) .insn rsy,0xeb0000000030,%r1,%r2,74565(%r15)
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llvm/test/MC/WebAssembly/objdump.s

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.functype test1 (i32, i64) -> (i32) .functype test1 (i32, i64) -> (i32)
.local i32, i64, exnref .local i32, i64, exnref
local.get 3 local.get 3
end_function end_function
# CHECK-LABEL: CODE: # CHECK-LABEL: CODE:
# CHECK: # 2 functions in section. # CHECK: # 2 functions in section.
# CHECK-LABEL: test0: # CHECK-LABEL: <test0>:
# CHECK-NEXT: .local f32, f64, v128, v128 # CHECK-NEXT: .local f32, f64, v128, v128
# CHECK-NEXT: 9: 20 02 local.get 2 # CHECK-NEXT: 9: 20 02 local.get 2
# CHECK-NEXT: b: 0b end # CHECK-NEXT: b: 0b end
# CHECK-LABEL: test1: # CHECK-LABEL: <test1>:
# CHECK-NEXT: .local i32, i64, exnref # CHECK-NEXT: .local i32, i64, exnref
# CHECK-NEXT: 14: 20 03 local.get 3 # CHECK-NEXT: 14: 20 03 local.get 3
# CHECK-NEXT: 16: 0b end # CHECK-NEXT: 16: 0b end

llvm/test/MC/X86/AlignedBundling/labeloffset.s

# RUN: llvm-mc -triple=i686-linux -filetype=obj %s -o - | \ # RUN: llvm-mc -triple=i686-linux -filetype=obj %s -o - | \
# RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s # RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s
# RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - | \ # RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - | \
# RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s # RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s
# RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - | \ # RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - | \
# RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s # RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s
.bundle_align_mode 5 .bundle_align_mode 5
.text .text
.globl main .globl main
.align 32, 0x90 .align 32, 0x90
.type main,@function .type main,@function
main: # @main main: # @main
# CHECK-LABEL: main: # CHECK-LABEL: <main>:
# Call + pop sequence for determining the PIC base. # Call + pop sequence for determining the PIC base.
.bundle_lock align_to_end .bundle_lock align_to_end
calll .L0$pb calll .L0$pb
.bundle_unlock .bundle_unlock
.L0$pb: .L0$pb:
popl %eax popl %eax
# CHECK: 20: popl # CHECK: 20: popl
# 26 bytes of instructions between the pop and the use of the pic base symbol. # 26 bytes of instructions between the pop and the use of the pic base symbol.
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foo: foo:
inc %eax inc %eax
tmp3: tmp3:
.rodata .rodata
.type obj,@object .type obj,@object
.comm obj,4,4 .comm obj,4,4
.section .text.foo .section .text.foo
inc %eax inc %eax
# CHECK: tmp3: # CHECK: <tmp3>:
# CHECK-NEXT: 1: incl # CHECK-NEXT: 1: incl

llvm/test/MC/X86/AlignedBundling/nesting.s

# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
# Will be bundle-aligning to 16 byte boundaries # Will be bundle-aligning to 16 byte boundaries
.bundle_align_mode 4 .bundle_align_mode 4
.text .text
# CHECK-LABEL: foo: # CHECK-LABEL: <foo>:
.type foo,@function .type foo,@function
foo: foo:
# Test that bundle alignment mode can be set more than once. # Test that bundle alignment mode can be set more than once.
.bundle_align_mode 4 .bundle_align_mode 4
# Each of these callq instructions is 5 bytes long # Each of these callq instructions is 5 bytes long
callq bar callq bar
callq bar callq bar
.bundle_lock .bundle_lock
.bundle_lock .bundle_lock
callq bar callq bar
callq bar callq bar
.bundle_unlock .bundle_unlock
.bundle_unlock .bundle_unlock
# CHECK: 10: callq {{.*}} <bar> # CHECK: 10: callq {{.*}} <bar>
# CHECK-NEXT: 15: callq {{.*}} <bar> # CHECK-NEXT: 15: callq {{.*}} <bar>
.p2align 4 .p2align 4
# CHECK-LABEL: bar: # CHECK-LABEL: <bar>:
.type bar,@function .type bar,@function
bar: bar:
callq foo callq foo
callq foo callq foo
# Check that the callqs get bundled together, and that the whole group is # Check that the callqs get bundled together, and that the whole group is
# align_to_end # align_to_end
.bundle_lock .bundle_lock
callq bar callq bar
.bundle_lock align_to_end .bundle_lock align_to_end
callq bar callq bar
.bundle_unlock .bundle_unlock
.bundle_unlock .bundle_unlock
# CHECK: 36: callq {{.*}} <bar> # CHECK: 36: callq {{.*}} <bar>
# CHECK-NEXT: 3b: callq {{.*}} <bar> # CHECK-NEXT: 3b: callq {{.*}} <bar>
# CHECK-LABEL: baz: # CHECK-LABEL: <baz>:
.type baz,@function .type baz,@function
baz: baz:
callq foo callq foo
callq foo callq foo
# Check that the callqs get bundled together, and that the whole group is # Check that the callqs get bundled together, and that the whole group is
# align_to_end (with the outer directive marked align_to_end) # align_to_end (with the outer directive marked align_to_end)
.bundle_lock align_to_end .bundle_lock align_to_end
callq bar callq bar
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llvm/test/MC/X86/align-branch-32-1a.s

# Check NOP padding is disabled before instruction that has variant symbol operand. # Check NOP padding is disabled before instruction that has variant symbol operand.
# RUN: llvm-mc -filetype=obj -triple i386-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=call %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple i386-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=call %s | llvm-objdump -d - | FileCheck %s
# CHECK: 00000000 foo: # CHECK: 00000000 <foo>:
# CHECK-COUNT-5: : 64 a3 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-5: : 64 a3 01 00 00 00 movl %eax, %fs:1
# CHECK: 1e: e8 fc ff ff ff calll {{.*}} # CHECK: 1e: e8 fc ff ff ff calll {{.*}}
# CHECK-COUNT-4: : 64 a3 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-4: : 64 a3 01 00 00 00 movl %eax, %fs:1
# CHECK: 3b: 55 pushl %ebp # CHECK: 3b: 55 pushl %ebp
# CHECK-NEXT: 3c: ff 91 00 00 00 00 calll *(%ecx) # CHECK-NEXT: 3c: ff 91 00 00 00 00 calll *(%ecx)
# CHECK-COUNT-4: : 64 a3 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-4: : 64 a3 01 00 00 00 movl %eax, %fs:1
# CHECK: 5a: c1 e9 02 shrl $2, %ecx # CHECK: 5a: c1 e9 02 shrl $2, %ecx
# CHECK-NEXT: 5d: 55 pushl %ebp # CHECK-NEXT: 5d: 55 pushl %ebp
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llvm/test/MC/X86/align-branch-64-1a.s

# Check only fused conditional jumps, conditional jumps and unconditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp # Check only fused conditional jumps, conditional jumps and unconditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp %p/Inputs/align-branch-64-1.s -o %t1 && llvm-objdump -d %t1 | FileCheck %s # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp %p/Inputs/align-branch-64-1.s -o %t1 && llvm-objdump -d %t1 | FileCheck %s
# Check that -x86-branches-within-32B-boundaries matches the above command line # Check that -x86-branches-within-32B-boundaries matches the above command line
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-branches-within-32B-boundaries %p/Inputs/align-branch-64-1.s -o %t2 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-branches-within-32B-boundaries %p/Inputs/align-branch-64-1.s -o %t2
# RUN: cmp %t1 %t2 # RUN: cmp %t1 %t2
# Check no branches is aligned with option --x86-align-branch-boundary=0 # Check no branches is aligned with option --x86-align-branch-boundary=0
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=0 --x86-align-branch=fused+jcc+jmp %p/Inputs/align-branch-64-1.s | llvm-objdump -d - > %t3 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=0 --x86-align-branch=fused+jcc+jmp %p/Inputs/align-branch-64-1.s | llvm-objdump -d - > %t3
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown %p/Inputs/align-branch-64-1.s | llvm-objdump -d - > %t4 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown %p/Inputs/align-branch-64-1.s | llvm-objdump -d - > %t4
# RUN: cmp %t3 %t4 # RUN: cmp %t3 %t4
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 18: 48 39 c5 cmpq %rax, %rbp # CHECK: 18: 48 39 c5 cmpq %rax, %rbp
# CHECK-NEXT: 1b: 31 c0 xorl %eax, %eax # CHECK-NEXT: 1b: 31 c0 xorl %eax, %eax
# CHECK-COUNT-3: : 90 nop # CHECK-COUNT-3: : 90 nop
# CHECK: 20: 48 39 c5 cmpq %rax, %rbp # CHECK: 20: 48 39 c5 cmpq %rax, %rbp
# CHECK-NEXT: 23: 74 5d je {{.*}} # CHECK-NEXT: 23: 74 5d je {{.*}}
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 3d: 31 c0 xorl %eax, %eax # CHECK: 3d: 31 c0 xorl %eax, %eax
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llvm/test/MC/X86/align-branch-64-1b.s

# Check only fused conditional jumps and conditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc # Check only fused conditional jumps and conditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc %p/Inputs/align-branch-64-1.s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc %p/Inputs/align-branch-64-1.s | llvm-objdump -d - | FileCheck %s
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-NEXT: 18: 48 39 c5 cmpq %rax, %rbp # CHECK-NEXT: 18: 48 39 c5 cmpq %rax, %rbp
# CHECK-NEXT: 1b: 31 c0 xorl %eax, %eax # CHECK-NEXT: 1b: 31 c0 xorl %eax, %eax
# CHECK-COUNT-3: : 90 nop # CHECK-COUNT-3: : 90 nop
# CHECK-NEXT: 20: 48 39 c5 cmpq %rax, %rbp # CHECK-NEXT: 20: 48 39 c5 cmpq %rax, %rbp
# CHECK-NEXT: 23: 74 5b je {{.*}} # CHECK-NEXT: 23: 74 5b je {{.*}}
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 3d: 31 c0 xorl %eax, %eax # CHECK: 3d: 31 c0 xorl %eax, %eax
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llvm/test/MC/X86/align-branch-64-1c.s

# Check only conditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=jcc # Check only conditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=jcc
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jcc %p/Inputs/align-branch-64-1.s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jcc %p/Inputs/align-branch-64-1.s | llvm-objdump -d - | FileCheck %s
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 18: 48 39 c5 cmpq %rax, %rbp # CHECK: 18: 48 39 c5 cmpq %rax, %rbp
# CHECK-NEXT: 1b: 31 c0 xorl %eax, %eax # CHECK-NEXT: 1b: 31 c0 xorl %eax, %eax
# CHECK-NEXT: 1d: 48 39 c5 cmpq %rax, %rbp # CHECK-NEXT: 1d: 48 39 c5 cmpq %rax, %rbp
# CHECK-NEXT: 20: 74 5b je {{.*}} # CHECK-NEXT: 20: 74 5b je {{.*}}
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 3a: 31 c0 xorl %eax, %eax # CHECK: 3a: 31 c0 xorl %eax, %eax
# CHECK-NEXT: 3c: 74 3f je {{.*}} # CHECK-NEXT: 3c: 74 3f je {{.*}}
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llvm/test/MC/X86/align-branch-64-1d.s

# Check only conditional jumps and unconditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=jcc+jmp # Check only conditional jumps and unconditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=jcc+jmp
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jcc+jmp %p/Inputs/align-branch-64-1.s | llvm-objdump -d - > %t1 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jcc+jmp %p/Inputs/align-branch-64-1.s | llvm-objdump -d - > %t1
# RUN: FileCheck --input-file=%t1 %s --check-prefixes=CHECK,SHORT-NOP # RUN: FileCheck --input-file=%t1 %s --check-prefixes=CHECK,SHORT-NOP
# Check long NOP can be emitted to align branch if the target cpu support long nop. # Check long NOP can be emitted to align branch if the target cpu support long nop.
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 -mcpu=x86-64 --x86-align-branch=jcc+jmp %p/Inputs/align-branch-64-1.s | llvm-objdump -d - >%t2 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 -mcpu=x86-64 --x86-align-branch=jcc+jmp %p/Inputs/align-branch-64-1.s | llvm-objdump -d - >%t2
# RUN: FileCheck --input-file=%t2 %s --check-prefixes=CHECK,LONG-NOP # RUN: FileCheck --input-file=%t2 %s --check-prefixes=CHECK,LONG-NOP
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 18: 48 39 c5 cmpq %rax, %rbp # CHECK: 18: 48 39 c5 cmpq %rax, %rbp
# CHECK-NEXT: 1b: 31 c0 xorl %eax, %eax # CHECK-NEXT: 1b: 31 c0 xorl %eax, %eax
# CHECK-NEXT: 1d: 48 39 c5 cmpq %rax, %rbp # CHECK-NEXT: 1d: 48 39 c5 cmpq %rax, %rbp
# CHECK-NEXT: 20: 74 5d je {{.*}} # CHECK-NEXT: 20: 74 5d je {{.*}}
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 3a: 31 c0 xorl %eax, %eax # CHECK: 3a: 31 c0 xorl %eax, %eax
# CHECK-NEXT: 3c: 74 41 je {{.*}} # CHECK-NEXT: 3c: 74 41 je {{.*}}
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llvm/test/MC/X86/align-branch-64-2a.s

# Check only indirect jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=indirect # Check only indirect jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=indirect
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=indirect %p/Inputs/align-branch-64-2.s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=indirect %p/Inputs/align-branch-64-2.s | llvm-objdump -d - | FileCheck %s
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-COUNT-2: : 89 75 f4 movl %esi, -12(%rbp) # CHECK-COUNT-2: : 89 75 f4 movl %esi, -12(%rbp)
# CHECK-COUNT-2: : 90 nop # CHECK-COUNT-2: : 90 nop
# CHECK: 20: ff e0 jmpq *%rax # CHECK: 20: ff e0 jmpq *%rax
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 3a: 89 75 f4 movl %esi, -12(%rbp) # CHECK: 3a: 89 75 f4 movl %esi, -12(%rbp)
# CHECK-NEXT: 3d: 55 pushq %rbp # CHECK-NEXT: 3d: 55 pushq %rbp
# CHECK-NEXT: 3e: ff d0 callq *%rax # CHECK-NEXT: 3e: ff d0 callq *%rax
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-NEXT: 58: 55 pushq %rbp # CHECK-NEXT: 58: 55 pushq %rbp
# CHECK-NEXT: 59: e8 00 00 00 00 callq {{.*}} # CHECK-NEXT: 59: e8 00 00 00 00 callq {{.*}}
# CHECK-COUNT-4: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-4: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 7e: ff 14 25 00 00 00 00 callq *0 # CHECK: 7e: ff 14 25 00 00 00 00 callq *0

llvm/test/MC/X86/align-branch-64-2b.s

# Check only calls are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=call # Check only calls are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=call
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=call %p/Inputs/align-branch-64-2.s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=call %p/Inputs/align-branch-64-2.s | llvm-objdump -d - | FileCheck %s
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-COUNT-2: : 89 75 f4 movl %esi, -12(%rbp) # CHECK-COUNT-2: : 89 75 f4 movl %esi, -12(%rbp)
# CHECK: 1e: ff e0 jmpq *%rax # CHECK: 1e: ff e0 jmpq *%rax
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 38: 89 75 f4 movl %esi, -12(%rbp) # CHECK: 38: 89 75 f4 movl %esi, -12(%rbp)
# CHECK-NEXT: 3b: 55 pushq %rbp # CHECK-NEXT: 3b: 55 pushq %rbp
# CHECK-NEXT: 3c: ff d0 callq *%rax # CHECK-NEXT: 3c: ff d0 callq *%rax
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 56: 55 pushq %rbp # CHECK: 56: 55 pushq %rbp
# CHECK-NEXT: 57: e8 00 00 00 00 callq {{.*}} # CHECK-NEXT: 57: e8 00 00 00 00 callq {{.*}}
# CHECK-COUNT-4: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-4: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-COUNT-4: : 90 nop # CHECK-COUNT-4: : 90 nop
# CHECK: 80: ff 14 25 00 00 00 00 callq *0 # CHECK: 80: ff 14 25 00 00 00 00 callq *0

llvm/test/MC/X86/align-branch-64-2c.s

# Check only indirect jumps and calls are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=indirect+call # Check only indirect jumps and calls are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=indirect+call
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=indirect+call %p/Inputs/align-branch-64-2.s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=indirect+call %p/Inputs/align-branch-64-2.s | llvm-objdump -d - | FileCheck %s
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-COUNT-2: : 89 75 f4 movl %esi, -12(%rbp) # CHECK-COUNT-2: : 89 75 f4 movl %esi, -12(%rbp)
# CHECK-COUNT-2: : 90 nop # CHECK-COUNT-2: : 90 nop
# CHECK: 20: ff e0 jmpq *%rax # CHECK: 20: ff e0 jmpq *%rax
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 3a: 89 75 f4 movl %esi, -12(%rbp) # CHECK: 3a: 89 75 f4 movl %esi, -12(%rbp)
# CHECK-NEXT: 3d: 55 pushq %rbp # CHECK-NEXT: 3d: 55 pushq %rbp
# CHECK-COUNT-2: : 90 nop # CHECK-COUNT-2: : 90 nop
# CHECK: 40: ff d0 callq *%rax # CHECK: 40: ff d0 callq *%rax
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 5a: 55 pushq %rbp # CHECK: 5a: 55 pushq %rbp
# CHECK-COUNT-5: : 90 nop # CHECK-COUNT-5: : 90 nop
# CHECK: 60: e8 00 00 00 00 callq {{.*}} # CHECK: 60: e8 00 00 00 00 callq {{.*}}
# CHECK-COUNT-4: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-4: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 85: ff 14 25 00 00 00 00 callq *0 # CHECK: 85: ff 14 25 00 00 00 00 callq *0

llvm/test/MC/X86/align-branch-64-3a.s

# Check NOP padding is disabled before instruction that has variant symbol operand. # Check NOP padding is disabled before instruction that has variant symbol operand.
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jmp+call %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jmp+call %s | llvm-objdump -d - | FileCheck %s
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-COUNT-2: : 48 89 e5 movq %rsp, %rbp # CHECK-COUNT-2: : 48 89 e5 movq %rsp, %rbp
# CHECK: 1e: e8 00 00 00 00 callq {{.*}} # CHECK: 1e: e8 00 00 00 00 callq {{.*}}
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 3b: 55 pushq %rbp # CHECK: 3b: 55 pushq %rbp
# CHECK-NEXT: 3c: 89 75 f4 movl %esi, -12(%rbp) # CHECK-NEXT: 3c: 89 75 f4 movl %esi, -12(%rbp)
# CHECK-NEXT: 3f: ff 15 00 00 00 00 callq *(%rip) # CHECK-NEXT: 3f: ff 15 00 00 00 00 callq *(%rip)
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
Show All 29 Lines

llvm/test/MC/X86/align-branch-64-4a.s

# Check only rets are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=ret # Check only rets are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=ret
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=ret %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=ret %s | llvm-objdump -d - | FileCheck %s
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-COUNT-2: : 48 89 e5 movq %rsp, %rbp # CHECK-COUNT-2: : 48 89 e5 movq %rsp, %rbp
# CHECK: 1e: 5a popq %rdx # CHECK: 1e: 5a popq %rdx
# CHECK-NEXT: 1f: 90 nop # CHECK-NEXT: 1f: 90 nop
# CHECK-NEXT: 20: c3 retq # CHECK-NEXT: 20: c3 retq
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 39: 89 75 f4 movl %esi, -12(%rbp) # CHECK: 39: 89 75 f4 movl %esi, -12(%rbp)
# CHECK-NEXT: 3c: 31 c0 xorl %eax, %eax # CHECK-NEXT: 3c: 31 c0 xorl %eax, %eax
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llvm/test/MC/X86/align-branch-64-5a.s

# Check no nop is inserted if no branch cross or is against the boundary # Check no nop is inserted if no branch cross or is against the boundary
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp+indirect+call+ret %s | llvm-objdump -d - > %t1 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp+indirect+call+ret %s | llvm-objdump -d - > %t1
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown %s | llvm-objdump -d - > %t2 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown %s | llvm-objdump -d - > %t2
# RUN: cmp %t1 %t2 # RUN: cmp %t1 %t2
# RUN: FileCheck --input-file=%t1 %s # RUN: FileCheck --input-file=%t1 %s
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-3: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK: 18: c1 e9 02 shrl $2, %ecx # CHECK: 18: c1 e9 02 shrl $2, %ecx
# CHECK-NEXT: 1b: 89 d1 movl %edx, %ecx # CHECK-NEXT: 1b: 89 d1 movl %edx, %ecx
# CHECK-NEXT: 1d: 75 fc jne {{.*}} # CHECK-NEXT: 1d: 75 fc jne {{.*}}
# CHECK-NEXT: 1f: 55 pushq %rbp # CHECK-NEXT: 1f: 55 pushq %rbp
# CHECK-NEXT: 20: f6 c2 02 testb $2, %dl # CHECK-NEXT: 20: f6 c2 02 testb $2, %dl
# CHECK-NEXT: 23: 75 fa jne {{.*}} # CHECK-NEXT: 23: 75 fa jne {{.*}}
# CHECK-COUNT-2: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-COUNT-2: : 64 89 04 25 01 00 00 00 movl %eax, %fs:1
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llvm/test/MC/X86/align-branch-64-6a.s

# Check option --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp+indirect+call+ret can cowork with option --mc-relax-all # Check option --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp+indirect+call+ret can cowork with option --mc-relax-all
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp+indirect+call+ret --mc-relax-all %s | llvm-objdump -d - > %t1 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp+indirect+call+ret --mc-relax-all %s | llvm-objdump -d - > %t1
# RUN: FileCheck --input-file=%t1 %s # RUN: FileCheck --input-file=%t1 %s
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-NEXT: 0: 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-NEXT: 0: 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-NEXT: 8: 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-NEXT: 8: 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-NEXT: 10: 64 89 04 25 01 00 00 00 movl %eax, %fs:1 # CHECK-NEXT: 10: 64 89 04 25 01 00 00 00 movl %eax, %fs:1
# CHECK-NEXT: 18: c1 e9 02 shrl $2, %ecx # CHECK-NEXT: 18: c1 e9 02 shrl $2, %ecx
# CHECK-NEXT: 1b: 89 d1 movl %edx, %ecx # CHECK-NEXT: 1b: 89 d1 movl %edx, %ecx
# CHECK-NEXT: 1d: 90 nop # CHECK-NEXT: 1d: 90 nop
# CHECK-NEXT: 1e: 90 nop # CHECK-NEXT: 1e: 90 nop
# CHECK-NEXT: 1f: 90 nop # CHECK-NEXT: 1f: 90 nop
Show All 37 Lines

llvm/test/MC/X86/align-branch-64-7a.s

# Check using option --x86-align-branch-boundary=16 --x86-align-branch=fused+jcc --mc-relax-all with bundle won't make code crazy # Check using option --x86-align-branch-boundary=16 --x86-align-branch=fused+jcc --mc-relax-all with bundle won't make code crazy
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=16 --x86-align-branch=fused+jcc --mc-relax-all %s | llvm-objdump -d - > %t1 # RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=16 --x86-align-branch=fused+jcc --mc-relax-all %s | llvm-objdump -d - > %t1
# RUN: FileCheck --input-file=%t1 %s # RUN: FileCheck --input-file=%t1 %s
# CHECK: 0000000000000000 foo: # CHECK: 0000000000000000 <foo>:
# CHECK-NEXT: 0: 55 pushq %rbp # CHECK-NEXT: 0: 55 pushq %rbp
# CHECK-NEXT: 1: 48 f7 c2 02 00 00 00 testq $2, %rdx # CHECK-NEXT: 1: 48 f7 c2 02 00 00 00 testq $2, %rdx
# CHECK-NEXT: 8: 0f 85 f2 ff ff ff jne {{.*}} # CHECK-NEXT: 8: 0f 85 f2 ff ff ff jne {{.*}}
# CHECK-NEXT: e: 90 nop # CHECK-NEXT: e: 90 nop
# CHECK-NEXT: f: 90 nop # CHECK-NEXT: f: 90 nop
# CHECK-NEXT: 10: 0f 8e ea ff ff ff jle {{.*}} # CHECK-NEXT: 10: 0f 8e ea ff ff ff jle {{.*}}
.text .text
Show All 10 Lines

llvm/test/MC/X86/align-branch-64-negative.s

# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=call+jmp+indirect+ret+jcc+fused %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=call+jmp+indirect+ret+jcc+fused %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
# This file includes cases which are problematic to apply automatic padding # This file includes cases which are problematic to apply automatic padding
# in the assembler. These are the examples brought up in review and # in the assembler. These are the examples brought up in review and
# discussion which motivate the need for a assembler directive to # discussion which motivate the need for a assembler directive to
# selectively enable/disable. # selectively enable/disable.
# FIXME: the checks are checking current *incorrect* behavior # FIXME: the checks are checking current *incorrect* behavior
.text .text
# In the first test, we have a label which is expected to be bound to the # In the first test, we have a label which is expected to be bound to the
# start of the call. For instance, we want to associate a fault on the call # start of the call. For instance, we want to associate a fault on the call
# target with some bit of higher level sementic. # target with some bit of higher level sementic.
# CHECK: labeled_call_test1: # CHECK-LABEL: <labeled_call_test1>:
# CHECK: 1f label_before # CHECK: 1f <label_before>:
# CHECK: 1f: nop # CHECK: 1f: nop
# CHECK: 20: callq # CHECK: 20: callq
.globl labeled_call_test1 .globl labeled_call_test1
.p2align 5 .p2align 5
labeled_call_test1: labeled_call_test1:
.rept 31 .rept 31
int3 int3
.endr .endr
label_before: label_before:
callq bar callq bar
# In the second test, we have a label which is expected to be bound to the # In the second test, we have a label which is expected to be bound to the
# end of the call. For instance, we want the to associate some data with # end of the call. For instance, we want the to associate some data with
# the return address of the call. # the return address of the call.
# CHECK: labeled_call_test2: # CHECK-LABEL: <labeled_call_test2>:
# CHECK: 5a: callq # CHECK: 5a: callq
# CHECK: 5f: nop # CHECK: 5f: nop
# CHECK: 60 label_after # CHECK: 60 <label_after>:
# CHECK: 60: jmp # CHECK: 60: jmp
.globl labeled_call_test2 .globl labeled_call_test2
.p2align 5 .p2align 5
labeled_call_test2: labeled_call_test2:
.rept 26 .rept 26
int3 int3
.endr .endr
callq bar callq bar
label_after: label_after:
jmp bar jmp bar
# Our third test is like the first w/a labeled fault, but specifically to # Our third test is like the first w/a labeled fault, but specifically to
# a fused memory comparison. This is the form produced by implicit null # a fused memory comparison. This is the form produced by implicit null
# checks for instance. # checks for instance.
# CHECK: implicit_null_check: # CHECK-LABEL: <implicit_null_check>:
# CHECK: 9f fault_addr # CHECK: 9f <fault_addr>:
# CHECK: 9f: nop # CHECK: 9f: nop
# CHECK: a0: cmpq # CHECK: a0: cmpq
.globl implicit_null_check .globl implicit_null_check
.p2align 5 .p2align 5
implicit_null_check: implicit_null_check:
.rept 31 .rept 31
int3 int3
.endr .endr
fault_addr: fault_addr:
cmpq (%rsi), %rdi cmpq (%rsi), %rdi
jne bar jne bar
.p2align 4 .p2align 4
.type bar,@function .type bar,@function
bar: bar:
retq retq

llvm/test/MC/X86/align-branch-64.s

# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=call+jmp+indirect+ret+jcc %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=call+jmp+indirect+ret+jcc %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
# These tests are checking the basic cases for each instructions, and a # These tests are checking the basic cases for each instructions, and a
# bit of the alignment checking logic itself. Fused instruction cases are # bit of the alignment checking logic itself. Fused instruction cases are
# excluded, as are details of argument parsing. # excluded, as are details of argument parsing.
# instruction sizes for reference: # instruction sizes for reference:
# callq is 5 bytes long # callq is 5 bytes long
# int3 is 1 byte # int3 is 1 byte
# jmp <near-label> is 2 bytes # jmp <near-label> is 2 bytes
# jmp <far-label> is 5 bytes # jmp <far-label> is 5 bytes
# ret N is 2 bytes # ret N is 2 bytes
# Next couple tests are checking the edge cases on the alignment computation # Next couple tests are checking the edge cases on the alignment computation
.text .text
# CHECK: test1: # CHECK: <test1>:
# CHECK: 20: callq # CHECK: 20: callq
.globl test1 .globl test1
.p2align 5 .p2align 5
test1: test1:
.rept 29 .rept 29
int3 int3
.endr .endr
callq bar callq bar
# CHECK: test2: # CHECK: <test2>:
# CHECK: 60: callq # CHECK: 60: callq
.globl test2 .globl test2
.p2align 5 .p2align 5
test2: test2:
.rept 31 .rept 31
int3 int3
.endr .endr
callq bar callq bar
# CHECK: test3: # CHECK: <test3>:
# CHECK: a0: callq # CHECK: a0: callq
.globl test3 .globl test3
.p2align 5 .p2align 5
test3: test3:
.rept 27 .rept 27
int3 int3
.endr .endr
callq bar callq bar
# next couple check instruction type coverage # next couple check instruction type coverage
# CHECK: test_jmp: # CHECK: <test_jmp>:
# CHECK: e0: jmp # CHECK: e0: jmp
.globl test_jmp .globl test_jmp
.p2align 5 .p2align 5
test_jmp: test_jmp:
.rept 31 .rept 31
int3 int3
.endr .endr
jmp bar jmp bar
# CHECK: test_ret: # CHECK: <test_ret>:
# CHECK: 120: retq # CHECK: 120: retq
.globl test_ret .globl test_ret
.p2align 5 .p2align 5
test_ret: test_ret:
.rept 31 .rept 31
int3 int3
.endr .endr
retq $0 retq $0
# check a case with a relaxable instruction # check a case with a relaxable instruction
# CHECK: test_jmp_far: # CHECK: <test_jmp_far>:
# CHECK: 160: jmp # CHECK: 160: jmp
.globl test_jmp_far .globl test_jmp_far
.p2align 5 .p2align 5
test_jmp_far: test_jmp_far:
.rept 31 .rept 31
int3 int3
.endr .endr
jmp baz jmp baz
# CHECK: test_jcc: # CHECK: <test_jcc>:
# CHECK: 1a0: jne # CHECK: 1a0: jne
.globl test_jcc .globl test_jcc
.p2align 5 .p2align 5
test_jcc: test_jcc:
.rept 31 .rept 31
int3 int3
.endr .endr
jne bar jne bar
# CHECK: test_indirect: # CHECK: <test_indirect>:
# CHECK: 1e0: jmp # CHECK: 1e0: jmp
.globl test_indirect .globl test_indirect
.p2align 5 .p2align 5
test_indirect: test_indirect:
.rept 31 .rept 31
int3 int3
.endr .endr
jmpq *(%rax) jmpq *(%rax)
.p2align 4 .p2align 4
.type bar,@function .type bar,@function
bar: bar:
retq retq
# CHECK: test_pad_via_relax: # CHECK: <test_pad_via_relax>:
# CHECK: 200: testq # CHECK: 200: testq
# CHECK: 203: jne # CHECK: 203: jne
# CHECK: 209: int3 # CHECK: 209: int3
# note 6 byte jne which could be a 2 byte jne, but is instead # note 6 byte jne which could be a 2 byte jne, but is instead
# expanded for padding purposes # expanded for padding purposes
# CHECK-NOT: nop # CHECK-NOT: nop
# CHECK: 220: callq # CHECK: 220: callq
.global test_pad_via_relax .global test_pad_via_relax
.p2align 5 .p2align 5
test_pad_via_relax: test_pad_via_relax:
testq %rax, %rax testq %rax, %rax
jnz bar jnz bar
.rept 23 .rept 23
int3 int3
.endr .endr
callq bar callq bar
# This case looks really tempting to pad, but doing so for the call causes # This case looks really tempting to pad, but doing so for the call causes
# the jmp to be misaligned. # the jmp to be misaligned.
# CHECK: test_pad_via_relax_neg1: # CHECK: <test_pad_via_relax_neg1>:
# CHECK: 240: int3 # CHECK: 240: int3
# CHECK: 25a: testq # CHECK: 25a: testq
# CHECK: 25d: jne # CHECK: 25d: jne
# CHECK: 25f: nop # CHECK: 25f: nop
# CHECK: 260: callq # CHECK: 260: callq
.global test_pad_via_relax_neg1 .global test_pad_via_relax_neg1
.p2align 5 .p2align 5
test_pad_via_relax_neg1: test_pad_via_relax_neg1:
.rept 26 .rept 26
int3 int3
.endr .endr
testq %rax, %rax testq %rax, %rax
jnz bar jnz bar
callq bar callq bar
# Same as previous, but without fusion # Same as previous, but without fusion
# CHECK: test_pad_via_relax_neg2: # CHECK: <test_pad_via_relax_neg2>:
# CHECK: 280: int3 # CHECK: 280: int3
# CHECK: 29d: jmp # CHECK: 29d: jmp
# CHECK: 29f: nop # CHECK: 29f: nop
# CHECK: 2a0: callq # CHECK: 2a0: callq
.global test_pad_via_relax_neg2 .global test_pad_via_relax_neg2
.p2align 5 .p2align 5
test_pad_via_relax_neg2: test_pad_via_relax_neg2:
.rept 29 .rept 29
Show All 12 Lines

llvm/test/MC/X86/align-via-relaxation.s

Show All 24 Lines# RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu %s | llvm-objdump -d --section=.text - | FileCheck %s
jmp foo jmp foo
.p2align 5 .p2align 5
int3 int3
foo: foo:
ret ret
# Check that we're not shifting aroudn the offsets of labels - doing # Check that we're not shifting aroudn the offsets of labels - doing
# that would require a further round of relaxation # that would require a further round of relaxation
# CHECK: bar: # CHECK: <bar>:
# CHECK: 22: eb fe jmp -2 <bar> # CHECK: 22: eb fe jmp -2 <bar>
# CHECK: 24: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:(%rax,%rax) # CHECK: 24: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:(%rax,%rax)
# CHECK: 2e: 66 90 nop # CHECK: 2e: 66 90 nop
# CHECK: 30: 0f 0b ud2 # CHECK: 30: 0f 0b ud2
bar: bar:
jmp bar jmp bar
nobypass: nobypass:
.p2align 4 .p2align 4
ud2 ud2
# Canonical toy loop to show benefit - we can align the loop header with # Canonical toy loop to show benefit - we can align the loop header with
# fewer nops by relaxing the branch, even though we don't need to # fewer nops by relaxing the branch, even though we don't need to
# CHECK: loop_preheader: # CHECK: <loop_preheader>:
# CHECK: 45: 48 85 c0 testq %rax, %rax # CHECK: 45: 48 85 c0 testq %rax, %rax
# CHECK: 48: 0f 8e 22 00 00 00 jle 34 <loop_exit> # CHECK: 48: 0f 8e 22 00 00 00 jle 34 <loop_exit>
# CHECK: 4e: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:(%rax,%rax) # CHECK: 4e: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:(%rax,%rax)
# CHECK: 58: 0f 1f 84 00 00 00 00 00 nopl (%rax,%rax) # CHECK: 58: 0f 1f 84 00 00 00 00 00 nopl (%rax,%rax)
# CHECK: loop_header: # CHECK: <loop_header>:
# CHECK: 60: 48 83 e8 01 subq $1, %rax # CHECK: 60: 48 83 e8 01 subq $1, %rax
# CHECK: 64: 48 85 c0 testq %rax, %rax # CHECK: 64: 48 85 c0 testq %rax, %rax
# CHECK: 67: 7e 07 jle 7 <loop_exit> # CHECK: 67: 7e 07 jle 7 <loop_exit>
# CHECK: 69: e9 f2 ff ff ff jmp -14 <loop_header> # CHECK: 69: e9 f2 ff ff ff jmp -14 <loop_header>
# CHECK: 6e: 66 90 nop # CHECK: 6e: 66 90 nop
# CHECK: loop_exit: # CHECK: <loop_exit>:
# CHECK: 70: c3 retq # CHECK: 70: c3 retq
.p2align 5 .p2align 5
.skip 5 .skip 5
loop_preheader: loop_preheader:
testq %rax, %rax testq %rax, %rax
jle loop_exit jle loop_exit
.p2align 5 .p2align 5
loop_header: loop_header:
subq $1, %rax subq $1, %rax
testq %rax, %rax testq %rax, %rax
jle loop_exit jle loop_exit
jmp loop_header jmp loop_header
.p2align 4 .p2align 4
loop_exit: loop_exit:
ret ret

llvm/test/MC/X86/code16-32-64.s

# RUN: llvm-mc %s -triple x86_64-linux-gnu -filetype=obj -o - | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc %s -triple x86_64-linux-gnu -filetype=obj -o - | llvm-objdump -d - | FileCheck %s
# RUN: llvm-mc %s -triple x86_64-windows-msvc -filetype=obj -o - | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc %s -triple x86_64-windows-msvc -filetype=obj -o - | llvm-objdump -d - | FileCheck %s
# RUN: llvm-mc %s -triple x86_64-apple-macos -filetype=obj -o - | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc %s -triple x86_64-apple-macos -filetype=obj -o - | llvm-objdump -d - | FileCheck %s
.text .text
.global foo .global foo
foo: foo:
.code64 .code64
movl (%eax), %eax movl (%eax), %eax
.code32 .code32
movl (%eax), %eax movl (%eax), %eax
.code16 .code16
movl (%eax), %eax movl (%eax), %eax
.code64 .code64
retq retq
# CHECK: foo: # CHECK: <foo>:
# CHECK-NEXT: 67 8b 00 movl (%eax), %eax # CHECK-NEXT: 67 8b 00 movl (%eax), %eax
# CHECK-NEXT: 8b 00 movl (%rax), %eax # CHECK-NEXT: 8b 00 movl (%rax), %eax
# CHECK-NEXT: 67 66 8b 00 movw (%eax), %ax # CHECK-NEXT: 67 66 8b 00 movw (%eax), %ax
# CHECK-NEXT: c3 retq # CHECK-NEXT: c3 retq

llvm/test/MC/X86/disassemble-zeroes.s

// RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown %s -o %t // RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown %s -o %t
// RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=NODISASM // RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=NODISASM
// The exact rules of skipping the bytes you can find in the code. // The exact rules of skipping the bytes you can find in the code.
// This test checks that we follow these rules and can force // This test checks that we follow these rules and can force
// dissasembly of zero blocks with the -z and --disassemble-zeroes options. // dissasembly of zero blocks with the -z and --disassemble-zeroes options.
// NODISASM: 0000000000000000 main: // NODISASM: 0000000000000000 <main>:
// NODISASM-NEXT: 0: 00 00 addb %al, (%rax) // NODISASM-NEXT: 0: 00 00 addb %al, (%rax)
// NODISASM-NEXT: 2: 00 00 addb %al, (%rax) // NODISASM-NEXT: 2: 00 00 addb %al, (%rax)
// NODISASM-NEXT: 4: 00 00 addb %al, (%rax) // NODISASM-NEXT: 4: 00 00 addb %al, (%rax)
// NODISASM-NEXT: 6: 00 90 00 00 00 00 addb %dl, (%rax) // NODISASM-NEXT: 6: 00 90 00 00 00 00 addb %dl, (%rax)
// NODISASM-NEXT: ... // NODISASM-NEXT: ...
// NODISASM-NEXT: 20: 90 nop // NODISASM-NEXT: 20: 90 nop
// NODISASM-NEXT: ... // NODISASM-NEXT: ...
// NODISASM: 0000000000000031 foo: // NODISASM: 0000000000000031 <foo>:
// NODISASM-NEXT: 31: 00 00 addb %al, (%rax) // NODISASM-NEXT: 31: 00 00 addb %al, (%rax)
// NODISASM-NEXT: 33: 00 00 addb %al, (%rax) // NODISASM-NEXT: 33: 00 00 addb %al, (%rax)
// NODISASM: 0000000000000035 bar: // NODISASM: 0000000000000035 <bar>:
// NODISASM-NEXT: ... // NODISASM-NEXT: ...
// Check that with -z we disassemble blocks of zeroes. // Check that with -z we disassemble blocks of zeroes.
// RUN: llvm-objdump -d -z %t | FileCheck %s --check-prefix=DISASM // RUN: llvm-objdump -d -z %t | FileCheck %s --check-prefix=DISASM
// DISASM: 0000000000000000 main: // DISASM: 0000000000000000 <main>:
// DISASM-NEXT: 0: 00 00 addb %al, (%rax) // DISASM-NEXT: 0: 00 00 addb %al, (%rax)
// DISASM-NEXT: 2: 00 00 addb %al, (%rax) // DISASM-NEXT: 2: 00 00 addb %al, (%rax)
// DISASM-NEXT: 4: 00 00 addb %al, (%rax) // DISASM-NEXT: 4: 00 00 addb %al, (%rax)
// DISASM-NEXT: 6: 00 90 00 00 00 00 addb %dl, (%rax) // DISASM-NEXT: 6: 00 90 00 00 00 00 addb %dl, (%rax)
// DISASM-NEXT: c: 00 00 addb %al, (%rax) // DISASM-NEXT: c: 00 00 addb %al, (%rax)
// DISASM-NEXT: e: 00 00 addb %al, (%rax) // DISASM-NEXT: e: 00 00 addb %al, (%rax)
// DISASM-NEXT: 10: 00 00 addb %al, (%rax) // DISASM-NEXT: 10: 00 00 addb %al, (%rax)
// DISASM-NEXT: 12: 00 00 addb %al, (%rax) // DISASM-NEXT: 12: 00 00 addb %al, (%rax)
// DISASM-NEXT: 14: 00 00 addb %al, (%rax) // DISASM-NEXT: 14: 00 00 addb %al, (%rax)
// DISASM-NEXT: 16: 00 00 addb %al, (%rax) // DISASM-NEXT: 16: 00 00 addb %al, (%rax)
// DISASM-NEXT: 18: 00 00 addb %al, (%rax) // DISASM-NEXT: 18: 00 00 addb %al, (%rax)
// DISASM-NEXT: 1a: 00 00 addb %al, (%rax) // DISASM-NEXT: 1a: 00 00 addb %al, (%rax)
// DISASM-NEXT: 1c: 00 00 addb %al, (%rax) // DISASM-NEXT: 1c: 00 00 addb %al, (%rax)
// DISASM-NEXT: 1e: 00 00 addb %al, (%rax) // DISASM-NEXT: 1e: 00 00 addb %al, (%rax)
// DISASM-NEXT: 20: 90 nop // DISASM-NEXT: 20: 90 nop
// DISASM-NEXT: 21: 00 00 addb %al, (%rax) // DISASM-NEXT: 21: 00 00 addb %al, (%rax)
// DISASM-NEXT: 23: 00 00 addb %al, (%rax) // DISASM-NEXT: 23: 00 00 addb %al, (%rax)
// DISASM-NEXT: 25: 00 00 addb %al, (%rax) // DISASM-NEXT: 25: 00 00 addb %al, (%rax)
// DISASM-NEXT: 27: 00 00 addb %al, (%rax) // DISASM-NEXT: 27: 00 00 addb %al, (%rax)
// DISASM-NEXT: 29: 00 00 addb %al, (%rax) // DISASM-NEXT: 29: 00 00 addb %al, (%rax)
// DISASM-NEXT: 2b: 00 00 addb %al, (%rax) // DISASM-NEXT: 2b: 00 00 addb %al, (%rax)
// DISASM-NEXT: 2d: 00 00 addb %al, (%rax) // DISASM-NEXT: 2d: 00 00 addb %al, (%rax)
// DISASM-NEXT: 2f: 00 00 addb %al, (%rax) // DISASM-NEXT: 2f: 00 00 addb %al, (%rax)
// DISASM: 0000000000000031 foo: // DISASM: 0000000000000031 <foo>:
// DISASM-NEXT: 31: 00 00 addb %al, (%rax) // DISASM-NEXT: 31: 00 00 addb %al, (%rax)
// DISASM-NEXT: 33: 00 00 addb %al, (%rax) // DISASM-NEXT: 33: 00 00 addb %al, (%rax)
// DISASM: 0000000000000035 bar: // DISASM: 0000000000000035 <bar>:
// DISASM-NEXT: 35: 00 00 addb %al, (%rax) // DISASM-NEXT: 35: 00 00 addb %al, (%rax)
// DISASM-NEXT: 37: 00 00 addb %al, (%rax) // DISASM-NEXT: 37: 00 00 addb %al, (%rax)
// DISASM-NEXT: 39: 00 00 addb %al, (%rax) // DISASM-NEXT: 39: 00 00 addb %al, (%rax)
// DISASM-NEXT: 3b: 00 00 addb %al, (%rax) // DISASM-NEXT: 3b: 00 00 addb %al, (%rax)
// Check that --disassemble-zeroes work as alias for -z. // Check that --disassemble-zeroes work as alias for -z.
// RUN: llvm-objdump -d --disassemble-zeroes %t | FileCheck %s --check-prefix=DISASM // RUN: llvm-objdump -d --disassemble-zeroes %t | FileCheck %s --check-prefix=DISASM
Show All 19 Lines

llvm/test/Object/AMDGPU/objdump.s

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 LinesBB5:
v_addc_u32_e32 v11, vcc, v6, v11, vcc v_addc_u32_e32 v11, vcc, v6, v11, vcc
flat_load_dword v0, v[10:11] flat_load_dword v0, v[10:11]
v_lshlrev_b32_e32 v6, 5, v8 v_lshlrev_b32_e32 v6, 5, v8
v_lshlrev_b32_e32 v7, 2, v7 v_lshlrev_b32_e32 v7, 2, v7
s_endpgm s_endpgm
// CHECK: file format elf64-amdgpu // CHECK: file format elf64-amdgpu
// CHECK: Disassembly of section .text: // CHECK: Disassembly of section .text:
// CHECK: hello_world: // CHECK: <hello_world>:
// CHECK: s_mov_b32 m0, 0x10000 // 000000000100: BEFC00FF 00010000 // CHECK: s_mov_b32 m0, 0x10000 // 000000000100: BEFC00FF 00010000
// CHECK: s_load_dwordx2 s[0:1], s[4:5], 0x8 // 000000000108: C0060002 00000008 // CHECK: s_load_dwordx2 s[0:1], s[4:5], 0x8 // 000000000108: C0060002 00000008
// CHECK: s_waitcnt lgkmcnt(0) // 000000000110: BF8C007F // CHECK: s_waitcnt lgkmcnt(0) // 000000000110: BF8C007F
// CHECK: s_add_u32 s0, s7, s0 // 000000000114: 80000007 // CHECK: s_add_u32 s0, s7, s0 // 000000000114: 80000007
// CHECK: BB0: // CHECK: <BB0>:
// CHECK: v_add_u32_e32 v1, vcc, s0, v1 // 000000000118: 32020200 // CHECK: v_add_u32_e32 v1, vcc, s0, v1 // 000000000118: 32020200
// CHECK: BB1: // CHECK: <BB1>:
// CHECK: s_movk_i32 s0, 0x483 // 00000000011C: B0000483 // CHECK: s_movk_i32 s0, 0x483 // 00000000011C: B0000483
// CHECK: v_cmp_ge_i32_e32 vcc, s0, v0 // 000000000120: 7D8C0000 // CHECK: v_cmp_ge_i32_e32 vcc, s0, v0 // 000000000120: 7D8C0000
// CHECK: s_and_saveexec_b64 s[0:1], vcc // 000000000124: BE80206A // CHECK: s_and_saveexec_b64 s[0:1], vcc // 000000000124: BE80206A
// CHECK: v_lshlrev_b32_e32 v4, 2, v0 // 000000000128: 24080082 // CHECK: v_lshlrev_b32_e32 v4, 2, v0 // 000000000128: 24080082
// CHECK: BB3: // CHECK: <BB3>:
// CHECK: s_cbranch_execz 21 // 00000000012C: BF880015 // CHECK: s_cbranch_execz 21 // 00000000012C: BF880015
// CHECK: s_mov_b64 s[2:3], exec // 000000000130: BE82017E // CHECK: s_mov_b64 s[2:3], exec // 000000000130: BE82017E
// CHECK: s_mov_b64 s[10:11], exec // 000000000134: BE8A017E // CHECK: s_mov_b64 s[10:11], exec // 000000000134: BE8A017E
// CHECK: v_mov_b32_e32 v3, v0 // 000000000138: 7E060300 // CHECK: v_mov_b32_e32 v3, v0 // 000000000138: 7E060300
// CHECK: s_endpgm // 00000000013C: BF810000 // CHECK: s_endpgm // 00000000013C: BF810000
// CHECK: hello_world2: // CHECK: <hello_world2>:
// CHECK: s_and_saveexec_b64 s[0:1], vcc // 000000000240: BE80206A // CHECK: s_and_saveexec_b64 s[0:1], vcc // 000000000240: BE80206A
// CHECK: s_cbranch_execz 85 // 000000000244: BF880055 // CHECK: s_cbranch_execz 85 // 000000000244: BF880055
// CHECK: s_load_dwordx4 s[8:11], s[4:5], 0x40 // 000000000248: C00A0202 00000040 // CHECK: s_load_dwordx4 s[8:11], s[4:5], 0x40 // 000000000248: C00A0202 00000040
// CHECK: BB5: // CHECK: <BB5>:
// CHECK: v_ashrrev_i32_e32 v77, 31, v76 // 000000000250: 229A989F // CHECK: v_ashrrev_i32_e32 v77, 31, v76 // 000000000250: 229A989F
// CHECK: v_lshlrev_b64 v[10:11], 2, v[76:77] // 000000000254: D28F000A 00029882 // CHECK: v_lshlrev_b64 v[10:11], 2, v[76:77] // 000000000254: D28F000A 00029882
// CHECK: s_waitcnt lgkmcnt(0) // 00000000025C: BF8C007F // CHECK: s_waitcnt lgkmcnt(0) // 00000000025C: BF8C007F
// CHECK: v_add_u32_e32 v10, vcc, s8, v10 // 000000000260: 32141408 // CHECK: v_add_u32_e32 v10, vcc, s8, v10 // 000000000260: 32141408
// CHECK: v_mov_b32_e32 v6, s9 // 000000000264: 7E0C0209 // CHECK: v_mov_b32_e32 v6, s9 // 000000000264: 7E0C0209
// CHECK: v_addc_u32_e32 v11, vcc, v6, v11, vcc // 000000000268: 38161706 // CHECK: v_addc_u32_e32 v11, vcc, v6, v11, vcc // 000000000268: 38161706
// CHECK: flat_load_dword v0, v[10:11] // 00000000026C: DC500000 0000000A // CHECK: flat_load_dword v0, v[10:11] // 00000000026C: DC500000 0000000A
// CHECK: v_lshlrev_b32_e32 v6, 5, v8 // 000000000274: 240C1085 // CHECK: v_lshlrev_b32_e32 v6, 5, v8 // 000000000274: 240C1085
// CHECK: v_lshlrev_b32_e32 v7, 2, v7 // 000000000278: 240E0E82 // CHECK: v_lshlrev_b32_e32 v7, 2, v7 // 000000000278: 240E0E82
// CHECK: s_endpgm // 00000000027C: BF810000 // CHECK: s_endpgm // 00000000027C: BF810000

llvm/test/Object/Mips/feature.test

RUN: llvm-objdump -disassemble %p/../Inputs/dext-test.elf-mips64r2 | FileCheck %s RUN: llvm-objdump -disassemble %p/../Inputs/dext-test.elf-mips64r2 | FileCheck %s
CHECK: Disassembly of section .text: CHECK: Disassembly of section .text:
CHECK: dext: CHECK: <dext>:
CHECK: 0: 08 00 e0 03 jr $ra CHECK: 0: 08 00 e0 03 jr $ra
CHECK: 4: 43 49 82 7c dext $2, $4, 5, 10 CHECK: 4: 43 49 82 7c dext $2, $4, 5, 10
CHECK: dextu: CHECK: <dextu>:
CHECK: 8: 08 00 e0 03 jr $ra CHECK: 8: 08 00 e0 03 jr $ra
CHECK: c: 83 28 82 7c dext $2, $4, 2, 6 CHECK: c: 83 28 82 7c dext $2, $4, 2, 6
CHECK: dextm: CHECK: <dextm>:
CHECK: 10: 08 00 e0 03 jr $ra CHECK: 10: 08 00 e0 03 jr $ra
CHECK: 14: 43 09 82 7c dext $2, $4, 5, 2 CHECK: 14: 43 09 82 7c dext $2, $4, 5, 2

llvm/test/Object/Mips/objdump-micro-mips.test

RUN: llvm-objdump -d %p/../Inputs/micro-mips.elf-mipsel | FileCheck %s RUN: llvm-objdump -d %p/../Inputs/micro-mips.elf-mipsel | FileCheck %s
CHECK: foo: CHECK: <foo>:
CHECK-NEXT: 330: bd 33 f8 ff addiu $sp, $sp, -8 CHECK-NEXT: 330: bd 33 f8 ff addiu $sp, $sp, -8
CHECK-NEXT: 334: dd fb 04 00 sw $fp, 4($sp) CHECK-NEXT: 334: dd fb 04 00 sw $fp, 4($sp)
CHECK-NEXT: 338: 1d 00 50 f1 addu $fp, $sp, $zero CHECK-NEXT: 338: 1d 00 50 f1 addu $fp, $sp, $zero
CHECK: bar: CHECK: <bar>:
CHECK-NEXT: 350: a2 41 02 00 lui $2, 2 CHECK-NEXT: 350: a2 41 02 00 lui $2, 2
CHECK-NEXT: 354: 42 30 8f 80 addiu $2, $2, -32625 CHECK-NEXT: 354: 42 30 8f 80 addiu $2, $2, -32625
CHECK-NEXT: 358: bd 33 e8 ff addiu $sp, $sp, -24 CHECK-NEXT: 358: bd 33 e8 ff addiu $sp, $sp, -24

llvm/test/Object/X86/objdump-disassembly-inline-relocations.test

Show All 31 Lines
# COFF-x86-64: 21: 48 83 c4 28 addq $40, %rsp # COFF-x86-64: 21: 48 83 c4 28 addq $40, %rsp
# COFF-x86-64: 25: c3 ret # COFF-x86-64: 25: c3 ret
# RUN: llvm-objdump -d -r %p/../Inputs/trivial-object-test.macho-i386 \ # RUN: llvm-objdump -d -r %p/../Inputs/trivial-object-test.macho-i386 \
# RUN: | FileCheck %s -check-prefix MACHO-i386 # RUN: | FileCheck %s -check-prefix MACHO-i386
# MACHO-i386: file format mach-o 32-bit i386 # MACHO-i386: file format mach-o 32-bit i386
# MACHO-i386: Disassembly of section __TEXT,__text: # MACHO-i386: Disassembly of section __TEXT,__text:
# MACHO-i386: _main: # MACHO-i386: <_main>:
# MACHO-i386: 0: 83 ec 0c subl $12, %esp # MACHO-i386: 0: 83 ec 0c subl $12, %esp
# MACHO-i386: 3: c7 44 24 08 00 00 00 00 movl $0, 8(%esp) # MACHO-i386: 3: c7 44 24 08 00 00 00 00 movl $0, 8(%esp)
# MACHO-i386: b: c7 04 24 24 00 00 00 movl $36, (%esp) # MACHO-i386: b: c7 04 24 24 00 00 00 movl $36, (%esp)
# MACHO-i386: e: GENERIC_RELOC_VANILLA __cstring # MACHO-i386: e: GENERIC_RELOC_VANILLA __cstring
# MACHO-i386: 12: e8 1f 00 00 00 calll 31 # MACHO-i386: 12: e8 1f 00 00 00 calll 31
# MACHO-i386: 13: GENERIC_RELOC_VANILLA __jump_table # MACHO-i386: 13: GENERIC_RELOC_VANILLA __jump_table
# MACHO-i386: 17: e8 15 00 00 00 calll 21 # MACHO-i386: 17: e8 15 00 00 00 calll 21
# MACHO-i386: 18: GENERIC_RELOC_VANILLA __jump_table # MACHO-i386: 18: GENERIC_RELOC_VANILLA __jump_table
# MACHO-i386: 1c: 8b 44 24 08 movl 8(%esp), %eax # MACHO-i386: 1c: 8b 44 24 08 movl 8(%esp), %eax
# MACHO-i386: 20: 83 c4 0c addl $12, %esp # MACHO-i386: 20: 83 c4 0c addl $12, %esp
# MACHO-i386: 23: c3 ret # MACHO-i386: 23: c3 ret
# RUN: llvm-objdump -d -r %p/../Inputs/trivial-object-test.macho-x86-64 \ # RUN: llvm-objdump -d -r %p/../Inputs/trivial-object-test.macho-x86-64 \
# RUN: | FileCheck %s -check-prefix MACHO-x86-64 # RUN: | FileCheck %s -check-prefix MACHO-x86-64
# MACHO-x86-64: file format mach-o 64-bit x86-64 # MACHO-x86-64: file format mach-o 64-bit x86-64
# MACHO-x86-64: Disassembly of section __TEXT,__text: # MACHO-x86-64: Disassembly of section __TEXT,__text:
# MACHO-x86-64: _main: # MACHO-x86-64: <_main>:
# MACHO-x86-64: 0: 48 83 ec 08 subq $8, %rsp # MACHO-x86-64: 0: 48 83 ec 08 subq $8, %rsp
# MACHO-x86-64: 4: c7 44 24 04 00 00 00 00 movl $0, 4(%rsp) # MACHO-x86-64: 4: c7 44 24 04 00 00 00 00 movl $0, 4(%rsp)
# MACHO-x86-64: c: 48 8d 3d 00 00 00 00 leaq (%rip), %rdi # MACHO-x86-64: c: 48 8d 3d 00 00 00 00 leaq (%rip), %rdi
# MACHO-x86-64: f: X86_64_RELOC_SIGNED L_.str # MACHO-x86-64: f: X86_64_RELOC_SIGNED L_.str
# MACHO-x86-64: 13: e8 00 00 00 00 callq 0 # MACHO-x86-64: 13: e8 00 00 00 00 callq 0
# MACHO-x86-64: 14: X86_64_RELOC_BRANCH _puts # MACHO-x86-64: 14: X86_64_RELOC_BRANCH _puts
# MACHO-x86-64: 18: 30 c0 xorb %al, %al # MACHO-x86-64: 18: 30 c0 xorb %al, %al
# MACHO-x86-64: 1a: e8 00 00 00 00 callq 0 # MACHO-x86-64: 1a: e8 00 00 00 00 callq 0
# MACHO-x86-64: 1b: X86_64_RELOC_BRANCH _SomeOtherFunction # MACHO-x86-64: 1b: X86_64_RELOC_BRANCH _SomeOtherFunction
# MACHO-x86-64: 1f: 8b 44 24 04 movl 4(%rsp), %eax # MACHO-x86-64: 1f: 8b 44 24 04 movl 4(%rsp), %eax
# MACHO-x86-64: 23: 48 83 c4 08 addq $8, %rsp # MACHO-x86-64: 23: 48 83 c4 08 addq $8, %rsp
# MACHO-x86-64: 27: c3 ret # MACHO-x86-64: 27: c3 ret
# RUN: yaml2obj --docnum=1 %s -o %t.elf-i386 # RUN: yaml2obj --docnum=1 %s -o %t.elf-i386
# RUN: llvm-objdump -d -r %t.elf-i386 | FileCheck %s -check-prefix ELF-i386 # RUN: llvm-objdump -d -r %t.elf-i386 | FileCheck %s -check-prefix ELF-i386
# ELF-i386: file format elf32-i386 # ELF-i386: file format elf32-i386
# ELF-i386: Disassembly of section .text: # ELF-i386: Disassembly of section .text:
# ELF-i386: main: # ELF-i386: <main>:
# ELF-i386: 0: 83 ec 0c subl $12, %esp # ELF-i386: 0: 83 ec 0c subl $12, %esp
# ELF-i386: 3: c7 44 24 08 00 00 00 00 movl $0, 8(%esp) # ELF-i386: 3: c7 44 24 08 00 00 00 00 movl $0, 8(%esp)
# ELF-i386: b: c7 04 24 00 00 00 00 movl $0, (%esp) # ELF-i386: b: c7 04 24 00 00 00 00 movl $0, (%esp)
# ELF-i386: e: R_386_32 .rodata.str1.1 # ELF-i386: e: R_386_32 .rodata.str1.1
# ELF-i386: 12: e8 fc ff ff ff calll -4 # ELF-i386: 12: e8 fc ff ff ff calll -4
# ELF-i386: 13: R_386_PC32 puts # ELF-i386: 13: R_386_PC32 puts
# ELF-i386: 17: e8 fc ff ff ff calll -4 # ELF-i386: 17: e8 fc ff ff ff calll -4
# ELF-i386: 18: R_386_PC32 SomeOtherFunction # ELF-i386: 18: R_386_PC32 SomeOtherFunction
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines - Name: main
Binding: STB_GLOBAL Binding: STB_GLOBAL
- Name: SomeOtherFunction - Name: SomeOtherFunction
Binding: STB_GLOBAL Binding: STB_GLOBAL
- Name: puts - Name: puts
Binding: STB_GLOBAL Binding: STB_GLOBAL
# ELF-x86-64: file format elf64-x86-64 # ELF-x86-64: file format elf64-x86-64
# ELF-x86-64: Disassembly of section .text: # ELF-x86-64: Disassembly of section .text:
# ELF-x86-64: main: # ELF-x86-64: <main>:
# ELF-x86-64: 0: 48 83 ec 08 subq $8, %rsp # ELF-x86-64: 0: 48 83 ec 08 subq $8, %rsp
# ELF-x86-64: 4: c7 44 24 04 00 00 00 00 movl $0, 4(%rsp) # ELF-x86-64: 4: c7 44 24 04 00 00 00 00 movl $0, 4(%rsp)
# ELF-x86-64: c: bf 00 00 00 00 movl $0, %edi # ELF-x86-64: c: bf 00 00 00 00 movl $0, %edi
# ELF-x86-64: d: R_X86_64_32S .rodata.str1.1 # ELF-x86-64: d: R_X86_64_32S .rodata.str1.1
# ELF-x86-64: 11: e8 00 00 00 00 callq 0 # ELF-x86-64: 11: e8 00 00 00 00 callq 0
# ELF-x86-64: 12: R_X86_64_PC32 puts-0x4 # ELF-x86-64: 12: R_X86_64_PC32 puts-0x4
# ELF-x86-64: 16: 30 c0 xorb %al, %al # ELF-x86-64: 16: 30 c0 xorb %al, %al
# ELF-x86-64: 18: e8 00 00 00 00 callq 0 # ELF-x86-64: 18: e8 00 00 00 00 callq 0
# ELF-x86-64: 19: R_X86_64_PC32 SomeOtherFunction-0x4 # ELF-x86-64: 19: R_X86_64_PC32 SomeOtherFunction-0x4
# ELF-x86-64: 1d: 8b 44 24 04 movl 4(%rsp), %eax # ELF-x86-64: 1d: 8b 44 24 04 movl 4(%rsp), %eax
# ELF-x86-64: 21: 48 83 c4 08 addq $8, %rsp # ELF-x86-64: 21: 48 83 c4 08 addq $8, %rsp
# ELF-x86-64: 25: c3 ret # ELF-x86-64: 25: c3 ret

llvm/test/Object/X86/objdump-label.test

RUN: llvm-objdump -d %p/../Inputs/trivial-label-test.elf-x86-64 \ RUN: llvm-objdump -d %p/../Inputs/trivial-label-test.elf-x86-64 \
RUN: | FileCheck %s -check-prefix ELF-x86-64 RUN: | FileCheck %s -check-prefix ELF-x86-64
ELF-x86-64: file format elf64-x86-64 ELF-x86-64: file format elf64-x86-64
ELF-x86-64: Disassembly of section .text: ELF-x86-64: Disassembly of section .text:
ELF-x86-64: foo: ELF-x86-64: <foo>:
ELF-x86-64: 0: 90 nop ELF-x86-64: 0: 90 nop
ELF-x86-64: bum: ELF-x86-64: <bum>:
ELF-x86-64: 1: 90 nop ELF-x86-64: 1: 90 nop

llvm/test/tools/llvm-objdump/AArch64/elf-aarch64-mapping-symbols.test

Show All 9 Lines
.section .myothersection,"ax",@progbits .section .myothersection,"ax",@progbits
adrp x1,mystr adrp x1,mystr
mystr: mystr:
.asciz "blah" .asciz "blah"
.size mystr, 4 .size mystr, 4
# CHECK: Disassembly of section .mysection: # CHECK: Disassembly of section .mysection:
# CHECK: _start: # CHECK: <_start>:
# CHECK: 0: 21 00 00 10 adr x1, #4 # CHECK: 0: 21 00 00 10 adr x1, #4
# CHECK: msg: # CHECK: <msg>:
# CHECK: 4: 48 65 6c 6c .word # CHECK: 4: 48 65 6c 6c .word
# CHECK: 8: 6f 2c 20 77 .word # CHECK: 8: 6f 2c 20 77 .word
# CHECK: c: 6f 72 6c 64 .word # CHECK: c: 6f 72 6c 64 .word
# CHECK: 10: 0a 00 .short 0x000a # CHECK: 10: 0a 00 .short 0x000a
# CHECK: Disassembly of section .myothersection: # CHECK: Disassembly of section .myothersection:
# CHECK: $x.2: # CHECK: <$x.2>:
# CHECK: 0: 01 00 00 90 adrp x1, #0 # CHECK: 0: 01 00 00 90 adrp x1, #0
# CHECK: mystr: # CHECK: <mystr>:
# CHECK: 4: 62 6c 61 68 .word # CHECK: 4: 62 6c 61 68 .word
# CHECK: 8: 00 .byte 0x01 # CHECK: 8: 00 .byte 0x01

llvm/test/tools/llvm-objdump/AArch64/macho-zerofill.s

// RUN: llvm-mc < %s -triple aarch64-macho -filetype=obj | llvm-objdump -triple=aarch64-- -D - | FileCheck %s // RUN: llvm-mc < %s -triple aarch64-macho -filetype=obj | llvm-objdump -triple=aarch64-- -D - | FileCheck %s
// Check that we don't print garbage when we dump zerofill sections. // Check that we don't print garbage when we dump zerofill sections.
.zerofill __DATA,__common,_data64unsigned,472,3 .zerofill __DATA,__common,_data64unsigned,472,3
// CHECK: Disassembly of section __DATA,__common: // CHECK: Disassembly of section __DATA,__common:
// CHECK: ltmp1: // CHECK: <ltmp1>:
// CHECK-NEXT: ... // CHECK-NEXT: ...

llvm/test/tools/llvm-objdump/AArch64/plt.test

# RUN: llvm-objdump -d %p/Inputs/cfi.elf-aarch64 | FileCheck %s # RUN: llvm-objdump -d %p/Inputs/cfi.elf-aarch64 | FileCheck %s
# CHECK: Disassembly of section .plt: # CHECK: Disassembly of section .plt:
# CHECK: __cfi_slowpath@plt: # CHECK: <__cfi_slowpath@plt>:
# CHECK-NEXT: adrp x16, {{.*}} # CHECK-NEXT: adrp x16, {{.*}}
# CHECK: bl {{.*}} <__cfi_slowpath@plt> # CHECK: bl {{.*}} <__cfi_slowpath@plt>
# RUN: yaml2obj %s -o %t.aarch64 # RUN: yaml2obj %s -o %t.aarch64
# RUN: llvm-objdump -d -mattr=+bti %t.aarch64 | \ # RUN: llvm-objdump -d -mattr=+bti %t.aarch64 | \
# RUN: FileCheck --check-prefix=CHECK-BTI %s # RUN: FileCheck --check-prefix=CHECK-BTI %s
# CHECK-BTI: bl {{.*}} <f1@plt> # CHECK-BTI: bl {{.*}} <f1@plt>
# CHECK-BTI: bl {{.*}} <f2@plt> # CHECK-BTI: bl {{.*}} <f2@plt>
# CHECK-BTI: Disassembly of section .plt: # CHECK-BTI: Disassembly of section .plt:
# CHECK-BTI: f1@plt: # CHECK-BTI: <f1@plt>:
# CHECK-BTI-NEXT: bti c # CHECK-BTI-NEXT: bti c
# CHECK-BTI-NEXT: adrp x16, {{.*}} # CHECK-BTI-NEXT: adrp x16, {{.*}}
# CHECK-BTI: f2@plt: # CHECK-BTI: <f2@plt>:
# CHECK-BTI-NEXT: bti c # CHECK-BTI-NEXT: bti c
# CHECK-BTI-NEXT: adrp x16, {{.*}} # CHECK-BTI-NEXT: adrp x16, {{.*}}
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_EXEC Type: ET_EXEC
Show All 35 Lines

llvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll

; RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %s > %t.ll ; RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %s > %t.ll
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj -O0 -o %t.o %t.ll ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj -O0 -o %t.o %t.ll
; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa -mcpu=gfx802 -disassemble -line-numbers %t.o | FileCheck --check-prefix=LINE %t.ll ; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa -mcpu=gfx802 -disassemble -line-numbers %t.o | FileCheck --check-prefix=LINE %t.ll
; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa -mcpu=gfx802 -disassemble -source %t.o | FileCheck --check-prefix=SOURCE %t.ll ; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa -mcpu=gfx802 -disassemble -source %t.o | FileCheck --check-prefix=SOURCE %t.ll
; Prologue. ; Prologue.
; LINE: source_lines_test: ; LINE: source_lines_test{{>?}}:
; LINE-NEXT: ; source_lines_test(): ; LINE-NEXT: ; source_lines_test():
; LINE-NEXT: ; {{.*}}source-lines.cl:1 ; LINE-NEXT: ; {{.*}}source-lines.cl:1
; Kernel. ; Kernel.
; LINE: v_mov_b32_e32 v{{[0-9]+}}, 0x777 ; LINE: v_mov_b32_e32 v{{[0-9]+}}, 0x777
; LINE: ; {{.*}}source-lines.cl:2 ; LINE: ; {{.*}}source-lines.cl:2
; LINE: v_mov_b32_e32 v{{[0-9]+}}, 0x888 ; LINE: v_mov_b32_e32 v{{[0-9]+}}, 0x888
; LINE: ; {{.*}}source-lines.cl:3 ; LINE: ; {{.*}}source-lines.cl:3
; LINE: ; {{.*}}source-lines.cl:4 ; LINE: ; {{.*}}source-lines.cl:4
; LINE: v_add_u32_e64 ; LINE: v_add_u32_e64
; LINE: ; {{.*}}source-lines.cl:5 ; LINE: ; {{.*}}source-lines.cl:5
; LINE: flat_store_dword ; LINE: flat_store_dword
; Epilogue. ; Epilogue.
; LINE: ; {{.*}}source-lines.cl:6 ; LINE: ; {{.*}}source-lines.cl:6
; LINE-NEXT: s_endpgm ; LINE-NEXT: s_endpgm
; Prologue. ; Prologue.
; SOURCE: source_lines_test: ; SOURCE: source_lines_test{{>?}}:
; SOURCE-NEXT: ; kernel void source_lines_test(global int *Out) { ; SOURCE-NEXT: ; kernel void source_lines_test(global int *Out) {
; Kernel. ; Kernel.
; SOURCE: v_mov_b32_e32 v{{[0-9]+}}, 0x777 ; SOURCE: v_mov_b32_e32 v{{[0-9]+}}, 0x777
; SOURCE: ; int var0 = 0x777; ; SOURCE: ; int var0 = 0x777;
; SOURCE: v_mov_b32_e32 v{{[0-9]+}}, 0x888 ; SOURCE: v_mov_b32_e32 v{{[0-9]+}}, 0x888
; SOURCE: ; int var1 = 0x888; ; SOURCE: ; int var1 = 0x888;
; SOURCE: ; int var2 = var0 + var1; ; SOURCE: ; int var2 = var0 + var1;
; SOURCE: v_add_u32_e64 ; SOURCE: v_add_u32_e64
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/test/tools/llvm-objdump/ARM/unknown-instr.test

# RUN: yaml2obj %s -o %t # RUN: yaml2obj %s -o %t
# RUN: llvm-objdump -D -triple=thumbv8.1m.main-none-eabi %t | FileCheck %s # RUN: llvm-objdump -D -triple=thumbv8.1m.main-none-eabi %t | FileCheck %s
## This is a test case with "random" data/instructions, checking that ## This is a test case with "random" data/instructions, checking that
## llvm-objdump handles such instructions cleanly. Disassembly of instructions ## llvm-objdump handles such instructions cleanly. Disassembly of instructions
## can fail when it e.g. is not given the right set of architecture features, ## can fail when it e.g. is not given the right set of architecture features,
## for example when the source is compiled with: ## for example when the source is compiled with:
## ##
## clang -march=..+ext1+ext2 ## clang -march=..+ext1+ext2
## ##
## and disassembly is attempted with: ## and disassembly is attempted with:
## ##
## llvm-objdump -mattr=+ext1 ## llvm-objdump -mattr=+ext1
# CHECK: 00000000 .text: # CHECK: 00000000 <.text>:
# CHECK-NEXT: 0: cb <unknown> # CHECK-NEXT: 0: cb <unknown>
# CHECK-NEXT: 1: f3 f7 8b be b.w #-49898 # CHECK-NEXT: 1: f3 f7 8b be b.w #-49898
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS32 Class: ELFCLASS32
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_REL Type: ET_REL
Machine: EM_ARM Machine: EM_ARM
Sections: Sections:
- Name: .text - Name: .text
Type: SHT_PROGBITS Type: SHT_PROGBITS
Content: "cbf3f78bbe" Content: "cbf3f78bbe"

llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
!16 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !5, size: 32, align: 32) !16 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !5, size: 32, align: 32)
!17 = !DIExpression() !17 = !DIExpression()
!18 = !DILocation(line: 7, column: 8, scope: !14) !18 = !DILocation(line: 7, column: 8, scope: !14)
!19 = !DILocation(line: 8, column: 11, scope: !14) !19 = !DILocation(line: 8, column: 11, scope: !14)
!20 = !DILocation(line: 8, column: 10, scope: !14) !20 = !DILocation(line: 8, column: 10, scope: !14)
!21 = !DILocation(line: 8, column: 15, scope: !14) !21 = !DILocation(line: 8, column: 15, scope: !14)
!22 = !DILocation(line: 8, column: 13, scope: !14) !22 = !DILocation(line: 8, column: 13, scope: !14)
!23 = !DILocation(line: 8, column: 3, scope: !14) !23 = !DILocation(line: 8, column: 3, scope: !14)
; LINES: main: ; LINES: <main>:
; LINES-NEXT: main(): ; LINES-NEXT: main():
; LINES-NEXT: SRC_COMPDIR/source-interleave-hexagon.c:6 ; LINES-NEXT: SRC_COMPDIR/source-interleave-hexagon.c:6
; SOURCE: main: ; SOURCE: <main>:
; SOURCE-NEXT: int main() { ; SOURCE-NEXT: int main() {

llvm/test/tools/llvm-objdump/PowerPC/branch-offset.s

# RUN: llvm-mc -triple=powerpc64le-unknown-linux -filetype=obj %s -o %t.o # RUN: llvm-mc -triple=powerpc64le-unknown-linux -filetype=obj %s -o %t.o
# RUN: llvm-objdump -d %t.o | FileCheck %s # RUN: llvm-objdump -d %t.o | FileCheck %s
# RUN: llvm-mc -triple=powerpc64-unknown-linux -filetype=obj %s -o %t.o # RUN: llvm-mc -triple=powerpc64-unknown-linux -filetype=obj %s -o %t.o
# RUN: llvm-objdump -d %t.o | FileCheck %s # RUN: llvm-objdump -d %t.o | FileCheck %s
# RUN: llvm-mc -triple=powerpc-unknown-linux -filetype=obj %s -o %t.o # RUN: llvm-mc -triple=powerpc-unknown-linux -filetype=obj %s -o %t.o
# RUN: llvm-objdump -d %t.o | FileCheck %s # RUN: llvm-objdump -d %t.o | FileCheck %s
# CHECK: {{0*}}00000000 callee_back: # CHECK: {{0*}}00000000 <callee_back>:
# CHECK: 18: {{.*}} bl .-24 # CHECK: 18: {{.*}} bl .-24
# CHECK: 20: {{.*}} bl .+16 # CHECK: 20: {{.*}} bl .+16
# CHECK: {{0*}}00000030 callee_forward: # CHECK: {{0*}}00000030 <callee_forward>:
.text .text
.global caller .global caller
.type caller,@function .type caller,@function
.type callee_forward,@function .type callee_forward,@function
.type callee_back,@function .type callee_back,@function
.p2align 4 .p2align 4
Show All 22 Lines

llvm/test/tools/llvm-objdump/X86/adjust-vma.test

Show All 26 Lines
# ADJUST-NEXT: 7 .strtab 00000010 0000000000000000 # ADJUST-NEXT: 7 .strtab 00000010 0000000000000000
# ADJUST-NEXT: 8 .shstrtab 0000003c 0000000000000000 # ADJUST-NEXT: 8 .shstrtab 0000003c 0000000000000000
# COMMON: SYMBOL TABLE: # COMMON: SYMBOL TABLE:
# COMMON-NEXT: 0000000000000001 l F .text 0000000000000000 func # COMMON-NEXT: 0000000000000001 l F .text 0000000000000000 func
# COMMON-NEXT: 0000000000000000 l .text 0000000000000000 sym # COMMON-NEXT: 0000000000000000 l .text 0000000000000000 sym
# COMMON-NEXT: 0000000000000000 l d .text 0000000000000000 .text # COMMON-NEXT: 0000000000000000 l d .text 0000000000000000 .text
# NOADJUST: 0000000000000000 sym: # NOADJUST: 0000000000000000 <sym>:
# NOADJUST-NEXT: 0: {{.*}} nop # NOADJUST-NEXT: 0: {{.*}} nop
# NOADJUST: 0000000000000001 func: # NOADJUST: 0000000000000001 <func>:
# NOADJUST-NEXT: 1: {{.*}} retq # NOADJUST-NEXT: 1: {{.*}} retq
# ADJUST: 0000000000123000 sym: # ADJUST: 0000000000123000 <sym>:
# ADJUST-NEXT: 123000: {{.*}} nop # ADJUST-NEXT: 123000: {{.*}} nop
# ADJUST: 0000000000123001 func: # ADJUST: 0000000000123001 <func>:
# ADJUST-NEXT: 123001: {{.*}} retq # ADJUST-NEXT: 123001: {{.*}} retq
# NOADJUST: 0000000000000000 .debug_str: # NOADJUST: 0000000000000000 <.debug_str>:
# NOADJUST-NEXT: 0: {{.*}} %al, (%rax) # NOADJUST-NEXT: 0: {{.*}} %al, (%rax)
# NOADJUST-NEXT: 0000000000000001: R_X86_64_32 .text # NOADJUST-NEXT: 0000000000000001: R_X86_64_32 .text
# NOADJUST-NEXT: 2: {{.*}} addb %al, (%rax) # NOADJUST-NEXT: 2: {{.*}} addb %al, (%rax)
# ADJUST: 0000000000000000 .debug_str: # ADJUST: 0000000000000000 <.debug_str>:
# ADJUST-NEXT: 0: {{.*}} %al, (%rax) # ADJUST-NEXT: 0: {{.*}} %al, (%rax)
# ADJUST-NEXT: 0000000000123001: R_X86_64_32 .text # ADJUST-NEXT: 0000000000123001: R_X86_64_32 .text
# ADJUST-NEXT: 2: {{.*}} addb %al, (%rax) # ADJUST-NEXT: 2: {{.*}} addb %al, (%rax)
# COMMON: 0000000000000000 .rela.debug_str: # COMMON: 0000000000000000 <.rela.debug_str>:
# COMMON-NEXT: 0: {{.*}} addl %eax, (%rax) # COMMON-NEXT: 0: {{.*}} addl %eax, (%rax)
## ... There are more lines here. We do not care. ## ... There are more lines here. We do not care.
# NOADJUST: 0000000000000000 .data: # NOADJUST: 0000000000000000 <.data>:
# NOADJUST-NEXT: 0: {{.*}} addb %al, (%rax) # NOADJUST-NEXT: 0: {{.*}} addb %al, (%rax)
# NOADJUST-NEXT: 0000000000000000: R_X86_64_32 .text # NOADJUST-NEXT: 0000000000000000: R_X86_64_32 .text
# NOADJUST-NEXT: 2: {{.*}} addb %al, (%rax) # NOADJUST-NEXT: 2: {{.*}} addb %al, (%rax)
# ADJUST: 0000000000123000 .data: # ADJUST: 0000000000123000 <.data>:
# ADJUST-NEXT: 123000: {{.*}} addb %al, (%rax) # ADJUST-NEXT: 123000: {{.*}} addb %al, (%rax)
# ADJUST-NEXT: 0000000000123000: R_X86_64_32 .text # ADJUST-NEXT: 0000000000123000: R_X86_64_32 .text
# ADJUST-NEXT: 123002: {{.*}} addb %al, (%rax) # ADJUST-NEXT: 123002: {{.*}} addb %al, (%rax)
# COMMON: 0000000000000000 .rela.data: # COMMON: 0000000000000000 <.rela.data>:
# COMMON-NEXT: 0: {{.*}} addb %al, (%rax) # COMMON-NEXT: 0: {{.*}} addb %al, (%rax)
## ... There are more lines here. We do not care. ## ... There are more lines here. We do not care.
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_REL Type: ET_REL
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llvm/test/tools/llvm-objdump/X86/coff-disassemble-export.test

// RUN: llvm-objdump -d %p/Inputs/disassemble.dll.coff-i386 | \ // RUN: llvm-objdump -d %p/Inputs/disassemble.dll.coff-i386 | \
// RUN: FileCheck %s // RUN: FileCheck %s
// CHECK-LABEL: g: // CHECK-LABEL: <g>:
// CHECK: calll 8 <f> // CHECK: calll 8 <f>
// CHECK-LABEL: f: // CHECK-LABEL: f:
// CHECK: calll -24 <g> // CHECK: calll -24 <g>

llvm/test/tools/llvm-objdump/X86/demangle.s

# RUN: llvm-mc %s -filetype=obj -triple=x86_64-pc-linux -o %t # RUN: llvm-mc %s -filetype=obj -triple=x86_64-pc-linux -o %t
# RUN: llvm-objdump -t -r --demangle %t | FileCheck %s # RUN: llvm-objdump -t -r --demangle %t | FileCheck %s
## Check we demangle symbols when printing symbol table. ## Check we demangle symbols when printing symbol table.
# CHECK: SYMBOL TABLE: # CHECK: SYMBOL TABLE:
# CHECK-NEXT: 0000000000000000 g F .text 0000000000000000 foo() # CHECK-NEXT: 0000000000000000 g F .text 0000000000000000 foo()
## Check we demangle symbols when printing relocations. ## Check we demangle symbols when printing relocations.
# CHECK: 000000000000001 R_X86_64_PLT32 foo()-0x4 # CHECK: 000000000000001 R_X86_64_PLT32 foo()-0x4
## Check the case when relocations are inlined into disassembly. ## Check the case when relocations are inlined into disassembly.
# RUN: llvm-objdump -d -r --demangle %t | FileCheck %s --check-prefix=INLINE # RUN: llvm-objdump -d -r --demangle %t | FileCheck %s --check-prefix=INLINE
# INLINE: foo(): # INLINE: <foo()>:
# INLINE-NEXT: 0: {{.*}} callq 0 <_Z3foov+0x5> # INLINE-NEXT: 0: {{.*}} callq 0 <_Z3foov+0x5>
# INLINE-NEXT: 0000000000000001: R_X86_64_PLT32 foo()-0x4 # INLINE-NEXT: 0000000000000001: R_X86_64_PLT32 foo()-0x4
.text .text
.globl _Z3foov .globl _Z3foov
.type _Z3foov,@function .type _Z3foov,@function
_Z3foov: _Z3foov:
callq _Z3foov@PLT callq _Z3foov@PLT

llvm/test/tools/llvm-objdump/X86/disassemble-functions-mangling.test

Show All 13 Lines
## --disassemble-functions with --demangle. ## --disassemble-functions with --demangle.
# RUN: llvm-objdump -C --disassemble-functions='foo()' %t.o | FileCheck %s --check-prefix=DEMANGLED # RUN: llvm-objdump -C --disassemble-functions='foo()' %t.o | FileCheck %s --check-prefix=DEMANGLED
# RUN: llvm-objdump -C --disassemble-functions='_Z3foov' %t.o 2>&1 \ # RUN: llvm-objdump -C --disassemble-functions='_Z3foov' %t.o 2>&1 \
# RUN: | FileCheck %s --check-prefix=DEMANGLED-MISS # RUN: | FileCheck %s --check-prefix=DEMANGLED-MISS
# RUN: llvm-objdump -C --disassemble-functions='i,f' %t.o | FileCheck %s --check-prefix=NOMANGLE # RUN: llvm-objdump -C --disassemble-functions='i,f' %t.o | FileCheck %s --check-prefix=NOMANGLE
# RUN: llvm-objdump -C --disassemble-functions='std::allocator<wchar_t>::allocator()' %t.o 2>&1 \ # RUN: llvm-objdump -C --disassemble-functions='std::allocator<wchar_t>::allocator()' %t.o 2>&1 \
# RUN: | FileCheck %s --check-prefix=DEMANGLED-MULTI # RUN: | FileCheck %s --check-prefix=DEMANGLED-MULTI
# MANGLED: _Z3foov: # MANGLED: <_Z3foov>:
# MANGLED-MISS: warning: '{{.*}}': failed to disassemble missing function foo # MANGLED-MISS: warning: '{{.*}}': failed to disassemble missing function foo
# DEMANGLED: foo(): # DEMANGLED: <foo()>:
# DEMANGLED-MISS: warning: '{{.*}}': failed to disassemble missing function _Z3foov # DEMANGLED-MISS: warning: '{{.*}}': failed to disassemble missing function _Z3foov
# NOMANGLE: i: # NOMANGLE: <i>:
# NOMANGLE: f: # NOMANGLE: <f>:
# DEMANGLED-MULTI: std::allocator<wchar_t>::allocator(): # DEMANGLED-MULTI: <std::allocator<wchar_t>::allocator()>:
# DEMANGLED-MULTI: std::allocator<wchar_t>::allocator(): # DEMANGLED-MULTI: <std::allocator<wchar_t>::allocator()>:
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_EXEC Type: ET_EXEC
Machine: EM_X86_64 Machine: EM_X86_64
Sections: Sections:
Show All 21 Lines

llvm/test/tools/llvm-objdump/X86/disassemble-functions.test

## Show that the --diassemble-functions switch disassembles only the specified ## Show that the --diassemble-functions switch disassembles only the specified
## functions. ## functions.
# RUN: yaml2obj -o %t.out %p/Inputs/simple-executable-x86_64.yaml # RUN: yaml2obj -o %t.out %p/Inputs/simple-executable-x86_64.yaml
# RUN: llvm-objdump -d %t.out --disassemble-functions=main \ # RUN: llvm-objdump -d %t.out --disassemble-functions=main \
# RUN: | FileCheck %s --check-prefix=MAIN --implicit-check-not=foo --implicit-check-not=somedata # RUN: | FileCheck %s --check-prefix=MAIN --implicit-check-not=foo --implicit-check-not=somedata
# RUN: llvm-objdump -d %t.out --disassemble-functions=main,foo \ # RUN: llvm-objdump -d %t.out --disassemble-functions=main,foo \
# RUN: | FileCheck %s --check-prefixes=MAIN,FOO --implicit-check-not=somedata # RUN: | FileCheck %s --check-prefixes=MAIN,FOO --implicit-check-not=somedata
# FOO: foo: # FOO: <foo>:
# MAIN: main: # MAIN: <main>:
## Unknown symbol name. ## Unknown symbol name.
# RUN: llvm-objdump -d %t.out --disassemble-functions=baz \ # RUN: llvm-objdump -d %t.out --disassemble-functions=baz \
# RUN: | FileCheck %s --implicit-check-not=Disassembly # RUN: | FileCheck %s --implicit-check-not=Disassembly
## Data symbol. ## Data symbol.
# RUN: llvm-objdump -d %t.out --disassemble-functions=a \ # RUN: llvm-objdump -d %t.out --disassemble-functions=a \
# RUN: | FileCheck %s --implicit-check-not=Disassembly # RUN: | FileCheck %s --implicit-check-not=Disassembly
## Data symbol + --disassemble-all. ## Data symbol + --disassemble-all.
# RUN: llvm-objdump -D %t.out --disassemble-functions=a \ # RUN: llvm-objdump -D %t.out --disassemble-functions=a \
# RUN: | FileCheck %s --check-prefix=DATA # RUN: | FileCheck %s --check-prefix=DATA
# DATA: a: # DATA: a:

llvm/test/tools/llvm-objdump/X86/disassemble-implied-by-disassemble-functions.test

Show All 12 Lines - Name: .text
Flags: [ SHF_EXECINSTR ] Flags: [ SHF_EXECINSTR ]
Content: 90 Content: 90
Symbols: Symbols:
- Name: main - Name: main
Type: STT_FUNC Type: STT_FUNC
Section: .text Section: .text
... ...
# CHECK: 0000000000000000 main: # CHECK: 0000000000000000 <main>:
# CHECK-NEXT: 0: 90 nop # CHECK-NEXT: 0: 90 nop

llvm/test/tools/llvm-objdump/X86/disassemble-invalid-byte-sequences.test

## Show that llvm-objdump handles invalid byte sequences, and continues. ## Show that llvm-objdump handles invalid byte sequences, and continues.
# RUN: yaml2obj %s -o %t.o # RUN: yaml2obj %s -o %t.o
# RUN: llvm-objdump %t.o -d | FileCheck %s # RUN: llvm-objdump %t.o -d | FileCheck %s
# CHECK: 0000000000000000 .text: # CHECK: 0000000000000000 <.text>:
# CHECK: 0: d9 e2 <unknown> # CHECK: 0: d9 e2 <unknown>
# CHECK-NEXT: 2: 90 nop # CHECK-NEXT: 2: 90 nop
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_EXEC Type: ET_EXEC
Machine: EM_X86_64 Machine: EM_X86_64
Sections: Sections:
- Name: .text - Name: .text
Type: SHT_PROGBITS Type: SHT_PROGBITS
Flags: [SHF_ALLOC, SHF_EXECINSTR] Flags: [SHF_ALLOC, SHF_EXECINSTR]
Content: 'd9e290' Content: 'd9e290'

llvm/test/tools/llvm-objdump/X86/disassemble-no-symbol-at-section-start.test

## Test that we disassemble the start of the section even ## Test that we disassemble the start of the section even
## if there is no start symbol. ## if there is no start symbol.
# RUN: yaml2obj %s -o %t # RUN: yaml2obj %s -o %t
# RUN: llvm-objdump -d %t | FileCheck %s # RUN: llvm-objdump -d %t | FileCheck %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: .text: # CHECK-NEXT: <.text>:
# CHECK-NEXT: 0: 90 nop # CHECK-NEXT: 0: 90 nop
# CHECK: foo: # CHECK: <foo>:
# CHECK-NEXT: 1: 90 nop # CHECK-NEXT: 1: 90 nop
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_REL Type: ET_REL
Machine: EM_X86_64 Machine: EM_X86_64
Show All 9 Lines

llvm/test/tools/llvm-objdump/X86/disassemble-section-name.s

# RUN: yaml2obj %p/Inputs/simple-executable-x86_64.yaml -o %t # RUN: yaml2obj %p/Inputs/simple-executable-x86_64.yaml -o %t
# RUN: llvm-objdump -d %t | FileCheck %s # RUN: llvm-objdump -d %t | FileCheck %s
# CHECK: : file format elf64-x86-64 # CHECK: : file format elf64-x86-64
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: Disassembly of section .text: # CHECK-NEXT: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 0000000000000000 foo: # CHECK-NEXT: 0000000000000000 <foo>:

llvm/test/tools/llvm-objdump/X86/disassemble-text.test

# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o -| \ # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o -| \
# RUN: llvm-objdump -d - | FileCheck %s # RUN: llvm-objdump -d - | FileCheck %s
.globl foo .globl foo
.type foo, @object .type foo, @object
foo: foo:
.ascii "this is a test" .ascii "this is a test"
# CHECK: foo: # CHECK: <foo>:
# CHECK: 0:{{.*}}this is # CHECK: 0:{{.*}}this is
# CHECK: 8:{{.*}}a test # CHECK: 8:{{.*}}a test

llvm/test/tools/llvm-objdump/X86/disassemble-zeroes-relocations.test

Show All 12 Lines
# CHECK-NEXT: 0000000000000008: R_X86_64_64 *ABS* # CHECK-NEXT: 0000000000000008: R_X86_64_64 *ABS*
# CHECK-NEXT: a: 00 00 addb %al, (%rax) # CHECK-NEXT: a: 00 00 addb %al, (%rax)
# CHECK-NEXT: c: 00 00 addb %al, (%rax) # CHECK-NEXT: c: 00 00 addb %al, (%rax)
# CHECK-NEXT: e: 00 00 addb %al, (%rax) # CHECK-NEXT: e: 00 00 addb %al, (%rax)
## Check that without -reloc all zeroes would be omitted. ## Check that without -reloc all zeroes would be omitted.
# RUN: llvm-objdump -D %t | FileCheck %s --check-prefix=SKIP # RUN: llvm-objdump -D %t | FileCheck %s --check-prefix=SKIP
# SKIP: 0000000000000000 .rodata: # SKIP: 0000000000000000 <.rodata>:
# SKIP-NEXT: ... # SKIP-NEXT: ...
# SKIP-EMPTY: # SKIP-EMPTY:
# SKIP-NEXT: Disassembly of section .rela.rodata: # SKIP-NEXT: Disassembly of section .rela.rodata:
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Show All 25 Lines

llvm/test/tools/llvm-objdump/X86/elf-disassemble-bss.test

## Check that when BSS is larger than the file llvm-objdump doesn't ## Check that when BSS is larger than the file llvm-objdump doesn't
## assert with an unexpected end of file error. ## assert with an unexpected end of file error.
# RUN: yaml2obj --docnum=1 %s -o %t # RUN: yaml2obj --docnum=1 %s -o %t
# RUN: yaml2obj --docnum=2 %s -o %t.2 # RUN: yaml2obj --docnum=2 %s -o %t.2
# RUN: llvm-objdump -D %t | FileCheck %s # RUN: llvm-objdump -D %t | FileCheck %s
# RUN: llvm-objdump -D %t.2 | FileCheck %s # RUN: llvm-objdump -D %t.2 | FileCheck %s
# CHECK: Disassembly of section .bss: # CHECK: Disassembly of section .bss:
# CHECK: .bss: # CHECK: <.bss>:
# CHECK-NEXT: ... # CHECK-NEXT: ...
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_EXEC Type: ET_EXEC
Machine: EM_X86_64 Machine: EM_X86_64
Show All 20 Lines

llvm/test/tools/llvm-objdump/X86/elf-disassemble-dynamic-symbols.test

## Show the disassembly behaviour when dynamic symbols are present. ## Show the disassembly behaviour when dynamic symbols are present.
# RUN: yaml2obj %s -o %t # RUN: yaml2obj %s -o %t
## Case 1: Both static and dynamic symbols are present. Only static ## Case 1: Both static and dynamic symbols are present. Only static
## symbols are displayed. ## symbols are displayed.
# RUN: llvm-objdump -d %t | FileCheck %s --check-prefixes=CHECK,STATIC # RUN: llvm-objdump -d %t | FileCheck %s --check-prefixes=CHECK,STATIC
## Case 2: Only the dynamic symbols are present. These should be displayed, if ## Case 2: Only the dynamic symbols are present. These should be displayed, if
## they meet the necessary criteria. ## they meet the necessary criteria.
# RUN: llvm-objcopy --strip-all %t %t2 # RUN: llvm-objcopy --strip-all %t %t2
# RUN: llvm-objdump -d %t2 | FileCheck %s --check-prefixes=CHECK,DYN # RUN: llvm-objdump -d %t2 | FileCheck %s --check-prefixes=CHECK,DYN
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# STATIC-NEXT: 0000000000001000 .text: # STATIC-NEXT: 0000000000001000 <.text>:
# DYN-NEXT: 0000000000001000 only_dyn: # DYN-NEXT: 0000000000001000 <only_dyn>:
# CHECK-NEXT: 1000: # CHECK-NEXT: 1000:
# CHECK-EMPTY: # CHECK-EMPTY:
# STATIC-NEXT: 0000000000001001 both_static: # STATIC-NEXT: 0000000000001001 <both_static>:
# DYN-NEXT: 0000000000001001 both_dyn: # DYN-NEXT: 0000000000001001 <both_dyn>:
# CHECK-NEXT: 1001: # CHECK-NEXT: 1001:
# STATIC-EMPTY: # STATIC-EMPTY:
# STATIC-NEXT: 0000000000001002 only_static: # STATIC-NEXT: 0000000000001002 <only_static>:
# CHECK-NEXT: 1002: # CHECK-NEXT: 1002:
# DYN-EMPTY: # DYN-EMPTY:
# DYN-NEXT: 0000000000001003 object: # DYN-NEXT: 0000000000001003 <object>:
# CHECK-NEXT: 1003: # CHECK-NEXT: 1003:
# DYN-EMPTY: # DYN-EMPTY:
# DYN-NEXT: 0000000000001004 zero_sized: # DYN-NEXT: 0000000000001004 <zero_sized>:
# CHECK-NEXT: 1004: # CHECK-NEXT: 1004:
# DYN-EMPTY: # DYN-EMPTY:
# DYN-NEXT: 0000000000001005 common: # DYN-NEXT: 0000000000001005 <common>:
# CHECK-NEXT: 1005: # CHECK-NEXT: 1005:
# DYN-EMPTY: # DYN-EMPTY:
# DYN-NEXT: 0000000000001006 loos: # DYN-NEXT: 0000000000001006 <loos>:
# CHECK-NEXT: 1006: # CHECK-NEXT: 1006:
# DYN-EMPTY: # DYN-EMPTY:
# DYN-NEXT: 0000000000001007 loproc: # DYN-NEXT: 0000000000001007 <loproc>:
# CHECK-NEXT: 1007: # CHECK-NEXT: 1007:
# CHECK-NEXT: 1008: # CHECK-NEXT: 1008:
# CHECK-NEXT: 1009: # CHECK-NEXT: 1009:
# CHECK-NEXT: 100a: # CHECK-NEXT: 100a:
# CHECK-NEXT: 100b:{{.*}} # CHECK-NEXT: 100b:{{.*}}
# CHECK-NOT: {{.}} # CHECK-NOT: {{.}}
--- !ELF --- !ELF
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

llvm/test/tools/llvm-objdump/X86/elf-disassemble-no-symtab.test

## Show that llvm-objdump can handle a missing symbol table when printing ## Show that llvm-objdump can handle a missing symbol table when printing
## references and labels. ## references and labels.
# RUN: yaml2obj %s -o %t # RUN: yaml2obj %s -o %t
# RUN: llvm-objcopy -R .symtab %t # RUN: llvm-objcopy -R .symtab %t
# RUN: llvm-objdump %t -d | FileCheck %s # RUN: llvm-objdump %t -d | FileCheck %s
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 0000000000004000 .text: # CHECK-NEXT: 0000000000004000 <.text>:
# CHECK-NEXT: 4000: e8 42 00 00 00 callq 66 <.text+0x47> # CHECK-NEXT: 4000: e8 42 00 00 00 callq 66 <.text+0x47>
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_EXEC Type: ET_EXEC
Machine: EM_X86_64 Machine: EM_X86_64
Sections: Sections:
- Name: .text - Name: .text
Type: SHT_PROGBITS Type: SHT_PROGBITS
Address: 0x4000 Address: 0x4000
Flags: [SHF_ALLOC, SHF_EXECINSTR] Flags: [SHF_ALLOC, SHF_EXECINSTR]
Content: 'e842000000' Content: 'e842000000'

llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-labels-exec.test

## Show which labels are printed in disassembly of an executable. ## Show which labels are printed in disassembly of an executable.
# RUN: yaml2obj %s -o %t # RUN: yaml2obj %s -o %t
# RUN: llvm-objdump %t -d | FileCheck %s --implicit-check-not=stt_section \ # RUN: llvm-objdump %t -d | FileCheck %s --implicit-check-not=stt_section \
# RUN: --implicit-check-not=fourth \ # RUN: --implicit-check-not=fourth \
# RUN: --implicit-check-not=absolute \ # RUN: --implicit-check-not=absolute \
# RUN: --implicit-check-not=other # RUN: --implicit-check-not=other
# Match this line so the implicit check-nots don't match the path. # Match this line so the implicit check-nots don't match the path.
# CHECK: {{^.*}}file format elf64-x86-64 # CHECK: {{^.*}}file format elf64-x86-64
# CHECK: 0000000000004000 first: # CHECK: 0000000000004000 <first>:
# CHECK: 0000000000004001 second: # CHECK: 0000000000004001 <second>:
# CHECK: 0000000000004002 third: # CHECK: 0000000000004002 <third>:
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_EXEC Type: ET_EXEC
Machine: EM_X86_64 Machine: EM_X86_64
Sections: Sections:
Show All 35 Lines

llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-labels-rel.test

## Show which labels are printed in disassembly of a relocatable object. ## Show which labels are printed in disassembly of a relocatable object.
# RUN: yaml2obj %s -o %t # RUN: yaml2obj %s -o %t
# RUN: llvm-objdump %t -d | FileCheck %s --implicit-check-not=stt_section \ # RUN: llvm-objdump %t -d | FileCheck %s --implicit-check-not=stt_section \
# RUN: --implicit-check-not=first \ # RUN: --implicit-check-not=first \
# RUN: --implicit-check-not=second \ # RUN: --implicit-check-not=second \
# RUN: --implicit-check-not=third \ # RUN: --implicit-check-not=third \
# RUN: --implicit-check-not=fourth \ # RUN: --implicit-check-not=fourth \
# RUN: --implicit-check-not=absolute \ # RUN: --implicit-check-not=absolute \
# RUN: --implicit-check-not=other # RUN: --implicit-check-not=other
# CHECK: {{.*}}: file format {{.*}} # CHECK: {{.*}}: file format {{.*}}
# CHECK: Disassembly of section .text: # CHECK: Disassembly of section .text:
# CHECK: 0000000000000000 first: # CHECK: 0000000000000000 <first>:
# CHECK: 0000000000000001 second: # CHECK: 0000000000000001 <second>:
# CHECK: 0000000000000002 third: # CHECK: 0000000000000002 <third>:
# CHECK: Disassembly of section .text2: # CHECK: Disassembly of section .text2:
# CHECK: 0000000000000004 other: # CHECK: 0000000000000004 <other>:
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_REL Type: ET_REL
Machine: EM_X86_64 Machine: EM_X86_64
Sections: Sections:
Show All 33 Lines

llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines - Name: fourth
Section: .text3 Section: .text3
Value: 0x400A Value: 0x400A
# RUN: yaml2obj %s --docnum=2 -o %t.o # RUN: yaml2obj %s --docnum=2 -o %t.o
# RUN: llvm-objdump %t.o -d | FileCheck %s --check-prefix=REL # RUN: llvm-objdump %t.o -d | FileCheck %s --check-prefix=REL
# REL: Disassembly of section .text1: # REL: Disassembly of section .text1:
# REL-EMPTY: # REL-EMPTY:
# REL-NEXT: 0000000000000000 .text1: # REL-NEXT: 0000000000000000 <.text1>:
# REL-NEXT: 0: e8 00 00 00 00 callq 0 <.text1+0x5> # REL-NEXT: 0: e8 00 00 00 00 callq 0 <.text1+0x5>
# REL-EMPTY: # REL-EMPTY:
# REL-NEXT: Disassembly of section .text2: # REL-NEXT: Disassembly of section .text2:
# REL-EMPTY: # REL-EMPTY:
# REL-NEXT: 0000000000000000 .text2: # REL-NEXT: 0000000000000000 <.text2>:
# REL-NEXT: 0: e8 00 00 00 00 callq 0 <sym2> # REL-NEXT: 0: e8 00 00 00 00 callq 0 <sym2>
# REL-EMPTY: # REL-EMPTY:
# REL-NEXT: Disassembly of section .text3: # REL-NEXT: Disassembly of section .text3:
# REL-EMPTY: # REL-EMPTY:
# REL-NEXT: 0000000000000000 .text3: # REL-NEXT: 0000000000000000 <.text3>:
# REL-NEXT: 0: e8 00 00 00 00 callq 0 <.text3+0x5> # REL-NEXT: 0: e8 00 00 00 00 callq 0 <.text3+0x5>
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_REL Type: ET_REL
Machine: EM_X86_64 Machine: EM_X86_64
Show All 33 Lines

llvm/test/tools/llvm-objdump/X86/elf-disassemble.test

## Show that disassembly is printed correctly, for only the desired sections. ## Show that disassembly is printed correctly, for only the desired sections.
# RUN: yaml2obj %s -o %t.o # RUN: yaml2obj %s -o %t.o
# RUN: llvm-objdump %t.o --disassemble | FileCheck %s --implicit-check-not=Disassembly # RUN: llvm-objdump %t.o --disassemble | FileCheck %s --implicit-check-not=Disassembly
# RUN: llvm-objdump %t.o --disassemble-all | FileCheck %s --check-prefixes=CHECK,ALL # RUN: llvm-objdump %t.o --disassemble-all | FileCheck %s --check-prefixes=CHECK,ALL
# CHECK: Disassembly of section .executable: # CHECK: Disassembly of section .executable:
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 0000000000001000 .executable: # CHECK-NEXT: 0000000000001000 <.executable>:
# CHECK-NEXT: 0: 90 nop # CHECK-NEXT: 0: 90 nop
# ALL-EMPTY: # ALL-EMPTY:
# ALL-NEXT: Disassembly of section .writable: # ALL-NEXT: Disassembly of section .writable:
# ALL-EMPTY: # ALL-EMPTY:
# ALL-NEXT: 0000000000002000 .writable: # ALL-NEXT: 0000000000002000 <.writable>:
# ALL-NEXT: 0: c3 retq # ALL-NEXT: 0: c3 retq
# ALL-EMPTY: # ALL-EMPTY:
# ALL-NEXT: Disassembly of section .readonly: # ALL-NEXT: Disassembly of section .readonly:
# ALL-EMPTY: # ALL-EMPTY:
# ALL-NEXT: 0000000000003000 .readonly: # ALL-NEXT: 0000000000003000 <.readonly>:
# ALL-NEXT: 0: 01 00 addl %eax, (%rax) # ALL-NEXT: 0: 01 00 addl %eax, (%rax)
# ALL-EMPTY: # ALL-EMPTY:
# ALL-NEXT: Disassembly of section .nobits: # ALL-NEXT: Disassembly of section .nobits:
# ALL-EMPTY: # ALL-EMPTY:
# ALL-NEXT: 0000000000004000 .nobits: # ALL-NEXT: 0000000000004000 <.nobits>:
# ALL-NEXT: ... # ALL-NEXT: ...
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_REL Type: ET_REL
Machine: EM_X86_64 Machine: EM_X86_64
Show All 19 Lines

llvm/test/tools/llvm-objdump/X86/function-sections-line-numbers.s

# The code below is the reduced version of the output # The code below is the reduced version of the output
# from the following invocation and source: # from the following invocation and source:
# #
# // test.cpp: # // test.cpp:
#void f1() {} #void f1() {}
#void f2() {} #void f2() {}
# #
# clang -gdwarf-5 -ffunction-sections test.cpp -o test.s -S # clang -gdwarf-5 -ffunction-sections test.cpp -o test.s -S
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux -dwarf-version=5 %s -o %t.o # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux -dwarf-version=5 %s -o %t.o
# RUN: llvm-objdump -disassemble -line-numbers -r -s -section-headers -t %t.o | FileCheck %s # RUN: llvm-objdump -disassemble -line-numbers -r -s -section-headers -t %t.o | FileCheck %s
# CHECK: 0000000000000000 _Z2f1v # CHECK: 0000000000000000 <_Z2f1v>
# CHECK-NOT: test.cpp:2 # CHECK-NOT: test.cpp:2
# CHECK: test.cpp:1 # CHECK: test.cpp:1
# CHECK-NOT: test.cpp:2 # CHECK-NOT: test.cpp:2
# CHECK: 0000000000000000 _Z2f2v # CHECK: 0000000000000000 <_Z2f2v>
# CHECK-NOT: test.cpp:1 # CHECK-NOT: test.cpp:1
# CHECK: test.cpp:2 # CHECK: test.cpp:2
# CHECK-NOT: test.cpp:1 # CHECK-NOT: test.cpp:1
.text .text
.file "test.cpp" .file "test.cpp"
.section .text._Z2f1v,"ax",@progbits .section .text._Z2f1v,"ax",@progbits
▲ Show 20 Lines • Show All 194 Lines • Show Last 20 Lines

llvm/test/tools/llvm-objdump/X86/out-of-section-sym.test

// Check that llvm-objdump does not attempt to disassemble symbols outside // Check that llvm-objdump does not attempt to disassemble symbols outside
// of section boundaries. // of section boundaries.
// RUN: llvm-objdump -d -t %p/Inputs/out-of-section-sym.elf-i386 >%t0 // RUN: llvm-objdump -d -t %p/Inputs/out-of-section-sym.elf-i386 >%t0
// RUN: llvm-objdump -dt %p/Inputs/out-of-section-sym.elf-i386 >%t1 // RUN: llvm-objdump -dt %p/Inputs/out-of-section-sym.elf-i386 >%t1
// RUN: cmp %t0 %t1 // RUN: cmp %t0 %t1
// RUN: FileCheck --input-file %t0 %s // RUN: FileCheck --input-file %t0 %s
CHECK: SYMBOL TABLE: CHECK: SYMBOL TABLE:
CHECK-NEXT: 00000010 l d .text 00000000 .text CHECK-NEXT: 00000010 l d .text 00000000 .text
CHECK-NEXT: 00000010 l .text 00000000 _start CHECK-NEXT: 00000010 l .text 00000000 _start
CHECK-NEXT: 00000020 g .text 00000000 _fdata CHECK-NEXT: 00000020 g .text 00000000 _fdata
CHECK-NEXT: 00000010 g .text 00000000 _ftext CHECK-NEXT: 00000010 g .text 00000000 _ftext
CHECK-EMPTY: CHECK-EMPTY:
CHECK-NEXT: Disassembly of section .text: CHECK-NEXT: Disassembly of section .text:
CHECK-EMPTY: CHECK-EMPTY:
CHECK-NEXT: _start: CHECK-NEXT: <_start>:
CHECK-NEXT: 10: c3 retl CHECK-NEXT: 10: c3 retl

llvm/test/tools/llvm-objdump/X86/plt.test

// RUN: llvm-objdump -d %p/Inputs/stripped-elf.so | FileCheck -check-prefix=64 %s // RUN: llvm-objdump -d %p/Inputs/stripped-elf.so | FileCheck -check-prefix=64 %s
// RUN: llvm-objdump -d %p/Inputs/hello.exe.elf-i386 | FileCheck -check-prefix=32 %s // RUN: llvm-objdump -d %p/Inputs/hello.exe.elf-i386 | FileCheck -check-prefix=32 %s
// RUN: llvm-objdump -d %p/Inputs/hello.exe.nopie.elf-i386 | FileCheck -check-prefix=32 %s // RUN: llvm-objdump -d %p/Inputs/hello.exe.nopie.elf-i386 | FileCheck -check-prefix=32 %s
# 64: Disassembly of section .plt: # 64: Disassembly of section .plt:
# 64: __gmon_start__@plt: # 64: <__gmon_start__@plt>:
# 64: __cxa_finalize@plt: # 64: <__cxa_finalize@plt>:
# 64: callq {{.*}} <__cxa_finalize@plt> # 64: callq {{.*}} <__cxa_finalize@plt>
# 32: Disassembly of section .plt: # 32: Disassembly of section .plt:
# 32: puts@plt: # 32: <puts@plt>:
# 32: __libc_start_main@plt: # 32: <__libc_start_main@plt>:
# 32: calll {{.*}} <puts@plt> # 32: calll {{.*}} <puts@plt>
# 32: calll {{.*}} <__libc_start_main@plt> # 32: calll {{.*}} <__libc_start_main@plt>

llvm/test/tools/llvm-objdump/X86/print-symbol-addr.s

# RUN: llvm-mc %s -filetype=obj -triple=i386 -o %t.32.o # RUN: llvm-mc %s -filetype=obj -triple=i386 -o %t.32.o
# RUN: llvm-mc %s -filetype=obj -triple=x86_64 -o %t.64.o # RUN: llvm-mc %s -filetype=obj -triple=x86_64 -o %t.64.o
## Check we print the address of `foo` and `bar`. ## Check we print the address of `foo` and `bar`.
# RUN: llvm-objdump -d %t.32.o | FileCheck --check-prefixes=ADDR32,ADDR %s # RUN: llvm-objdump -d %t.32.o | FileCheck --check-prefixes=ADDR32,ADDR %s
# RUN: llvm-objdump -d %t.64.o | FileCheck --check-prefixes=ADDR64,ADDR %s # RUN: llvm-objdump -d %t.64.o | FileCheck --check-prefixes=ADDR64,ADDR %s
# ADDR32: 00000000 foo: # ADDR32: 00000000 <foo>:
# ADDR64: 0000000000000000 foo: # ADDR64: 0000000000000000 <foo>:
# ADDR-NEXT: 0: {{.*}} nop # ADDR-NEXT: 0: {{.*}} nop
# ADDR-NEXT: 1: {{.*}} nop # ADDR-NEXT: 1: {{.*}} nop
# ADDR32: 00000002 bar: # ADDR32: 00000002 <bar>:
# ADDR64: 0000000000000002 bar: # ADDR64: 0000000000000002 <bar>:
# ADDR-NEXT: 2: {{.*}} nop # ADDR-NEXT: 2: {{.*}} nop
## Check we do not print the addresses with --no-leading-addr. ## Check we do not print the addresses with --no-leading-addr.
# RUN: llvm-objdump -d --no-leading-addr %t.32.o | FileCheck %s --check-prefix=NOADDR # RUN: llvm-objdump -d --no-leading-addr %t.32.o | FileCheck %s --check-prefix=NOADDR
# RUN: llvm-objdump -d --no-leading-addr %t.64.o | FileCheck %s --check-prefix=NOADDR # RUN: llvm-objdump -d --no-leading-addr %t.64.o | FileCheck %s --check-prefix=NOADDR
# NOADDR: {{^}}foo: # NOADDR: <foo>:
# NOADDR-NEXT: {{.*}} nop # NOADDR-NEXT: {{.*}} nop
# NOADDR-NEXT: {{.*}} nop # NOADDR-NEXT: {{.*}} nop
# NOADDR: {{^}}bar: # NOADDR: <bar>:
# NOADDR-NEXT: {{.*}} nop # NOADDR-NEXT: {{.*}} nop
.text .text
.globl foo .globl foo
.type foo, @function .type foo, @function
foo: foo:
nop nop
nop nop
bar: bar:
nop nop

llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test

## Test that --section works correctly for -d with -r. ## Test that --section works correctly for -d with -r.
# RUN: yaml2obj %s -o %t.o # RUN: yaml2obj %s -o %t.o
## Show that only the specified sections are disassembled. ## Show that only the specified sections are disassembled.
## Also show that no relocation sections are dumped because none are ## Also show that no relocation sections are dumped because none are
## specified. ## specified.
# RUN: llvm-objdump -d -r %t.o --section=.text --section=.rodata \ # RUN: llvm-objdump -d -r %t.o --section=.text --section=.rodata \
# RUN: | FileCheck %s --check-prefixes=DISASM,RELOC --implicit-check-not=.text2 # RUN: | FileCheck %s --check-prefixes=DISASM,RELOC --implicit-check-not=.text2
# DISASM: Disassembly of section .text: # DISASM: Disassembly of section .text:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: 0000000000000400 .text: # DISASM-NEXT: 0000000000000400 <.text>:
# DISASM-NEXT: 400: e8 00 00 00 00 callq 0 <.text+0x5> # DISASM-NEXT: 400: e8 00 00 00 00 callq 0 <.text+0x5>
# RELOC-NEXT: 00000401: R_X86_64_PC32 foo+0x1 # RELOC-NEXT: 00000401: R_X86_64_PC32 foo+0x1
# RELOC-NEXT: 00000401: R_X86_64_GOT32 foo # RELOC-NEXT: 00000401: R_X86_64_GOT32 foo
# DISASM: Disassembly of section .rodata: # DISASM: Disassembly of section .rodata:
# DISASM-EMPTY: # DISASM-EMPTY:
# DISASM-NEXT: 0000000000000000 .rodata: # DISASM-NEXT: 0000000000000000 <.rodata>:
# DISASM-NEXT: 0: 00 00 addb %al, (%rax) # DISASM-NEXT: 0: 00 00 addb %al, (%rax)
# RELOC-NEXT: 0000000000000000: R_X86_64_NONE foo # RELOC-NEXT: 0000000000000000: R_X86_64_NONE foo
# DISASM-NEXT: 2: 00 00 addb %al, (%rax) # DISASM-NEXT: 2: 00 00 addb %al, (%rax)
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/test/tools/llvm-objdump/X86/source-interleave-function-from-debug.test

;; Verify that llvm-objdump -l also prints the function name in disassembly ;; Verify that llvm-objdump -l also prints the function name in disassembly
;; output, getting it from the debug info. ;; output, getting it from the debug info.
; RUN: llc < %s -o %t.o -filetype=obj -mtriple=x86_64-unknown-linux-gnu ; RUN: llc < %s -o %t.o -filetype=obj -mtriple=x86_64-unknown-linux-gnu
; RUN: llvm-objdump -dl %t.o | FileCheck %s --check-prefixes=CHECK,CHECK-NO-DEMANGLE ; RUN: llvm-objdump -dl %t.o | FileCheck %s --check-prefixes=CHECK,CHECK-NO-DEMANGLE
; RUN: llc < %s -o %t.o -filetype=obj -mtriple=x86_64-unknown-linux-gnu ; RUN: llc < %s -o %t.o -filetype=obj -mtriple=x86_64-unknown-linux-gnu
; RUN: llvm-objdump -dlC %t.o | FileCheck %s --check-prefixes=CHECK,CHECK-DEMANGLE ; RUN: llvm-objdump -dlC %t.o | FileCheck %s --check-prefixes=CHECK,CHECK-DEMANGLE
; CHECK: 0000000000000000 foo: ; CHECK: 0000000000000000 <foo>:
; CHECK-NEXT: ; foo(): ; CHECK-NEXT: ; foo():
; CHECK-NEXT: ; /tmp{{/|\\}}src.cc:1 ; CHECK-NEXT: ; /tmp{{/|\\}}src.cc:1
; CHECK-NEXT: 0: b8 05 00 00 00 movl $5, %eax ; CHECK-NEXT: 0: b8 05 00 00 00 movl $5, %eax
; CHECK-NEXT: 5: c3 retq ; CHECK-NEXT: 5: c3 retq
; CHECK-NO-DEMANGLE: 0000000000000010 _ZN3xyz3barEv: ; CHECK-NO-DEMANGLE: 0000000000000010 <_ZN3xyz3barEv>:
; CHECK-NO-DEMANGLE-NEXT: ; _ZN3xyz3barEv(): ; CHECK-NO-DEMANGLE-NEXT: ; _ZN3xyz3barEv():
; CHECK-DEMANGLE: 0000000000000010 xyz::bar(): ; CHECK-DEMANGLE: 0000000000000010 <xyz::bar()>:
; CHECK-DEMANGLE-NEXT: ; xyz::bar(): ; CHECK-DEMANGLE-NEXT: ; xyz::bar():
; CHECK-NEXT: ; /tmp{{/|\\}}src.cc:3 ; CHECK-NEXT: ; /tmp{{/|\\}}src.cc:3
; CHECK-NEXT: 10: b8 0a 00 00 00 movl $10, %eax ; CHECK-NEXT: 10: b8 0a 00 00 00 movl $10, %eax
; CHECK-NEXT: 15: c3 retq ; CHECK-NEXT: 15: c3 retq
; CHECK-NO-DEMANGLE: 0000000000000020 _ZN3xyz3bazEv: ; CHECK-NO-DEMANGLE: 0000000000000020 <_ZN3xyz3bazEv>:
; CHECK-NO-DEMANGLE-NEXT: ; _ZN3xyz3bazEv(): ; CHECK-NO-DEMANGLE-NEXT: ; _ZN3xyz3bazEv():
; CHECK-DEMANGLE: 0000000000000020 xyz::baz(): ; CHECK-DEMANGLE: 0000000000000020 <xyz::baz()>:
; CHECK-DEMANGLE-NEXT: ; xyz::baz(): ; CHECK-DEMANGLE-NEXT: ; xyz::baz():
; CHECK-NEXT: ; /tmp{{/|\\}}src.cc:3 ; CHECK-NEXT: ; /tmp{{/|\\}}src.cc:3
; CHECK-NEXT: 20: b8 14 00 00 00 movl $20, %eax ; CHECK-NEXT: 20: b8 14 00 00 00 movl $20, %eax
; CHECK-NEXT: 25: c3 retq ; CHECK-NEXT: 25: c3 retq
;; When symbol information is missing, we can get function names from debug ;; When symbol information is missing, we can get function names from debug
;; info. The IR is intentionally doctored to have different names in debug info ;; info. The IR is intentionally doctored to have different names in debug info
;; for the test case here. ;; for the test case here.
; RUN: llvm-strip %t.o -N foo -N _ZN3xyz3barEv -N _ZN3xyz3bazEv -o %t-stripped.o ; RUN: llvm-strip %t.o -N foo -N _ZN3xyz3barEv -N _ZN3xyz3bazEv -o %t-stripped.o
; RUN: llvm-objdump -dlC %t-stripped.o | FileCheck %s --check-prefix=STRIPPED ; RUN: llvm-objdump -dlC %t-stripped.o | FileCheck %s --check-prefix=STRIPPED
; STRIPPED: 0000000000000000 .text: ; STRIPPED: 0000000000000000 <.text>:
; STRIPPED-NEXT: ; Function1(): ; STRIPPED-NEXT: ; Function1():
; STRIPPED-NEXT: ; /tmp{{/|\\}}src.cc:1 ; STRIPPED-NEXT: ; /tmp{{/|\\}}src.cc:1
; STRIPPED-NEXT: 0: b8 05 00 00 00 movl $5, %eax ; STRIPPED-NEXT: 0: b8 05 00 00 00 movl $5, %eax
; STRIPPED-NEXT: 5: c3 retq ; STRIPPED-NEXT: 5: c3 retq
; STRIPPED: ; xyz::bar(): ; STRIPPED: ; xyz::bar():
; STRIPPED-NEXT: ; /tmp{{/|\\}}src.cc:3 ; STRIPPED-NEXT: ; /tmp{{/|\\}}src.cc:3
; STRIPPED-NEXT: 10: b8 0a 00 00 00 movl $10, %eax ; STRIPPED-NEXT: 10: b8 0a 00 00 00 movl $10, %eax
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

llvm/test/tools/llvm-objdump/X86/source-interleave-invalid-source.test

## Test llvm-objdump's --source behaviour when a line number is greater than the ## Test llvm-objdump's --source behaviour when a line number is greater than the
## file length and ensure that we emit a warning. ## file length and ensure that we emit a warning.
# RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %p/Inputs/source-interleave.ll > %t.ll # RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %p/Inputs/source-interleave.ll > %t.ll
# RUN: sed -e "s,line: 7,line: 9999,g" %t.ll > %t2.ll # RUN: sed -e "s,line: 7,line: 9999,g" %t.ll > %t2.ll
# RUN: llc -o %t.o -filetype=obj -mtriple=x86_64-pc-linux %t.ll # RUN: llc -o %t.o -filetype=obj -mtriple=x86_64-pc-linux %t.ll
# RUN: llc -o %t2.o -filetype=obj -mtriple=x86_64-pc-linux %t2.ll # RUN: llc -o %t2.o -filetype=obj -mtriple=x86_64-pc-linux %t2.ll
# RUN: llvm-objdump --source %t.o | FileCheck %s --check-prefixes=CHECK,GOOD # RUN: llvm-objdump --source %t.o | FileCheck %s --check-prefixes=CHECK,GOOD
# RUN: llvm-objdump --source %t2.o 2> %t2.e | FileCheck %s --check-prefixes=CHECK --implicit-check-not="int *b = &a;" # RUN: llvm-objdump --source %t2.o 2> %t2.e | FileCheck %s --check-prefixes=CHECK --implicit-check-not="int *b = &a;"
# RUN: FileCheck %s --input-file %t2.e --check-prefixes=WARN # RUN: FileCheck %s --input-file %t2.e --check-prefixes=WARN
# CHECK: main: # CHECK: <main>:
# CHECK-NEXT: ; int main() { # CHECK-NEXT: ; int main() {
# WARN: warning: '{{.*}}': debug info line number 9999 exceeds the number of lines in {{.*}}source-interleave-x86_64.c # WARN: warning: '{{.*}}': debug info line number 9999 exceeds the number of lines in {{.*}}source-interleave-x86_64.c
# GOOD: ; int *b = &a; # GOOD: ; int *b = &a;
# CHECK: ; return *b + foo(); # CHECK: ; return *b + foo();

llvm/test/tools/llvm-objdump/X86/source-interleave-missing-source.test

## Test that if the source cannot be found that disassembly is still printed, ## Test that if the source cannot be found that disassembly is still printed,
## that no source is printed, and that we emit a warning. ## that no source is printed, and that we emit a warning.
# RUN: sed -e "s,SRC_COMPDIR,%/t,g" %p/Inputs/source-interleave.ll > %t.ll # RUN: sed -e "s,SRC_COMPDIR,%/t,g" %p/Inputs/source-interleave.ll > %t.ll
# RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %p/Inputs/source-interleave.ll > %t2.ll # RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %p/Inputs/source-interleave.ll > %t2.ll
# RUN: llc -o %t.o -filetype=obj -mtriple=x86_64-pc-linux %t.ll # RUN: llc -o %t.o -filetype=obj -mtriple=x86_64-pc-linux %t.ll
# RUN: llc -o %t2.o -filetype=obj -mtriple=x86_64-pc-linux %t2.ll # RUN: llc -o %t2.o -filetype=obj -mtriple=x86_64-pc-linux %t2.ll
# RUN: llvm-objdump --source %t.o 2> %t.e | FileCheck %s --check-prefixes=CHECK --implicit-check-not='main()' # RUN: llvm-objdump --source %t.o 2> %t.e | FileCheck %s --check-prefixes=CHECK --implicit-check-not='main()'
# RUN: llvm-objdump --source %t2.o | FileCheck %s --check-prefixes=CHECK,SOURCE # RUN: llvm-objdump --source %t2.o | FileCheck %s --check-prefixes=CHECK,SOURCE
# RUN: FileCheck %s --input-file %t.e --check-prefixes=WARN # RUN: FileCheck %s --input-file %t.e --check-prefixes=WARN
# WARN: warning: '{{.*}}': failed to find source {{.*}}source-interleave-x86_64.c # WARN: warning: '{{.*}}': failed to find source {{.*}}source-interleave-x86_64.c
# CHECK: 0000000000000010 main: # CHECK: 0000000000000010 <main>:
# SOURCE-NEXT: ; int main() { # SOURCE-NEXT: ; int main() {
# CHECK-NEXT: 10: 55 pushq %rbp # CHECK-NEXT: 10: 55 pushq %rbp

llvm/test/tools/llvm-objdump/X86/source-interleave-no-debug-info.test

## Test that if an object has no debug information, only the disassembly is ## Test that if an object has no debug information, only the disassembly is
## printed when --source is specified, and that we emit a warning. ## printed when --source is specified, and that we emit a warning.
# RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %p/Inputs/source-interleave.ll > %t.ll # RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %p/Inputs/source-interleave.ll > %t.ll
# RUN: llc -o %t.o -filetype=obj -mtriple=x86_64-pc-linux %t.ll # RUN: llc -o %t.o -filetype=obj -mtriple=x86_64-pc-linux %t.ll
# RUN: llvm-objcopy --strip-debug %t.o %t2.o # RUN: llvm-objcopy --strip-debug %t.o %t2.o
# RUN: llvm-objdump --source %t.o | FileCheck %s --check-prefixes=CHECK,SOURCE # RUN: llvm-objdump --source %t.o | FileCheck %s --check-prefixes=CHECK,SOURCE
# RUN: llvm-objdump --source %t2.o 2> %t2.e | FileCheck %s --check-prefixes=CHECK --implicit-check-not='main()' # RUN: llvm-objdump --source %t2.o 2> %t2.e | FileCheck %s --check-prefixes=CHECK --implicit-check-not='main()'
# RUN: FileCheck %s --input-file %t2.e --check-prefixes=WARN # RUN: FileCheck %s --input-file %t2.e --check-prefixes=WARN
# WARN: warning: '{{.*}}2.o': failed to parse debug information # WARN: warning: '{{.*}}2.o': failed to parse debug information
# CHECK: 0000000000000010 main: # CHECK: 0000000000000010 <main>:
# SOURCE-NEXT: ; int main() { # SOURCE-NEXT: ; int main() {
# CHECK-NEXT: 10: 55 pushq %rbp # CHECK-NEXT: 10: 55 pushq %rbp

llvm/test/tools/llvm-objdump/X86/source-interleave-relative-paths.test

Show All 25 Lines
# RUN: llvm-objdump --source c.o | FileCheck %s --check-prefixes=CHECK,SOURCE # RUN: llvm-objdump --source c.o | FileCheck %s --check-prefixes=CHECK,SOURCE
# RUN: llvm-objdump --source d.o | FileCheck %s --implicit-check-not='main()' # RUN: llvm-objdump --source d.o | FileCheck %s --implicit-check-not='main()'
# RUN: cd b # RUN: cd b
# RUN: llvm-objdump --source ../a.o | FileCheck %s --implicit-check-not='main()' # RUN: llvm-objdump --source ../a.o | FileCheck %s --implicit-check-not='main()'
# RUN: llvm-objdump --source ../b.o | FileCheck %s --implicit-check-not='main()' # RUN: llvm-objdump --source ../b.o | FileCheck %s --implicit-check-not='main()'
# RUN: llvm-objdump --source ../c.o | FileCheck %s --implicit-check-not='main()' # RUN: llvm-objdump --source ../c.o | FileCheck %s --implicit-check-not='main()'
# RUN: llvm-objdump --source ../d.o | FileCheck %s --check-prefixes=CHECK,SOURCE # RUN: llvm-objdump --source ../d.o | FileCheck %s --check-prefixes=CHECK,SOURCE
# CHECK: 0000000000000010 main: # CHECK: 0000000000000010 <main>:
# SOURCE-NEXT: ; int main() { # SOURCE-NEXT: ; int main() {
# CHECK-NEXT: 10: 55 pushq %rbp # CHECK-NEXT: 10: 55 pushq %rbp

llvm/test/tools/llvm-objdump/X86/source-interleave-same-line-different-file.test

## Test that source is printed when subsequent lines in the translation unit ## Test that source is printed when subsequent lines in the translation unit
## come from the same line in two different files. ## come from the same line in two different files.
# RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %p/Inputs/source-interleave-same-line-different-file.ll > %t.ll # RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %p/Inputs/source-interleave-same-line-different-file.ll > %t.ll
# RUN: llc -o %t.o -filetype=obj -mtriple=x86_64-pc-linux %t.ll # RUN: llc -o %t.o -filetype=obj -mtriple=x86_64-pc-linux %t.ll
# RUN: llvm-objdump --source %t.o | FileCheck %s # RUN: llvm-objdump --source %t.o | FileCheck %s
# CHECK: 0000000000000000 add1: # CHECK: 0000000000000000 <add1>:
# CHECK-NEXT: ; int add1(int a) { return a + 1; } # CHECK-NEXT: ; int add1(int a) { return a + 1; }
# #
# CHECK: 0000000000000010 return4: # CHECK: 0000000000000010 <return4>:
# CHECK-NEXT: ; int return4() { return 4; } # CHECK-NEXT: ; int return4() { return 4; }

llvm/test/tools/llvm-objdump/X86/source-interleave-x86_64.test

# RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %p/Inputs/source-interleave.ll > %t.ll # RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %p/Inputs/source-interleave.ll > %t.ll
# RUN: llc -o %t.o -filetype=obj -mtriple=x86_64-pc-linux %t.ll # RUN: llc -o %t.o -filetype=obj -mtriple=x86_64-pc-linux %t.ll
# RUN: llvm-objdump -d -l %t.o >%t0 # RUN: llvm-objdump -d -l %t.o >%t0
# RUN: llvm-objdump -dl %t.o >%t1 # RUN: llvm-objdump -dl %t.o >%t1
# RUN: llvm-objdump -d -S %t.o >%t2 # RUN: llvm-objdump -d -S %t.o >%t2
# RUN: llvm-objdump -dS %t.o >%t3 # RUN: llvm-objdump -dS %t.o >%t3
# RUN: cmp %t0 %t1 # RUN: cmp %t0 %t1
# RUN: cmp %t2 %t3 # RUN: cmp %t2 %t3
# RUN: FileCheck --check-prefix=LINES %s < %t0 # RUN: FileCheck --check-prefix=LINES %s < %t0
# RUN: FileCheck --check-prefix=SOURCE --strict-whitespace %s < %t2 # RUN: FileCheck --check-prefix=SOURCE --strict-whitespace %s < %t2
# LINES: main: # LINES: <main>:
# LINES-NEXT: ; main(): # LINES-NEXT: ; main():
# LINES-NEXT: ; {{[ -\(\)_A-Za-z0-9.\\/:]+}}source-interleave-x86_64.c:6 # LINES-NEXT: ; {{[ -\(\)_A-Za-z0-9.\\/:]+}}source-interleave-x86_64.c:6
# SOURCE: main: # SOURCE: <main>:
# SOURCE-NEXT: ; int main() { # SOURCE-NEXT: ; int main() {
# SOURCE: ; int *b = &a; # SOURCE: ; int *b = &a;

llvm/test/tools/llvm-objdump/X86/start-stop-address-relocatable-object.test

## Show how --start-address and --stop-address work in a relocatable object. ## Show how --start-address and --stop-address work in a relocatable object.
## They limit the disassembly to the relative offset ranges within sections. ## They limit the disassembly to the relative offset ranges within sections.
# RUN: yaml2obj %s -o %t.o # RUN: yaml2obj %s -o %t.o
# RUN: llvm-objdump -d %t.o --start-address=1 --stop-address=2 | FileCheck %s --check-prefix=COMMON # RUN: llvm-objdump -d %t.o --start-address=1 --stop-address=2 | FileCheck %s --check-prefix=COMMON
# RUN: llvm-objdump -d %t.o --start-address=1 | FileCheck %s --check-prefixes=START,COMMON # RUN: llvm-objdump -d %t.o --start-address=1 | FileCheck %s --check-prefixes=START,COMMON
# RUN: llvm-objdump -d %t.o --stop-address=2 | FileCheck %s --check-prefixes=STOP,COMMON # RUN: llvm-objdump -d %t.o --stop-address=2 | FileCheck %s --check-prefixes=STOP,COMMON
# COMMON: Disassembly of section .text: # COMMON: Disassembly of section .text:
# COMMON-EMPTY: # COMMON-EMPTY:
# COMMON-NEXT: 0000000000000000 .text: # COMMON-NEXT: 0000000000000000 <.text>:
# STOP-NEXT: 0: 90 nop # STOP-NEXT: 0: 90 nop
# COMMON-NEXT: 1: 90 nop # COMMON-NEXT: 1: 90 nop
# START-NEXT: 2: 90 nop # START-NEXT: 2: 90 nop
# COMMON-EMPTY: # COMMON-EMPTY:
# COMMON-NEXT: Disassembly of section .text2: # COMMON-NEXT: Disassembly of section .text2:
# COMMON-EMPTY: # COMMON-EMPTY:
# COMMON-NEXT: 0000000000000000 .text2: # COMMON-NEXT: 0000000000000000 <.text2>:
# STOP-NEXT: 0: c3 retq # STOP-NEXT: 0: c3 retq
# COMMON-NEXT: 1: c3 retq # COMMON-NEXT: 1: c3 retq
# START-NEXT: 2: c3 retq # START-NEXT: 2: c3 retq
# STOP-EMPTY: # STOP-EMPTY:
# STOP-NEXT: Disassembly of section .text3: # STOP-NEXT: Disassembly of section .text3:
# STOP-EMPTY: # STOP-EMPTY:
# STOP-NEXT: 0000000000000000 .text3: # STOP-NEXT: 0000000000000000 <.text3>:
# STOP-NEXT: 0: cc int3 # STOP-NEXT: 0: cc int3
# COMMON-NOT: {{.}} # COMMON-NOT: {{.}}
--- !ELF --- !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_REL Type: ET_REL
Show All 14 Lines

llvm/test/tools/llvm-objdump/X86/start-stop-address.test

// RUN: yaml2obj -o %t.out %p/Inputs/simple-executable-x86_64.yaml // RUN: yaml2obj -o %t.out %p/Inputs/simple-executable-x86_64.yaml
// RUN: llvm-objdump -d %t.out --start-address=0x18 --stop-address=0x2f | FileCheck %s // RUN: llvm-objdump -d %t.out --start-address=0x18 --stop-address=0x2f | FileCheck %s
// RUN: llvm-objdump -d %t.out --start-address=0xc --stop-address=0x11 | FileCheck %s --check-prefix CROSSSECTION // RUN: llvm-objdump -d %t.out --start-address=0xc --stop-address=0x11 | FileCheck %s --check-prefix CROSSSECTION
// RUN: llvm-objdump -d %t.out --start-address=0x40 --stop-address=0x47 | FileCheck %s --check-prefix CROSSDATA // RUN: llvm-objdump -d %t.out --start-address=0x40 --stop-address=0x47 | FileCheck %s --check-prefix CROSSDATA
// RUN: llvm-objdump -d %t.out --start-address=0x40 | FileCheck %s --check-prefix START // RUN: llvm-objdump -d %t.out --start-address=0x40 | FileCheck %s --check-prefix START
// RUN: llvm-objdump -d %t.out --stop-address=0x11 | FileCheck %s --check-prefix STOP // RUN: llvm-objdump -d %t.out --stop-address=0x11 | FileCheck %s --check-prefix STOP
// RUN: llvm-objdump -d %t.out --start-address=0xffffffff | FileCheck %s --check-prefix OUT-OF-RANGE // RUN: llvm-objdump -d %t.out --start-address=0xffffffff | FileCheck %s --check-prefix OUT-OF-RANGE
// CHECK-NOT: Disassembly // CHECK-NOT: Disassembly
// CHECK: Disassembly of section .anothertext: // CHECK: Disassembly of section .anothertext:
// CHECK-EMPTY: // CHECK-EMPTY:
// CHECK-NEXT: main: // CHECK-NEXT: <main>:
// CHECK-NEXT: 18: 48 8d 04 25 a8 00 00 00 leaq 168, %rax // CHECK-NEXT: 18: 48 8d 04 25 a8 00 00 00 leaq 168, %rax
// CHECK-NEXT: 20: c7 45 fc 00 00 00 00 movl $0, -4(%rbp) // CHECK-NEXT: 20: c7 45 fc 00 00 00 00 movl $0, -4(%rbp)
// CHECK-NEXT: 27: 48 89 45 f0 movq %rax, -16(%rbp) // CHECK-NEXT: 27: 48 89 45 f0 movq %rax, -16(%rbp)
// CHECK-NEXT: 2b: 48 8b 45 f0 movq -16(%rbp), %rax // CHECK-NEXT: 2b: 48 8b 45 f0 movq -16(%rbp), %rax
// CHECK-NOT: {{.}} // CHECK-NOT: {{.}}
// CROSSECTION-NOT: Disassembly // CROSSECTION-NOT: Disassembly
// CROSSSECTION: Disassembly of section .text: // CROSSSECTION: Disassembly of section .text:
// CROSSSECTION-EMPTY: // CROSSSECTION-EMPTY:
// CROSSSECTION-NEXT: foo: // CROSSSECTION-NEXT: <foo>:
// CROSSSECTION-NEXT: c: c3 retq // CROSSSECTION-NEXT: c: c3 retq
// CROSSSECTION-NEXT: d: 0f 1f 00 nopl (%rax) // CROSSSECTION-NEXT: d: 0f 1f 00 nopl (%rax)
// CROSSSECTION-EMPTY: // CROSSSECTION-EMPTY:
// CROSSSECTION-NEXT: Disassembly of section .anothertext: // CROSSSECTION-NEXT: Disassembly of section .anothertext:
// CROSSSECTION-EMPTY: // CROSSSECTION-EMPTY:
// CROSSSECTION-NEXT: main: // CROSSSECTION-NEXT: <main>:
// CROSSSECTION-NEXT: 10: 55 pushq %rbp // CROSSSECTION-NEXT: 10: 55 pushq %rbp
// CROSSSECTION-NOT: {{.}} // CROSSSECTION-NOT: {{.}}
// CROSSDATA-NOT: Disassembly // CROSSDATA-NOT: Disassembly
// CROSSDATA: Disassembly of section .anothertext: // CROSSDATA: Disassembly of section .anothertext:
// CROSSDATA: main: // CROSSDATA: <main>:
// CROSSDATA: 40: 48 83 c4 20 addq $32, %rsp // CROSSDATA: 40: 48 83 c4 20 addq $32, %rsp
// CROSSDATA: 44: 5d popq %rbp // CROSSDATA: 44: 5d popq %rbp
// CROSSDATA-DAG: somedata: // CROSSDATA-DAG: <somedata>:
// CROSSDATA-NEXT: 45: 74 65 te // CROSSDATA-NEXT: 45: 74 65 te
// CROSSDATA-NOT: {{.}} // CROSSDATA-NOT: {{.}}
// START-NOT: Disassembly // START-NOT: Disassembly
// START: Disassembly of section .anothertext: // START: Disassembly of section .anothertext:
// START-EMPTY: // START-EMPTY:
// START-NEXT: 0000000000000010 main: // START-NEXT: 0000000000000010 <main>:
// START-NEXT: 40: 48 83 c4 20 addq $32, %rsp // START-NEXT: 40: 48 83 c4 20 addq $32, %rsp
// START-NEXT: 44: 5d popq %rbp // START-NEXT: 44: 5d popq %rbp
// START-EMPTY: // START-EMPTY:
// START-NEXT: 0000000000000045 somedata: // START-NEXT: 0000000000000045 <somedata>:
// START-NEXT: 45: 74 65 73 74 20 73 74 72 test str // START-NEXT: 45: 74 65 73 74 20 73 74 72 test str
// START-NEXT: 4d: 00 c3 .. // START-NEXT: 4d: 00 c3 ..
// STOP: Disassembly of section .text: // STOP: Disassembly of section .text:
// STOP-EMPTY: // STOP-EMPTY:
// STOP-NEXT: 0000000000000000 foo: // STOP-NEXT: 0000000000000000 <foo>:
// STOP-NEXT: 0: 55 pushq %rbp // STOP-NEXT: 0: 55 pushq %rbp
// STOP-NEXT: 1: 48 89 e5 movq %rsp, %rbp // STOP-NEXT: 1: 48 89 e5 movq %rsp, %rbp
// STOP-NEXT: 4: 8b 04 25 a8 00 00 00 movl 168, %eax // STOP-NEXT: 4: 8b 04 25 a8 00 00 00 movl 168, %eax
// STOP-NEXT: b: 5d popq %rbp // STOP-NEXT: b: 5d popq %rbp
// STOP-NEXT: c: c3 retq // STOP-NEXT: c: c3 retq
// STOP-NEXT: d: 0f 1f 00 nopl (%rax) // STOP-NEXT: d: 0f 1f 00 nopl (%rax)
// STOP-EMPTY: // STOP-EMPTY:
// STOP-NEXT: Disassembly of section .anothertext: // STOP-NEXT: Disassembly of section .anothertext:
// STOP-EMPTY: // STOP-EMPTY:
// STOP-NEXT: 0000000000000010 main: // STOP-NEXT: 0000000000000010 <main>:
// STOP-NEXT: 10: 55 pushq %rbp // STOP-NEXT: 10: 55 pushq %rbp
// STOP-NOT: {{.}} // STOP-NOT: {{.}}
// OUT-OF-RANGE-NOT: Disassembly // OUT-OF-RANGE-NOT: Disassembly
// RUN: not llvm-objdump %t.out --start-address=0x40 --stop-address=0x3f 2>&1 | FileCheck %s --check-prefix ERRMSG // RUN: not llvm-objdump %t.out --start-address=0x40 --stop-address=0x3f 2>&1 | FileCheck %s --check-prefix ERRMSG
// RUN: not llvm-objdump %t.out --start-address=0x40 --stop-address=0x40 2>&1 | FileCheck %s --check-prefix ERRMSG // RUN: not llvm-objdump %t.out --start-address=0x40 --stop-address=0x40 2>&1 | FileCheck %s --check-prefix ERRMSG
// ERRMSG: start address should be less than stop address // ERRMSG: start address should be less than stop address

llvm/test/tools/llvm-objdump/embedded-source.test

; RUN: llvm-objdump -disassemble -line-numbers %p/Inputs/embedded-source | FileCheck --check-prefix=LINE %s ; RUN: llvm-objdump -disassemble -line-numbers %p/Inputs/embedded-source | FileCheck --check-prefix=LINE %s
; RUN: llvm-objdump -disassemble -source %p/Inputs/embedded-source | FileCheck --check-prefix=SOURCE %s ; RUN: llvm-objdump -disassemble -source %p/Inputs/embedded-source | FileCheck --check-prefix=SOURCE %s
; REQUIRES: x86-registered-target ; REQUIRES: x86-registered-target
; Source for embedded-source.c ; Source for embedded-source.c
; To regenerate this file: ; To regenerate this file:
; clang -gdwarf-5 -gembed-source embedded-source.c -o embedded-source ; clang -gdwarf-5 -gembed-source embedded-source.c -o embedded-source
; ;
; int main(int argc, char *argv[]) { ; int main(int argc, char *argv[]) {
; int i = 2; ; int i = 2;
; i += 1; ; i += 1;
; return i; ; return i;
; } ; }
; LINE: main: ; LINE: <main>:
; LINE-NEXT: ; main(): ; LINE-NEXT: ; main():
; LINE-NEXT: ; {{.*}}embedded-source.c:1 ; LINE-NEXT: ; {{.*}}embedded-source.c:1
; LINE-NEXT: pushq %rbp ; LINE-NEXT: pushq %rbp
; LINE: ; {{.*}}embedded-source.c:2 ; LINE: ; {{.*}}embedded-source.c:2
; LINE-NEXT: movl $2 ; LINE-NEXT: movl $2
; LINE: ; {{.*}}embedded-source.c:3 ; LINE: ; {{.*}}embedded-source.c:3
; LINE: addl $1 ; LINE: addl $1
; LINE: ; {{.*}}embedded-source.c:4 ; LINE: ; {{.*}}embedded-source.c:4
; LINE: retq ; LINE: retq
; SOURCE: main: ; SOURCE: <main>:
; SOURCE-NEXT: ; int main(int argc, char *argv[]) { ; SOURCE-NEXT: ; int main(int argc, char *argv[]) {
; SOURCE-NEXT: pushq %rbp ; SOURCE-NEXT: pushq %rbp
; SOURCE: ; int i = 2; ; SOURCE: ; int i = 2;
; SOURCE-NEXT: movl $2 ; SOURCE-NEXT: movl $2
; SOURCE: ; i += 1; ; SOURCE: ; i += 1;
; SOURCE: addl $1 ; SOURCE: addl $1
; SOURCE: ; return i; ; SOURCE: ; return i;
; SOURCE: retq ; SOURCE: retq

llvm/test/tools/llvm-objdump/xcoff-disassemble-all.test

Show All 9 Lines
# __thread double d = 3.14159; # __thread double d = 3.14159;
# #
# int func(void) { # int func(void) {
# return a; # return a;
# } # }
; REQUIRES: powerpc-registered-target ; REQUIRES: powerpc-registered-target
CHECK: Inputs/xcoff-section-headers.o: file format aixcoff-rs6000 CHECK: Inputs/xcoff-section-headers.o: file format aixcoff-rs6000
CHECK: Disassembly of section .text: CHECK: Disassembly of section .text:
CHECK: 00000000 .text: CHECK: 00000000 <.text>:
CHECK-NEXT: 0: 80 62 00 04 lwz 3, 4(2) CHECK-NEXT: 0: 80 62 00 04 lwz 3, 4(2)
CHECK-NEXT: 4: 80 63 00 00 lwz 3, 0(3) CHECK-NEXT: 4: 80 63 00 00 lwz 3, 0(3)
CHECK-NEXT: 8: 4e 80 00 20 blr CHECK-NEXT: 8: 4e 80 00 20 blr
CHECK-NEXT: c: 00 00 00 00 <unknown> CHECK-NEXT: c: 00 00 00 00 <unknown>
CHECK-NEXT: 10: 00 00 20 40 <unknown> CHECK-NEXT: 10: 00 00 20 40 <unknown>
CHECK-NEXT: 14: 00 00 00 01 <unknown> CHECK-NEXT: 14: 00 00 00 01 <unknown>
CHECK-NEXT: 18: 00 00 00 0c <unknown> CHECK-NEXT: 18: 00 00 00 0c <unknown>
CHECK-NEXT: 1c: 00 04 66 75 <unknown> CHECK-NEXT: 1c: 00 04 66 75 <unknown>
CHECK-NEXT: 20: 6e 63 00 00 xoris 3, 19, 0 CHECK-NEXT: 20: 6e 63 00 00 xoris 3, 19, 0
CHECK-NEXT: ... CHECK-NEXT: ...
CHECK: Disassembly of section .data: CHECK: Disassembly of section .data:
CHECK: 00000080 func: CHECK: 00000080 <func>:
CHECK-NEXT: 80: 00 00 00 94 <unknown> CHECK-NEXT: 80: 00 00 00 94 <unknown>
CHECK: 00000084 a: CHECK: 00000084 <a>:
CHECK-NEXT: 84: 00 00 00 a4 <unknown> CHECK-NEXT: 84: 00 00 00 a4 <unknown>
CHECK: 00000088 b: CHECK: 00000088 <b>:
CHECK-NEXT: 88: 00 00 00 a0 <unknown> CHECK-NEXT: 88: 00 00 00 a0 <unknown>
CHECK: 0000008c c: CHECK: 0000008c <c>:
CHECK-NEXT: 8c: 00 00 00 08 <unknown> CHECK-NEXT: 8c: 00 00 00 08 <unknown>
CHECK: 00000090 d: CHECK: 00000090 <d>:
CHECK-NEXT: 90: 00 00 00 00 <unknown> CHECK-NEXT: 90: 00 00 00 00 <unknown>
CHECK: 00000094 func: CHECK: 00000094 <func>:
CHECK-NEXT: 94: 00 00 00 00 <unknown> CHECK-NEXT: 94: 00 00 00 00 <unknown>
CHECK-NEXT: 98: 00 00 00 80 <unknown> CHECK-NEXT: 98: 00 00 00 80 <unknown>
CHECK-NEXT: 9c: 00 00 00 00 <unknown> CHECK-NEXT: 9c: 00 00 00 00 <unknown>
CHECK: 000000a0 b: CHECK: 000000a0 <b>:
CHECK-NEXT: a0: 00 00 30 39 <unknown> CHECK-NEXT: a0: 00 00 30 39 <unknown>
CHECK: Disassembly of section .bss: CHECK: Disassembly of section .bss:
CHECK: 000000a4 a: CHECK: 000000a4 <a>:
CHECK-NEXT: ... CHECK-NEXT: ...
CHECK: Disassembly of section .tdata: CHECK: Disassembly of section .tdata:
CHECK: 00000000 d: CHECK: 00000000 <d>:
CHECK-NEXT: 0: 40 09 21 f9 bdnzfl 9, .+8696 CHECK-NEXT: 0: 40 09 21 f9 bdnzfl 9, .+8696
CHECK-NEXT: 4: f0 1b 86 6e <unknown> CHECK-NEXT: 4: f0 1b 86 6e <unknown>
CHECK: Disassembly of section .tbss: CHECK: Disassembly of section .tbss:
CHECK: 00000008 c: CHECK: 00000008 <c>:
CHECK-NEXT: ... CHECK-NEXT: ...

llvm/tools/llvm-objdump/llvm-objdump.cpp

Show First 20 Lines • Show All 1,366 Lines • ▼ Show 20 Lines for (unsigned SI = 0, SE = Symbols.size(); SI != SE; ++SI) {
} }
} }
outs() << '\n'; outs() << '\n';
if (!NoLeadingAddr) if (!NoLeadingAddr)
outs() << format(Is64Bits ? "%016" PRIx64 " " : "%08" PRIx64 " ", outs() << format(Is64Bits ? "%016" PRIx64 " " : "%08" PRIx64 " ",
SectionAddr + Start + VMAAdjustment); SectionAddr + Start + VMAAdjustment);
outs() << SymbolName << ":\n"; outs() << '<' << SymbolName << ">:\n";
// Don't print raw contents of a virtual section. A virtual section // Don't print raw contents of a virtual section. A virtual section
// doesn't have any contents in the file. // doesn't have any contents in the file.
if (Section.isVirtual()) { if (Section.isVirtual()) {
outs() << "...\n"; outs() << "...\n";
continue; continue;
} }
▲ Show 20 Lines • Show All 993 Lines • Show Last 20 Lines