This is equivalent to previous patches (e.g. 07355c1c0) for the x86 ABIs.
One name fixup is needed -- lldb refers to the floating/vector registers by
their vector name (vN). Llvm does not use this name, so we map it to qN,
representing the register as a single 128 bit value (this choice is fairly
arbitrary -- any other name would also work fine as they all have the same
DWARF number).
This is here to ensure identical behavior to the previous code, but I am not sure it is really needed/correct. Arm-dwarf spec does not assign a register number to the pc (number 32, used by lldb, is reserved) or cpsr (number 33 is assigned to ELR_mode).
Llvm does not use either of these numbers, so at least no llvm-based toolchain should be generating them.