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[PowerPC] Exploit VSX neg, abs and nabs instruction for f32
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Authored by qiucf on Feb 28 2020, 4:57 AM.

Details

Summary

xsnegdp, xsabsdp and xsnabsdp can all be used to operate on f32 operand, but we don't have patterns to generate them. This patch adds the missing patterns since we prefer VSX instructions when available.

Diff Detail

Event Timeline

qiucf created this revision.Feb 28 2020, 4:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 28 2020, 4:57 AM
qiucf marked an inline comment as done.Feb 28 2020, 5:00 AM
qiucf added inline comments.
llvm/test/CodeGen/PowerPC/fma.ll
130

I know here looks like a regression. But I'm drafting another patch to disable nmsub instruction when no nsz flag set. So the pattern will be removed from td file and we can get xsnmsubadp naturally.

steven.zhang added inline comments.
llvm/test/CodeGen/PowerPC/fma.ll
130

So, could you please post that patch here as the parent revision of this one, then update the patch, so that, we could have a clear picture.

Thanks for posting this. This LGTM.

Could you also help to check if the following pairs can also be changed accordingly?
{stxsspx, stfsx}
{lxsspx, lfsx}
{stxsiwx, stfiwx}
{xssubsp, fsubs}
{xsmulsp, fmuls}
{xsdivsp, fdivs}
{xssqrtsp, fsqrts}
{xsrsqrtesq, frsqrtes}
{lxsiwzx, lfiwzx}
{lxsiwax, lfiwax}
{xsresp, fres}
{xsmsubasp, fmsubs}
{xsnmsubasp, fnmsubs}

What is the status of this? Also, there is no description for the patch.

qiucf updated this revision to Diff 255904.Apr 7 2020, 11:33 PM
qiucf marked 3 inline comments as done.
qiucf edited the summary of this revision. (Show Details)

Update patch to set proper complexity for XSNEGDP.

qiucf added a comment.Apr 7 2020, 11:41 PM

What is the status of this? Also, there is no description for the patch.

I added description and removed unnecessary parent revision. So this patch is ready for review now.

llvm/test/CodeGen/PowerPC/fma.ll
130

Oh, that's not related to this regression. I've updated this patch to change pattern priority.

steven.zhang added inline comments.Apr 22 2020, 10:30 PM
llvm/lib/Target/PowerPC/PPCInstrVSX.td
1025

Can we use the pred that checking the pwr7 cpu type instead of harding code the complexity ? And the comment here is also unclear to me. You want to have fneg in P7 so that, it could be combined into fnmsub. We cannot combine fmsub + xsnegdp to fnmsub, is it right ? General speaking, still emit the fneg for P7 makes sense to me.

qiucf updated this revision to Diff 259507.Apr 23 2020, 3:25 AM
qiucf marked an inline comment as done.

Address Steven's comments to put xsnegdp pattern under P8.

steven.zhang accepted this revision.Apr 23 2020, 10:42 PM

The patch LGTM now with some comments update. But please hold for several days to see if Nemanjai(@nemanjai) has comments.

llvm/lib/Target/PowerPC/PPCInstrVSX.td
1590

The comments here is confusing. We are adding pattern for fneg and it has nothing to do with XSNMSUBASP though it is combined from fneg + fmsub. We need some comments indicate that, though xsnegdp is added in P7, we still only want to select it starting from P8, as we won't break the combine pattern for fneg + fmsub because XSNMSUBASP is only available starting from P8.

This revision is now accepted and ready to land.Apr 23 2020, 10:42 PM
This revision was automatically updated to reflect the committed changes.