[PowerPC] Exploit VSX neg, abs and nabs instruction for f32

[qiucf]

Summary

xsnegdp, xsabsdp and xsnabsdp can all be used to operate on f32 operand, but we don't have patterns to generate them. This patch adds the missing patterns since we prefer VSX instructions when available.

[qiucf]

llvm/test/CodeGen/PowerPC/fma.ll

130 ↗

(On Diff #247228)

I know here looks like a regression. But I'm drafting another patch to disable nmsub instruction when no nsz flag set. So the pattern will be removed from td file and we can get xsnmsubadp naturally.

[steven.zhang]

llvm/test/CodeGen/PowerPC/fma.ll

130 ↗

(On Diff #247228)

So, could you please post that patch here as the parent revision of this one, then update the patch, so that, we could have a clear picture.

[shchenz]

Thanks for posting this. This LGTM.

Could you also help to check if the following pairs can also be changed accordingly?
{stxsspx, stfsx}
{lxsspx, lfsx}
{stxsiwx, stfiwx}
{xssubsp, fsubs}
{xsmulsp, fmuls}
{xsdivsp, fdivs}
{xssqrtsp, fsqrts}
{xsrsqrtesq, frsqrtes}
{lxsiwzx, lfiwzx}
{lxsiwax, lfiwax}
{xsresp, fres}
{xsmsubasp, fmsubs}
{xsnmsubasp, fnmsubs}

[nemanjai]

What is the status of this? Also, there is no description for the patch.

[qiucf]

Update patch to set proper complexity for XSNEGDP.

[qiucf]

In D75344#1967991, @nemanjai wrote:

What is the status of this? Also, there is no description for the patch.

I added description and removed unnecessary parent revision. So this patch is ready for review now.

llvm/test/CodeGen/PowerPC/fma.ll

130 ↗

(On Diff #247228)

Oh, that's not related to this regression. I've updated this patch to change pattern priority.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1025

Can we use the pred that checking the pwr7 cpu type instead of harding code the complexity ? And the comment here is also unclear to me. You want to have fneg in P7 so that, it could be combined into fnmsub. We cannot combine fmsub + xsnegdp to fnmsub, is it right ? General speaking, still emit the fneg for P7 makes sense to me.

[qiucf]

Address Steven's comments to put xsnegdp pattern under P8.

[steven.zhang]

The patch LGTM now with some comments update. But please hold for several days to see if Nemanjai(@nemanjai) has comments.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1590

The comments here is confusing. We are adding pattern for fneg and it has nothing to do with XSNMSUBASP though it is combined from fneg + fmsub. We need some comments indicate that, though xsnegdp is added in P7, we still only want to select it starting from P8, as we won't break the combine pattern for fneg + fmsub because XSNMSUBASP is only available starting from P8.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def : Pat<(v2f64 (scalar_to_vector f64:$A)),
                            (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;
 
 def : Pat<(f64 (extractelt v2f64:$S, 0)),
           (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
 def : Pat<(f64 (extractelt v2f64:$S, 1)),
           (f64 (EXTRACT_SUBREG $S, sub_64))>;
 }
 
+// Additional patterns for VSX f32 fabs and fnabs
+def : Pat<(f32 (fabs f32:$S)),
+          (f32 (COPY_TO_REGCLASS (XSABSDP
+               (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
+def : Pat<(f32 (fneg (fabs f32:$S))),
+          (f32 (COPY_TO_REGCLASS (XSNABSDP
+               (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
+
+// Additional pattern for VSX f32 fneg
+// XSNMSUBASP was firstly introduced in POWER ISA v2.07, while XSNEGDP exists
+// in v2.06. Reduce extra complexity to generate FNMSUBS in POWER7 targets.
+let AddedComplexity = 1 in
+def : Pat<(f32 (fneg f32:$S)),
+          (f32 (COPY_TO_REGCLASS (XSNEGDP
+               (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
+
 // Additional fnmsub patterns: -a*b + c == -(a*b - c)
 def : Pat<(fma (fneg f64:$A), f64:$B, f64:$C),
           (XSNMSUBADP $C, $A, $B)>;
 def : Pat<(fma f64:$A, (fneg f64:$B), f64:$C),
           (XSNMSUBADP $C, $A, $B)>;
 
 def : Pat<(fma (fneg v2f64:$A), v2f64:$B, v2f64:$C),
           (XVNMSUBADP $C, $A, $B)>;
def XSNMSUBASP : XX3Form<60, 145,
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsnmsubasp $XT, $XA, $XB", IIC_VecFP,
                           [(set f32:$XT, (fneg (fma f32:$XA, f32:$XB,
                                                     (fneg f32:$XTi))))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XSNMSUBMSP : XX3Form<60, 153,
                           (outs vssrc:$XT),
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   // Additional xsnmsubasp patterns: -a*b + c == -(a*b - c)
   def : Pat<(fma (fneg f32:$A), f32:$B, f32:$C),

llvm/test/CodeGen/PowerPC/float-logic-ops.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s
 
 define float @absf(float %a) {
 ; CHECK-LABEL: absf:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    fabs f1, f1
+; CHECK-NEXT:    xsabsdp f1, f1
 ; CHECK-NEXT:    blr
 entry:
   %conv = bitcast float %a to i32
   %and = and i32 %conv, 2147483647
   %conv1 = bitcast i32 %and to float
   ret float %conv1
 }
 
entry:
   %and = and <2 x i64> %conv, <i64 9223372036854775807, i64 9223372036854775807>
   %conv1 = bitcast <2 x i64> %and to <2 x double>
   ret <2 x double> %conv1
 }
 
 define float @negf(float %a) {
 ; CHECK-LABEL: negf:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    fneg f1, f1
+; CHECK-NEXT:    xsnegdp f1, f1
 ; CHECK-NEXT:    blr
 entry:
   %conv = bitcast float %a to i32
   %and = xor i32 %conv, -2147483648
   %conv1 = bitcast i32 %and to float
   ret float %conv1
 }
 
entry:
   %conv = bitcast <2 x double> %a to <2 x i64>
   %and = xor <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
   %conv1 = bitcast <2 x i64> %and to <2 x double>
   ret <2 x double> %conv1
 }
 define float @nabsf(float %a) {
 ; CHECK-LABEL: nabsf:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    fnabs f1, f1
+; CHECK-NEXT:    xsnabsdp f1, f1
 ; CHECK-NEXT:    blr
 entry:
   %conv = bitcast float %a to i32
   %and = or i32 %conv, -2147483648
   %conv1 = bitcast i32 %and to float
   ret float %conv1
 }
 

llvm/test/CodeGen/PowerPC/fmf-propagation.ll

 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_afn_ieee:'
 ; GLOBALDEBUG:         fmul ninf afn {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_afn_ieee:'
 
 define float @sqrt_afn_ieee(float %x) #0 {
 ; FMF-LABEL: sqrt_afn_ieee:
 ; FMF:       # %bb.0:
+; FMF-NEXT:    xsabsdp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI10_2@toc@ha
-; FMF-NEXT:    fabs 0, 1
 ; FMF-NEXT:    lfs 2, .LCPI10_2@toc@l(3)
 ; FMF-NEXT:    fcmpu 0, 0, 2
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    blt 0, .LBB10_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
 ; FMF-NEXT:    addis 4, 2, .LCPI10_1@toc@ha
 ; FMF-NEXT:    lfs 2, .LCPI10_0@toc@l(3)
 ; FMF-NEXT:    lfs 3, .LCPI10_1@toc@l(4)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:    xsmulsp 1, 1, 2
 ; FMF-NEXT:    xsaddsp 0, 0, 3
 ; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:  .LBB10_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_afn_ieee:
 ; GLOBAL:       # %bb.0:
+; GLOBAL-NEXT:    xsabsdp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI10_2@toc@ha
-; GLOBAL-NEXT:    fabs 0, 1
 ; GLOBAL-NEXT:    lfs 2, .LCPI10_2@toc@l(3)
 ; GLOBAL-NEXT:    fcmpu 0, 0, 2
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
 ; GLOBAL-NEXT:    blt 0, .LBB10_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
 ; GLOBAL-NEXT:    addis 4, 2, .LCPI10_1@toc@ha

 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_ieee:'
 ; GLOBALDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_ieee:'
 
 define float @sqrt_fast_ieee(float %x) #0 {
 ; FMF-LABEL: sqrt_fast_ieee:
 ; FMF:       # %bb.0:
+; FMF-NEXT:    xsabsdp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI14_2@toc@ha
-; FMF-NEXT:    fabs 0, 1
 ; FMF-NEXT:    lfs 2, .LCPI14_2@toc@l(3)
 ; FMF-NEXT:    fcmpu 0, 0, 2
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    blt 0, .LBB14_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
 ; FMF-NEXT:    addis 4, 2, .LCPI14_1@toc@ha
 ; FMF-NEXT:    lfs 2, .LCPI14_0@toc@l(3)
 ; FMF-NEXT:    lfs 3, .LCPI14_1@toc@l(4)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmaddasp 2, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 3
 ; FMF-NEXT:    xsmulsp 0, 0, 2
 ; FMF-NEXT:  .LBB14_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_fast_ieee:
 ; GLOBAL:       # %bb.0:
+; GLOBAL-NEXT:    xsabsdp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI14_2@toc@ha
-; GLOBAL-NEXT:    fabs 0, 1
 ; GLOBAL-NEXT:    lfs 2, .LCPI14_2@toc@l(3)
 ; GLOBAL-NEXT:    fcmpu 0, 0, 2
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
 ; GLOBAL-NEXT:    blt 0, .LBB14_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
 ; GLOBAL-NEXT:    addis 4, 2, .LCPI14_1@toc@ha

llvm/test/CodeGen/PowerPC/fsub-fneg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le < %s | FileCheck %s
 
 ; When fpext is free, we should look through it for optimizations
 ; even if it has multiple uses and produce an 'fadd' here.
 ; Y - (fpext(-X)) --> Y + fpext(X)
 
 define double @neg_ext_op1_extra_use(float %x, double %y) nounwind {
 ; CHECK-LABEL: neg_ext_op1_extra_use:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xsadddp 0, 2, 1
-; CHECK-NEXT:    fneg 1, 1
-; CHECK-NEXT:    xsdivdp 1, 1, 0
+; CHECK-NEXT:    xsnegdp 0, 1
+; CHECK-NEXT:    xsadddp 1, 2, 1
+; CHECK-NEXT:    xsdivdp 1, 0, 1
 ; CHECK-NEXT:    blr
   %t1 = fsub float -0.0, %x
   %t2 = fpext float %t1 to double
   %t3 = fsub double %y, %t2
   %t4 = fdiv double %t2, %t3
   ret double %t4
 }