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[AMDGPU] Implement wave64 DWARF register mapping

Authored by scott.linder on Feb 20 2020, 10:49 AM.



Implement the DWARF register mapping described in

This is currently limited to wave64 VGPRs/AGPRs.

This also includes some minor changes in AMDGPUInstPrinter and
AMDGPUMCTargetDesc to make generating CFI assembly text and ELF sections
possible to ease testing, although complete CFI support is not yet

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Event Timeline

scott.linder created this revision.Feb 20 2020, 10:49 AM
arsenm added inline comments.Feb 20 2020, 11:03 AM

Should be marked as an artificial register?

Mark PC artificial and accept it in AsmParser

Accepting a "pc" register in AsmParser isn't strictly required until we start
emitting CFI, but I think it makes more sense to add here than include in a
patch later.

scott.linder marked an inline comment as done.Feb 20 2020, 1:27 PM
arsenm accepted this revision.Feb 20 2020, 1:38 PM
This revision is now accepted and ready to land.Feb 20 2020, 1:38 PM
This revision was automatically updated to reflect the committed changes.