Mark statepoint instructions as clobbering LR on AArch64

[loicottet]

Summary

Intrinsic operations emitted as calls (stackmap, patchpoint and statepoint) are defined globally and are lowered after register allocation. This means that on ARM backends LR has to be marked as implicitly defined by these instructions, otherwise the register allocator may use it as a temporary register, expecting it to keep its value across the intrinsic.
This patch enables the correct emission of garbage collection statepoints on AArch64 (https://reviews.llvm.org/D66012).

[reames]

No test case provided, implementation probably not right approach. Please provide a test case so that correct approach can be found.

[loicottet]

Abandoning since https://reviews.llvm.org/D111114 fixes the issue this revision was aiming to fix.

llvm/lib/Target/AArch64/AArch64.h

 
 FunctionPass *createAArch64CollectLOHPass();
 InstructionSelector *
 createAArch64InstructionSelector(const AArch64TargetMachine &,
                                  AArch64Subtarget &, AArch64RegisterBankInfo &);
 FunctionPass *createAArch64PreLegalizeCombiner(bool IsOptNone);
 FunctionPass *createAArch64StackTaggingPass(bool MergeInit);
 FunctionPass *createAArch64StackTaggingPreRAPass();
+FunctionPass *createAArch64ClobberLRPass();
 
 void initializeAArch64A53Fix835769Pass(PassRegistry&);
 void initializeAArch64A57FPLoadBalancingPass(PassRegistry&);
 void initializeAArch64AdvSIMDScalarPass(PassRegistry&);
 void initializeAArch64BranchTargetsPass(PassRegistry&);
 void initializeAArch64CollectLOHPass(PassRegistry&);
 void initializeAArch64CondBrTuningPass(PassRegistry &);
 void initializeAArch64CompressJumpTablesPass(PassRegistry&);
 void initializeAArch64ConditionalComparesPass(PassRegistry&);
 void initializeAArch64ConditionOptimizerPass(PassRegistry&);
 void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry&);
 void initializeAArch64ExpandPseudoPass(PassRegistry&);
 void initializeAArch64SpeculationHardeningPass(PassRegistry&);
 void initializeAArch64LoadStoreOptPass(PassRegistry&);
 void initializeAArch64SIMDInstrOptPass(PassRegistry&);
 void initializeAArch64PreLegalizerCombinerPass(PassRegistry&);
 void initializeAArch64PromoteConstantPass(PassRegistry&);
 void initializeAArch64RedundantCopyEliminationPass(PassRegistry&);
 void initializeAArch64StorePairSuppressPass(PassRegistry&);
 void initializeFalkorHWPFFixPass(PassRegistry&);
 void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry&);
 void initializeLDTLSCleanupPass(PassRegistry&);
 void initializeAArch64StackTaggingPass(PassRegistry&);
 void initializeAArch64StackTaggingPreRAPass(PassRegistry&);
+void initializeAArch64ClobberLRPass(PassRegistry &);
 } // end namespace llvm
 
 #endif

llvm/lib/Target/AArch64/AArch64ClobberLRPass.cpp

+//===- AArch64ClobberLRPass.cpp - Clobber LR on call intrinsics -----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains a pass that sets LR as implicit-def for statepoints,
+// patchpoints and stackmap instrinsics. This is needed as these instructions
+// are defined globally with no knowledge of AArch64-specific requirements.
+// As these intrinsics are lowered to calls after the register allocator runs,
+// it is necessary to specify that they clobber the link register beforehand.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AArch64.h"
+#include "AArch64RegisterInfo.h"
+#include "AArch64Subtarget.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "aarch64-dead-defs"
+
+#define AARCH64_CLOBBER_LR_NAME "AArch64 statepoint LR clobbering pass"
+
+namespace {
+struct AArch64ClobberLR : public MachineFunctionPass {
+public:
+  static char ID;
+
+  AArch64ClobberLR() : MachineFunctionPass(ID) {
+    initializeAArch64ClobberLRPass(*PassRegistry::getPassRegistry());
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  StringRef getPassName() const override { return AARCH64_CLOBBER_LR_NAME; }
+};
+} // namespace
+
+char AArch64ClobberLR::ID = 0;
+
+INITIALIZE_PASS(AArch64ClobberLR, "aarch64-clobber-lr", AARCH64_CLOBBER_LR_NAME,
+                false, false)
+
+bool AArch64ClobberLR::runOnMachineFunction(MachineFunction &MF) {
+  auto TRI = MF.getSubtarget().getRegisterInfo();
+  bool Modified = false;
+  for (MachineBasicBlock &MBB : MF) {
+    for (MachineInstr &MI : MBB) {
+      if (MI.getOpcode() == TargetOpcode::STACKMAP ||
+          MI.getOpcode() == TargetOpcode::PATCHPOINT ||
+          MI.getOpcode() == TargetOpcode::STATEPOINT) {
+        MI.addRegisterDefined(AArch64::LR, TRI);
+        Modified = true;
+      }
+    }
+  }
+  return Modified;
+}
+
+FunctionPass *llvm::createAArch64ClobberLRPass() {
+  return new AArch64ClobberLR();
+}
 No newline at end of file

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
   initializeAArch64RedundantCopyEliminationPass(*PR);
   initializeAArch64StorePairSuppressPass(*PR);
   initializeFalkorHWPFFixPass(*PR);
   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
   initializeLDTLSCleanupPass(*PR);
   initializeAArch64SpeculationHardeningPass(*PR);
   initializeAArch64StackTaggingPass(*PR);
   initializeAArch64StackTaggingPreRAPass(*PR);
+  initializeAArch64ClobberLRPass(*PR);
 }
 
 //===----------------------------------------------------------------------===//
 // AArch64 Lowering public interface.
 //===----------------------------------------------------------------------===//
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
   if (TT.isOSBinFormatMachO())
     return std::make_unique<AArch64_MachoTargetObjectFile>();
void AArch64PassConfig::addPreRegAlloc() {
 
   // Use AdvSIMD scalar instructions whenever profitable.
   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
     addPass(createAArch64AdvSIMDScalar());
     // The AdvSIMD pass may produce copies that can be rewritten to
     // be register coalescer friendly.
     addPass(&PeepholeOptimizerID);
   }
+
+  addPass(createAArch64ClobberLRPass());
 }
 
 void AArch64PassConfig::addPostRegAlloc() {
   // Remove redundant copy instructions.
   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
     addPass(createAArch64RedundantCopyEliminationPass());
 
   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())

llvm/lib/Target/AArch64/CMakeLists.txt

 add_llvm_target(AArch64CodeGen
   AArch64A57FPLoadBalancing.cpp
   AArch64AdvSIMDScalarPass.cpp
   AArch64AsmPrinter.cpp
   AArch64BranchTargets.cpp
   AArch64CallingConvention.cpp
   AArch64CallLowering.cpp
   AArch64CleanupLocalDynamicTLSPass.cpp
+  AArch64ClobberLRPass.cpp
   AArch64CollectLOH.cpp
   AArch64CondBrTuning.cpp
   AArch64ConditionalCompares.cpp
   AArch64DeadRegisterDefinitionsPass.cpp
   AArch64ExpandImm.cpp
   AArch64ExpandPseudoInsts.cpp
   AArch64FalkorHWPFFix.cpp
   AArch64FastISel.cpp