[GlobalISel] Add buildMerge with SrcOp initializer list

[Petar.Avramovic]

Summary

Allows more flexible use of buildMerge in places where
use operands are available as SrcOp since it does not
require explicit conversion to Register.
Simplify code with new buildMerge.

[foad]

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

792

Why std::initializer_list instead of ArrayRef? Is it something to do with ambiguous overloads? Do we still need the ArrayRef<Register> overload at all?

[Petar.Avramovic]

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

792

Old one with ArrayRef<Register> is required when argument is something like an actual SmallVector<Register>. It could also be used with brace enclosed initializer list filled with Registers.
New one is for brace enclosed initializer list with arguments that can be converted to SrcOp.

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

public:
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre The entire register \p Res (and no more) must be covered by the input
   ///      registers.
   /// \pre The type of all \p Ops registers must be identical.
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
   MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
+  MachineInstrBuilder buildMerge(const DstOp &Res,
+                                 std::initializer_list<SrcOp> Ops);
 
   /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
   ///
   /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre The entire register \p Res (and no more) must be covered by the input
   ///      registers.

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

if (Amt.ugt(VTBits)) {
       auto OrRHS = MIRBuilder.buildShl(
           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
 
       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
     }
   }
 
-  MIRBuilder.buildMerge(MI.getOperand(0), {Lo.getReg(), Hi.getReg()});
+  MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi});
   MI.eraseFromParent();
 
   return Legalized;
 }
 
 // TODO: Optimize if constant shift amount.
 LegalizerHelper::LegalizeResult
 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
     auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
                                 UnmergeSrc.getReg(1), C_0);
     auto LoCTLZ = B.buildCTLZ(NarrowTy, UnmergeSrc.getReg(0));
     auto C_NarrowSize = B.buildConstant(NarrowTy, NarrowSize);
     auto HiIsZeroCTLZ = B.buildAdd(NarrowTy, LoCTLZ, C_NarrowSize);
     auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(NarrowTy, UnmergeSrc.getReg(1));
     auto LoOut = B.buildSelect(NarrowTy, HiIsZero, HiIsZeroCTLZ, HiCTLZ);
 
-    B.buildMerge(MI.getOperand(0), {LoOut.getReg(0), C_0.getReg(0)});
+    B.buildMerge(MI.getOperand(0), {LoOut, C_0});
 
     MI.eraseFromParent();
     return Legalized;
   }
 
   return UnableToLegalize;
 }
 
if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
     auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
                                 UnmergeSrc.getReg(0), C_0);
     auto HiCTTZ = B.buildCTTZ(NarrowTy, UnmergeSrc.getReg(1));
     auto C_NarrowSize = B.buildConstant(NarrowTy, NarrowSize);
     auto LoIsZeroCTTZ = B.buildAdd(NarrowTy, HiCTTZ, C_NarrowSize);
     auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(NarrowTy, UnmergeSrc.getReg(0));
     auto LoOut = B.buildSelect(NarrowTy, LoIsZero, LoIsZeroCTTZ, LoCTTZ);
 
-    B.buildMerge(MI.getOperand(0), {LoOut.getReg(0), C_0.getReg(0)});
+    B.buildMerge(MI.getOperand(0), {LoOut, C_0});
 
     MI.eraseFromParent();
     return Legalized;
   }
 
   return UnableToLegalize;
 }
 

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
   // we need some temporary storage for the DstOp objects. Here we use a
   // sufficiently large SmallVector to not go through the heap.
   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
   assert(TmpVec.size() > 1);
   return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
 }
 
+MachineInstrBuilder
+MachineIRBuilder::buildMerge(const DstOp &Res,
+                             std::initializer_list<SrcOp> Ops) {
+  assert(Ops.size() > 1);
+  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, Ops);
+}
+
 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
                                                    const SrcOp &Op) {
   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
   // we need some temporary storage for the DstOp objects. Here we use a
   // sufficiently large SmallVector to not go through the heap.
   SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
   assert(TmpVec.size() > 1);
   return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);

llvm/lib/Target/AArch64/AArch64CallLowering.cpp

for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
                 // We don't handle VA types which are not exactly twice the
                 // size, but can easily be done in future.
                 if (NewLLT.getNumElements() != OldLLT.getNumElements() * 2) {
                   LLVM_DEBUG(dbgs() << "Outgoing vector ret has too many elts");
                   return false;
                 }
                 auto Undef = MIRBuilder.buildUndef({OldLLT});
                 CurVReg =
-                    MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef.getReg(0)})
-                        .getReg(0);
+                    MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0);
               } else {
                 // Just do a vector extend.
                 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
                               .getReg(0);
               }
             } else if (NewLLT.getNumElements() == 2) {
               // We need to pad a <1 x S> type to <2 x S>. Since we don't have
               // <1 x S> vector types in GISel we use a build_vector instead

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

if (SrcAS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
     const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
     uint32_t AddrHiVal = Info->get32BitAddressHighBits();
 
     // FIXME: This is a bit ugly due to creating a merge of 2 pointers to
     // another. Merge operands are required to be the same type, but creating an
     // extra ptrtoint would be kind of pointless.
     auto HighAddr = B.buildConstant(
       LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS_32BIT, 32), AddrHiVal);
-    B.buildMerge(Dst, {Src, HighAddr.getReg(0)});
+    B.buildMerge(Dst, {Src, HighAddr});
     MI.eraseFromParent();
     return true;
   }
 
   if (SrcAS == AMDGPUAS::FLAT_ADDRESS) {
     assert(DestAS == AMDGPUAS::LOCAL_ADDRESS ||
            DestAS == AMDGPUAS::PRIVATE_ADDRESS);
     unsigned NullVal = TM.getNullPointerValue(DestAS);
bool AMDGPULegalizerInfo::legalizeIntrinsicTrunc(
   const auto SignBitMask = B.buildConstant(S32, UINT32_C(1) << 31);
   auto SignBit = B.buildAnd(S32, Hi, SignBitMask);
 
   const auto FractMask = B.buildConstant(S64, (UINT64_C(1) << FractBits) - 1);
 
   const auto Zero32 = B.buildConstant(S32, 0);
 
   // Extend back to 64-bits.
-  auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)});
+  auto SignBit64 = B.buildMerge(S64, {Zero32, SignBit});
 
   auto Shr = B.buildAShr(S64, FractMask, Exp);
   auto Not = B.buildNot(S64, Shr);
   auto Tmp0 = B.buildAnd(S64, Src, Not);
   auto FiftyOne = B.buildConstant(S32, FractBits - 1);
 
   auto ExpLt0 = B.buildICmp(CmpInst::ICMP_SLT, S1, Exp, Zero32);
   auto ExpGt51 = B.buildICmp(CmpInst::ICMP_SGT, S1, Exp, FiftyOne);
bool AMDGPULegalizerInfo::legalizeFPTOI(
   auto FloorMul = B.buildFFloor(S64, Mul, Flags);
   auto Fma = B.buildFMA(S64, FloorMul, K1, Trunc, Flags);
 
   auto Hi = Signed ?
     B.buildFPTOSI(S32, FloorMul) :
     B.buildFPTOUI(S32, FloorMul);
   auto Lo = B.buildFPTOUI(S32, Fma);
 
-  B.buildMerge(Dst, { Lo.getReg(0), Hi.getReg(0) });
+  B.buildMerge(Dst, { Lo, Hi });
   MI.eraseFromParent();
 
   return true;
 }
 
 bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(
   MachineInstr &MI, MachineRegisterInfo &MRI,
   MachineIRBuilder &B) const {

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

TEST_F(GISelMITest, WidenScalarMergeValuesPointer) {
 
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
   const LLT P0 = LLT::pointer(0, 64);
 
   auto Lo = B.buildTrunc(S32, Copies[0]);
   auto Hi = B.buildTrunc(S32, Copies[1]);
 
-  auto Merge = B.buildMerge(P0, {Lo.getReg(0), Hi.getReg(0)});
+  auto Merge = B.buildMerge(P0, {Lo, Hi});
 
   EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
             Helper.widenScalar(*Merge, 1, S64));
 
   auto CheckStr = R"(
    CHECK: [[TRUNC0:%[0-9]+]]:_(s32) = G_TRUNC
    CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC
    CHECK: [[ZEXT_TRUNC0:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC0]]