[AArch64] Predictably disassemble system registers with the same encoding

[chill]

Summary

The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers, defined by
separate extension specifications (ETM and ETE, respectively), yet they use the
same encoding in MSR/MRS.

When performing a system register lookup by encoding, we would essentially
return a random one, depending on the number, relative position in the TableGen
file, whether the TableGen records for system registers are named or not, and,
if they are names, depending on record (not register!) name as well.

This issue could be solved by some system register aliases plus preferred
disassembly mechanism. We lack that, implementing it, is moderately non-trivial,
and not clear if it's worth it at all.

As a workaround, if we give the "conflicting" records names, and relying on
TableGen internals (keeping records in an ordered map, emitting lookup tables in
record name order, using std::lower_bound for the lookup), we get disassembly
always consistent with the lexicographical order of the record names.

[ostannard]

We already have a hack for a similar problem in AArch64InstPrinter::printMRSSystemRegister and AArch64InstPrinter::printMSRSystemRegister, I think it would be better to do this there to keep all of the related hacks together. This avoids relying on the sorting order of the table (which isn't obvious that it needs to be preserved), and will make it more obvious once we have enough of these hacks to be worth improving the tablegen backend to handle them.

If you still think it's better to do it here, please add comments both here (explaining why these names are significant) and in tablegen (explaining that we rely on sorting by name).

[sdesmalen]

FYI - @kmclaughlin sees a failure with test/MC/Disassembler/AArch64/trace-regs.txt when applying D73719, which is an otherwise totally unrelated patch; this patch seems to resolve the issue.
I like the suggestion by @ostannard to have an explicit workaround in AArch64InstPrinter instead, as we probably shouldn't rely on the order of definitions in the TableGen file to get the output we expect.

[chill]

In D73953#1858998, @sdesmalen wrote:

we probably shouldn't rely on the order of definitions in the TableGen file to get the output we expect.

The unnamed TableGen records get a name like annonymous_NNN...NN where NNN...NN
are monotonically increasing numbers, assigned in the order of definitions. The lexicographic order of the names
does not correspond to the numerical order. We are not relying on the order of definitions, but on the order
of explicitly spelled names.

[ostannard]

We are not relying on the order of definitions, but on the order of explicitly spelled names.

I'd rather we avoid doing either of them, because they are both surprising and non-obvious. How many languages can you name where the lexicographic ordering of variable names matters?

[chill]

Alright, I'll do it the other way.

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : RWSysReg<"TRCVDCTLR",          0b10, 0b001, 0b0000, 0b1000, 0b010>;
 def : RWSysReg<"TRCVDSACCTLR",       0b10, 0b001, 0b0000, 0b1001, 0b010>;
 def : RWSysReg<"TRCVDARCCTLR",       0b10, 0b001, 0b0000, 0b1010, 0b010>;
 def : RWSysReg<"TRCSEQEVR0",         0b10, 0b001, 0b0000, 0b0000, 0b100>;
 def : RWSysReg<"TRCSEQEVR1",         0b10, 0b001, 0b0000, 0b0001, 0b100>;
 def : RWSysReg<"TRCSEQEVR2",         0b10, 0b001, 0b0000, 0b0010, 0b100>;
 def : RWSysReg<"TRCSEQRSTEVR",       0b10, 0b001, 0b0000, 0b0110, 0b100>;
 def : RWSysReg<"TRCSEQSTR",          0b10, 0b001, 0b0000, 0b0111, 0b100>;
-def : RWSysReg<"TRCEXTINSELR",       0b10, 0b001, 0b0000, 0b1000, 0b100>;
+def TRCEXTINSELR_PRIO_0 : RWSysReg<"TRCEXTINSELR",       0b10, 0b001, 0b0000, 0b1000, 0b100>;
 def : RWSysReg<"TRCCNTRLDVR0",       0b10, 0b001, 0b0000, 0b0000, 0b101>;
 def : RWSysReg<"TRCCNTRLDVR1",       0b10, 0b001, 0b0000, 0b0001, 0b101>;
 def : RWSysReg<"TRCCNTRLDVR2",       0b10, 0b001, 0b0000, 0b0010, 0b101>;
 def : RWSysReg<"TRCCNTRLDVR3",       0b10, 0b001, 0b0000, 0b0011, 0b101>;
 def : RWSysReg<"TRCCNTCTLR0",        0b10, 0b001, 0b0000, 0b0100, 0b101>;
 def : RWSysReg<"TRCCNTCTLR1",        0b10, 0b001, 0b0000, 0b0101, 0b101>;
 def : RWSysReg<"TRCCNTCTLR2",        0b10, 0b001, 0b0000, 0b0110, 0b101>;
 def : RWSysReg<"TRCCNTCTLR3",        0b10, 0b001, 0b0000, 0b0111, 0b101>;

 def : ROSysReg<"GMID_EL1",         0b11, 0b001, 0b0000, 0b0000, 0b100>;
 } // HasMTE
 
 // Embedded Trace Extension R/W System registers
 let Requires = [{ {AArch64::FeatureETE} }] in {
 //              Name            Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"TRCRSR",        0b10, 0b001, 0b0000, 0b1010, 0b000>;
 //  TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR
-def : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>;
+def TRCEXTINSELR_PRIO_1 : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>;
 def : RWSysReg<"TRCEXTINSELR1", 0b10, 0b001, 0b0000, 0b1001, 0b100>;
 def : RWSysReg<"TRCEXTINSELR2", 0b10, 0b001, 0b0000, 0b1010, 0b100>;
 def : RWSysReg<"TRCEXTINSELR3", 0b10, 0b001, 0b0000, 0b1011, 0b100>;
 } // FeatureETE
 
 // Trace Buffer Extension System registers
 let Requires = [{ {AArch64::FeatureTRBE} }] in {
 //                   Name       Op0   Op1    CRn     CRm     Op2

llvm/test/MC/AArch64/ete-sysregs.s

 // ETE System registers
 //
 // RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s
 
 // Read from system register
 mrs x0, TRCRSR
 mrs x0, TRCEXTINSELR
 mrs x0, TRCEXTINSELR0
 mrs x0, TRCEXTINSELR1
 mrs x0, TRCEXTINSELR2
 mrs x0, TRCEXTINSELR3
 
 // CHECK: mrs x0, TRCRSR        // encoding: [0x00,0x0a,0x31,0xd5]
-// CHECK: mrs x0, TRCEXTINSELR0 // encoding: [0x80,0x08,0x31,0xd5]
-// CHECK: mrs x0, TRCEXTINSELR0 // encoding: [0x80,0x08,0x31,0xd5]
+// CHECK: mrs x0, TRCEXTINSELR  // encoding: [0x80,0x08,0x31,0xd5]
+// CHECK: mrs x0, TRCEXTINSELR  // encoding: [0x80,0x08,0x31,0xd5]
 // CHECK: mrs x0, TRCEXTINSELR1 // encoding: [0x80,0x09,0x31,0xd5]
 // CHECK: mrs x0, TRCEXTINSELR2 // encoding: [0x80,0x0a,0x31,0xd5]
 // CHECK: mrs x0, TRCEXTINSELR3 // encoding: [0x80,0x0b,0x31,0xd5]
 
 // Write to system register
 msr TRCRSR, x0
 msr TRCEXTINSELR,  x0
 msr TRCEXTINSELR0, x0
 msr TRCEXTINSELR1, x0
 msr TRCEXTINSELR2, x0
 msr TRCEXTINSELR3, x0
 
 // CHECK: msr TRCRSR, x0        // encoding: [0x00,0x0a,0x11,0xd5]
-// CHECK: msr TRCEXTINSELR0, x0 // encoding: [0x80,0x08,0x11,0xd5]
-// CHECK: msr TRCEXTINSELR0, x0 // encoding: [0x80,0x08,0x11,0xd5]
+// CHECK: msr TRCEXTINSELR, x0  // encoding: [0x80,0x08,0x11,0xd5]
+// CHECK: msr TRCEXTINSELR, x0  // encoding: [0x80,0x08,0x11,0xd5]
 // CHECK: msr TRCEXTINSELR1, x0 // encoding: [0x80,0x09,0x11,0xd5]
 // CHECK: msr TRCEXTINSELR2, x0 // encoding: [0x80,0x0a,0x11,0xd5]
 // CHECK: msr TRCEXTINSELR3, x0 // encoding: [0x80,0x0b,0x11,0xd5]

llvm/test/MC/AArch64/trace-regs.s

 // CHECK: mrs      x27, {{trcvdctlr|TRCVDCTLR}}             // encoding: [0x5b,0x08,0x31,0xd5]
 // CHECK: mrs      x9, {{trcvdsacctlr|TRCVDSACCTLR}}           // encoding: [0x49,0x09,0x31,0xd5]
 // CHECK: mrs      x0, {{trcvdarcctlr|TRCVDARCCTLR}}           // encoding: [0x40,0x0a,0x31,0xd5]
 // CHECK: mrs      x13, {{trcseqevr0|TRCSEQEVR0}}            // encoding: [0x8d,0x00,0x31,0xd5]
 // CHECK: mrs      x11, {{trcseqevr1|TRCSEQEVR1}}            // encoding: [0x8b,0x01,0x31,0xd5]
 // CHECK: mrs      x26, {{trcseqevr2|TRCSEQEVR2}}            // encoding: [0x9a,0x02,0x31,0xd5]
 // CHECK: mrs      x14, {{trcseqrstevr|TRCSEQRSTEVR}}          // encoding: [0x8e,0x06,0x31,0xd5]
 // CHECK: mrs      x4, {{trcseqstr|TRCSEQSTR}}              // encoding: [0x84,0x07,0x31,0xd5]
-// CHECK: mrs      x17, {{trcextinselr|TRCEXTINSELR0}}         // encoding: [0x91,0x08,0x31,0xd5]
+// CHECK: mrs      x17, {{trcextinselr|TRCEXTINSELR}}         // encoding: [0x91,0x08,0x31,0xd5]
 // CHECK: mrs      x21, {{trccntrldvr0|TRCCNTRLDVR0}}          // encoding: [0xb5,0x00,0x31,0xd5]
 // CHECK: mrs      x10, {{trccntrldvr1|TRCCNTRLDVR1}}          // encoding: [0xaa,0x01,0x31,0xd5]
 // CHECK: mrs      x20, {{trccntrldvr2|TRCCNTRLDVR2}}          // encoding: [0xb4,0x02,0x31,0xd5]
 // CHECK: mrs      x5, {{trccntrldvr3|TRCCNTRLDVR3}}           // encoding: [0xa5,0x03,0x31,0xd5]
 // CHECK: mrs      x17, {{trccntctlr0|TRCCNTCTLR0}}           // encoding: [0xb1,0x04,0x31,0xd5]
 // CHECK: mrs      x1, {{trccntctlr1|TRCCNTCTLR1}}            // encoding: [0xa1,0x05,0x31,0xd5]
 // CHECK: mrs      x17, {{trccntctlr2|TRCCNTCTLR2}}           // encoding: [0xb1,0x06,0x31,0xd5]
 // CHECK: mrs      x6, {{trccntctlr3|TRCCNTCTLR3}}            // encoding: [0xa6,0x07,0x31,0xd5]

 // CHECK: msr      {{trcvdctlr|TRCVDCTLR}}, x7              // encoding: [0x47,0x08,0x11,0xd5]
 // CHECK: msr      {{trcvdsacctlr|TRCVDSACCTLR}}, x18          // encoding: [0x52,0x09,0x11,0xd5]
 // CHECK: msr      {{trcvdarcctlr|TRCVDARCCTLR}}, x24          // encoding: [0x58,0x0a,0x11,0xd5]
 // CHECK: msr      {{trcseqevr0|TRCSEQEVR0}}, x28            // encoding: [0x9c,0x00,0x11,0xd5]
 // CHECK: msr      {{trcseqevr1|TRCSEQEVR1}}, x21            // encoding: [0x95,0x01,0x11,0xd5]
 // CHECK: msr      {{trcseqevr2|TRCSEQEVR2}}, x16            // encoding: [0x90,0x02,0x11,0xd5]
 // CHECK: msr      {{trcseqrstevr|TRCSEQRSTEVR}}, x16          // encoding: [0x90,0x06,0x11,0xd5]
 // CHECK: msr      {{trcseqstr|TRCSEQSTR}}, x25             // encoding: [0x99,0x07,0x11,0xd5]
-// CHECK: msr      {{trcextinselr|TRCEXTINSELR0}}, x29         // encoding: [0x9d,0x08,0x11,0xd5]
+// CHECK: msr      {{trcextinselr|TRCEXTINSELR}}, x29         // encoding: [0x9d,0x08,0x11,0xd5]
 // CHECK: msr      {{trccntrldvr0|TRCCNTRLDVR0}}, x20          // encoding: [0xb4,0x00,0x11,0xd5]
 // CHECK: msr      {{trccntrldvr1|TRCCNTRLDVR1}}, x20          // encoding: [0xb4,0x01,0x11,0xd5]
 // CHECK: msr      {{trccntrldvr2|TRCCNTRLDVR2}}, x22          // encoding: [0xb6,0x02,0x11,0xd5]
 // CHECK: msr      {{trccntrldvr3|TRCCNTRLDVR3}}, x12          // encoding: [0xac,0x03,0x11,0xd5]
 // CHECK: msr      {{trccntctlr0|TRCCNTCTLR0}}, x20           // encoding: [0xb4,0x04,0x11,0xd5]
 // CHECK: msr      {{trccntctlr1|TRCCNTCTLR1}}, x4            // encoding: [0xa4,0x05,0x11,0xd5]
 // CHECK: msr      {{trccntctlr2|TRCCNTCTLR2}}, x8            // encoding: [0xa8,0x06,0x11,0xd5]
 // CHECK: msr      {{trccntctlr3|TRCCNTCTLR3}}, x16           // encoding: [0xb0,0x07,0x11,0xd5]

llvm/test/MC/Disassembler/AArch64/ete.txt

 # CHECK:  mrs x0, TRCEXTINSELR3
 
 
 # Write to system register
 [0x00,0x0a,0x11,0xd5]
 # CHECK:   msr TRCRSR, x0
 
 [0x80,0x08,0x11,0xd5]
-# CHECK:   msr TRCEXTINSELR0, x0
+# CHECK:   msr TRCEXTINSELR, x0
 
 [0x80,0x09,0x11,0xd5]
 # CHECK:   msr TRCEXTINSELR1, x0
 
 [0x80,0x0a,0x11,0xd5]
 # CHECK:   msr TRCEXTINSELR2, x0
 
 [0x80,0x0b,0x11,0xd5]
 # CHECK:   msr TRCEXTINSELR3, x0

llvm/test/MC/Disassembler/AArch64/trace-regs.txt

 # CHECK: msr      {{trcseqevr1|TRCSEQEVR1}}, x21
 0x90 0x2 0x11 0xd5
 # CHECK: msr      {{trcseqevr2|TRCSEQEVR2}}, x16
 0x90 0x6 0x11 0xd5
 # CHECK: msr      {{trcseqrstevr|TRCSEQRSTEVR}}, x16
 0x99 0x7 0x11 0xd5
 # CHECK: msr      {{trcseqstr|TRCSEQSTR}}, x25
 0x9d 0x8 0x11 0xd5
-# CHECK: msr      {{trcextinselr|TRCEXTINSELR0}}, x29
+# CHECK: msr      {{trcextinselr|TRCEXTINSELR}}, x29
 0xb4 0x0 0x11 0xd5
 # CHECK: msr      {{trccntrldvr0|TRCCNTRLDVR0}}, x20
 0xb4 0x1 0x11 0xd5
 # CHECK: msr      {{trccntrldvr1|TRCCNTRLDVR1}}, x20
 0xb6 0x2 0x11 0xd5
 # CHECK: msr      {{trccntrldvr2|TRCCNTRLDVR2}}, x22
 0xac 0x3 0x11 0xd5
 # CHECK: msr      {{trccntrldvr3|TRCCNTRLDVR3}}, x12