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[ARM,MVE] Add intrinsics for vdupq.
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Authored by simon_tatham on Jan 24 2020, 8:00 AM.

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Summary

The unpredicated case of this is trivial: the clang codegen just makes
a vector splat of the input, and LLVM isel is already prepared to
handle that. For the predicated version, I've generated a select
between the same vector splat and the inactive input parameter, and
added new Tablegen isel rules to match that pattern into a predicated
MVE_VDUP instruction.

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Event Timeline

simon_tatham created this revision.Jan 24 2020, 8:00 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJan 24 2020, 8:00 AM
dmgreen accepted this revision.Jan 28 2020, 5:47 AM

LGTM.

This revision is now accepted and ready to land.Jan 28 2020, 5:47 AM
This revision was automatically updated to reflect the committed changes.