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Differential D73034

[ARM,MVE] Fix confusing MC names for MVE VMINA/VMAXA insns.
ClosedPublic

Authored by simon_tatham on Jan 20 2020, 5:07 AM.

Details

Reviewers
MarkMurrayARM
dmgreen
miyuki
ostannard
Commits
rGf3e73e88fdd6: [ARM,MVE] Fix confusing MC names for MVE VMINA/VMAXA insns.
Summary

A recent commit accidentally defined names like MVE_VMAXAs8 as
instances of the multiclass MVE_VMINA, and vice versa. This has no
effect on the test suite, because nothing directly refers to those
instruction names (the isel patterns are generated in Tablegen using
!cast<Instruction>(NAME) inside a lower-level multiclass). But it
means that llvm-mc -show-inst was listing VMAXA as VMINA, and it
would also affect any further draft code gen patches that use those
instruction ids.

Diff Detail

Event Timeline

simon_tatham created this revision.Jan 20 2020, 5:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 20 2020, 5:07 AM
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls. · View Herald Transcript
Harbormaster completed remote builds in B44393: Diff 239083.Jan 20 2020, 5:12 AM
dmgreen accepted this revision.Jan 20 2020, 5:19 AM

LGTM

This revision is now accepted and ready to land.Jan 20 2020, 5:19 AM
Closed by commit rGf3e73e88fdd6: [ARM,MVE] Fix confusing MC names for MVE VMINA/VMAXA insns. (authored by simon_tatham). · Explain WhyJan 20 2020, 5:31 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
12 lines

Diff 239083

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,306 Lines • ▼ Show 20 Lines def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm), (VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm),
ARMVCCThen, (VTI.Pred VCCR:$mask)))>; ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
} }
} }
multiclass MVE_VMINA<MVEVectorVTInfo VTI> multiclass MVE_VMINA<MVEVectorVTInfo VTI>
: MVE_VMINMAXA_m<"vmina", VTI, umin, int_arm_mve_vmina_predicated, 0b1>; : MVE_VMINMAXA_m<"vmina", VTI, umin, int_arm_mve_vmina_predicated, 0b1>;
defm MVE_VMAXAs8 : MVE_VMINA<MVE_v16s8>; defm MVE_VMINAs8 : MVE_VMINA<MVE_v16s8>;
defm MVE_VMAXAs16 : MVE_VMINA<MVE_v8s16>; defm MVE_VMINAs16 : MVE_VMINA<MVE_v8s16>;
defm MVE_VMAXAs32 : MVE_VMINA<MVE_v4s32>; defm MVE_VMINAs32 : MVE_VMINA<MVE_v4s32>;
multiclass MVE_VMAXA<MVEVectorVTInfo VTI> multiclass MVE_VMAXA<MVEVectorVTInfo VTI>
: MVE_VMINMAXA_m<"vmaxa", VTI, umax, int_arm_mve_vmaxa_predicated, 0b0>; : MVE_VMINMAXA_m<"vmaxa", VTI, umax, int_arm_mve_vmaxa_predicated, 0b0>;
defm MVE_VMINAs8 : MVE_VMAXA<MVE_v16s8>; defm MVE_VMAXAs8 : MVE_VMAXA<MVE_v16s8>;
defm MVE_VMINAs16 : MVE_VMAXA<MVE_v8s16>; defm MVE_VMAXAs16 : MVE_VMAXA<MVE_v8s16>;
defm MVE_VMINAs32 : MVE_VMAXA<MVE_v4s32>; defm MVE_VMAXAs32 : MVE_VMAXA<MVE_v4s32>;
// end of MVE Integer instructions // end of MVE Integer instructions
// start of mve_imm_shift instructions // start of mve_imm_shift instructions
def MVE_VSHLC : MVE_p<(outs rGPR:$RdmDest, MQPR:$Qd), def MVE_VSHLC : MVE_p<(outs rGPR:$RdmDest, MQPR:$Qd),
(ins MQPR:$QdSrc, rGPR:$RdmSrc, long_shift:$imm), (ins MQPR:$QdSrc, rGPR:$RdmSrc, long_shift:$imm),
NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm", NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm",
▲ Show 20 Lines • Show All 4,107 Lines • Show Last 20 Lines