[mlir] NFC: Fix trivial typos in comments

[merge_guards_bot]

Unit tests: pass. 62002 tests passed, 0 failed and 783 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[mehdi_amini]

LGTM.

Do you have an account or do you need someone to land this for you?

[kiszk]

Thank you.
Since I have not the right yet, I would like to ask someone to land and commit.

mlir/docs/ConversionToLLVMDialect.md

 ```mlir
 %0 = load %m[1,2,3,4] : memref<10x?x13x?xf32>
 ```
 
 is transformed into the equivalent of the following code:
 
 ```mlir
 // Compute the linearized index from strides. Each block below extracts one
-// stride from the descriptor, multipllies it with the index and accumulates
+// stride from the descriptor, multiplies it with the index and accumulates
 // the total offset.
 %stride1 = llvm.extractvalue[4, 0] : !llvm<"{float*, float*, i64, i64[4], i64[4]}">
 %idx1 = llvm.mlir.constant(1 : index) !llvm.i64
 %addr1 = muli %stride1, %idx1 : !llvm.i64
 
 %stride2 = llvm.extractvalue[4, 1] : !llvm<"{float*, float*, i64, i64[4], i64[4]}">
 %idx2 = llvm.mlir.constant(2 : index) !llvm.i64
 %addr2 = muli %stride2, %idx2 : !llvm.i64

mlir/docs/Dialects/Vector.md

 
 ### Implication on Lowering to Accelerators
 To target accelerators that support higher dimensional vectors natively, we
 can start from either `1-D` or `n-D` vectors in MLIR and use `vector.cast` to
 flatten the most minor dimensions to `1-D` `vector<Kxf32>` where `K` is an
 appropriate constant. Then, the existing lowering to LLVM-IR immediately
 applies, with extensions for accelerator-specific intrinsics.
 
-It is the role of an Accelerator-specfic vector dialect (see codegen flow in
+It is the role of an Accelerator-specific vector dialect (see codegen flow in
 the figure above) to lower the `vector.cast`. Accelerator -> LLVM lowering
 would then consist of a bunch of `Accelerator -> Accelerator` rewrites to
 perform the casts composed with `Accelerator -> LLVM` conversions + intrinsics
 that operate on `1-D` `vector<Kxf32>`.
 
 Some of those rewrites may need extra handling, especially if a reduction is
 involved. For example, `vector.cast %0: vector<K1x...xKnxf32> to
 vector<Kxf32>` when `K != K1 * … * Kn` and some arbitrary irregular

mlir/docs/ShapeInference.md

 exceptional case.
 
 ## Testing
 
 Shape inference is currently tested alongside type inference by
 `TestReturnTypeDriver` in the test dialect. The driver performs two checks:
 
 1.  Verification that the return types specified matches the infered types. This
-    explicit check will be removed and made part of Op verificaton instead.
+    explicit check will be removed and made part of Op verification instead.
 2.  Test the creation of Ops without specifying the return type explicitly in
     function `testCreateFunctions` by creating new binary Ops (Op classes
     specified in `TestReturnTypeDriver`) using 1) all operands to
     `testCreateFunctions` as both operands, and 2) using combinations of input
     operands of the function.
 
 ## WIP/Future considerations
 

mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td

def Linalg_ReshapeOp : Linalg_Op<"reshape", [NoSideEffect]>,
     Results<(outs AnyStridedMemRef)> {
   let summary = "linalg.reshape produces a new view into the operand view";
   let description = [{
     The `linalg.reshape` op produces a new view whose sizes are a reassociation
     of the original `view`. Depending on whether or not the reassociated
     MemRefType is contiguous, the resulting memref may require explicit alloc
     and copies.
 
-    A reassociation is defined as a continous grouping of dimensions and is
-    represented with an affine map array attribute. In the future, non-continous
-    groupings may be allowed (i.e. permutations, reindexings etc).
+    A reassociation is defined as a continuous grouping of dimensions and is
+    represented with an affine map array attribute. In the future,
+    non-continuous groupings may be allowed (i.e. permutations, reindexings
+    etc).
 
     For now, it is assumed that either:
       1. a reassociation produces and consumes contiguous MemRefType or,
       2. the reshape op will be folded into its consumers (by changing the shape
          of the computations).
     All other cases are undefined behavior and a reshape op may not lower to
     LLVM if it cannot be proven statically that it does not require alloc+copy.
 

mlir/include/mlir/Dialect/LoopOps/LoopOps.td

let arguments = (ins Variadic<Index>:$lowerBound,
                        Variadic<Index>:$step);
   let results = (outs Variadic<AnyType>:$results);
   let regions = (region SizedRegion<1>:$body);
 }
 
 def ReduceOp : Loop_Op<"reduce", [HasParent<"ParallelOp">]> {
   let summary = "reduce operation for parallel for";
   let description = [{
-    "loop.reduce" is an operation occuring inside "loop.parallel" operations. It
-    consists of one block with two arguments which have the same type as the
+    "loop.reduce" is an operation occurring inside "loop.parallel" operations.
+    It consists of one block with two arguments which have the same type as the
     operand of "loop.reduce".
 
     "loop.reduce" is used to model the value for reduction computations of a
     "loop.parallel" operation. It has to appear as an immediate child of a
     "loop.parallel" and is associated with a result value of its parent
     operation.
 
     Association is in the order of appearance in the body where the first result

mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td

class Extension<list<StrEnumAttrCase> extensions> : Availability {
   let interfaceName = "QueryExtensionInterface";
   let interfaceDescription = [{
     Querying interface for required SPIR-V extensions.
 
     This interface provides a `getExtensions()` method to query the required
     extensions for the implementing SPIR-V operation. The returned value
     is a nested vector whose element is `mlir::spirv::Extension`s. The outer
     vector's elements (which are vectors) should be interpreted as conjunction
-    while the innner vector's elements (which are `mlir::spirv::Extension`s)
+    while the inner vector's elements (which are `mlir::spirv::Extension`s)
     should be interpreted as disjunction. For example, given
 
     ```
     {{Extension::A, Extension::B}, {Extension::C}, {{Extension::D, Extension::E}}
     ```
 
     The operation instance is available when (`Extension::A` OR `Extension::B`)
     AND (`Extension::C`) AND (`Extension::D` OR `Extension::E`) is enabled.

 
 class Capability<list<I32EnumAttrCase> capabilities> : Availability {
   let interfaceName = "QueryCapabilityInterface";
   let interfaceDescription = [{
     Querying interface for required SPIR-V capabilities.
 
     This interface provides a `getCapabilities()` method to query the required
     capabilities for the implementing SPIR-V operation. The returned value
-    is a neted vector whose element is `mlir::spirv::Capability`s. The outer
+    is a nested vector whose element is `mlir::spirv::Capability`s. The outer
     vector's elements (which are vectors) should be interpreted as conjunction
-    while the innner vector's elements (which are `mlir::spirv::Capability`s)
+    while the inner vector's elements (which are `mlir::spirv::Capability`s)
     should be interpreted as disjunction. For example, given
 
     ```
     {{Capability::A, Capability::B}, {Capability::C}, {{Capability::D, Capability::E}}
     ```
 
     The operation instance is available when (`Capability::A` OR `Capability::B`)
     AND (`Capability::C`) AND (`Capability::D` OR `Capability::E`) is enabled.

mlir/include/mlir/IR/StandardTypes.h

 ///   3. For offset: ? strides: ?, ?, ? return
 ///         (i, j, k)[off, M, N, P]->(off + M * i + N * j + P * k)
 AffineMap makeStridedLinearLayoutMap(ArrayRef<int64_t> strides, int64_t offset,
                                      MLIRContext *context);
 
 /// Return a version of `t` with identity layout if it can be determined
 /// statically that the layout is the canonical contiguous strided layout.
 /// Otherwise pass `t`'s layout into `simplifyAffineMap` and return a copy of
-/// `t` with simplifed layout.
+/// `t` with simplified layout.
 MemRefType canonicalizeStridedLayout(MemRefType t);
 
 /// Return true if the layout for `t` is compatible with strided semantics.
 bool isStrided(MemRefType t);
 
 } // end namespace mlir
 
 #endif // MLIR_IR_STANDARDTYPES_H

mlir/include/mlir/Support/STLExtras.h

 };
 
 namespace detail {
 /// The class represents the base of a range of indexed_accessor_iterators. It
 /// provides support for many different range functionalities, e.g.
 /// drop_front/slice/etc.. Derived range classes must implement the following
 /// static methods:
 ///   * ReferenceT dereference_iterator(const BaseT &base, ptrdiff_t index)
-///     - Derefence an iterator pointing to the base object at the given index.
+///     - Dereference an iterator pointing to the base object at the given
+///       index.
 ///   * BaseT offset_base(const BaseT &base, ptrdiff_t index)
 ///     - Return a new base that is offset from the provide base by 'index'
 ///       elements.
 template <typename DerivedT, typename BaseT, typename T,
           typename PointerT = T *, typename ReferenceT = T &>
 class indexed_accessor_range_base {
 public:
   using RangeBaseT =

 } // end namespace detail
 
 /// This class provides an implementation of a range of
 /// indexed_accessor_iterators where the base is not indexable. Ranges with
 /// bases that are offsetable should derive from indexed_accessor_range_base
 /// instead. Derived range classes are expected to implement the following
 /// static method:
 ///   * ReferenceT dereference(const BaseT &base, ptrdiff_t index)
-///     - Derefence an iterator pointing to a parent base at the given index.
+///     - Dereference an iterator pointing to a parent base at the given index.
 template <typename DerivedT, typename BaseT, typename T,
           typename PointerT = T *, typename ReferenceT = T &>
 class indexed_accessor_range
     : public detail::indexed_accessor_range_base<
           DerivedT, std::pair<BaseT, ptrdiff_t>, T, PointerT, ReferenceT> {
 public:
   indexed_accessor_range(BaseT base, ptrdiff_t startIndex, ptrdiff_t count)
       : detail::indexed_accessor_range_base<

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp

 private:
   // Expands the given source value over all the ranks, as defined
   // by the source and destination type (a null source type denotes
   // expansion from a scalar value into a vector).
   //
   // TODO(ajcbik): consider replacing this one-pattern lowering
   //               with a two-pattern lowering using other vector
   //               ops once all insert/extract/shuffle operations
-  //               are available with lowering implemention.
+  //               are available with lowering implementation.
   //
   Value expandRanks(Value value, Location loc, VectorType srcVectorType,
                     VectorType dstVectorType,
                     ConversionPatternRewriter &rewriter) const {
     assert((dstVectorType != nullptr) && "invalid result type in broadcast");
     // Determine rank of source and destination.
     int64_t srcRank = srcVectorType ? srcVectorType.getRank() : 0;
     int64_t dstRank = dstVectorType.getRank();

mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp

static ParseResult parseConstantOp(OpAsmParser &parser,
   result.addTypes(type);
   return success();
 }
 
 //===----------------------------------------------------------------------===//
 // Builder, printer and verifier for LLVM::GlobalOp.
 //===----------------------------------------------------------------------===//
 
-/// Returns the name used for the linkge attribute. This *must* correspond to
+/// Returns the name used for the linkage attribute. This *must* correspond to
 /// the name of the attribute in ODS.
 static StringRef getLinkageAttrName() { return "linkage"; }
 
 void GlobalOp::build(Builder *builder, OperationState &result, LLVMType type,
                      bool isConstant, Linkage linkage, StringRef name,
                      Attribute value, unsigned addrSpace,
                      ArrayRef<NamedAttribute> attrs) {
   result.addAttribute(SymbolTable::getSymbolAttrName(),

mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp

if (maxVersion.getMaxVersion() < givenVersion) {
                  << op->getName() << " illegal: requiring max version "
                  << spirv::stringifyVersion(maxVersion.getMaxVersion())
                  << "\n");
       return false;
     }
 
   // Make sure this op's required extensions are allowed to use. For each op,
   // we return a vector of vector for its extension requirements following
-  // ((Extension::A OR Extenion::B) AND (Extension::C OR Extension::D))
+  // ((Extension::A OR Extension::B) AND (Extension::C OR Extension::D))
   // convention. Ops not implementing QueryExtensionInterface do not require
   // extensions to be available.
   if (auto extensions = dyn_cast<spirv::QueryExtensionInterface>(op)) {
     auto exts = extensions.getExtensions();
     for (const auto &ors : exts)
       if (llvm::all_of(ors, [this](spirv::Extension ext) {
             return this->givenExtensions.count(ext) == 0;
           })) {
         LLVM_DEBUG(llvm::dbgs() << op->getName()
                                 << " illegal: missing required extension\n");
         return false;
       }
   }
 
   // Make sure this op's required extensions are allowed to use. For each op,
   // we return a vector of vector for its capability requirements following
-  // ((Capability::A OR Extenion::B) AND (Capability::C OR Capability::D))
+  // ((Capability::A OR Extension::B) AND (Capability::C OR Capability::D))
   // convention. Ops not implementing QueryExtensionInterface do not require
   // extensions to be available.
   if (auto capabilities = dyn_cast<spirv::QueryCapabilityInterface>(op)) {
     auto caps = capabilities.getCapabilities();
     for (const auto &ors : caps)
       if (llvm::all_of(ors, [this](spirv::Capability cap) {
             return this->givenCapabilities.count(cap) == 0;
           })) {
         LLVM_DEBUG(llvm::dbgs() << op->getName()
                                 << " illegal: missing required capability\n");
         return false;
       }
   }
 
   return true;
 }

mlir/lib/Dialect/VectorOps/VectorTransforms.cpp

SmallVector<Value, 1> mlir::vector::unrollSingleResultOpMatchingType(
   assert(op->getNumResults() == 1 && "Expected single result operation");
 
   // Populate 'iterationBounds', 'vectors' and 'resultIndex' to unroll 'op'.
   SmallVector<int64_t, 6> iterationBounds;
   std::vector<VectorState> vectors;
   unsigned resultIndex;
 
   if (auto contractionOp = dyn_cast<vector::ContractionOp>(op)) {
-    // Popultate state for vector ContractionOp.
+    // Populate state for vector ContractionOp.
     getVectorContractionOpUnrollState(contractionOp, targetShape,
                                       iterationBounds, vectors, resultIndex);
   } else {
     // Populate state for vector elementwise op.
     getVectorElementwiseOpUnrollState(op, targetShape, iterationBounds, vectors,
                                       resultIndex);
   }
 

 namespace {
 // Splits vector TransferReadOp into smaller TransferReadOps based on slicing
 // scheme of its unique ExtractSlicesOp user.
 struct SplitTransferReadOp : public OpRewritePattern<vector::TransferReadOp> {
   using OpRewritePattern<vector::TransferReadOp>::OpRewritePattern;
 
   PatternMatchResult matchAndRewrite(vector::TransferReadOp xferReadOp,
                                      PatternRewriter &rewriter) const override {
-    // TODO(andydavis, ntv) Support spliting TransferReadOp with non-identity
+    // TODO(andydavis, ntv) Support splitting TransferReadOp with non-identity
     // permutation maps. Repurpose code from MaterializeVectors transformation.
     if (!xferReadOp.permutation_map().isIdentity())
       return matchFailure();
     // Return unless the unique 'xferReadOp' user is an ExtractSlicesOp.
     Value xferReadResult = xferReadOp.getResult();
     auto extractSlicesOp =
         dyn_cast<vector::ExtractSlicesOp>(*xferReadResult.getUsers().begin());
     if (!xferReadResult.hasOneUse() || !extractSlicesOp)

 };
 
 // Splits vector TransferWriteOp into smaller TransferWriteOps for each source.
 struct SplitTransferWriteOp : public OpRewritePattern<vector::TransferWriteOp> {
   using OpRewritePattern<vector::TransferWriteOp>::OpRewritePattern;
 
   PatternMatchResult matchAndRewrite(vector::TransferWriteOp xferWriteOp,
                                      PatternRewriter &rewriter) const override {
-    // TODO(andydavis, ntv) Support spliting TransferWriteOp with non-identity
+    // TODO(andydavis, ntv) Support splitting TransferWriteOp with non-identity
     // permutation maps. Repurpose code from MaterializeVectors transformation.
     if (!xferWriteOp.permutation_map().isIdentity())
       return matchFailure();
     // Return unless the 'xferWriteOp' 'vector' operand is an 'InsertSlicesOp'.
     auto *vectorDefOp = xferWriteOp.vector().getDefiningOp();
     auto insertSlicesOp = dyn_cast_or_null<vector::InsertSlicesOp>(vectorDefOp);
     if (!insertSlicesOp)
       return matchFailure();

mlir/lib/IR/AsmPrinter.cpp

 //===----------------------------------------------------------------------===//
 // SSANameState
 //===----------------------------------------------------------------------===//
 
 namespace {
 /// This class manages the state of SSA value names.
 class SSANameState {
 public:
-  /// A sentinal value used for values with names set.
+  /// A sentinel value used for values with names set.
   enum : unsigned { NameSentinel = ~0U };
 
   SSANameState(Operation *op,
                DialectInterfaceCollection<OpAsmDialectInterface> &interfaces);
 
   /// Print the SSA identifier for the given value to 'stream'. If
   /// 'printResultNo' is true, it also presents the result number ('#' number)
   /// of this value.

mlir/lib/IR/StandardTypes.cpp

AffineMap mlir::makeStridedLinearLayoutMap(ArrayRef<int64_t> strides,
   }
 
   return AffineMap::get(strides.size(), nSymbols, expr);
 }
 
 /// Return a version of `t` with identity layout if it can be determined
 /// statically that the layout is the canonical contiguous strided layout.
 /// Otherwise pass `t`'s layout into `simplifyAffineMap` and return a copy of
-/// `t` with simplifed layout.
+/// `t` with simplified layout.
 /// If `t` has multiple layout maps or a multi-result layout, just return `t`.
 MemRefType mlir::canonicalizeStridedLayout(MemRefType t) {
   auto affineMaps = t.getAffineMaps();
   // Already in canonical form.
   if (affineMaps.empty())
     return t;
 
   // Can't reduce to canonical identity form, return in canonical form.

mlir/lib/IR/Visitors.cpp

-//===- Visitors.cpp - MLIR Visitor Utilties -------------------------------===//
+//===- Visitors.cpp - MLIR Visitor Utilities ------------------------------===//
 //
 // Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "mlir/IR/Visitors.h"

mlir/lib/Target/LLVMIR/ModuleTranslation.cpp

buildSequentialConstant(ArrayRef<llvm::Constant *> &constants,
   }
 
   if (shape.size() == 1 && type->isVectorTy())
     return llvm::ConstantVector::get(nested);
   return llvm::ConstantArray::get(
       llvm::ArrayType::get(elementType, shape.front()), nested);
 }
 
-/// Returns the first non-sequential type netsed in sequential types.
+/// Returns the first non-sequential type nested in sequential types.
 static llvm::Type *getInnermostElementType(llvm::Type *type) {
   while (isa<llvm::SequentialType>(type))
     type = type->getSequentialElementType();
   return type;
 }
 
 /// Create an LLVM IR constant of `llvmType` from the MLIR attribute `attr`.
 /// This currently supports integer, floating point, splat and dense element

mlir/lib/Transforms/LoopFusion.cpp

Operation *getFusedLoopNestInsertionPoint(unsigned srcId, unsigned dstId) {
     return dstNodeInst;
   }
 
   // Updates edge mappings from node 'srcId' to node 'dstId' after 'oldMemRef'
   // has been replaced in node at 'dstId' by a private memref depending
   // on the value of 'createPrivateMemRef'.
   void updateEdges(unsigned srcId, unsigned dstId, Value oldMemRef,
                    bool createPrivateMemRef) {
-    // For each edge in 'inEdges[srcId]': add new edge remaping to 'dstId'.
+    // For each edge in 'inEdges[srcId]': add new edge remapping to 'dstId'.
     if (inEdges.count(srcId) > 0) {
       SmallVector<Edge, 2> oldInEdges = inEdges[srcId];
       for (auto &inEdge : oldInEdges) {
         // Add edge from 'inEdge.id' to 'dstId' if not for 'oldMemRef'.
         if (inEdge.value != oldMemRef)
           addEdge(inEdge.id, dstId, inEdge.value);
       }
     }

mlir/test/Dialect/SPIRV/target-env.mlir

 // RUN: mlir-opt -disable-pass-threading -test-spirv-target-env %s | FileCheck %s
 
 // Note: The following tests check that a spv.target_env can properly control
 // the conversion target and filter unavailable ops during the conversion.
 // We don't care about the op argument consistency too much; so certain enum
 // values for enum attributes may not make much sense for the test op.
 
 // spv.AtomicCompareExchangeWeak is available from SPIR-V 1.0 to 1.3 under
 // Kernel capability.
 // spv.AtomicCompareExchangeWeak has two memory semantics enum attribute,
 // whose value, if containing AtomicCounterMemory bit, additionally requires
 // AtomicStorage capability.
 
-// spv.BitReverse is available in all SPIR-V versiosn under Shader capability.
+// spv.BitReverse is available in all SPIR-V versions under Shader capability.
 
 // spv.GroupNonUniformBallot is available starting from SPIR-V 1.3 under
 // GroupNonUniform capability.
 
 // spv.SubgroupBallotKHR is available under in all SPIR-V versions under
 // SubgroupBallotKHR capability and SPV_KHR_shader_ballot extension.
 
 // The GeometryPointSize capability implies the Geometry capability, which

mlir/test/lib/TestDialect/TestPatterns.cpp

 static mlir::PassRegistration<TestPatternDriver>
     pass("test-patterns", "Run test dialect patterns");
 
 //===----------------------------------------------------------------------===//
 // ReturnType Driver.
 //===----------------------------------------------------------------------===//
 
 namespace {
-// Generate ops for each instance where the type can be succesfully infered.
+// Generate ops for each instance where the type can be successfully infered.
 template <typename OpTy>
 static void invokeCreateWithInferedReturnType(Operation *op) {
   auto *context = op->getContext();
   auto fop = op->getParentOfType<FuncOp>();
   auto location = UnknownLoc::get(context);
   OpBuilder b(op);
   b.setInsertionPointAfter(op);
 

mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp

public:
   /// in the record name otherwise.
   std::string getOperationName() const {
     llvm::StringRef name = record.getValueAsString(fieldName);
     if (!name.empty())
       return name.str();
 
     name = record.getName();
     assert(name.startswith("int_") &&
-           "LLVM intinsic names are expected to start with 'int_'");
+           "LLVM intrinsic names are expected to start with 'int_'");
     name = name.drop_front(4);
     llvm::SmallVector<llvm::StringRef, 8> chunks;
     name.split(chunks, '_');
     return llvm::join(chunks, ".");
   }
 
   /// Get the name of the record without the "intrinsic" prefix.
   llvm::StringRef getProperRecordName() const {
     llvm::StringRef name = record.getName();
     assert(name.startswith("int_") &&
-           "LLVM intinsic names are expected to start with 'int_'");
+           "LLVM intrinsic names are expected to start with 'int_'");
     return name.drop_front(4);
   }
 
   /// Get the number of operands.
   unsigned getNumOperands() const {
     auto operands = record.getValueAsListOfDefs(fieldOperands);
     for (const llvm::Record *r : operands) {
       (void)r;
bool isCommutative() const {
     for (const llvm::Record *r : props) {
       if (r->getName() == "Commutative")
         return true;
     }
     return false;
   }
 
 private:
-  /// Names of the fileds in the Intrinsic LLVM Tablegen class.
+  /// Names of the fields in the Intrinsic LLVM Tablegen class.
   const char *fieldName = "LLVMName";
   const char *fieldOperands = "ParamTypes";
   const char *fieldResults = "RetTypes";
   const char *fieldTraits = "IntrProperties";
 
   const llvm::Record &record;
 };
 } // namespace

mlir/tools/mlir-tblgen/RewriterGen.cpp

bool isBroadcastable =
       resultOp.getTrait("OpTrait::BroadcastableTwoOperandsOneResult");
   bool usePartialResults = valuePackName != resultValue;
 
   if (isBroadcastable || usePartialResults || depth > 0 || resultIndex < 0) {
     // For these cases (broadcastable ops, op results used both as auxiliary
     // values and replacement values, ops in nested patterns, auxiliary ops), we
     // still need to supply the result types when building the op. But because
     // we don't generate a builder automatically with ODS for them, it's the
-    // developer's responsiblity to make sure such a builder (with result type
+    // developer's responsibility to make sure such a builder (with result type
     // deduction ability) exists. We go through the separate-parameter builder
     // here given that it's easier for developers to write compared to
     // aggregate-parameter builders.
     createSeparateLocalVarsForOpArgs(tree, childNodeNames);
     os.indent(6) << formatv("{0} = rewriter.create<{1}>(loc", valuePackName,
                             resultOp.getQualCppClassName());
     supplyValuesForOpArgs(tree, childNodeNames);
     os << "\n      );\n";

mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp

 }
 
 //===----------------------------------------------------------------------===//
 // SPIR-V Capability Implication Hook Registration
 //===----------------------------------------------------------------------===//
 
 static mlir::GenRegistration
     genCapabilityImplication("gen-spirv-capability-implication",
-                             "Generate utilty function to return implied "
+                             "Generate utility function to return implied "
                              "capabilities for a given capability",
                              [](const RecordKeeper &records, raw_ostream &os) {
                                return emitCapabilityImplication(records, os);
                              });