[PowerPC] set instruction number as 1st priority for lsr cost model

[shchenz]

Summary

This issue comes from case in file test/CodeGen/PowerPC/lsr-insns-cost.ll

Three iteration IVs are used while we expect one. This is because, on PowerPC, register number is 1st priority for lsr cost model now.

This patch changes instruction number as 1st priority.

[merge_guards_bot]

Unit tests: pass. 61801 tests passed, 0 failed and 781 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[shchenz]

ping

[steven.zhang]

llvm/test/CodeGen/PowerPC/unal-altivec.ll

36

The "add" here is new added ? Does it mean that, for this case, it produces bad code ?

[shchenz]

llvm/test/CodeGen/PowerPC/unal-altivec.ll

36

Thanks for reviewing this.
Yes, for this case, the inst number inside the loop becomes larger. I plan to look into it later.
For big applications, I get the perf data for cpu spec2017, we get a positive result.

[steven.zhang]

LGTM as the perf number shows good. But please hold on some days in case others have other concern. And please follow up with the bad case.

[jsji]

Can we add an option to control the strategy here, so that people can fall back to old behavior? Thanks.

[shchenz]

In D72683#1874943, @jsji wrote:

Can we add an option to control the strategy here, so that people can fall back to old behavior? Thanks.

Good Idea! Will do it in next patch.

[shchenz]

add option ppc-lsr-no-insns-cost to support using default lsr cost model on PowerPC & one test case for the option.

[jsji]

LGTM. Thanks.

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h

bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
                                 AssumptionCache &AC,
                                 TargetLibraryInfo *LibInfo,
                                 HardwareLoopInfo &HWLoopInfo);
   bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI,
                   DominatorTree *DT, AssumptionCache *AC,
                   TargetLibraryInfo *LibInfo);
   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                TTI::UnrollingPreferences &UP);
+  bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
+                     TargetTransformInfo::LSRCost &C2);
 
   /// @}
 
   /// \name Vector TTI Implementations
   /// @{
   bool useColdCCForColdCall(Function &F);
   bool enableAggressiveInterleaving(bool LoopHasReductions);
   TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

 CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
               cl::desc("The loop prefetch cache line size"));
 
 static cl::opt<bool>
 EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false),
                 cl::desc("Enable using coldcc calling conv for cold "
                          "internal functions"));
 
+static cl::opt<bool>
+LsrNoInsnsCost("ppc-lsr-no-insns-cost", cl::Hidden, cl::init(false),
+               cl::desc("Do not add instruction count to lsr cost model"));
+
 // The latency of mtctr is only justified if there are more than 4
 // comparisons that will be removed as a result.
 static cl::opt<unsigned>
 SmallCTRLoopThreshold("min-ctr-loop-threshold", cl::init(4), cl::Hidden,
                       cl::desc("Loops with a constant trip count smaller than "
                                "this value will not use the count register."));
 
 //===----------------------------------------------------------------------===//
if (!isHardwareLoopProfitable(L, *SE, *AC, LibInfo, HWLoopInfo))
     return false;
 
   if (!HWLoopInfo.isHardwareLoopCandidate(*SE, *LI, *DT))
     return false;
 
   *BI = HWLoopInfo.ExitBranch;
   return true;
 }
+
+bool PPCTTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
+                               TargetTransformInfo::LSRCost &C2) {
+  // PowerPC default behaviour here is "instruction number 1st priority".
+  // If LsrNoInsnsCost is set, call default implementation.
+  if (!LsrNoInsnsCost)
+    return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, C1.NumIVMuls,
+                    C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
+           std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, C2.NumIVMuls,
+                    C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost);
+  else
+    return TargetTransformInfoImplBase::isLSRCostLess(C1, C2);
+}

llvm/test/CodeGen/PowerPC/addi-licm.ll

entry:
   call void @llvm.lifetime.start.p0i8(i64 8192, i8* %0) #2
   %1 = bitcast [2048 x float]* %y to i8*
   call void @llvm.lifetime.start.p0i8(i64 8192, i8* %1) #2
   br label %for.body.i
 
 ; CHECK-LABEL: @foo
 ; CHECK: addi [[REG1:[0-9]+]], 1,
 ; CHECK: addi [[REG2:[0-9]+]], 1,
+; CHECK: li [[REG3:[0-9]+]], 0
 ; CHECK: %for.body.i
-; CHECK-DAG: lfs {{[0-9]+}}, 0([[REG1]])
-; CHECK-DAG: lfs {{[0-9]+}}, 0([[REG2]])
+; CHECK-DAG: lfsx {{[0-9]+}}, [[REG1]], [[REG3]]
+; CHECK-DAG: lfsx {{[0-9]+}}, [[REG2]], [[REG3]]
 ; CHECK: blr
 
 ; PIP-LABEL: @foo
 ; PIP: addi [[REG1:[0-9]+]], 1,
 ; PIP: addi [[REG2:[0-9]+]], 1,
 ; PIP: %for.body.i
 ; PIP-DAG: lfsu {{[0-9]+}}, 4([[REG1]])
 ; PIP-DAG: lfsu {{[0-9]+}}, 4([[REG2]])

llvm/test/CodeGen/PowerPC/lsr-insns-cost.ll

-; RUN: llc -ppc-asm-full-reg-names  -verify-machineinstrs < %s \
-; RUN:   -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=INST
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -ppc-lsr-no-insns-cost=true \
+; RUN:   < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=REG
 
 ; void test(unsigned *a, unsigned *b, unsigned *c)
 ; {
 ;   for (unsigned long i = 0; i < 1024; i++)
 ;       c[i] = a[i] + b[i];
 ; }
 ;
 ; compile with -fno-unroll-loops
 
 define void @lsr-insts-cost(i32* %0, i32* %1, i32* %2) {
-; CHECK-LABEL: lsr-insts-cost
-; CHECK:       .LBB0_4: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    lxvd2x vs34, 0, r3
-; CHECK-NEXT:    lxvd2x vs35, 0, r4
-; CHECK-NEXT:    addi r4, r4, 16
-; CHECK-NEXT:    addi r3, r3, 16
-; CHECK-NEXT:    vadduwm v2, v3, v2
-; CHECK-NEXT:    stxvd2x vs34, 0, r5
-; CHECK-NEXT:    addi r5, r5, 16
-; CHECK-NEXT:    bdnz .LBB0_4
+; INST-LABEL: lsr-insts-cost
+; INST:       .LBB0_4: # =>This Inner Loop Header: Depth=1
+; INST-NEXT:    lxvd2x vs34, r3, r6
+; INST-NEXT:    lxvd2x vs35, r4, r6
+; INST-NEXT:    vadduwm v2, v3, v2
+; INST-NEXT:    stxvd2x vs34, r5, r6
+; INST-NEXT:    addi r6, r6, 16
+; INST-NEXT:    bdnz .LBB0_4
+;
+; REG-LABEL: lsr-insts-cost
+; REG:       .LBB0_4: # =>This Inner Loop Header: Depth=1
+; REG-NEXT:    lxvd2x vs34, 0, r3
+; REG-NEXT:    lxvd2x vs35, 0, r4
+; REG-NEXT:    addi r4, r4, 16
+; REG-NEXT:    addi r3, r3, 16
+; REG-NEXT:    vadduwm v2, v3, v2
+; REG-NEXT:    stxvd2x vs34, 0, r5
+; REG-NEXT:    addi r5, r5, 16
+; REG-NEXT:    bdnz .LBB0_4
   %4 = getelementptr i32, i32* %2, i64 1024
   %5 = getelementptr i32, i32* %0, i64 1024
   %6 = getelementptr i32, i32* %1, i64 1024
   %7 = icmp ugt i32* %5, %2
   %8 = icmp ugt i32* %4, %0
   %9 = and i1 %7, %8
   %10 = icmp ugt i32* %6, %2
   %11 = icmp ugt i32* %4, %1

llvm/test/CodeGen/PowerPC/unal-altivec.ll

vector.body:                                      ; preds = %vector.body, %vector.ph
   %8 = getelementptr float, float* %a, i64 %.sum12
   %9 = bitcast float* %8 to <4 x float>*
   store <4 x float> %5, <4 x float>* %9, align 4
   %index.next = add i64 %index, 8
   %10 = icmp eq i64 %index.next, 16000
   br i1 %10, label %for.end, label %vector.body
 
 ; CHECK: @foo
-; CHECK-DAG: li [[C16:[0-9]+]], 16
+; CHECK-DAG: li [[C0:[0-9]+]], 0
 ; CHECK-DAG: lvx [[CNST:[0-9]+]],
 ; CHECK: .LBB0_1:
-; CHECK-DAG: lvx [[LD1:[0-9]+]], 0, [[C0:[0-9]+]]
-; CHECK-DAG: lvx [[LD2:[0-9]+]], [[C0]], [[C16]]
-; CHECK-DAG: lvsl [[MASK1:[0-9]+]], 0, [[C0]]
-; CHECK-DAG: vperm [[VR1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
-; CHECK-DAG: vaddfp {{[0-9]+}}, [[VR1]], [[CNST]]
+; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
+; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]]
+; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
+; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]],
+; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
+; CHECK-DAG: vaddfp {{[0-9]+}}, [[R1]], [[CNST]]
 ; CHECK: blr
 
 for.end:                                          ; preds = %vector.body
   ret void
 }
 
 attributes #0 = { nounwind }