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[RFC] Support SVE registers access on AArch64 Linux
AbandonedPublic

Authored by omjavaid on Jan 6 2020, 3:49 AM.

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Summary

This is an RFC patch for the on going effort to support SVE registers access on AArch64 Linux. This patch lays down the structure and major parts of the implementation and seeks community feedback on overall design approach more specifically to the generic areas of gdb-remote process, register infos and register context classes.

The Scalable Vector Extension (SVE) is an optional extension introduced by the ARMv8.2 architecture and can be implemented by underlying hardware AArch64 execution state. SVE has introduced 32 Z registers (Z0..Z31), 16 P register (P0..P15) and an FFR register. All these registers can change their size dynamically during execution. SVE register sizes is governed by currently set vector length in multiples of 16 bytes. Z register has a 16 byte default size and its size can increase in multiples of 16 bytes upto 128 bytes. While size of P and FFR registers is equal to size of Z register divided by 8. Linux tracks SVE register per thread and each thread can have its own setting of vector length upon which its size is decided.

First part of this implementation deals with adding capability for dynamic size/offset update in register info description hosted by gdb-remote process and also on native Linux side. Also we have to make these register description per_thread so that they can have their own size and offset.

Also there has to be a way to exchange update size information between remote target and host. This is where VG (Vector Granule) pseudo register comes in, VG is the size of a Z register in 8 bytes (64bits) multiples. This information is read from PTRACE and sent back via expedited registers list. We have altered expedited register list to send a custom register set other than the register set at index 0 which is choosen by default. Once read by the host VG will help updated register sizes and offsets in DynamicRegisterInfos hosted by each gdb-remote thread.

Similarly on native size there is ConfigureRegisterContext function which will update register infos accordingly. Rest of code is implementation of register infos for SVE, some modifications to register infos to support SVE and register context linux ptrace access routines.

I am still working on some areas like offset sync and register data resizing. Looking forward to hear your feedback.

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omjavaid created this revision.Jan 6 2020, 3:49 AM

This doesn't seem too bad from a quick pass, the thing I'd like to see here is to split this up into several patches (and least client vs. server side) and have proper tests for each part (I'm particularly interested in gdb-client-like tests to give coverage to the per-thread register infos for people without an arm sve chip).

omjavaid abandoned this revision.Apr 1 2020, 4:22 AM

Abandoned in favor of following patches and more to come as suggested by labath in separate patches.

https://reviews.llvm.org/D77047

https://reviews.llvm.org/D77045

https://reviews.llvm.org/D77044

https://reviews.llvm.org/D77043

labath added a comment.Apr 1 2020, 5:17 AM

Thanks for splitting this up.