[llvm-exegesis] Add pfm counters for Zen2 (znver2).

[courbet]

Summary

They are the same as zen1.

[RKSimon]

This will not work once D66088 lands - @GGanesh are you ready to commit D66088 yet?

[courbet]

Thanks. I'll wait for the other patch to be submitted and then change the binding.

[GGanesh]

We are checking the libpfm enablement. I can commit D66088 if we are okay without libpfm.

[dblaikie]

I take it there's no way to write a portable test for this patch? (one that doesn't have to run on the specific hardware, but still demonstrates the presence of this newly added support?)

[RKSimon]

In D72032#1799891, @GGanesh wrote:

We are checking the libpfm enablement. I can commit D66088 if we are okay without libpfm.

@GGanesh D66088 has already been accepted and (as discussed on its review) committing that straight away as a baseline makes sense, @courbet can then rebase this patch to get llvm-exegesis working with the new model and then you can further polish the model in follow up patches.

[courbet]

In D72032#1800035, @dblaikie wrote:

I take it there's no way to write a portable test for this patch? (one that doesn't have to run on the specific hardware, but still demonstrates the presence of this newly added support?)

You're right.

[GGanesh]

RKSimon could you please commit D66088 on my behalf. I think my github account is not added.

[courbet]

Rebase after D66088.

[RKSimon]

llvm/lib/Target/X86/X86PfmCounters.td

234

typo?

[courbet]

fix typo

llvm/lib/Target/X86/X86PfmCounters.td

234

Yes, thanks.

[courbet]

Ping ?

[GGanesh]

llvm/lib/Target/X86/X86PfmCounters.td

231

Can you please help me to comprehend this better.
Zen2 has an AGU scheduler which services the AGU pipelines.
So why are we considering only two will be able to compute load addresses?

[courbet]

llvm/lib/Target/X86/X86PfmCounters.td

231

I'm not familiar at all with how AMD microarchitetcures work, but from https://en.wikichip.org/wiki/amd/microarchitectures/zen_2 I understand that not all AGUs can do the same things ?

Two AGUs can generate addresses for load operations and send them to the load queue. All three AGUs can generate addresses for store operations and send them to the store queue.

[GGanesh]

llvm/lib/Target/X86/X86PfmCounters.td

231

Well! I think I need to get the wikichip URL edited. I will try to get that done.

Load and Store micro ops are sent to one 28-entry address generation unit (AGU) scheduler. There are 3 AGUs for all load and store address generation.

[courbet]

Remove FIXME as per the explanations from GGanesh@.

[courbet]

OK, thanks for the clarification !

[GGanesh]

Good with me! I am have moved some stones to get the wikichip URL updated.

llvm/lib/Target/X86/X86PfmCounters.td

let IssueCounters = [
     PfmIssueCounter<"ZnFPU0", "fpu_pipe_assignment:total0">,
     PfmIssueCounter<"ZnFPU1", "fpu_pipe_assignment:total1">,
     PfmIssueCounter<"ZnFPU2", "fpu_pipe_assignment:total2">,
     PfmIssueCounter<"ZnFPU3", "fpu_pipe_assignment:total3">,
     PfmIssueCounter<"ZnDivider", "div_op_count">
   ];
 }
 def : PfmCountersBinding<"znver1", ZnVer1PfmCounters>;
+
+def ZnVer2PfmCounters : ProcPfmCounters {
+  let CycleCounter = PfmCounter<"cycles_not_in_halt">;
+  let UopsCounter = PfmCounter<"retired_uops">;
+  let IssueCounters = [
+    PfmIssueCounter<"Zn2AGU", "ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">,
+    PfmIssueCounter<"Zn2Divider", "div_op_count">
+  ];
+}
+def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>;