[PowerPC] Set the SideEffects of branch & call instructions from 1 to 0

[qiucf]

Summary

If we didn't set the value for hasSideEffects bit in our td file, llvm-tblgen will set it as true for those instructions which has no match pattern.
But for branch & call instructions, PPC can model, so those instructions don't need the hasSideEffects flag.

This patch is to set the SideEffects of branch & call instructions from 1 to 0. The SideEffects flag of below instructions have been set from 1 to 0:

Below instructions can be generated:

BCC
BCCCTR
BCCCTR8
BCCCTRL
BCCCTRL8
BCCLR
BCCTR
BCCTR8
BCCTR8n
BCCTRL
BCCTRL8
BCCTRL8n
BCCTRLn
BCCTRn
BCLR
BCLRn
BCLalways
BCTR
BCTR8
BDNZ
BDNZ8
BDNZLR
BDNZLR8
BDZ
BDZ8
BDZLR
BDZLR8
BL8_NOP_TLS
BL_TLS
CTRL_DEP
TAILB
TAILB8
TAILBA
TAILBA8
TAILBCTR
TAILBCTR8

Below instructions can't be generated:

BA
BCL
BCLRL
BCLRLn
BCLn
BDNZA
BDNZAm
BDNZAp
BDNZL
BDNZLA
BDNZLAm
BDNZLAp
BDNZLRL
BDNZLRLm
BDNZLRLp
BDNZLRm
BDNZLRp
BDNZLm
BDNZLp
BDNZm
BDNZp
BDZA
BDZAm
BDZAp
BDZL
BDZLA
BDZLAm
BDZLAp
BDZLRL
BDZLRLm
BDZLRLp
BDZLRm
BDZLRp
BDZLm
BDZLp
BDZm
BDZwap
BL8_TLS
BL8_TLS_
BLRL

BCCA
BCCL
BCCLA
BCCLRL
gBC
gBCA
gBCAat
gBCCTR
gBCCTRL
gBCL
gBCLA
gBCLAat
gBCLR
gBCLRL
gBCLat
gBCat

[ZhangKang]

I have tested the spec performance for this patch, there is no degression.

[hfinkel]

Do you expect any effect at all from doing this? These are all scheduling barriers?

[ZhangKang]

In D71983#1799470, @hfinkel wrote:

Do you expect any effect at all from doing this? These are all scheduling barriers?

I do the performance test just to confirm there is no degression, because this patch is not a NFC patch.
From the definition of hasUnmodeledSideEffects(), we can know calling, branching and returning instructions shouldn't set hasSideEffect flag, because we can model them.
I do this patch to fix the hasSideEffect flag, it may give us more potential optimization opportunities.

/// Return true if this instruction has side
  /// effects that are not modeled by other flags.  This does not return true
  /// for instructions whose effects are captured by:
  ///
  ///  1. Their operand list and implicit definition/use list.  Register use/def
  ///     info is explicit for instructions.
  ///  2. Memory accesses.  Use mayLoad/mayStore.
  ///  3. Calling, branching, returning: use isCall/isReturn/isBranch.
  ///
  /// Examples of side effects would be modifying 'invisible' machine state like
  /// a control register, flushing a cache, modifying a register invisible to
  /// LLVM, etc.
  bool hasUnmodeledSideEffects() const {
    return Flags & (1ULL << MCID::UnmodeledSideEffects);
  }

[ZhangKang]

In D71983#1799470, @hfinkel wrote:

Do you expect any effect at all from doing this? These are all scheduling barriers?

The SideEffect flag is not only used for scheduling, for example:

bool ImplicitNullChecks::canHandle(const MachineInstr *MI) {
  if (MI->isCall() || MI->mayRaiseFPException() ||
      MI->hasUnmodeledSideEffects())
    return false;
  auto IsRegMask = [](const MachineOperand &MO) { return MO.isRegMask(); };
  (void)IsRegMask;

  assert(!llvm::any_of(MI->operands(), IsRegMask) &&
         "Calls were filtered out above!");

  auto IsUnordered = [](MachineMemOperand *MMO) { return MMO->isUnordered(); };
  return llvm::all_of(MI->memoperands(), IsUnordered);
}

[steven.zhang]

In D71983#1799470, @hfinkel wrote:

Do you expect any effect at all from doing this? These are all scheduling barriers?

I think, there are more than scheduling affected with this flag and from the documentation in the .td, we should clear it for branch instruction as the isBranch bit already model it.

./Target/Lanai/LanaiInstrInfo.cpp:  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
./Target/Lanai/LanaiDelaySlotFiller.cpp:    if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isLabel() ||
./Target/PowerPC/PPCQPXLoadSplat.cpp:      if (MI->hasUnmodeledSideEffects() || MI->isCall()) {
./Target/PowerPC/PPCInstrInfo.cpp:  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
./Target/Hexagon/HexagonStoreWidening.cpp:    if (MI->isCall() || MI->hasUnmodeledSideEffects())
./Target/Hexagon/HexagonEarlyIfConv.cpp:  if (MI->hasUnmodeledSideEffects())
./Target/Hexagon/HexagonInstrInfo.cpp:  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
./Target/Hexagon/RDFDeadCode.cpp:  if (MI->hasOrderedMemoryRef() || MI->hasUnmodeledSideEffects() ||
./Target/Hexagon/HexagonCopyToCombine.cpp:         MI.hasUnmodeledSideEffects() || MI.isInlineAsm() ||
./Target/Hexagon/HexagonExpandCondsets.cpp:  if (MI->hasUnmodeledSideEffects() || MI->mayStore())
./Target/Hexagon/HexagonExpandCondsets.cpp:  if (TheI.hasUnmodeledSideEffects())
./Target/Hexagon/HexagonExpandCondsets.cpp:    if (MI->hasUnmodeledSideEffects())
./Target/Hexagon/HexagonBitSimplify.cpp:    if (MI->isPHI() || MI->hasUnmodeledSideEffects() || MI->isInlineAsm())
./Target/Hexagon/HexagonBitSimplify.cpp:  if (MI->hasUnmodeledSideEffects() || MI->isInlineAsm())
./Target/Mips/MipsDelaySlotFiller.cpp:          Candidate.hasUnmodeledSideEffects());
./Target/WebAssembly/WebAssemblyRegStackify.cpp:      // These instruction have hasUnmodeledSideEffects() returning true
./Target/WebAssembly/WebAssemblyRegStackify.cpp:  if (MI.hasUnmodeledSideEffects()) {
./Target/WebAssembly/WebAssemblyRegStackify.cpp:      // These instructions have hasUnmodeledSideEffects() returning true
./Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp:              I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
./Target/AMDGPU/SIInstrInfo.cpp:    if (!MI.mayLoad() || MI.hasUnmodeledSideEffects())
./Target/AMDGPU/SIInstrInfo.cpp:  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects())
./Target/AMDGPU/SILoadStoreOptimizer.cpp:      if (MBBI->hasUnmodeledSideEffects()) {
./Target/AMDGPU/log:85f38901266a6 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (Matt Arsenault          2019-07-19 19:47:30 +0000 1551)     if (!MI.mayLoad() || MI.hasUnmodeledSideEffects())
./Target/AMDGPU/log:9cfc75c214d42 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (Duncan P. N. Exon Smith 2016-06-30 00:01:54 +0000 2557)   if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects())
./Target/ARM/ARMOptimizeBarriersPass.cpp:          MI->hasUnmodeledSideEffects() ||
./Target/ARM/ARMLoadStoreOptimizer.cpp:    if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects())
./Target/ARC/ARCOptAddrMode.cpp:        MI->hasUnmodeledSideEffects())
./Target/ARC/ARCOptAddrMode.cpp:        MI->hasUnmodeledSideEffects())
./Target/RISCV/RISCVInstrInfo.cpp:  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
./Target/RISCV/RISCVISelLowering.cpp:      if (SequenceMBBI->hasUnmodeledSideEffects() ||
./Target/SystemZ/SystemZElimCompare.cpp:        (MI.isCall() || MI.hasUnmodeledSideEffects()))
./Target/AArch64/AArch64InstrInfo.cpp:  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
./Target/Sparc/DelaySlotFiller.cpp:    if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
./CodeGen/MachineInstr.cpp:      mayRaiseFPException() || hasUnmodeledSideEffects())
./CodeGen/MachineInstr.cpp:      !hasUnmodeledSideEffects())
./CodeGen/MachineInstr.cpp:bool MachineInstr::hasUnmodeledSideEffects() const {
./CodeGen/MachineInstr.cpp:  return mayStore() || isCall() || hasUnmodeledSideEffects();
./CodeGen/PeepholeOptimizer.cpp:      if (MI->isInlineAsm() || MI->hasUnmodeledSideEffects()) {
./CodeGen/PeepholeOptimizer.cpp:  if (Def->mayRaiseFPException() || Def->hasUnmodeledSideEffects())
./CodeGen/ScheduleDAGInstrs.cpp:  return MI->isCall() || MI->hasUnmodeledSideEffects() ||
./CodeGen/MachineCSE.cpp:      MI->mayRaiseFPException() || MI->hasUnmodeledSideEffects())
./CodeGen/TargetInstrInfo.cpp:      MI.hasUnmodeledSideEffects())
./CodeGen/MachinePipeliner.cpp:         MI.hasUnmodeledSideEffects() ||
./CodeGen/MachinePipeliner.cpp:  if (SI->hasUnmodeledSideEffects() || DI->hasUnmodeledSideEffects() ||
./CodeGen/LiveRangeShrink.cpp:        if (MI.hasUnmodeledSideEffects() && Next != MBB.end()) {
./CodeGen/ImplicitNullChecks.cpp:      MI->hasUnmodeledSideEffects())
./CodeGen/GlobalISel/InstructionSelector.cpp:         !MI.hasUnmodeledSideEffects() && MI.implicit_operands().empty();
./CodeGen/MachineLICM.cpp:  if (!MI.mayStore() || MI.hasUnmodeledSideEffects() ||
./CodeGen/TwoAddressInstructionPass.cpp:  if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
./CodeGen/TwoAddressInstructionPass.cpp:    if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
./CodeGen/TwoAddressInstructionPass.cpp:    if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
./MCA/InstrBuilder.cpp:                        !MCDesc.hasUnmodeledSideEffects();
./MCA/InstrBuilder.cpp:                        !MCDesc.hasUnmodeledSideEffects();
./MCA/InstrBuilder.cpp:  ID->HasSideEffects = MCDesc.hasUnmodeledSideEffects();

[jsji]

Yes, in theory, it might affect scheduling and other opts as well.
Can we please prove it by providing a test case that has changes due to this patch. Thanks.

[jsji]

Set it back , please update with testcases.

[qiucf]

Provide a test case. (not pre-commited)

[shchenz]

LGTM.

The sinking in the test after unset hasSideEffects is right and profitable.

[jsji]

LGTM. But maybe we should try to see whether we can set hasSideEffects = 0 as default on PowerPC as well when there are no match patterns?

[qiucf]

In D71983#2967171, @jsji wrote:

LGTM. But maybe we should try to see whether we can set hasSideEffects = 0 as default on PowerPC as well when there are no match patterns?

Yes. Will clean them up in a future patch.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 }]>;
 
 
 //===----------------------------------------------------------------------===//
 // Calls.
 //
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
-let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
+let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
   let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in
     def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
                             [(retflag)]>, Requires<[In64BitMode]>;
   let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
     let isPredicable = 1 in
       def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
                                []>,
           Requires<[In64BitMode]>;
def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
         Requires<[In64BitMode]>;
   }
 }
 
 let Defs = [LR8] in
   def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>,
                     PPC970_Unit_BRU;
 
-let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
   let Defs = [CTR8], Uses = [CTR8] in {
     def BDZ8  : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
                         "bdz $dst">;
     def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
                         "bdnz $dst">;
   }
 
   let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
     def BDZLR8  : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
                               "bdzlr", IIC_BrB, []>;
     def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
                               "bdnzlr", IIC_BrB, []>;
   }
 }
 
 
 
-let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
+let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {
   // Convenient aliases for call instructions
   let Uses = [RM] in {
     def BL8  : IForm<18, 0, 1, (outs), (ins calltarget:$func),
                      "bl $func", IIC_BrB, []>;  // See Pat patterns below.
 
     def BL8_TLS  : IForm<18, 0, 1, (outs), (ins tlscall:$func),
                          "bl $func", IIC_BrB, []>;
 
def BCTRL8_LDinto_toc :
     Requires<[In64BitMode]>;
 }
 
 } // Interpretation64Bit
 
 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
 // previous definition must be marked as CodeGen only to prevent decoding
 // conflicts.
-let Interpretation64Bit = 1, isAsmParserOnly = 1 in
+let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in
 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
                      "bl $func", IIC_BrB, []>;
 
 // Calls
 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
           (BL8 tglobaladdr:$dst)>;
 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
                  "#TC_RETURNa8 $func $offset",
                  [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
 
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
 def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
                  "#TC_RETURNr8 $dst $offset",
                  []>;
 
+let hasSideEffects = 0 in {
 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
     isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
                              []>,
     Requires<[In64BitMode]>;
 
 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
     isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
 def TAILB8   : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
                   "b $dst", IIC_BrB,
                   []>;
 
 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
     isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
 def TAILBA8   : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
                   "ba $dst", IIC_BrB,
                   []>;
+}
 } // Interpretation64Bit
 
 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst),  imm:$imm),
           (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
 
 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
           (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
 

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 // spilled), so we'll need to scavenge a register for it.
 let mayLoad = 1 in {
 def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F),
                      "#RESTORE_CR", []>;
 def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F),
                            "#RESTORE_CRBIT", []>;
 }
 
-let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
+let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
   let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in
     def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
                            [(retflag)]>, Requires<[In32BitMode]>;
   let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
     let isPredicable = 1 in
       def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
                               []>;
 

 
 let Defs = [LR] in
   def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>,
                    PPC970_Unit_BRU;
 let Defs = [LR] in
   def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>,
                     PPC970_Unit_BRU;
 
-let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
+    hasSideEffects = 0 in {
   let isBarrier = 1 in {
     let isPredicable = 1 in
       def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
                     "b $dst", IIC_BrB,
                     [(br bb:$dst)]>;
   def BA  : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
                   "ba $dst", IIC_BrB, []>;
   }
let Defs = [CTR], Uses = [CTR] in {
     def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
                         "bdza- $dst">;
     def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
                         "bdnza- $dst">;
   }
 }
 
 // The unconditional BCL used by the SjLj setjmp code.
-let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
+let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7,
+    hasSideEffects = 0 in {
   let Defs = [LR], Uses = [RM] in {
     def BCLalways  : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
                             "bcl 20, 31, $dst">;
   }
 }
 
 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
   // Convenient aliases for call instructions
let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
   def BCTRL_LWZinto_toc:
     XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
      (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB,
      [(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>;
 
 }
 
 
-let isCodeGenOnly = 1 in {
+let isCodeGenOnly = 1, hasSideEffects = 0 in {
 
 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
     isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM]  in
 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
                             []>, Requires<[In32BitMode]>;
 
 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
     isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
                             (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
 def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
 def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
 
 // These generic branch instruction forms are used for the assembler parser only.
 // Defs and Uses are conservative, since we don't know the BO value.
-let PPC970_Unit = 7, isBranch = 1 in {
+let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in {
   let Defs = [CTR], Uses = [CTR, RM] in {
     def gBC : BForm_3<16, 0, 0, (outs),
                       (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
                       "bc $bo, $bi, $dst">;
     def gBCA : BForm_3<16, 1, 0, (outs),
                        (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
                        "bca $bo, $bi, $dst">;
     let isAsmParserOnly = 1 in {

llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir

body:             |
   ; CHECK: bb.12 (%ir-block.60):
   ; CHECK:   successors: %bb.15(0x2aaaaaab), %bb.13(0x55555555)
   ; CHECK:   [[PHI8:%[0-9]+]]:gprc = PHI [[ADDI2]], %bb.11, [[ISEL1]], %bb.10
   ; CHECK:   [[ADDI8_4:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[PHI7]], 8
   ; CHECK:   [[LWZU:%[0-9]+]]:gprc, [[LWZU1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LWZU 8, [[PHI6]] :: (load (s32) from %ir.46, !tbaa !2)
   ; CHECK:   [[ADD4_2:%[0-9]+]]:gprc = nsw ADD4 [[LWZU]], [[PHI5]]
   ; CHECK:   [[ADD4_3:%[0-9]+]]:gprc = nsw ADD4 [[PHI8]], [[ADD4_2]]
   ; CHECK:   STW killed [[ADD4_3]], 0, [[ADDI8_4]] :: (store (s32) into %ir.44, !tbaa !2)
-  ; CHECK:   [[LWZ:%[0-9]+]]:gprc = LWZ 4, [[LWZU1]] :: (load (s32) from %ir.uglygep1112.cast, !tbaa !2)
   ; CHECK:   BCC 76, [[CMPLWI2]], %bb.15
   ; CHECK:   B %bb.13
   ; CHECK: bb.13 (%ir-block.60):
   ; CHECK:   successors: %bb.14(0x40000001), %bb.16(0x3fffffff)
   ; CHECK:   BCC 68, [[CMPLWI1]], %bb.16
   ; CHECK:   B %bb.14
   ; CHECK: bb.14 (%ir-block.67):
   ; CHECK:   successors: %bb.17(0x80000000)
body:             |
   ; CHECK:   successors: %bb.17(0x80000000)
   ; CHECK:   [[ORI8_1:%[0-9]+]]:g8rc = ORI8 [[RLDICL2]], 1
   ; CHECK:   [[ADD8_1:%[0-9]+]]:g8rc = ADD8 [[PHI4]], [[ORI8_1]]
   ; CHECK:   [[COPY14:%[0-9]+]]:gprc = COPY [[ADD8_1]].sub_32
   ; CHECK: bb.17 (%ir-block.74):
   ; CHECK:   successors: %bb.9(0x7c000000), %bb.3(0x04000000)
   ; CHECK:   [[PHI9:%[0-9]+]]:gprc = PHI [[ADDI3]], %bb.14, [[RLWINM4]], %bb.15, [[COPY14]], %bb.16
   ; CHECK:   [[COPY15:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_4]]
+  ; CHECK:   [[LWZ:%[0-9]+]]:gprc = LWZ 4, [[LWZU1]] :: (load (s32) from %ir.uglygep1112.cast, !tbaa !2)
   ; CHECK:   [[ADD4_4:%[0-9]+]]:gprc = nsw ADD4 [[LWZ]], [[ADD4_2]]
   ; CHECK:   [[ADD4_5:%[0-9]+]]:gprc = nsw ADD4 [[PHI9]], [[ADD4_4]]
   ; CHECK:   STW killed [[ADD4_5]], 4, [[COPY15]] :: (store (s32) into %ir.uglygep78.cast, !tbaa !2)
   ; CHECK:   [[ADDI8_5:%[0-9]+]]:g8rc = nuw nsw ADDI8 [[PHI4]], 2
   ; CHECK:   BDNZ8 %bb.9, implicit-def dead $ctr8, implicit $ctr8
   ; CHECK:   B %bb.3
   bb.0 (%ir-block.5):
     successors: %bb.1(0x50000000), %bb.9(0x30000000)

llvm/test/CodeGen/PowerPC/sink-side-effect.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le -mcpu=pwr9 -verify-machineinstrs < %s | FileCheck %s
+
+define double @zot(i32* %arg, float* %arg1, i16* %arg2) {
+; CHECK-LABEL: zot:
+; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    bc 12, 20, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %bb3
+; CHECK-NEXT:    lhz 5, 0(5)
+; CHECK-NEXT:    rlwinm. 5, 5, 28, 30, 31
+; CHECK-NEXT:  .LBB0_2: # %bb10
+; CHECK-NEXT:    lfs 0, 0(4)
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    li 4, 2
+; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    b .LBB0_4
+; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:  .LBB0_3: # %bb17
+; CHECK-NEXT:    #
+; CHECK-NEXT:    addi 4, 4, 1
+; CHECK-NEXT:  .LBB0_4: # %bb17
+; CHECK-NEXT:    #
+; CHECK-NEXT:    cmpw 4, 3
+; CHECK-NEXT:    bge 0, .LBB0_3
+; CHECK-NEXT:  # %bb.5:
+; CHECK-NEXT:    xsmuldp 1, 1, 0
+; CHECK-NEXT:    b .LBB0_3
+bb:
+  %tmp = load i32, i32* %arg, align 8
+  br i1 undef, label %bb9, label %bb3
+
+bb3:
+  %tmp4 = load i16, i16* %arg2, align 4
+  %tmp5 = lshr i16 %tmp4, 4
+  %tmp6 = and i16 %tmp5, 3
+  %tmp7 = zext i16 %tmp6 to i32
+  %tmp8 = icmp eq i16 %tmp6, 0
+  br i1 %tmp8, label %bb9, label %bb10
+
+bb9:
+  br label %bb10
+
+bb10:
+  %tmp11 = phi i32 [ undef, %bb9 ], [ %tmp7, %bb3 ]
+  %tmp12 = icmp sgt i32 %tmp11, 1
+  br label %bb13
+
+bb13:
+  %tmp14 = load float, float* %arg1, align 4
+  %tmp15 = fpext float %tmp14 to double
+  br label %bb16
+
+bb16:
+  br label %bb17
+
+bb17:
+  %tmp18 = phi i32 [ %tmp23, %bb17 ], [ 2, %bb16 ]
+  %tmp19 = phi double [ %tmp22, %bb17 ], [ %tmp15, %bb16 ]
+  %tmp20 = icmp slt i32 %tmp18, %tmp
+  %tmp21 = fmul fast double %tmp19, %tmp15
+  %tmp22 = select i1 %tmp20, double %tmp21, double %tmp19
+  %tmp23 = add nuw i32 %tmp18, 1
+  br label %bb17
+}
+
+declare double @ham()