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[AArch64][SVE] Implement intrinsics for non-temporal loads & stores

Authored by kmclaughlin on Dec 4 2019, 2:21 AM.



Adds the following intrinsics:

  • llvm.aarch64.sve.ldnt1
  • llvm.aarch64.sve.stnt1

This patch creates masked loads and stores with the
MONonTemporal flag set when used with the intrinsics above.

Diff Detail

Event Timeline

kmclaughlin created this revision.Dec 4 2019, 2:21 AM
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kmclaughlin edited the summary of this revision. (Show Details)
  • Removed AArch64 specific ISDNodes for MLOAD & MSTORE
efriedma added inline comments.Dec 4 2019, 3:20 PM

In order for alias analysis to correctly handle a MachineMemOperand, the "Size" of an operation has to be conservative, in the sense that the the number of bytes accessed must be at most "Size". Otherwise we'll assume two operations don't alias when they actually do.

For a scaled vector, we don't know the size, so we have to conservatively pass "MemoryLocation::UnknownSize".

  • Set 'Size' to MemoryLocation::UnknownSize for scalable vectors in getMemIntrinsicNode
  • Ensure MLOAD zeroes inactive lanes by using a zero value for the PassThru in getMaskedLoad
kmclaughlin marked 2 inline comments as done.Dec 9 2019, 8:45 AM
kmclaughlin added inline comments.

Thanks @efriedma, I have changed this to use MemoryLocation::UnknownSize

efriedma accepted this revision.Dec 9 2019, 12:43 PM



Offset (the fifth argument) is supposed to be a scalar, not a vector. Probably nothing actually checks that for loads that aren't pre/post-indexed. (Same applies to MSTORE.)

This revision is now accepted and ready to land.Dec 9 2019, 12:43 PM
kmclaughlin marked an inline comment as done.
  • Changed 'Offset' value used by getMaskedLoad & getMaskedStore to scalar type
This revision was automatically updated to reflect the committed changes.