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Differential D70998

[ARM] Enable TypePromotion by default
ClosedPublic

Authored by samparker on Dec 4 2019, 2:07 AM.

Details

Reviewers
SjoerdMeijer
dmgreen
efriedma
t.p.northover
rnk
Commits
rGee7579409b7d: [ARM][TypePromotion] Enable by default
rG393dacacf7e7: [ARM] Enable TypePromotion by default
Summary

ARMCodeGenPrepare has already been generalized and renamed to TypePromotion. We've had it enabled and tested downstream for a while, so now enable it by default upstream.

Diff Detail

Event Timeline

samparker created this revision.Dec 4 2019, 2:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 4 2019, 2:07 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
SjoerdMeijer accepted this revision.Dec 4 2019, 5:29 AM

We've had this enabled by default for almost 1 year downstream now, which is a decent amount of time to shake out some codegen bugs. I agree that flipping the switch now make sense, and hopefully similar non-X86 targets enjoy decent performance improvements too.

This revision is now accepted and ready to land.Dec 4 2019, 5:29 AM
Closed by commit rG393dacacf7e7: [ARM] Enable TypePromotion by default (authored by samparker). · Explain WhyDec 5 2019, 6:24 AM
This revision was automatically updated to reflect the committed changes.
samparker added a comment.Dec 5 2019, 6:28 AM

@SjoerdMeijer I added some code before committing as an arm codegen test was failing and producing worse code with this patch. The new code checks whether the promotion should be beneficial.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
2 lines
test/
Transforms/
TypePromotion/
ARM/
2 lines
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Diff 232058

llvm/lib/CodeGen/TypePromotion.cpp

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#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#define DEBUG_TYPE "type-promotion" #define DEBUG_TYPE "type-promotion"
#define PASS_NAME "Type Promotion" #define PASS_NAME "Type Promotion"
using namespace llvm; using namespace llvm;
static cl::opt<bool> static cl::opt<bool>
DisablePromotion("disable-type-promotion", cl::Hidden, cl::init(true), DisablePromotion("disable-type-promotion", cl::Hidden, cl::init(false),
cl::desc("Disable type promotion pass")); cl::desc("Disable type promotion pass"));
// The goal of this pass is to enable more efficient code generation for // The goal of this pass is to enable more efficient code generation for
// operations on narrow types (i.e. types with < 32-bits) and this is a // operations on narrow types (i.e. types with < 32-bits) and this is a
// motivating IR code example: // motivating IR code example:
// //
// define hidden i32 @cmp(i8 zeroext) { // define hidden i32 @cmp(i8 zeroext) {
// %2 = add i8 %0, -49 // %2 = add i8 %0, -49
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llvm/test/Transforms/TypePromotion/ARM/calls.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s ; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
define i8 @call_with_imms(i8* %arg) { define i8 @call_with_imms(i8* %arg) {
; CHECK-LABEL: @call_with_imms( ; CHECK-LABEL: @call_with_imms(
; CHECK-NEXT: [[CALL:%.*]] = tail call arm_aapcs_vfpcc zeroext i8 @dummy2(i8* nonnull [[ARG:%.*]], i8 zeroext 0, i8 zeroext 0) ; CHECK-NEXT: [[CALL:%.*]] = tail call arm_aapcs_vfpcc zeroext i8 @dummy2(i8* nonnull [[ARG:%.*]], i8 zeroext 0, i8 zeroext 0)
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[CALL]], 0 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[CALL]], 0
; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i8 [[CALL]], i8 1 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i8 [[CALL]], i8 1
; CHECK-NEXT: ret i8 [[RES]] ; CHECK-NEXT: ret i8 [[RES]]
; ;
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llvm/test/Transforms/TypePromotion/ARM/casts.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s ; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
define i16 @dsp_trunc(i32 %arg0, i32 %arg1, i16* %gep0, i16* %gep1) { define i16 @dsp_trunc(i32 %arg0, i32 %arg1, i16* %gep0, i16* %gep1) {
; CHECK-LABEL: @dsp_trunc( ; CHECK-LABEL: @dsp_trunc(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[ADD0:%.*]] = add i32 [[ARG0:%.*]], [[ARG1:%.*]] ; CHECK-NEXT: [[ADD0:%.*]] = add i32 [[ARG0:%.*]], [[ARG1:%.*]]
; CHECK-NEXT: [[CONV0:%.*]] = trunc i32 [[ADD0]] to i16 ; CHECK-NEXT: [[CONV0:%.*]] = trunc i32 [[ADD0]] to i16
; CHECK-NEXT: [[SUB0:%.*]] = sub i16 0, [[CONV0]] ; CHECK-NEXT: [[SUB0:%.*]] = sub i16 0, [[CONV0]]
; CHECK-NEXT: [[LOAD0:%.*]] = load i16, i16* [[GEP0:%.*]], align 2 ; CHECK-NEXT: [[LOAD0:%.*]] = load i16, i16* [[GEP0:%.*]], align 2
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llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s ; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
define i32 @clear_structures(i8* nocapture readonly %fmt, [1 x i32] %ap.coerce, i8* %out, void (i32, i8*)* nocapture %write) { define i32 @clear_structures(i8* nocapture readonly %fmt, [1 x i32] %ap.coerce, i8* %out, void (i32, i8*)* nocapture %write) {
; CHECK-LABEL: @clear_structures( ; CHECK-LABEL: @clear_structures(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[WHILE_COND_OUTER:%.*]] ; CHECK-NEXT: br label [[WHILE_COND_OUTER:%.*]]
; CHECK: while.cond.outer: ; CHECK: while.cond.outer:
; CHECK-NEXT: [[FMT_ADDR_0_PH:%.*]] = phi i8* [ [[FMT:%.*]], [[ENTRY:%.*]] ], [ [[FMT_ADDR_3:%.*]], [[WHILE_COND_OUTER_BACKEDGE:%.*]] ] ; CHECK-NEXT: [[FMT_ADDR_0_PH:%.*]] = phi i8* [ [[FMT:%.*]], [[ENTRY:%.*]] ], [ [[FMT_ADDR_3:%.*]], [[WHILE_COND_OUTER_BACKEDGE:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[FMT_ADDR_0_PH]], align 1 ; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[FMT_ADDR_0_PH]], align 1
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llvm/test/Transforms/TypePromotion/ARM/icmps.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s ; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
define i32 @test_ult_254_inc_imm(i8 zeroext %x) { define i32 @test_ult_254_inc_imm(i8 zeroext %x) {
; CHECK-LABEL: @test_ult_254_inc_imm( ; CHECK-LABEL: @test_ult_254_inc_imm(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[ADD:%.*]] = add i8 [[X:%.*]], 1 ; CHECK-NEXT: [[ADD:%.*]] = add i8 [[X:%.*]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[ADD]], -2 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[ADD]], -2
; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 35, i32 47 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 35, i32 47
; CHECK-NEXT: ret i32 [[RES]] ; CHECK-NEXT: ret i32 [[RES]]
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llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s ; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
; Check that the arguments are extended but then nothing else is. ; Check that the arguments are extended but then nothing else is.
; This also ensures that the pass can handle loops. ; This also ensures that the pass can handle loops.
define void @phi_feeding_phi_args(i8 %a, i8 %b) { define void @phi_feeding_phi_args(i8 %a, i8 %b) {
; CHECK-LABEL: @phi_feeding_phi_args( ; CHECK-LABEL: @phi_feeding_phi_args(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[A:%.*]] to i32 ; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[A:%.*]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[B:%.*]] to i32 ; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[B:%.*]] to i32
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llvm/test/Transforms/TypePromotion/ARM/pointers.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s ; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
define void @phi_pointers(i16* %a, i16* %b, i8 zeroext %M, i8 zeroext %N) { define void @phi_pointers(i16* %a, i16* %b, i8 zeroext %M, i8 zeroext %N) {
; CHECK-LABEL: @phi_pointers( ; CHECK-LABEL: @phi_pointers(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[M:%.*]] to i32 ; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[M:%.*]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[N:%.*]] to i32 ; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[N:%.*]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP0]], 1 ; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP0]], 1
; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], 1 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], 1
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llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s ; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
define i8 @eq_sgt(i8* %x, i8 *%y, i8 zeroext %z) { define i8 @eq_sgt(i8* %x, i8 *%y, i8 zeroext %z) {
; CHECK-LABEL: @eq_sgt( ; CHECK-LABEL: @eq_sgt(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOAD0:%.*]] = load i8, i8* [[X:%.*]], align 1 ; CHECK-NEXT: [[LOAD0:%.*]] = load i8, i8* [[X:%.*]], align 1
; CHECK-NEXT: [[LOAD1:%.*]] = load i8, i8* [[Y:%.*]], align 1 ; CHECK-NEXT: [[LOAD1:%.*]] = load i8, i8* [[Y:%.*]], align 1
; CHECK-NEXT: [[ADD:%.*]] = add i8 [[LOAD0]], [[Z:%.*]] ; CHECK-NEXT: [[ADD:%.*]] = add i8 [[LOAD0]], [[Z:%.*]]
; CHECK-NEXT: [[SUB:%.*]] = sub i8 [[LOAD1]], 1 ; CHECK-NEXT: [[SUB:%.*]] = sub i8 [[LOAD1]], 1
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llvm/test/Transforms/TypePromotion/ARM/signed.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s ; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends. ; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends.
define i16 @test_signed_load(i16* %ptr) { define i16 @test_signed_load(i16* %ptr) {
; CHECK-LABEL: @test_signed_load( ; CHECK-LABEL: @test_signed_load(
; CHECK-NEXT: [[LOAD:%.*]] = load i16, i16* [[PTR:%.*]] ; CHECK-NEXT: [[LOAD:%.*]] = load i16, i16* [[PTR:%.*]]
; CHECK-NEXT: [[CONV0:%.*]] = zext i16 [[LOAD]] to i32 ; CHECK-NEXT: [[CONV0:%.*]] = zext i16 [[LOAD]] to i32
; CHECK-NEXT: [[CONV1:%.*]] = sext i16 [[LOAD]] to i32 ; CHECK-NEXT: [[CONV1:%.*]] = sext i16 [[LOAD]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CONV0]], [[CONV1]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CONV0]], [[CONV1]]
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llvm/test/Transforms/TypePromotion/ARM/switch.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s ; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
define void @truncate_source_phi_switch(i8* %memblock, i8* %store, i16 %arg) { define void @truncate_source_phi_switch(i8* %memblock, i8* %store, i16 %arg) {
; CHECK-LABEL: @truncate_source_phi_switch( ; CHECK-LABEL: @truncate_source_phi_switch(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[PRE:%.*]] = load i8, i8* [[MEMBLOCK:%.*]], align 1 ; CHECK-NEXT: [[PRE:%.*]] = load i8, i8* [[MEMBLOCK:%.*]], align 1
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[PRE]] to i32 ; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[PRE]] to i32
; CHECK-NEXT: [[CONV:%.*]] = trunc i16 [[ARG:%.*]] to i8 ; CHECK-NEXT: [[CONV:%.*]] = trunc i16 [[ARG:%.*]] to i8
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[CONV]] to i32 ; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[CONV]] to i32
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llvm/test/Transforms/TypePromotion/ARM/wrapping.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s ; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
define zeroext i16 @overflow_add(i16 zeroext %a, i16 zeroext %b) { define zeroext i16 @overflow_add(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: @overflow_add( ; CHECK-LABEL: @overflow_add(
; CHECK-NEXT: [[ADD:%.*]] = add i16 [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[ADD:%.*]] = add i16 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = or i16 [[ADD]], 1 ; CHECK-NEXT: [[OR:%.*]] = or i16 [[ADD]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i16 [[OR]], 1024 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i16 [[OR]], 1024
; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i16 2, i16 5 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i16 2, i16 5
; CHECK-NEXT: ret i16 [[RES]] ; CHECK-NEXT: ret i16 [[RES]]
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