[ARM] Enable TypePromotion by default

[samparker]

Summary

ARMCodeGenPrepare has already been generalized and renamed to TypePromotion. We've had it enabled and tested downstream for a while, so now enable it by default upstream.

[SjoerdMeijer]

We've had this enabled by default for almost 1 year downstream now, which is a decent amount of time to shake out some codegen bugs. I agree that flipping the switch now make sense, and hopefully similar non-X86 targets enjoy decent performance improvements too.

[samparker]

@SjoerdMeijer I added some code before committing as an arm codegen test was failing and producing worse code with this patch. The new code checks whether the promotion should be beneficial.

llvm/lib/CodeGen/TypePromotion.cpp

 #include "llvm/Support/CommandLine.h"
 
 #define DEBUG_TYPE "type-promotion"
 #define PASS_NAME "Type Promotion"
 
 using namespace llvm;
 
 static cl::opt<bool>
-DisablePromotion("disable-type-promotion", cl::Hidden, cl::init(true),
+DisablePromotion("disable-type-promotion", cl::Hidden, cl::init(false),
                  cl::desc("Disable type promotion pass"));
 
 // The goal of this pass is to enable more efficient code generation for
 // operations on narrow types (i.e. types with < 32-bits) and this is a
 // motivating IR code example:
 //
 //   define hidden i32 @cmp(i8 zeroext) {
 //     %2 = add i8 %0, -49
if (isSource(V) || shouldPromote(V)) {
       }
     }
   }
 
   LLVM_DEBUG(dbgs() << "IR Promotion: Visited nodes:\n";
              for (auto *I : CurrentVisited)
                I->dump();
              );
+
+  // Check that promoting this at the IR level is most likely beneficial. It's
+  // more likely if we're operating over multiple blocks and handling wrapping
+  // instructions.
   unsigned ToPromote = 0;
+  unsigned NonFreeArgs = 0;
+  SmallPtrSet<BasicBlock*, 4> Blocks;
   for (auto *V : CurrentVisited) {
-    if (Sources.count(V))
+    if (auto *I = dyn_cast<Instruction>(V))
+      Blocks.insert(I->getParent());
+
+    if (Sources.count(V)) {
+      if (auto *Arg = dyn_cast<Argument>(V)) {
+        if (!Arg->hasZExtAttr() && !Arg->hasSExtAttr())
+          ++NonFreeArgs;
+      }
       continue;
+    }
+
     if (Sinks.count(cast<Instruction>(V)))
       continue;
+
     ++ToPromote;
   }
 
-  if (ToPromote < 2)
+  // DAG optimisations should be able to handle these cases better, especially
+  // for function arguments.
+  if (ToPromote < 2 || (Blocks.size() == 1 && (NonFreeArgs > SafeWrap.size())))
     return false;
 
   Promoter->Mutate(OrigTy, PromotedWidth, CurrentVisited, Sources, Sinks,
                    SafeToPromote, SafeWrap);
   return true;
 }
 
 bool TypePromotion::doInitialization(Module &M) {

llvm/test/Transforms/TypePromotion/ARM/calls.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
 
 define i8 @call_with_imms(i8* %arg) {
 ; CHECK-LABEL: @call_with_imms(
 ; CHECK-NEXT:    [[CALL:%.*]] = tail call arm_aapcs_vfpcc zeroext i8 @dummy2(i8* nonnull [[ARG:%.*]], i8 zeroext 0, i8 zeroext 0)
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[CALL]], 0
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i8 [[CALL]], i8 1
 ; CHECK-NEXT:    ret i8 [[RES]]
 ;

llvm/test/Transforms/TypePromotion/ARM/casts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
 
 define i16 @dsp_trunc(i32 %arg0, i32 %arg1, i16* %gep0, i16* %gep1) {
 ; CHECK-LABEL: @dsp_trunc(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[ADD0:%.*]] = add i32 [[ARG0:%.*]], [[ARG1:%.*]]
 ; CHECK-NEXT:    [[CONV0:%.*]] = trunc i32 [[ADD0]] to i16
 ; CHECK-NEXT:    [[SUB0:%.*]] = sub i16 0, [[CONV0]]
 ; CHECK-NEXT:    [[LOAD0:%.*]] = load i16, i16* [[GEP0:%.*]], align 2

llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
 
 define i32 @clear_structures(i8* nocapture readonly %fmt, [1 x i32] %ap.coerce, i8* %out, void (i32, i8*)* nocapture %write) {
 ; CHECK-LABEL: @clear_structures(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[WHILE_COND_OUTER:%.*]]
 ; CHECK:       while.cond.outer:
 ; CHECK-NEXT:    [[FMT_ADDR_0_PH:%.*]] = phi i8* [ [[FMT:%.*]], [[ENTRY:%.*]] ], [ [[FMT_ADDR_3:%.*]], [[WHILE_COND_OUTER_BACKEDGE:%.*]] ]
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[FMT_ADDR_0_PH]], align 1

llvm/test/Transforms/TypePromotion/ARM/icmps.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
 
 define i32 @test_ult_254_inc_imm(i8 zeroext %x) {
 ; CHECK-LABEL: @test_ult_254_inc_imm(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[X:%.*]], 1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[ADD]], -2
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 35, i32 47
 ; CHECK-NEXT:    ret i32 [[RES]]

llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
 
 ; Check that the arguments are extended but then nothing else is.
 ; This also ensures that the pass can handle loops.
 define void @phi_feeding_phi_args(i8 %a, i8 %b) {
 ; CHECK-LABEL: @phi_feeding_phi_args(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[B:%.*]] to i32

llvm/test/Transforms/TypePromotion/ARM/pointers.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
 
 define void @phi_pointers(i16* %a, i16* %b, i8 zeroext %M, i8 zeroext %N) {
 ; CHECK-LABEL: @phi_pointers(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[M:%.*]] to i32
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[N:%.*]] to i32
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw i32 [[TMP0]], 1
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ADD]], 1

llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
 
 define i8 @eq_sgt(i8* %x, i8 *%y, i8 zeroext %z) {
 ; CHECK-LABEL: @eq_sgt(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[LOAD0:%.*]] = load i8, i8* [[X:%.*]], align 1
 ; CHECK-NEXT:    [[LOAD1:%.*]] = load i8, i8* [[Y:%.*]], align 1
 ; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[LOAD0]], [[Z:%.*]]
 ; CHECK-NEXT:    [[SUB:%.*]] = sub i8 [[LOAD1]], 1

llvm/test/Transforms/TypePromotion/ARM/signed.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
 
 ; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends.
 define i16 @test_signed_load(i16* %ptr) {
 ; CHECK-LABEL: @test_signed_load(
 ; CHECK-NEXT:    [[LOAD:%.*]] = load i16, i16* [[PTR:%.*]]
 ; CHECK-NEXT:    [[CONV0:%.*]] = zext i16 [[LOAD]] to i32
 ; CHECK-NEXT:    [[CONV1:%.*]] = sext i16 [[LOAD]] to i32
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[CONV0]], [[CONV1]]

llvm/test/Transforms/TypePromotion/ARM/switch.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
 
 define void @truncate_source_phi_switch(i8* %memblock, i8* %store, i16 %arg) {
 ; CHECK-LABEL: @truncate_source_phi_switch(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[PRE:%.*]] = load i8, i8* [[MEMBLOCK:%.*]], align 1
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[PRE]] to i32
 ; CHECK-NEXT:    [[CONV:%.*]] = trunc i16 [[ARG:%.*]] to i8
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[CONV]] to i32

llvm/test/Transforms/TypePromotion/ARM/wrapping.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
 
 define zeroext i16 @overflow_add(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: @overflow_add(
 ; CHECK-NEXT:    [[ADD:%.*]] = add i16 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = or i16 [[ADD]], 1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i16 [[OR]], 1024
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i16 2, i16 5
 ; CHECK-NEXT:    ret i16 [[RES]]