[AArch64][SVE] Implement element count intrinsics

[c-rhodes]

Summary

Adds intrinsics for the following:

• cntb
• cnth
• cntw
• cntd
• cntp

[efriedma]

llvm/include/llvm/IR/IntrinsicsAArch64.td

937

What is LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> supposed to do here? Why not just LLVMMatchType?

llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll

11

No operand for the MUL immediate? I guess you could try to pattern-match it, but that seems less reliable.

[c-rhodes]

llvm/include/llvm/IR/IntrinsicsAArch64.td

937

Downstream CNTP/SADDV/UADDV share the same implementation, I agree reading the definition it's misleading (I would expect a type signature that looks like SADDV/UADDV). I'll change this to LLVMMatchType.

llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll

11

These intrinsics are a reflection of the ACLE intrinsics which don't expose the multiplier for two reasons I guess: 1) at the C and C++ level it's usually simpler to write the multiply out as normal, e.g. svcntw() * 3;, and 2) the compiler should be able to fold a suitable multiply in.

We have a separate patch downstream I'll follow up with to support this:

define i64 @cntb_mul3() {
; CHECK-LABEL: cntb_mul3:
; CHECK: cntb x0, vl6, mul #3
; CHECK-NEXT: ret
  %cnt = call i64 @llvm.aarch64.sve.cntb(i32 6)
  %out = mul i64 %cnt, 3
  ret i64 %out
}

[c-rhodes]

Use LLVMMatchType in CNTP intrinsic definition.

[efriedma]

LGTM

llvm/include/llvm/IR/IntrinsicsAArch64.td

: Intrinsic<[llvm_anyvector_ty],
                 [IntrNoMem]>;
 
   class AdvSIMD_SVE_TSMUL_Intrinsic
     : Intrinsic<[llvm_anyvector_ty],
                 [LLVMMatchType<0>,
                  LLVMVectorOfBitcastsToInt<0>],
                 [IntrNoMem]>;
 
+  class AdvSIMD_SVE_CNTB_Intrinsic
+    : Intrinsic<[llvm_i64_ty],
+                [llvm_i32_ty],
+                [IntrNoMem]>;
+
+  class AdvSIMD_SVE_CNTP_Intrinsic
+    : Intrinsic<[llvm_i64_ty],
+                [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+                 llvm_anyvector_ty],
+                [IntrNoMem]>;
+
   class AdvSIMD_SVE_DOT_Intrinsic
     : Intrinsic<[llvm_anyvector_ty],
                 [LLVMMatchType<0>,
                  LLVMSubdivide4VectorType<0>,
                  LLVMSubdivide4VectorType<0>],
                 [IntrNoMem]>;
 
   class AdvSIMD_SVE_DOT_Indexed_Intrinsic

 // Counting bits
 //
 
 def int_aarch64_sve_cls : AdvSIMD_Merged1VectorArg_Intrinsic;
 def int_aarch64_sve_clz : AdvSIMD_Merged1VectorArg_Intrinsic;
 def int_aarch64_sve_cnt : AdvSIMD_SVE_CNT_Intrinsic;
 
 //
+// Counting elements
+//
+
+def int_aarch64_sve_cntb : AdvSIMD_SVE_CNTB_Intrinsic;
+def int_aarch64_sve_cnth : AdvSIMD_SVE_CNTB_Intrinsic;
+def int_aarch64_sve_cntw : AdvSIMD_SVE_CNTB_Intrinsic;
+def int_aarch64_sve_cntd : AdvSIMD_SVE_CNTB_Intrinsic;
+
+def int_aarch64_sve_cntp : AdvSIMD_SVE_CNTP_Intrinsic;
+
+//
 // Permutations and selection
 //
 
 def int_aarch64_sve_sunpkhi   : AdvSIMD_SVE_Unpack_Intrinsic;
 def int_aarch64_sve_sunpklo   : AdvSIMD_SVE_Unpack_Intrinsic;
 
 def int_aarch64_sve_uunpkhi   : AdvSIMD_SVE_Unpack_Intrinsic;
 def int_aarch64_sve_uunpklo   : AdvSIMD_SVE_Unpack_Intrinsic;

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   def CTERMNE_WW : sve_int_cterm<0b0, 0b1, "ctermne", GPR32>;
   def CTERMEQ_XX : sve_int_cterm<0b1, 0b0, "ctermeq", GPR64>;
   def CTERMNE_XX : sve_int_cterm<0b1, 0b1, "ctermne", GPR64>;
 
   def RDVLI_XI  : sve_int_read_vl_a<0b0, 0b11111, "rdvl">;
   def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">;
   def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">;
 
-  defm CNTB_XPiI : sve_int_count<0b000, "cntb">;
-  defm CNTH_XPiI : sve_int_count<0b010, "cnth">;
-  defm CNTW_XPiI : sve_int_count<0b100, "cntw">;
-  defm CNTD_XPiI : sve_int_count<0b110, "cntd">;
-  defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp">;
+  defm CNTB_XPiI : sve_int_count<0b000, "cntb", int_aarch64_sve_cntb>;
+  defm CNTH_XPiI : sve_int_count<0b010, "cnth", int_aarch64_sve_cnth>;
+  defm CNTW_XPiI : sve_int_count<0b100, "cntw", int_aarch64_sve_cntw>;
+  defm CNTD_XPiI : sve_int_count<0b110, "cntd", int_aarch64_sve_cntd>;
+  defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp", int_aarch64_sve_cntp>;
 
   defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb">;
   defm DECB_XPiI : sve_int_pred_pattern_a<0b001, "decb">;
   defm INCH_XPiI : sve_int_pred_pattern_a<0b010, "inch">;
   defm DECH_XPiI : sve_int_pred_pattern_a<0b011, "dech">;
   defm INCW_XPiI : sve_int_pred_pattern_a<0b100, "incw">;
   defm DECW_XPiI : sve_int_pred_pattern_a<0b101, "decw">;
   defm INCD_XPiI : sve_int_pred_pattern_a<0b110, "incd">;

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn),
   let Inst{18-16} = opc{3-1};
   let Inst{15-14} = 0b10;
   let Inst{13-10} = Pg;
   let Inst{9}     = opc{0};
   let Inst{8-5}   = Pn;
   let Inst{4-0}   = Rd;
 }
 
-multiclass sve_int_pcount_pred<bits<4> opc, string asm> {
+multiclass sve_int_pcount_pred<bits<4> opc, string asm,
+                               SDPatternOperator int_op> {
   def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>;
   def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>;
   def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>;
   def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>;
+
+  def : SVE_2_Op_Pat<i64, int_op, nxv16i1, nxv16i1, !cast<Instruction>(NAME # _B)>;
+  def : SVE_2_Op_Pat<i64, int_op, nxv8i1,  nxv8i1,  !cast<Instruction>(NAME # _H)>;
+  def : SVE_2_Op_Pat<i64, int_op, nxv4i1,  nxv4i1,  !cast<Instruction>(NAME # _S)>;
+  def : SVE_2_Op_Pat<i64, int_op, nxv2i1,  nxv2i1,  !cast<Instruction>(NAME # _D)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Element Count Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_count<bits<3> opc, string asm>
 : I<(outs GPR64:$Rd), (ins sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
   asm, "\t$Rd, $pattern, mul $imm4",
   "",
   []>, Sched<[]> {
   bits<5> Rd;
   bits<4> imm4;
   bits<5> pattern;
   let Inst{31-24} = 0b00000100;
   let Inst{23-22} = opc{2-1};
   let Inst{21-20} = 0b10;
   let Inst{19-16} = imm4;
   let Inst{15-11} = 0b11100;
   let Inst{10}    = opc{0};
   let Inst{9-5}   = pattern;
   let Inst{4-0}   = Rd;
 }
 
-multiclass sve_int_count<bits<3> opc, string asm> {
+multiclass sve_int_count<bits<3> opc, string asm, SDPatternOperator op> {
   def NAME : sve_int_count<opc, asm>;
 
   def : InstAlias<asm # "\t$Rd, $pattern",
                   (!cast<Instruction>(NAME) GPR64:$Rd, sve_pred_enum:$pattern, 1), 1>;
   def : InstAlias<asm # "\t$Rd",
                   (!cast<Instruction>(NAME) GPR64:$Rd, 0b11111, 1), 2>;
+
+  def : Pat<(i64 (op sve_pred_enum:$pattern)),
+            (!cast<Instruction>(NAME) sve_pred_enum:$pattern, 1)>;
 }
 
 class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty>
 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
   asm, "\t$Zdn, $pattern, mul $imm4",
   "",
   []>, Sched<[]> {
   bits<5> Zdn;

llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll

+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+;
+; CNTB
+;
+
+define i64 @cntb() {
+; CHECK-LABEL: cntb:
+; CHECK: cntb x0, vl2
+; CHECK-NEXT: ret
+  %out = call i64 @llvm.aarch64.sve.cntb(i32 2)
+  ret i64 %out
+}
+
+;
+; CNTH
+;
+
+define i64 @cnth() {
+; CHECK-LABEL: cnth:
+; CHECK: cnth x0, vl3
+; CHECK-NEXT: ret
+  %out = call i64 @llvm.aarch64.sve.cnth(i32 3)
+  ret i64 %out
+}
+
+;
+; CNTW
+;
+
+define i64 @cntw() {
+; CHECK-LABEL: cntw:
+; CHECK: cntw x0, vl4
+; CHECK-NEXT: ret
+  %out = call i64 @llvm.aarch64.sve.cntw(i32 4)
+  ret i64 %out
+}
+
+;
+; CNTD
+;
+
+define i64 @cntd() {
+; CHECK-LABEL: cntd:
+; CHECK: cntd x0, vl5
+; CHECK-NEXT: ret
+  %out = call i64 @llvm.aarch64.sve.cntd(i32 5)
+  ret i64 %out
+}
+
+;
+; CNTP
+;
+
+define i64 @cntp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
+; CHECK-LABEL: cntp_b8:
+; CHECK: cntp x0, p0, p1.b
+; CHECK-NEXT: ret
+  %out = call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %pg,
+                                                 <vscale x 16 x i1> %a)
+  ret i64 %out
+}
+
+define i64 @cntp_b16(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a) {
+; CHECK-LABEL: cntp_b16:
+; CHECK: cntp x0, p0, p1.h
+; CHECK-NEXT: ret
+  %out = call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %pg,
+                                                <vscale x 8 x i1> %a)
+  ret i64 %out
+}
+
+define i64 @cntp_b32(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a) {
+; CHECK-LABEL: cntp_b32:
+; CHECK: cntp x0, p0, p1.s
+; CHECK-NEXT: ret
+  %out = call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %pg,
+                                                <vscale x 4 x i1> %a)
+  ret i64 %out
+}
+
+define i64 @cntp_b64(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a) {
+; CHECK-LABEL: cntp_b64:
+; CHECK: cntp x0, p0, p1.d
+; CHECK-NEXT: ret
+  %out = call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %pg,
+                                                <vscale x 2 x i1> %a)
+  ret i64 %out
+}
+
+declare i64 @llvm.aarch64.sve.cntb(i32 %pattern)
+declare i64 @llvm.aarch64.sve.cnth(i32 %pattern)
+declare i64 @llvm.aarch64.sve.cntw(i32 %pattern)
+declare i64 @llvm.aarch64.sve.cntd(i32 %pattern)
+
+declare i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
+declare i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
+declare i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
+declare i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)