[X86] Add initialization of MXCSR in llvm-exegesis

[pengfei]

Summary

This patch is used to initialize the new added register MXCSR.

[craig.topper]

I'm not sure I understand why this needs to be initialized. Why don't we need to do it for FPCW?

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

506

Isn't the default value of MXCSR 0x1f80 not 0x1f8?

[pengfei]

Fix typo.

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

506

Yes! I missed an 0. Thanks!

[pengfei]

I'm not sure I understand why this needs to be initialized. Why don't we need to do it for FPCW?

I'm sorry for not giving comments. Yes, we do need for FPCW if this is a reasonable approach. But I'm not sure if we need to explicatly initialize registers like MXCSR and FPCW or not either.
Can we just return a MCInstBuilder(X86::NOOP) for them to make the check pass (In Assembler.cpp L44, it judges the IsSnippetSetupComplete by checking if the return value is empty).

[courbet]

In D70874#1764446, @craig.topper wrote:

I'm not sure I understand why this needs to be initialized. Why don't we need to do it for FPCW?

We make sure that every register that is used by an instruction in the snippet is initialized. This is to avoid having fluctuations in measurements due to performance depending on values in registers. I think it's great if SSE/AVX instructions start explicitly state their deps on MXCSR, because the behaviour does indeed depend on the value of these flags.

Regarding whether masking instruction is the right thing to do: Yes for now, because this will ensure that these instructions will at least pass, but on the other hand that might not be perfectly representative of the real performance characteristics. AFAICT @gchatelet still wants to work on value constraints & exploration.

So this looks good to me if Craig has no other remarks.

[craig.topper]

LGTM

[pengfei]

We make sure that every register that is used by an instruction in the snippet is initialized. This is to avoid having fluctuations in measurements due to performance depending on values in registers. I think it's great if SSE/AVX instructions start explicitly state their deps on MXCSR, because the behaviour does indeed depend on the value of these flags.

Thanks for the explanation. Please note that currently we only state the rounding modes and the IEEE masks bits of MXCSR. This means instructions like VRSQRT14PS, which only have dependence on FTZ and DAZ, wouldn't be modeled.

[pengfei]

Please note that currently we only state the rounding modes and the IEEE masks bits of MXCSR. This means instructions like VRSQRT14PS, which only have dependence on FTZ and DAZ, wouldn't be modeled.

FTZ and DAZ are modeled now by commit rGc8995de06994. Thanks.

[gchatelet]

In D70874#1764713, @courbet wrote:

Regarding whether masking instruction is the right thing to do: Yes for now, because this will ensure that these instructions will at least pass, but on the other hand that might not be perfectly representative of the real performance characteristics. AFAICT @gchatelet still wants to work on value constraints & exploration.

Yes definitely. LGTM as well.

llvm/test/tools/llvm-exegesis/X86/uops-VFMADDSS4rm.s

 # RUN: llvm-exegesis -mode=uops -opcode-name=VFMADDSS4rm -repetition-mode=duplicate | FileCheck %s
 # RUN: llvm-exegesis -mode=uops -opcode-name=VFMADDSS4rm -repetition-mode=loop | FileCheck %s
 
 CHECK:      mode:            uops
 CHECK-NEXT: key:
 CHECK-NEXT:   instructions:
 CHECK-NEXT:     VFMADDSS4rm
+CHECK:      register_initial_values:
+# FIXME: This will be changed to CHECK by the following patch that modeling MXCSR to VFMADDSS.
+CHECK-NOT:      MXCSR

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

std::vector<MCInst> loadAndFinalize(unsigned Reg, unsigned RegBitWidth,
                                       unsigned Opcode);
 
   std::vector<MCInst> loadX87STAndFinalize(unsigned Reg);
 
   std::vector<MCInst> loadX87FPAndFinalize(unsigned Reg);
 
   std::vector<MCInst> popFlagAndFinalize();
 
+  std::vector<MCInst> loadMXCSRAndFinalize(bool HasAVX);
+
 private:
   ConstantInliner &add(const MCInst &Inst) {
     Instructions.push_back(Inst);
     return *this;
   }
 
   void initStack(unsigned Bytes);
 

 }
 
 std::vector<MCInst> ConstantInliner::popFlagAndFinalize() {
   initStack(8);
   add(MCInstBuilder(X86::POPF64));
   return std::move(Instructions);
 }
 
+std::vector<MCInst> ConstantInliner::loadMXCSRAndFinalize(bool HasAVX) {
+  add(allocateStackSpace(4));
+  add(fillStackSpace(X86::MOV32mi, 0, 0x1f80)); // Mask all FP exceptions
+  add(MCInstBuilder(HasAVX ? X86::VLDMXCSR : X86::LDMXCSR)
+          // Address = ESP
+          .addReg(X86::RSP) // BaseReg
+          .addImm(1)        // ScaleAmt
+          .addReg(0)        // IndexReg
+          .addImm(0)        // Disp
+          .addReg(0));      // Segment
+  return std::move(Instructions);
+}
+
 void ConstantInliner::initStack(unsigned Bytes) {
   assert(Constant_.getBitWidth() <= Bytes * 8 &&
          "Value does not have the correct size");
   const APInt WideConstant = Constant_.getBitWidth() < Bytes * 8
                                  ? Constant_.sext(Bytes * 8)
                                  : Constant_;
   add(allocateStackSpace(Bytes));
   size_t ByteOffset = 0;
if (X86::RSTRegClass.contains(Reg)) {
     return CI.loadX87STAndFinalize(Reg);
   }
   if (X86::RFP32RegClass.contains(Reg) || X86::RFP64RegClass.contains(Reg) ||
       X86::RFP80RegClass.contains(Reg)) {
     return CI.loadX87FPAndFinalize(Reg);
   }
   if (Reg == X86::EFLAGS)
     return CI.popFlagAndFinalize();
+  if (Reg == X86::MXCSR)
+    return CI.loadMXCSRAndFinalize(STI.getFeatureBits()[X86::FeatureAVX]);
   return {}; // Not yet implemented.
 }
 
 static ExegesisTarget *getTheExegesisX86Target() {
   static ExegesisX86Target Target;
   return &Target;
 }
 
 void InitializeX86ExegesisTarget() {
   ExegesisTarget::registerTarget(getTheExegesisX86Target());
 }
 
 } // namespace exegesis
 } // namespace llvm