created a test case to verify the raw text section of xcoffobject file

[DiggerLin]

Summary

in the patch https://reviews.llvm.org/D66969 . we need a test case to verify the out text section of the xcoffobject file is correct or not.

but we do not have llvm disassembly tools to dump the xcoffobjectfile . since we commit the patch https://reviews.llvm.org/D70255, we have tools for it. we create this test case for it.

[daltenty]

llvm/test/CodeGen/PowerPC/aix-xcoff-textdata.ll

1 ↗

(On Diff #231075)

If find the name of this file a little confusing. I'd prefer aix-xcoff-textdisasembly.ll or the like.

15 ↗

(On Diff #231075)

Out of curiosity why don't we see the .foo label? Binutils objdump appears to show it.

[DiggerLin]

llvm/test/CodeGen/PowerPC/aix-xcoff-textdata.ll

1 ↗

(On Diff #231075)

changed the test case name as your suggestion

15 ↗

(On Diff #231075)

this is disassembly, for the symbol .text and .foo has the same address, the llvm-objdump use the .text(first met symbol entry in the symbol table) as label of memory address 0.

[DiggerLin]

changed test case filename

[daltenty]

LGTM with minor nit

llvm/test/CodeGen/PowerPC/aix-xcoff-textdisasembly.ll

1

nit: s/disasembly/disassembly/ (two s), sorry it was wrong in my earlier comment

[hubert.reinterpretcast]

My understanding is that D66969 was also missing testing over the text section size and its effect on the BSS section's virtual address. Has that since been addressed?

[DiggerLin]

In D70719#1771640, @hubert.reinterpretcast wrote:

My understanding is that D66969 was also missing testing over the text section size and its effect on the BSS section's virtual address. Has that since been addressed?

yes, there is no test section size in this patch, I will create a new patch for it.

llvm/test/CodeGen/PowerPC/aix-xcoff-textdisasembly.ll

+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o  < %s 
+; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECK %s
+
+define i32 @foo() #0 {
+entry:
+  ret i32 0
+}
+
+define i32 @foo1() #0 {
+entry:
+  ret i32 1
+}
+
+; CHECK:     Disassembly of section .text:{{[[:space:]] *}}
+; CHECK-NEXT:     00000000 .text:
+; CHECK-NEXT:        0: 38 60 00 00                   li 3, 0
+; CHECK-NEXT:        4: 4e 80 00 20                   blr
+; CHECK-NEXT:        8: 60 00 00 00                   nop
+; CHECK-NEXT:        c: 60 00 00 00                   nop
+; CHECK:     00000010 .foo1:
+; CHECK-NEXT:       10: 38 60 00 01                   li 3, 1
+; CHECK-NEXT:       14: 4e 80 00 20                   blr