D65884 added a set of Arm IR intrinsics for the MVE VCTP instruction,
to use in tail predication. But the 64-bit one doesn't work properly:
its predicate type is <2 x i1> / v2i1, which isn't a legal MVE
type (due to not having a full set of instructions that manipulate it
usefully). The test of vctp64 in basic-tail-pred.ll goes through
opt fine, as the test expects, but if you then feed it to llc it
causes a type legality failure at isel time.
The usual workaround we've been using in the rest of the MVE
intrinsics family is to bodge v2i1 into v4i1. So I've adjusted the
vctp64 IR intrinsic to do that, and completely removed the code (and
test) that uses that intrinsic for 64-bit tail predication. That will
allow me to add isel rules (upcoming in D70485) that actually generate
the VCTP64 instruction.
Also renamed all four of these IR intrinsics so that they have mve
in the name, since its absence was confusing.