[AArch64] Add isAuthenticating predicate to MCInstDesc

[vsk]

Summary

Add a predicate to MCInstDesc that allows tools to determine whether an
instruction authenticates a pointer. This can be used by diagnostic
tools to hint at pointer authentication failures.

[kristof.beyls]

IIUC, I think "isAuthenticating" would be a more accurate description/name than "isAuthenticated".
In that the instruction on which this property is set does authenticate a pointer, rather than the instruction itself having been authenticated (whatever that may mean) before.
Does that seem fair?

[vsk]

Rename isAuthenticated -> isAuthenticating, for clarity.

[vsk]

Gentle ping.

[rjmccall]

This looks like it covers the right set of instructions, but I don't really know enough about backends to review, sorry.

[vsk]

Ping.

[tellenbach]

Hi! Does this cover pre v8.3 pointer authenticating instructions (AUTIASP/AUTIBSP) too?

[vsk]

Cover pre-8.3 auti*sp instructions.

[ab]

Seems reasonable. This is an interesting use of MCID flags, in that llvm itself doesn't need it, but I'm all for better disassembler support!

IIUC, I think "isAuthenticating" would be a more accurate description/name than "isAuthenticated".

FWIW, I actually find "isAuthenticated" more idiomatic, but I'm not enough of a native speaker to justify it ;)

Hi! Does this cover pre v8.3 pointer authenticating instructions (AUTIASP/AUTIBSP) too?

I don't think it makes sense to include AUT* on v8.3a, but it does on v8.6a, and shouldn't hurt elsewhere, so I'm fine with having them.

llvm/include/llvm/Target/Target.td

533

nit: one too many spaces between ';' and '//'

llvm/lib/Target/AArch64/AArch64InstrInfo.td

822

I suggest wrapping the AUT defs with let isAuthenticating = 1, this doesn't need a class.

llvm/include/llvm/MC/MCInstrDesc.h

enum Flag {
   ExtraDefRegAllocReq,
   RegSequence,
   ExtractSubreg,
   InsertSubreg,
   Convergent,
   Add,
   Trap,
   VariadicOpsAreDefs,
+  Authenticating,
 };
 }
 
 /// Describe properties that are true of each instruction in the target
 /// description file.  This captures information about side effects, register
 /// use and many other things.  There is one instance of this struct for each
 /// target instruction class, and the MachineInstr class points to this struct
 /// directly to describe itself.
public:
   /// additional values.
   bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
 
   /// Return true if variadic operands of this instruction are definitions.
   bool variadicOpsAreDefs() const {
     return Flags & (1ULL << MCID::VariadicOpsAreDefs);
   }
 
+  /// Return true if this instruction authenticates a pointer (e.g. LDRAx/BRAx
+  /// from ARMv8.3, which perform loads/branches with authentication).
+  ///
+  /// An authenticating instruction may fail in an ABI-defined manner when
+  /// operating on an invalid signed pointer.
+  bool isAuthenticating() const {
+    return Flags & (1ULL << MCID::Authenticating);
+  }
+
   //===--------------------------------------------------------------------===//
   // Side Effect Analysis
   //===--------------------------------------------------------------------===//
 
   /// Return true if this instruction could possibly read memory.
   /// Instructions with this flag set are not necessarily simple load
   /// instructions, they may load a value and modify it, for example.
   bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }

llvm/include/llvm/Target/Target.td

class Instruction : InstructionEncoding {
   bit isUnpredicable = 0;   // 1 means this instruction is not predicable
                             // even if it _does_ have a predicate operand
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomInserter = 0; // Pseudo instr needing special help.
   bit hasPostISelHook = 0;  // To be *adjusted* after isel by target hook.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?
   bit isConvergent = 0;     // Is this instruction convergent?
+  bit isAuthenticating = 0;  // Does this instruction authenticate a pointer?
   bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
   bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
   bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
   bit isRegSequence = 0;    // Is this instruction a kind of reg sequence?
                             // If so, make sure to override
                             // TargetInstrInfo::getRegSequenceLikeInputs.
   bit isPseudo     = 0;     // Is this instruction a pseudo-instruction?
                             // If so, won't have encoding information for

llvm/lib/Target/AArch64/AArch64InstrFormats.td

   bits<4> CRm;
   let CRm = 0b0011;
   let Inst{31-12} = 0b11010101000000110010;
   let Inst{11-8} = CRm;
   let Inst{7-5} = op2;
   let Inst{4-0} = 0b11111;
 }
 
+class SystemNoOperandsAuth<bits<3> op2, string asm, list<dag> pattern = []>
+    : SystemNoOperands<op2, asm, pattern> {
+  let isAuthenticating = 1;
+}
+
 // MRS/MSR system instructions. These have different operand classes because
 // a different subset of registers can be accessed through each instruction.
 def MRSSystemRegisterOperand : AsmOperandClass {
   let Name = "MRSSystemRegister";
   let ParserMethod = "tryParseSysReg";
   let DiagnosticType = "MRS";
 }
 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.

   let Inst{29-10} = 0b11100010111111110000;
   let Inst{9-5} = Rn;
   let Inst{4-0} = Rt;
 }
 
 class AuthBase<bits<1> M, dag oops, dag iops, string asm, string operands,
                list<dag> pattern>
   : I<oops, iops, asm, operands, "", pattern>, Sched<[]> {
+  let isAuthenticating = 1;
   let Inst{31-25} = 0b1101011;
   let Inst{20-11} = 0b1111100001;
   let Inst{10} = M;
   let Inst{4-0} = 0b11111;
 }
 
 class AuthBranchTwoOperands<bits<1> op, bits<1> M, string asm>
   : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {

 
 let mayLoad = 1 in
 class BaseAuthLoad<bit M, bit W, dag oops, dag iops, string asm,
                    string operands, string cstr, Operand opr>
   : I<oops, iops, asm, operands, cstr, []>, Sched<[]> {
   bits<10> offset;
   bits<5> Rn;
   bits<5> Rt;
+  let isAuthenticating = 1;
   let Inst{31-24} = 0b11111000;
   let Inst{23} = M;
   let Inst{22} = offset{9};
   let Inst{21} = 1;
   let Inst{20-12} = offset{8-0};
   let Inst{11} = W;
   let Inst{10} = 1;
   let Inst{9-5} = Rn;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 }
 
 // v8.3a Pointer Authentication
 // These instructions inhabit part of the hint space and so can be used for
 // armv8 targets
 let Uses = [LR], Defs = [LR] in {
   def PACIAZ   : SystemNoOperands<0b000, "paciaz">;
   def PACIBZ   : SystemNoOperands<0b010, "pacibz">;
-  def AUTIAZ   : SystemNoOperands<0b100, "autiaz">;
-  def AUTIBZ   : SystemNoOperands<0b110, "autibz">;
+  def AUTIAZ   : SystemNoOperandsAuth<0b100, "autiaz">;
+  def AUTIBZ   : SystemNoOperandsAuth<0b110, "autibz">;
 }
 let Uses = [LR, SP], Defs = [LR] in {
   def PACIASP  : SystemNoOperands<0b001, "paciasp">;
   def PACIBSP  : SystemNoOperands<0b011, "pacibsp">;
-  def AUTIASP  : SystemNoOperands<0b101, "autiasp">;
-  def AUTIBSP  : SystemNoOperands<0b111, "autibsp">;
+  def AUTIASP  : SystemNoOperandsAuth<0b101, "autiasp">;
+  def AUTIBSP  : SystemNoOperandsAuth<0b111, "autibsp">;
 }
 let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in {
   def PACIA1716  : SystemNoOperands<0b000, "pacia1716">;
   def PACIB1716  : SystemNoOperands<0b010, "pacib1716">;
-  def AUTIA1716  : SystemNoOperands<0b100, "autia1716">;
-  def AUTIB1716  : SystemNoOperands<0b110, "autib1716">;
+  def AUTIA1716  : SystemNoOperandsAuth<0b100, "autia1716">;
+  def AUTIB1716  : SystemNoOperandsAuth<0b110, "autib1716">;
 }
 
 let Uses = [LR], Defs = [LR], CRm = 0b0000 in {
   def XPACLRI   : SystemNoOperands<0b111, "xpaclri">;
 }
 
 // These pointer authentication isntructions require armv8.3a
 let Predicates = [HasPA] in {

llvm/unittests/Target/AArch64/InstSizes.cpp

void runChecks(
   ASSERT_TRUE(F != nullptr);
   auto &MF = MMI.getOrCreateMachineFunction(*F);
 
   Checks(*II, MF);
 }
 
 } // anonymous namespace
 
+TEST(InstSizes, Authenticated) {
+  std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
+  ASSERT_TRUE(TM);
+  std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
+
+  auto isAuthInst = [](AArch64InstrInfo &II, MachineFunction &MF) {
+    auto I = MF.begin()->begin();
+    EXPECT_EQ(4u, II.getInstSizeInBytes(*I));
+    EXPECT_TRUE(I->getDesc().isAuthenticating());
+  };
+
+  runChecks(TM.get(), II.get(), "",
+            "    \n"
+            "    BLRAA $x10, $x9\n",
+            isAuthInst);
+
+  runChecks(TM.get(), II.get(), "",
+            "    \n"
+            "    RETAB implicit $lr, implicit $sp, implicit killed $x0\n",
+            isAuthInst);
+
+  runChecks(TM.get(), II.get(), "",
+            "    \n"
+            "    frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp\n",
+            isAuthInst);
+
+  runChecks(TM.get(), II.get(), "",
+            "    \n"
+            "    frame-destroy AUTIBSP implicit-def $lr, implicit killed $lr, implicit $sp\n",
+            isAuthInst);
+}
+
 TEST(InstSizes, STACKMAP) {
   std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
   ASSERT_TRUE(TM);
   std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
 
   runChecks(TM.get(), II.get(), "", "    STACKMAP 0, 16\n"
                                     "    STACKMAP 1, 32\n",
             [](AArch64InstrInfo &II, MachineFunction &MF) {

llvm/utils/TableGen/CodeGenInstruction.h

public:
     bool isExtractSubreg : 1;
     bool isInsertSubreg : 1;
     bool isConvergent : 1;
     bool hasNoSchedulingInfo : 1;
     bool FastISelShouldIgnore : 1;
     bool hasChain : 1;
     bool hasChain_Inferred : 1;
     bool variadicOpsAreDefs : 1;
+    bool isAuthenticating : 1;
 
     std::string DeprecatedReason;
     bool HasComplexDeprecationPredicate;
 
     /// Are there any undefined flags?
     bool hasUndefFlags() const {
       return mayLoad_Unset || mayStore_Unset || hasSideEffects_Unset;
     }

llvm/utils/TableGen/CodeGenInstruction.cpp

CodeGenInstruction::CodeGenInstruction(Record *R)
   isNotDuplicable = R->getValueAsBit("isNotDuplicable");
   isRegSequence = R->getValueAsBit("isRegSequence");
   isExtractSubreg = R->getValueAsBit("isExtractSubreg");
   isInsertSubreg = R->getValueAsBit("isInsertSubreg");
   isConvergent = R->getValueAsBit("isConvergent");
   hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
   FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
   variadicOpsAreDefs = R->getValueAsBit("variadicOpsAreDefs");
+  isAuthenticating = R->getValueAsBit("isAuthenticating");
 
   bool Unset;
   mayLoad      = R->getValueAsBitOrUnset("mayLoad", Unset);
   mayLoad_Unset = Unset;
   mayStore     = R->getValueAsBitOrUnset("mayStore", Unset);
   mayStore_Unset = Unset;
   mayRaiseFPException = R->getValueAsBit("mayRaiseFPException");
   hasSideEffects = R->getValueAsBitOrUnset("hasSideEffects", Unset);

llvm/utils/TableGen/InstrDocsEmitter.cpp

#define FLAG(f) if (II->f) { FlagStrings.push_back(str(f)); }
     FLAG(isCodeGenOnly)
     FLAG(isPseudo)
     FLAG(isRegSequence)
     FLAG(isExtractSubreg)
     FLAG(isInsertSubreg)
     FLAG(isConvergent)
     FLAG(hasNoSchedulingInfo)
     FLAG(variadicOpsAreDefs)
+    FLAG(isAuthenticating)
     if (!FlagStrings.empty()) {
       OS << "Flags: ";
       bool IsFirst = true;
       for (auto FlagString : FlagStrings) {
         if (!IsFirst)
           OS << ", ";
         OS << "``" << FlagString << "``";
         IsFirst = false;

llvm/utils/TableGen/InstrInfoEmitter.cpp

if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
     OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
   if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
     OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
   if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
   if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
   if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
   if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
   if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
+  if (Inst.isAuthenticating) OS << "|(1ULL<<MCID::Authenticating)";
 
   // Emit all of the target-specific flags...
   BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
   if (!TSF)
     PrintFatalError(Inst.TheDef->getLoc(), "no TSFlags?");
   uint64_t Value = 0;
   for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
     if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i)))