[mips][test] Add Mips CPU tests

[mstojanovic]

Summary

Adding tests check all available CPUs on Mips.

[atanasyan]

• I suggest to join both test cases into the single one
• Let's check more then empty stderr in case of success. For example, we can generate an object file, run llvm-readelf -A and check ISA: and ISA Extension: lines. Something like this:

; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64R3
; MIPS64R3: ISA: MIPS64r3

; RUN: llc -mtriple=mips64 -mcpu=octeon -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=OCTEON
; OCTEON: ISA: MIPS64r2
; OCTEON: ISA Extension: Cavium Networks Octeon

[mstojanovic]

Merged and expanded the test.

Do you think the tests from D70018 should also be in the same file or is it fine how it is?

[atanasyan]

In D70017#1742283, @mstojanovic wrote:

Do you think the tests from D70018 should also be in the same file or is it fine how it is?

Both patches now looks good. Thanks. I will commit them today or tomorrow.

[mstojanovic]

Thanks for the review. I forgot to mention that I've gotten commit access in meantime so I'll be able to commit future patches.

llvm/test/CodeGen/Mips/cpus.ll

+; Test that the CPU names work.
+
+; RUN: llc -mtriple=mips -mcpu=mips2 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS2
+; MIPS2: ISA: MIPS2
+; RUN: llc -mtriple=mips64 -mcpu=mips3 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS3
+; MIPS3: ISA: MIPS3
+; RUN: llc -mtriple=mips64 -mcpu=mips4 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS4
+; MIPS4: ISA: MIPS4
+
+; RUN: llc -mtriple=mips -mcpu=mips32 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS32
+; MIPS32: ISA: MIPS32
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS32R2
+; MIPS32R2: ISA: MIPS32r2
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS32R3
+; MIPS32R3: ISA: MIPS32r3
+; RUN: llc -mtriple=mips -mcpu=mips32r5 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS32R5
+; MIPS32R5: ISA: MIPS32r5
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS32R6
+; MIPS32R6: ISA: MIPS32r6
+
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64
+; MIPS64: ISA: MIPS64
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64R2
+; MIPS64R2: ISA: MIPS64r2
+; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64R3
+; MIPS64R3: ISA: MIPS64r3
+; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64R5
+; MIPS64R5: ISA: MIPS64r5
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64R6
+; MIPS64R6: ISA: MIPS64r6
+
+; RUN: llc -mtriple=mips64 -mcpu=octeon -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=OCTEON
+; OCTEON: ISA: MIPS64r2
+; OCTEON: ISA Extension: Cavium Networks Octeon
+; RUN: llc -mtriple=mips64 -mcpu=octeon+ -filetype=obj < %s | llvm-readelf -A | FileCheck %s --check-prefix=OCTEONP
+; OCTEONP: ISA: MIPS64r2
+; OCTEONP: ISA Extension: Cavium Networks OcteonP
+
+; Check that we reject CPUs that are not implemented.
+; CHECK-ERROR-NOT-IMPLEMENTED: LLVM ERROR: Code generation for MIPS-{{.}} is not implemented
+
+; RUN: not llc < %s -o /dev/null -mtriple=mips -mcpu=mips1 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR-NOT-IMPLEMENTED
+; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips5 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR-NOT-IMPLEMENTED
+
+define void @foo() {
+  ret void
+}