saa and saad are 32-bit and 64-bit store atomic add instructions.
memory[base] = memory[base] + rt
These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+".
Next patches will implement .set arch=octeon+ directive and AFL_EXT_OCTEONP ISA extension flag support.