[AMDGPU] Clean up update_llc_test_checks CodeGen tests

[scott.linder]

Summary

Some tests have been hand edited without removing the
update_llc_test_checks header, some have slightly outdated CHECK lines
which still pass, and some have additional comments which
update_llc_test_checks pushes towards the function body.

[thakis]

This broke a test on Windows: http://45.33.8.238/win/1083/step_10.txt

FAIL: LLVM :: CodeGen/AMDGPU/split-arg-dbg-value.ll (8621 of 34117)
******************** TEST 'LLVM :: CodeGen/AMDGPU/split-arg-dbg-value.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   c:\src\llvm-project\out\gn\bin\llc.exe -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < C:\src\llvm-project\llvm\test\CodeGen\AMDGPU\split-arg-dbg-value.ll | c:\src\llvm-project\out\gn\bin\filecheck.exe -check-prefix=GCN C:\src\llvm-project\llvm\test\CodeGen\AMDGPU\split-arg-dbg-value.ll
--
Exit Code: 1

Command Output (stdout):
--
$ ":" "RUN: at line 2"
$ "c:\src\llvm-project\out\gn\bin\llc.exe" "-mtriple=amdgcn-amd-amdhsa" "-mcpu=gfx900"
$ "c:\src\llvm-project\out\gn\bin\filecheck.exe" "-check-prefix=GCN" "C:\src\llvm-project\llvm\test\CodeGen\AMDGPU\split-arg-dbg-value.ll"
# command stderr:
C:\src\llvm-project\llvm\test\CodeGen\AMDGPU\split-arg-dbg-value.ll:8:13: error: GCN-NEXT: expected string not found in input
; GCN-NEXT: .file 0 "/tmp/dbg.cl" md5 0x0f834f91e91489a5ff6308040ddbd175
            ^
<stdin>:9:2: note: scanning from here
 .file 0 "/Users/matt/src/llvm/tmp/dbg.cl" md5 0x0f834f91e91489a5ff6308040ddbd175
 ^
<stdin>:9:24: note: possible intended match here
 .file 0 "/Users/matt/src/llvm/tmp/dbg.cl" md5 0x0f834f91e91489a5ff6308040ddbd175
                       ^

error: command failed with exit status: 1

Sadly the Windows bots on LLVM's real build waterfall are still pulling svn and haven't cycled since the github switch, but I'm almost certain that they'd see the same problem if they would cycle.

Can you take a look?

[scott.linder]

Yes, I can post a patch, I didn't consider the path at all. I think the test just can't use update_llc_test_checks.

[scott.linder]

Should be fixed in 7ad3636c30a

[thakis]

Thanks! That helped :)

llvm/test/CodeGen/AMDGPU/fexp.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;RUN: llc -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
 ;RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
 ;RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s
 
 define float @v_exp_f32(float %arg0) {
 ; SI-LABEL: v_exp_f32:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

llvm/test/CodeGen/AMDGPU/load-lo16.ll

 ; GFX906-NEXT:    global_store_dword v[0:1], v0, off
 ; GFX906-NEXT:    s_waitcnt vmcnt(0)
 ; GFX906-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX803-LABEL: load_flat_lo_v2f16_reghi_vreg:
 ; GFX803:       ; %bb.0: ; %entry
 ; GFX803-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX803-NEXT:    flat_load_ushort v0, v[0:1]
-; FIXME: and should be removable
 ; GFX803-NEXT:    v_and_b32_e32 v1, 0xffff0000, v2
 ; GFX803-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX803-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX803-NEXT:    flat_store_dword v[0:1], v0
 ; GFX803-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX803-NEXT:    s_setpc_b64 s[30:31]
+
+; FIXME: the and above should be removable
 entry:
   %reg.bc = bitcast i32 %reg to <2 x half>
   %load = load half, half* %in
   %build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
   store <2 x half> %build1, <2 x half> addrspace(1)* undef
   ret void
 }
 

llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
 ; Make sure dbg_value reports something for argument registers when they are split into multiple registers
 
 define hidden <4 x float> @split_v4f32_arg(<4 x float> returned %arg) local_unnamed_addr #0 !dbg !7 {
 ; GCN-LABEL: split_v4f32_arg:
 ; GCN:       .Lfunc_begin0:
-; GCN-NEXT:    .file 0
+; GCN-NEXT:    .file 0 "/tmp/dbg.cl" md5 0x0f834f91e91489a5ff6308040ddbd175
 ; GCN-NEXT:    .loc 0 3 0 ; /tmp/dbg.cl:3:0
 ; GCN-NEXT:  ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:  .Ltmp0:
 ; GCN-NEXT:    ;DEBUG_VALUE: split_v4f32_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 96 32] $vgpr3
 ; GCN-NEXT:    ;DEBUG_VALUE: split_v4f32_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 64 32] $vgpr2
 ; GCN-NEXT:    ;DEBUG_VALUE: split_v4f32_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 32 32] $vgpr1
 ; GCN-NEXT:    ;DEBUG_VALUE: split_v4f32_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 0 32] $vgpr0

llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900  < %s | FileCheck -check-prefix=GFX9 %s
 
 ; Make sure the stack is never realigned for entry functions.
 
 define amdgpu_kernel void @max_alignment_128() #0 {
 ; VI-LABEL: max_alignment_128:
 ; VI:       ; %bb.0:

llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mcpu=tahiti -amdgpu-dce-in-ra=0 -o - %s | FileCheck %s
 ; Don't crash when the use of an undefined value is only detected by the
 ; register coalescer because it is hidden with subregister insert/extract.
 target triple="amdgcn--"
 
 define amdgpu_kernel void @foobar(float %a0, float %a1, float addrspace(1)* %out) nounwind {
 ; CHECK-LABEL: foobar:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
 ; CHECK-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, -1, 0
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; CHECK-NEXT:    s_mov_b32 s2, -1
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
-
-; FIXME: The change related to the fact that
-; DetectDeadLanes pass hit "Copy across incompatible class" SGPR -> VGPR in analysis
-; and hence it cannot derive the fact that the vector element is unused.
-; Such a copies appear because the float4 vectors and their elements in the test are uniform
-; but the PHI node in "ife" block is divergent because of the CF dependency (divergent branch in bb0)
-
 ; CHECK-NEXT:    v_mov_b32_e32 v0, s4
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v2, s6
 ; CHECK-NEXT:    v_mov_b32_e32 v3, s7
-
 ; CHECK-NEXT:    s_and_saveexec_b64 s[6:7], vcc
 ; CHECK-NEXT:    ; mask branch BB0_2
 ; CHECK-NEXT:  BB0_1: ; %ift
 ; CHECK-NEXT:    s_mov_b32 s4, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, s4
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v2, s6
 ; CHECK-NEXT:    v_mov_b32_e32 v3, s7
 ; CHECK-NEXT:  BB0_2: ; %ife
 ; CHECK-NEXT:    s_or_b64 exec, exec, s[6:7]
 ; CHECK-NEXT:    s_mov_b32 s3, 0xf000
 ; CHECK-NEXT:    buffer_store_dword v1, off, s[0:3], 0
 ; CHECK-NEXT:    s_endpgm
+
+; FIXME: The change related to the fact that
+; DetectDeadLanes pass hit "Copy across incompatible class" SGPR -> VGPR in analysis
+; and hence it cannot derive the fact that the vector element in the "ift" block is unused.
+; Such a copies appear because the float4 vectors and their elements in the test are uniform
+; but the PHI node in "ife" block is divergent because of the CF dependency (divergent branch in bb0)
 entry:
   %v0 = insertelement <4 x float> undef, float %a0, i32 0
   %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
   %cnd = icmp eq i32 %tid, 0
   br i1 %cnd, label %ift, label %ife
 
 ift:
   %v1 = insertelement <4 x float> undef, float %a1, i32 0