[PowerPC] Spill CR LT bits on P9 using setb

[amyk]

Summary

This patch aims to spill CR[0-1]LT bits on POWER9 using the setb instruction.
The sequence on P9 to spill these bits will be:

setb %reg, %CRREG
stw %reg, $FI

Instead of the typical sequence:

mfocrf %reg, %CRREG
rlwinm %reg1, %reg, $SH, 0, 0
stw %reg1, $FI

The number of mfocrf instructions within SPEC 2017 decreases by ~2.6%.

[amyk]

Ping.

[NeHuang]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

792

nit: alignment. Two less space before "if"

799

nit: alignment. same as line 783.

[kamaub]

Looks good to me, just a note about the summary:

spill CR[0-1]LT bits on POWER9 using the setb instruction

I think you changed the spill for all fields' LT bit as per the if statement so, this might be due for a change.

llvm/test/CodeGen/PowerPC/spill_p9_setb.ll

2

nit: Add a note to describe this test case's purpose

[nemanjai]

LGTM aside from a couple of minor nits that can be addressed on the commit.

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

790

I think this would benefit from a slightly more elaborate explanation. Perhaps:

// On Power9, we can use SETB to extract the LT bit. This only works for
// the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
// of the bit we care about (32-bit sign bit) will be set to the value of
// the LT bit (regardless of the other bits in the CR field).

llvm/test/CodeGen/PowerPC/spill_p9_setb.ll

13

Rather than explicitly checking for the new sequence and not the old sequence, please just add a RUN line to this test case that will use -mcpu=pwr8 and produce the checks with the script.

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

case PPC::CRUNSET:
     SpillsKnownBit = true;
     break;
   case PPC::CRSET:
     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
       .addImm(-32768);
     SpillsKnownBit = true;
     break;
   default:
+    // On Power9, we can use SETB to extract the LT bit. This only works for
+    // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
+    // of the bit we care about (32-bit sign bit) will be set to the value of
+    // the LT bit (regardless of the other bits in the CR field).
+    if (Subtarget.isISA3_0()) {
+      if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT ||
+          SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT ||
+          SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
+          SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
+        BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg)
+          .addReg(getCRFromCRBit(SrcReg), RegState::Undef);
+        break;
+      }
+    }
+
     // We need to move the CR field that contains the CR bit we are spilling.
     // The super register may not be explicitly defined (i.e. it can be defined
     // by a CR-logical that only defines the subreg) so we state that the CR
     // field is undef. Also, in order to preserve the kill flag on the CR bit,
     // we add it as an implicit use.
     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
       .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
       .addReg(SrcReg,

llvm/test/CodeGen/PowerPC/spill_p9_setb.ll

+; NOTE: This test case aims to test the sequence of spilling the CR[0-7]LT bits
+; NOTE: on POWER9 using the setb instruction.
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \
+; RUN:     | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \
+; RUN:     | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \
+; RUN:     | FileCheck %s --check-prefix=CHECK-P8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \
+; RUN:     | FileCheck %s --check-prefix=CHECK-P8
+
+define void @p9_setb_spill() {
+; CHECK-P9-LABEL: p9_setb_spill:
+; CHECK-P9:       # %bb.1: # %if.then
+; CHECK-P9-DAG:    crnor 4*cr[[CREG:.*]]+lt, eq, eq
+; CHECK-P9-DAG:    setb [[REG1:.*]], cr[[CREG]]
+; CHECK-P9-DAG:    stw [[REG1]]
+; CHECK-P9:        blr
+; CHECK-P9:        .LBB0_4: # %if.then1
+;
+; CHECK-P8-LABEL: p9_setb_spill:
+; CHECK-P8:       # %bb.1: # %if.then
+; CHECK-P8-DAG:    crnor 4*cr[[CREG2:.*]]+lt, eq, eq
+; CHECK-P8-DAG:    mfocrf [[REG2:.*]],
+; CHECK-P8-DAG:    rlwinm [[REG2]], [[REG2]]
+; CHECK-P8-DAG:    stw [[REG2]]
+; CHECK-P8:        blr
+; CHECK-P8:        .LBB0_4: # %if.then1
+entry:
+  br i1 undef, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  %call = tail call signext i32 bitcast (i32 (...)* @fn_call to i32 ()*)()
+  %cmp1 = icmp ne i32 %call, 0
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  %off0 = phi i1 [ %cmp1, %if.then ], [ false, %entry ]
+  tail call void asm sideeffect "#Clobber", "~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}"()
+  %off0.not = xor i1 %off0, true
+  %or = or i1 false, %off0.not
+  br i1 %or, label %if.end2, label %if.then1
+
+if.then1:                                         ; preds = %if.end
+  unreachable
+
+if.end2:                                         ; preds = %if.end
+  ret void
+}
+
+declare signext i32 @fn_call(...)