Add support for intrinsics llvm.ppc.dcbfl and llvm.ppc.dcbflp

[anil9]

Summary

Added support for the intrinsic llvm.ppc.dcbfl and llvm.ppc.dcbflp. These will be used for emitting cache control instructions dcbfl and dcbflp which are actually mnemonics for using dcbf instruction with different immediate arguments.

dcbfl ra, rb -> dcbf ra, rb, 1
dcbflp, ra, rb -> dcbf ra, rb, 3

[lei]

Since these are just mnemonics for using dcbf, why not just add the tests to llvm/test/CodeGen/PowerPC/dcbf.ll instead of creating 2 small test files.

[anil9]

In D68411#1718116, @lei wrote:

Since these are just mnemonics for using dcbf, why not just add the tests to llvm/test/CodeGen/PowerPC/dcbf.ll instead of creating 2 small test files.

These are mnemonics true, but we have separate intrinsics for them as opposed to using one intrinsic with different constants and also the assembly code is different.
I think having multiple files gives more structure and in theory reduces chances of merge conflicts.

[nemanjai]

In D68411#1722968, @anil9 wrote:

In D68411#1718116, @lei wrote:

Since these are just mnemonics for using dcbf, why not just add the tests to llvm/test/CodeGen/PowerPC/dcbf.ll instead of creating 2 small test files.

These are mnemonics true, but we have separate intrinsics for them as opposed to using one intrinsic with different constants and also the assembly code is different.
I think having multiple files gives more structure and in theory reduces chances of merge conflicts.

I second Lei's suggestion to combine the test cases. As lightweight as LIT test cases are, there are already nearly 60k of them and there is a non-zero cost to running additional ones. So if there is no compelling reason to add multiple test cases, we should opt to combine them. And I don't see a compelling reason to separate these.

[anil9]

Integrated the test cases dcbfl.ll and dcbflp.ll in the previous differential to the previously existing test case dcbf.ll

[nemanjai]

LGTM other than a minor nit that can be addressed on the commit.

llvm/test/CodeGen/PowerPC/dcbf.ll

32 ↗

(On Diff #236628)

Perhaps change one of the calls to include an offset to ensure we are correctly materializing the immediate.

[nemanjai]

Forgot to accept.

[anil9]

Added an offset to a pointer in one of the tests, for added coverage.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

 //
 
 // Non-altivec intrinsics.
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   // dcba/dcbf/dcbi/dcbst/dcbt/dcbz/dcbzl(PPC970) instructions.
   def int_ppc_dcba  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbf  : GCCBuiltin<"__builtin_dcbf">,
                       Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbfl : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbflp: Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbi  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbt  : Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<0>]>;
   def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<0>]>;
   def int_ppc_dcbz  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
 def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
 def DCBTSTT  : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
 
 def DCBFx  : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>;
 def DCBFL  : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
 def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
 
+def : Pat<(int_ppc_dcbfl xoaddr:$dst),
+          (DCBFL xoaddr:$dst)>;
+def : Pat<(int_ppc_dcbflp xoaddr:$dst),
+          (DCBFLP xoaddr:$dst)>;
+
 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
 
 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
 

llvm/test/CodeGen/PowerPC/dcbfl.ll

+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr | FileCheck %s
+
+; Function Attrs: nounwind
+define void @dcbfl_test(i8* %a) {
+entry:
+  tail call void @llvm.ppc.dcbfl(i8* %a)
+; CHECK-LABEL: @dcbfl_test
+; CHECK: dcbfl 0, r3
+; CHECK-NEXT: blr
+ret void
+}
+
+declare void @llvm.ppc.dcbfl(i8*)

llvm/test/CodeGen/PowerPC/dcbflp.ll

+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr | FileCheck %s
+
+; Function Attrs: nounwind
+define void @dcbflp_test(i8* %a) {
+entry:
+  tail call void @llvm.ppc.dcbflp(i8* %a)
+; CHECK-LABEL: @dcbflp_test
+; CHECK: dcbflp 0, r3
+; CHECK-NEXT: blr
+ret void
+}
+
+declare void @llvm.ppc.dcbflp(i8*)