[SDAG] Peek through bitcasts before commuting setcc operands

[pengfei]

Summary

This patch fix a bug result from D63958.

On X86 32 bit, BUILD_VECTOR <2 x i64> will be broke into a combine of BUILD_VECTOR <4 x i32> and bitcast. So we should peek through it, otherwise it may fall into dead loop in some cases. e.g.

1 define <2 x i64> @test(<2 x i64> %a) {
2   %1 = sub <2 x i64> zeroinitializer, %a
3   %2 = icmp eq <2 x i64> %a, zeroinitializer
4   %3 = select <2 x i1> %2, <2 x i64> %a, <2 x i64> %1
5   ret <2 x i64> %3
6 }

llc -mtriple=i686 -matttr=+avx512f -mattr=avx512vl t.ll

[xbolva00]

Please add a testcase

[pengfei]

Add testcase. Thanks @xbolva00

[craig.topper]

I've removed the canonicalization in LowerIntVSETCC_AVX512 that was causing this in r372543. And I've moved it to X86ISelDAGToDAG in r372544. At the time LowerIntVSETCC_AVX512 we were using isel patterns for vptest and this was an attempt reduce the size of the table. We're now using custom isel in X86ISelDAGToDAG so the canonicalization is much cheaper to handle there.

[pengfei]

Craig had fixed this issue using a better solution. Abandoned.

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (isConstOrConstSplat(N0) &&
       (DCI.isBeforeLegalizeOps() ||
        isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
     return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
 
   // If we have a subtract with the same 2 non-constant operands as this setcc
   // -- but in reverse order -- then try to commute the operands of this setcc
   // to match. A matching pair of setcc (cmp) and sub may be combined into 1
   // instruction on some targets.
-  if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) &&
+  if (!isConstOrConstSplat(peekThroughBitcasts(N0)) &&
+      !isConstOrConstSplat(peekThroughBitcasts(N1)) &&
       (DCI.isBeforeLegalizeOps() ||
        isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) &&
       DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) &&
       !DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N0, N1 } ))
     return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
 
   if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
     const APInt &C1 = N1C->getAPIntValue();

llvm/test/CodeGen/X86/i686-setcc-commute.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686 -mattr=+avx512f -mattr=avx512vl | FileCheck %s
+
+define <2 x i64> @test(<2 x i64> %a) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT:    vpsubq %xmm0, %xmm1, %xmm1
+; CHECK-NEXT:    vptestnmq %xmm0, %xmm0, %k1
+; CHECK-NEXT:    vmovdqa64 %xmm0, %xmm1 {%k1}
+; CHECK-NEXT:    vmovdqa %xmm1, %xmm0
+; CHECK-NEXT:    retl
+  %1 = sub <2 x i64> zeroinitializer, %a
+  %2 = icmp eq <2 x i64> %a, zeroinitializer
+  %3 = select <2 x i1> %2, <2 x i64> %a, <2 x i64> %1
+  ret <2 x i64> %3
+}