[AMDGPU] Allow FP inline constant in v_madak_f16 and v_fmaak_f16

[tpr]

Summary

Change-Id: Ic38f47cb2079c2c1070a441b5943854844d80a7c

[arsenm]

LGTM. Can you also add a test for the mad case

[tpr]

In D67680#1673252, @arsenm wrote:

LGTM. Can you also add a test for the mad case

Thanks; will do.

lib/Target/AMDGPU/VOP2Instructions.td

multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {
   }
   let WaveSizePredicate = isWave64 in {
     def : VOP2eInstAlias<ps, inst, "vcc">;
   }
 }
 
 class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
   field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
-  field dag Ins32 = (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm);
+  field dag Ins32 = !if(!eq(vt.Size, 32),
+                        (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm),
+                        (ins VCSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm));
   field bit HasExt = 0;
 
   // Hack to stop printing _e64
   let DstRC = RegisterOperand<VGPR_32>;
   field string Asm32 = " $vdst, $src0, $src1, $imm";
 }
 
 def VOP_MADAK_F16 : VOP_MADAK <f16>;

test/CodeGen/AMDGPU/twoaddr-fma.mir

- { id: 0, name: "", type: default, offset: 0, size: 128, alignment: 8,
       debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
 
     %0 = V_MOV_B32_e32 1078523331, implicit $exec
     %1 = V_FMAC_F32_e32 %stack.0, %0, %2, implicit $exec
 
 ...
+
+# GCN-LABEL: name: test_fmaak_inline_literal_f16
+# GCN: %2:vgpr_32 = V_FMAAK_F16 16384, killed %0, 49664, implicit $exec
+
+---
+name:            test_fmaak_inline_literal_f16
+liveins:
+  - { reg: '$vgpr0', virtual-reg: '%3' }
+body:             |
+  bb.0:
+    liveins: $vgpr0
+  
+    %3:vgpr_32 = COPY killed $vgpr0
+
+    %26:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec
+    %28:vgpr_32 = V_FMAC_F16_e32 16384, killed %3, %26, implicit $exec
+    S_ENDPGM 0
+
+...
+