I believe all of the uniform/divergent pattern predicates are
redundant and can be removed. The uniformity bit already influences
the register class, and nothhing has broken when I've removed this and
As you remove the "!isDiverent" predicate, I'd like to see the test that ensures that V_MIN/MAX etc are not selected for uniform smin/smax/umin/umax IR operations. The test should check not GlobalIsel but current instruction selection case.
Yes. We have min.ll, max.ll and sminmax.ll
Formally, guarding both VALU and SALU variants with same predicate looks extensive.
Nevertheless, I'd like to have clean test base until we remove odd predicates.
The patterns are rejected for having custom predicate code. We don't need it as a standard pattern checks the register banks, which is what we really want. I think the cleanest compatibility solution would be to use divergence to guide register class selection, and somehow add the equivalent checks in the DAG patterns. Defining the equivalent GlobalISel pattern as always true would probably work, although leave a lot of clutter in the matching tables