[PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC register class.

[craig.topper]

Summary

Since the SPE4RC register class contains an identical set of registers
and an identical spill size to the GPRC class its slightly confusing
the tablegen emitter. It's preventing the GPRC_and_GPRC_NOR0 synthesized
register class from inheriting VTs and AltOrders from GPRC or GPRC_NOR0.
This is because SPE4C is found first in the super register class list
when inheriting these properties and it doesn't set the VTs or
AltOrders the same way as GPRC or GPRC_NOR0.

This patch replaces all uses of GPE4RC with GPRC and allows GPRC and
GPRC_NOR0 to contain f32.

The test changes here are because the AltOrders are being inherited
to GPRC_NOR0 now.

Found while trying to determine if getCommonSubClass needs to take
a VT argument. It was originally added to support fp128 on x86-64,
I've changed some things about that so that it might be needed
anymore. But a PowerPC test crashed without it and I think its
due to this subclass issue.

[jhibbits]

Thanks for getting rid of SPE4RC, I really did not like it, but couldn't think of a better way. Glad you did.

It looks like you're changing more than just removing SPE4RC in this diff. Do the tests really change because of the removal?

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

2457

Is this an extra change? Doesn't look to be needed for the SPE4RC removal.

[craig.topper]

In D67513#1668369, @jhibbits wrote:

Thanks for getting rid of SPE4RC, I really did not like it, but couldn't think of a better way. Glad you did.

It looks like you're changing more than just removing SPE4RC in this diff. Do the tests really change because of the removal?

Test changes are because the GPRC_GPRC_NOR0 register class was being inferred by tablegen, but was not inheriting the AltOrder from GPRC/GPRC_NOR0. Now its inherited and this causes R2 to be at the end of the allocation order list. This caused different registers to be used and removed the spill and restore of R2.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

2457

This is related to the removal of SOK_SPE4Spill which caused SOK_LastOpcodeSpill to become one less so the entry in the array needed to be removed.

[jhibbits]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

2457

Not entirely. The Power 9 block was not updated when SPE was added, only the Power 8 block was. Your removal on the Power 9 blocks, in both load and store cases, is unnecessary, and would likely break things. The only ones that should be removed are PPC::SPE*.

[craig.topper]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

2457

My mistake. I naively assumed the arrays were the same size without checking. I forgot that C++ would assume 0 for the unmentioned elements. But give a warning for the array being too large which it did for the Power8 array.

[craig.topper]

Remove bad change

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
 
 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   return decodeRegisterClass(Inst, RegNo, QFRegs);
 }
 
-static DecodeStatus DecodeSPE4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
-                                            uint64_t Address,
-                                            const void *Decoder) {
-  return decodeRegisterClass(Inst, RegNo, RRegs);
-}
-
 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SPERegs);
 }
 
 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass

llvm/lib/Target/PowerPC/PPCFastISel.cpp

bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
   // case we must make a conservative guess.  In particular, don't assign
   // R0 or X0 to the result register, as the result may be used in a load,
   // store, add-immediate, or isel that won't permit this.  (Though
   // perhaps the spill and reload of live-exit values would handle this?)
   const TargetRegisterClass *UseRC =
     (ResultReg ? MRI.getRegClass(ResultReg) :
      (RC ? RC :
       (VT == MVT::f64 ? (HasSPE ? &PPC::SPERCRegClass : &PPC::F8RCRegClass) :
-       (VT == MVT::f32 ? (HasSPE ? &PPC::SPE4RCRegClass : &PPC::F4RCRegClass) :
+       (VT == MVT::f32 ? (HasSPE ? &PPC::GPRCRegClass : &PPC::F4RCRegClass) :
         (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
          &PPC::GPRC_and_GPRC_NOR0RegClass)))));
 
   bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
 
   switch (VT.SimpleTy) {
     default: // e.g., vector types not handled
       return false;
bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
   unsigned SrcReg = getRegForValue(Src);
   if (!SrcReg)
     return false;
 
   // Round the result to single precision.
   unsigned DestReg;
   auto RC = MRI.getRegClass(SrcReg);
   if (PPCSubTarget->hasSPE()) {
-    DestReg = createResultReg(&PPC::SPE4RCRegClass);
+    DestReg = createResultReg(&PPC::GPRCRegClass);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
       TII.get(PPC::EFSCFD), DestReg)
       .addReg(SrcReg);
   } else if (isVSFRCRegClass(RC)) {
     DestReg = createResultReg(&PPC::VSSRCRegClass);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
       TII.get(PPC::XSRSP), DestReg)
       .addReg(SrcReg);
bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
   // entirely within FPRs or VSRs.
   unsigned DestReg;
   unsigned Opc;
   auto RC = MRI.getRegClass(SrcReg);
 
   if (PPCSubTarget->hasSPE()) {
     DestReg = createResultReg(&PPC::GPRCRegClass);
     if (IsSigned)
-      Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
+      Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
     else
-      Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
+      Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
   } else if (isVSFRCRegClass(RC)) {
     DestReg = createResultReg(&PPC::VSFRCRegClass);
     if (DstVT == MVT::i32) 
       Opc = IsSigned ? PPC::XSCVDPSXWS : PPC::XSCVDPUXWS;
     else
       Opc = IsSigned ? PPC::XSCVDPSXDS : PPC::XSCVDPUXDS;
   } else {
     DestReg = createResultReg(&PPC::F8RCRegClass);
unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
 
   // All FP constants are loaded from the constant pool.
   unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
   assert(Align > 0 && "Unexpectedly missing alignment information!");
   unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
   const bool HasSPE = PPCSubTarget->hasSPE();
   const TargetRegisterClass *RC;
   if (HasSPE)
-    RC = ((VT == MVT::f32) ? &PPC::SPE4RCRegClass : &PPC::SPERCRegClass);
+    RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass);
   else
     RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
 
   unsigned DestReg = createResultReg(RC);
   CodeModel::Model CModel = TM.getCodeModel();
 
   MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
       MachinePointerInfo::getConstantPool(*FuncInfo.MF),

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
   SmallVector<CalleeSavedInfo, 18> FPRegs;
   SmallVector<CalleeSavedInfo, 18> VRegs;
 
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     unsigned Reg = CSI[i].getReg();
     assert((!MF.getInfo<PPCFunctionInfo>()->mustSaveTOC() ||
             (Reg != PPC::X2 && Reg != PPC::R2)) &&
            "Not expecting to try to spill R2 in a function that must save TOC");
-    if (PPC::GPRCRegClass.contains(Reg) ||
-        PPC::SPE4RCRegClass.contains(Reg)) {
+    if (PPC::GPRCRegClass.contains(Reg)) {
       HasGPSaveArea = true;
 
       GPRegs.push_back(CSI[i]);
 
       if (Reg < MinGPR) {
         MinGPR = Reg;
       }
     } else if (PPC::G8RCRegClass.contains(Reg)) {

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
   // arguments are at least 4/8 bytes aligned.
   bool isPPC64 = Subtarget.isPPC64();
   setMinStackArgumentAlignment(isPPC64 ? llvm::Align(8) : llvm::Align(4));
 
   // Set up the register classes.
   addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
   if (!useSoftFloat()) {
     if (hasSPE()) {
-      addRegisterClass(MVT::f32, &PPC::SPE4RCRegClass);
+      addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
       addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
     } else {
       addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
       addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
     }
   }
 
   // Match BITREVERSE to customized fast code sequence in the td file.
if (VA.isRegLoc()) {
         case MVT::i1:
         case MVT::i32:
           RC = &PPC::GPRCRegClass;
           break;
         case MVT::f32:
           if (Subtarget.hasP8Vector())
             RC = &PPC::VSSRCRegClass;
           else if (Subtarget.hasSPE())
-            RC = &PPC::SPE4RCRegClass;
+            RC = &PPC::GPRCRegClass;
           else
             RC = &PPC::F4RCRegClass;
           break;
         case MVT::f64:
           if (Subtarget.hasVSX())
             RC = &PPC::VSFRCRegClass;
           else if (Subtarget.hasSPE())
             // SPE passes doubles in GPR pairs.
case 'r':   // R0-R31
       return std::make_pair(0U, &PPC::GPRCRegClass);
     // 'd' and 'f' constraints are both defined to be "the floating point
     // registers", where one is for 32-bit and the other for 64-bit. We don't
     // really care overly much here so just give them all the same reg classes.
     case 'd':
     case 'f':
       if (Subtarget.hasSPE()) {
         if (VT == MVT::f32 || VT == MVT::i32)
-          return std::make_pair(0U, &PPC::SPE4RCRegClass);
+          return std::make_pair(0U, &PPC::GPRCRegClass);
         if (VT == MVT::f64 || VT == MVT::i64)
           return std::make_pair(0U, &PPC::SPERCRegClass);
       } else {
         if (VT == MVT::f32 || VT == MVT::i32)
           return std::make_pair(0U, &PPC::F4RCRegClass);
         if (VT == MVT::f64 || VT == MVT::i64)
           return std::make_pair(0U, &PPC::F8RCRegClass);
         if (VT == MVT::v4f64 && Subtarget.hasQPX())

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

enum SpillOpcodeKey {
   SOK_VectorFloat8Spill,
   SOK_VectorFloat4Spill,
   SOK_VRSaveSpill,
   SOK_QuadFloat8Spill,
   SOK_QuadFloat4Spill,
   SOK_QuadBitSpill,
   SOK_SpillToVSR,
   SOK_SPESpill,
-  SOK_SPE4Spill,
   SOK_LastOpcodeSpill  // This must be last on the enum.
 };
 
 // Pin the vtable to this file.
 void PPCInstrInfo::anchor() {}
 
 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
     : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
              PPC::G8RCRegClass.contains(DestReg)) {
     assert(Subtarget.hasDirectMove() &&
            "Subtarget doesn't support directmove, don't know how to copy.");
     BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
     getKillRegState(KillSrc);
     return;
   } else if (PPC::SPERCRegClass.contains(SrcReg) &&
-             PPC::SPE4RCRegClass.contains(DestReg)) {
+             PPC::GPRCRegClass.contains(DestReg)) {
     BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
     getKillRegState(KillSrc);
     return;
-  } else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
+  } else if (PPC::GPRCRegClass.contains(SrcReg) &&
              PPC::SPERCRegClass.contains(DestReg)) {
     BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
     getKillRegState(KillSrc);
     return;
   }
 
   unsigned Opc;
   if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::QVFMR;
   else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::QVFMRs;
   else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::QVFMRb;
   else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::CROR;
-  else if (PPC::SPE4RCRegClass.contains(DestReg, SrcReg))
-    Opc = PPC::OR;
   else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::EVOR;
   else
     llvm_unreachable("Impossible reg-to-reg copy");
 
   const MCInstrDesc &MCID = get(Opc);
   if (MCID.getNumOperands() == 3)
     BuildMI(MBB, I, DL, MCID, DestReg)
if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
                PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_Int8Spill;
     } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_Float8Spill;
     } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_Float4Spill;
     } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_SPESpill;
-    } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
-      OpcodeIndex = SOK_SPE4Spill;
     } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_CRSpill;
     } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_CRBitSpill;
     } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_VRVectorSpill;
     } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_VSXVectorSpill;
if (PPC::GPRCRegClass.contains(Reg) ||
                PPC::G8RC_NOX0RegClass.contains(Reg)) {
       OpcodeIndex = SOK_Int8Spill;
     } else if (PPC::F8RCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_Float8Spill;
     } else if (PPC::F4RCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_Float4Spill;
     } else if (PPC::SPERCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_SPESpill;
-    } else if (PPC::SPE4RCRegClass.contains(Reg)) {
-      OpcodeIndex = SOK_SPE4Spill;
     } else if (PPC::CRRCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_CRSpill;
     } else if (PPC::CRBITRCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_CRBitSpill;
     } else if (PPC::VRRCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_VRVectorSpill;
     } else if (PPC::VSRCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_VSXVectorSpill;
if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
                PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_Int8Spill;
     } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_Float8Spill;
     } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_Float4Spill;
     } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_SPESpill;
-    } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
-      OpcodeIndex = SOK_SPE4Spill;
     } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_CRSpill;
     } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_CRBitSpill;
     } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_VRVectorSpill;
     } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
       OpcodeIndex = SOK_VSXVectorSpill;
if (PPC::GPRCRegClass.contains(Reg) ||
                PPC::G8RC_NOX0RegClass.contains(Reg)) {
       OpcodeIndex = SOK_Int8Spill;
     } else if (PPC::F8RCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_Float8Spill;
     } else if (PPC::F4RCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_Float4Spill;
     } else if (PPC::SPERCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_SPESpill;
-    } else if (PPC::SPE4RCRegClass.contains(Reg)) {
-      OpcodeIndex = SOK_SPE4Spill;
     } else if (PPC::CRRCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_CRSpill;
     } else if (PPC::CRBITRCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_CRBitSpill;
     } else if (PPC::VRRCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_VRVectorSpill;
     } else if (PPC::VSRCRegClass.contains(Reg)) {
       OpcodeIndex = SOK_VSXVectorSpill;

 }
 
 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
   static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
       // Power 8
       {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
        PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
        PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
-       PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
+       PPC::SPILLTOVSR_ST, PPC::EVSTDD},
       // Power 9
       {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
        PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
        PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
        PPC::SPILLTOVSR_ST}};
 
   return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
 }
 
 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
   static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
       // Power 8
       {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
        PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
        PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
-       PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
+       PPC::SPILLTOVSR_LD, PPC::EVLDD},
       // Power 9
       {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
        PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
        PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
        PPC::SPILLTOVSR_LD}};
 
   return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
 }
 
 void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,
                                      unsigned RegNo) const {
   const MachineRegisterInfo &MRI =
       StartMI.getParent()->getParent()->getRegInfo();

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def PPCRegSPERCAsmOperand : AsmOperandClass {
   let Name = "RegSPERC"; let PredicateMethod = "isRegNumber";
 }
 def sperc : RegisterOperand<SPERC> {
   let ParserMatchClass = PPCRegSPERCAsmOperand;
 }
 def PPCRegSPE4RCAsmOperand : AsmOperandClass {
   let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber";
 }
-def spe4rc : RegisterOperand<SPE4RC> {
+def spe4rc : RegisterOperand<GPRC> {
   let ParserMatchClass = PPCRegSPE4RCAsmOperand;
 }
 
 def PPCU1ImmAsmOperand : AsmOperandClass {
   let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
   let RenderMethod = "addImmOperands";
 }
 def u1imm   : Operand<i32> {

 // amounts.
 def : Pat<(sra i32:$rS, i32:$rB),
           (SRAW $rS, $rB)>;
 def : Pat<(srl i32:$rS, i32:$rB),
           (SRW $rS, $rB)>;
 def : Pat<(shl i32:$rS, i32:$rB),
           (SLW $rS, $rB)>;
 
-def : Pat<(zextloadi1 iaddr:$src),
+def : Pat<(i32 (zextloadi1 iaddr:$src)),
           (LBZ iaddr:$src)>;
-def : Pat<(zextloadi1 xaddr:$src),
+def : Pat<(i32 (zextloadi1 xaddr:$src)),
           (LBZX xaddr:$src)>;
-def : Pat<(extloadi1 iaddr:$src),
+def : Pat<(i32 (extloadi1 iaddr:$src)),
           (LBZ iaddr:$src)>;
-def : Pat<(extloadi1 xaddr:$src),
+def : Pat<(i32 (extloadi1 xaddr:$src)),
           (LBZX xaddr:$src)>;
-def : Pat<(extloadi8 iaddr:$src),
+def : Pat<(i32 (extloadi8 iaddr:$src)),
           (LBZ iaddr:$src)>;
-def : Pat<(extloadi8 xaddr:$src),
+def : Pat<(i32 (extloadi8 xaddr:$src)),
           (LBZX xaddr:$src)>;
-def : Pat<(extloadi16 iaddr:$src),
+def : Pat<(i32 (extloadi16 iaddr:$src)),
           (LHZ iaddr:$src)>;
-def : Pat<(extloadi16 xaddr:$src),
+def : Pat<(i32 (extloadi16 xaddr:$src)),
           (LHZX xaddr:$src)>;
 let Predicates = [HasFPU] in {
 def : Pat<(f64 (extloadf32 iaddr:$src)),
           (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
 def : Pat<(f64 (extloadf32 xaddr:$src)),
           (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
 
 def : Pat<(f64 (fpextend f32:$src)),

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
   const unsigned DefaultSafety = 1;
 
   switch (RC->getID()) {
   default:
     return 0;
   case PPC::G8RC_NOX0RegClassID:
   case PPC::GPRC_NOR0RegClassID:
   case PPC::SPERCRegClassID:
-  case PPC::SPE4RCRegClassID:
   case PPC::G8RCRegClassID:
   case PPC::GPRCRegClassID: {
     unsigned FP = TFI->hasFP(MF) ? 1 : 0;
     return 32 - FP - DefaultSafety;
   }
   case PPC::F8RCRegClassID:
   case PPC::F4RCRegClassID:
   case PPC::QFRCRegClassID:

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

 // most registers, it has to be done in code; to make this work all the
 // return and call instructions are described as Uses of RM, so instructions
 // that do nothing but change RM will not get deleted.
 def RM: PPCReg<"**ROUNDING MODE**">;
 
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
+def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
                                                     (sequence "R%u", 30, 13),
                                                     R31, R0, R1, FP, BP)> {
   // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
   // put it at the end of the list.
   let AltOrders = [(add (sub GPRC, R2), R2)];
   let AltOrderSelect = [{
     return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
   }];
 }
 
 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
                                                 (sequence "X%u", 30, 14),
                                                 X31, X13, X0, X1, FP8, BP8)> {
   // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
   // put it at the end of the list.
   let AltOrders = [(add (sub G8RC, X2), X2)];
   let AltOrderSelect = [{
     return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
   }];
 }
 
 // For some instructions r0 is special (representing the value 0 instead of
 // the value in the r0 register), and we use these register subclasses to
 // prevent r0 from being allocated for use by those instructions.
-def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)> {
+def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
   // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
   // put it at the end of the list.
   let AltOrders = [(add (sub GPRC_NOR0, R2), R2)];
   let AltOrderSelect = [{
     return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
   }];
 }
 
 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
   // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
   // put it at the end of the list.
   let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
   let AltOrderSelect = [{
     return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
   }];
 }
 
 def SPERC : RegisterClass<"PPC", [f64], 64, (add (sequence "S%u", 2, 12),
                                                 (sequence "S%u", 30, 13),
                                                 S31, S0, S1)>;
 
-def SPE4RC : RegisterClass<"PPC", [f32], 32, (add GPRC)>;
-
 // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
 // ABI the size of the Floating-point register save area is determined by the
 // allocated non-volatile register with the lowest register number, as FP
 // register N is spilled to offset 8 * (32 - N) below the back chain word of the
 // previous stack frame. By allocating non-volatiles in reverse order we make
 // sure that the Floating-point register save area is always as small as
 // possible because there aren't any unused spill slots.
 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),

llvm/test/CodeGen/PowerPC/inc-of-add.ll

 ; PPC64BE:       # %bb.0:
 ; PPC64BE-NEXT:    std 21, -88(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    lbz 21, 207(1)
 ; PPC64BE-NEXT:    lbz 11, 199(1)
 ; PPC64BE-NEXT:    lbz 12, 191(1)
 ; PPC64BE-NEXT:    std 23, -72(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 22, -80(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 26, -48(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 2, -96(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 25, -56(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 24, -64(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 29, -24(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 30, -16(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    lbz 0, 183(1)
 ; PPC64BE-NEXT:    add 6, 21, 6
 ; PPC64BE-NEXT:    lbz 21, 231(1)
 ; PPC64BE-NEXT:    add 5, 11, 5
 ; PPC64BE-NEXT:    lbz 11, 223(1)
 ; PPC64BE-NEXT:    add 4, 12, 4
 ; PPC64BE-NEXT:    lbz 12, 215(1)
 ; PPC64BE-NEXT:    lbz 23, 127(1)
 ; PPC64BE-NEXT:    add 9, 21, 9
 ; PPC64BE-NEXT:    lbz 21, 255(1)
 ; PPC64BE-NEXT:    lbz 22, 119(1)
 ; PPC64BE-NEXT:    add 8, 11, 8
 ; PPC64BE-NEXT:    lbz 11, 247(1)
 ; PPC64BE-NEXT:    add 7, 12, 7
 ; PPC64BE-NEXT:    lbz 12, 239(1)
 ; PPC64BE-NEXT:    lbz 26, 151(1)
-; PPC64BE-NEXT:    add 2, 21, 23
-; PPC64BE-NEXT:    lbz 23, 279(1)
+; PPC64BE-NEXT:    add 23, 21, 23
+; PPC64BE-NEXT:    lbz 21, 279(1)
 ; PPC64BE-NEXT:    lbz 25, 143(1)
 ; PPC64BE-NEXT:    add 11, 11, 22
 ; PPC64BE-NEXT:    lbz 22, 271(1)
 ; PPC64BE-NEXT:    lbz 24, 135(1)
 ; PPC64BE-NEXT:    add 10, 12, 10
 ; PPC64BE-NEXT:    lbz 12, 263(1)
 ; PPC64BE-NEXT:    lbz 30, 175(1)
 ; PPC64BE-NEXT:    lbz 29, 303(1)
-; PPC64BE-NEXT:    add 26, 23, 26
-; PPC64BE-NEXT:    lbz 23, 311(1)
+; PPC64BE-NEXT:    add 26, 21, 26
+; PPC64BE-NEXT:    lbz 21, 311(1)
 ; PPC64BE-NEXT:    std 28, -32(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    add 25, 22, 25
 ; PPC64BE-NEXT:    lbz 28, 167(1)
 ; PPC64BE-NEXT:    lbz 22, 295(1)
 ; PPC64BE-NEXT:    std 27, -40(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    add 12, 12, 24
 ; PPC64BE-NEXT:    lbz 27, 159(1)
 ; PPC64BE-NEXT:    lbz 24, 287(1)
 ; PPC64BE-NEXT:    add 30, 29, 30
-; PPC64BE-NEXT:    add 29, 23, 0
+; PPC64BE-NEXT:    add 29, 21, 0
 ; PPC64BE-NEXT:    addi 0, 29, 1
 ; PPC64BE-NEXT:    add 28, 22, 28
 ; PPC64BE-NEXT:    stb 0, 15(3)
 ; PPC64BE-NEXT:    addi 0, 30, 1
 ; PPC64BE-NEXT:    add 27, 24, 27
 ; PPC64BE-NEXT:    stb 0, 14(3)
 ; PPC64BE-NEXT:    addi 0, 28, 1
 ; PPC64BE-NEXT:    stb 0, 13(3)
 ; PPC64BE-NEXT:    addi 0, 27, 1
 ; PPC64BE-NEXT:    stb 0, 12(3)
 ; PPC64BE-NEXT:    addi 0, 26, 1
 ; PPC64BE-NEXT:    addi 12, 12, 1
 ; PPC64BE-NEXT:    stb 0, 11(3)
 ; PPC64BE-NEXT:    addi 0, 25, 1
 ; PPC64BE-NEXT:    stb 12, 9(3)
-; PPC64BE-NEXT:    addi 12, 2, 1
+; PPC64BE-NEXT:    addi 12, 23, 1
 ; PPC64BE-NEXT:    addi 11, 11, 1
 ; PPC64BE-NEXT:    addi 10, 10, 1
 ; PPC64BE-NEXT:    addi 9, 9, 1
 ; PPC64BE-NEXT:    addi 8, 8, 1
 ; PPC64BE-NEXT:    addi 7, 7, 1
 ; PPC64BE-NEXT:    addi 6, 6, 1
 ; PPC64BE-NEXT:    addi 5, 5, 1
 ; PPC64BE-NEXT:    addi 4, 4, 1
 ; PPC64BE-NEXT:    stb 0, 10(3)
 ; PPC64BE-NEXT:    stb 12, 8(3)
 ; PPC64BE-NEXT:    stb 11, 7(3)
 ; PPC64BE-NEXT:    stb 10, 6(3)
 ; PPC64BE-NEXT:    stb 9, 5(3)
 ; PPC64BE-NEXT:    stb 8, 4(3)
 ; PPC64BE-NEXT:    stb 7, 3(3)
 ; PPC64BE-NEXT:    stb 6, 2(3)
 ; PPC64BE-NEXT:    stb 5, 1(3)
 ; PPC64BE-NEXT:    stb 4, 0(3)
-; PPC64BE-NEXT:    ld 2, -96(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 27, -40(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 26, -48(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 25, -56(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 24, -64(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 23, -72(1) # 8-byte Folded Reload

llvm/test/CodeGen/PowerPC/sub-of-not.ll

 ; PPC64BE:       # %bb.0:
 ; PPC64BE-NEXT:    std 21, -88(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    lbz 21, 207(1)
 ; PPC64BE-NEXT:    lbz 11, 199(1)
 ; PPC64BE-NEXT:    lbz 12, 191(1)
 ; PPC64BE-NEXT:    std 23, -72(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 22, -80(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 26, -48(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 2, -96(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 25, -56(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 24, -64(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 29, -24(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    std 30, -16(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    lbz 0, 183(1)
 ; PPC64BE-NEXT:    add 6, 21, 6
 ; PPC64BE-NEXT:    lbz 21, 231(1)
 ; PPC64BE-NEXT:    add 5, 11, 5
 ; PPC64BE-NEXT:    lbz 11, 223(1)
 ; PPC64BE-NEXT:    add 4, 12, 4
 ; PPC64BE-NEXT:    lbz 12, 215(1)
 ; PPC64BE-NEXT:    lbz 23, 127(1)
 ; PPC64BE-NEXT:    add 9, 21, 9
 ; PPC64BE-NEXT:    lbz 21, 255(1)
 ; PPC64BE-NEXT:    lbz 22, 119(1)
 ; PPC64BE-NEXT:    add 8, 11, 8
 ; PPC64BE-NEXT:    lbz 11, 247(1)
 ; PPC64BE-NEXT:    add 7, 12, 7
 ; PPC64BE-NEXT:    lbz 12, 239(1)
 ; PPC64BE-NEXT:    lbz 26, 151(1)
-; PPC64BE-NEXT:    add 2, 21, 23
-; PPC64BE-NEXT:    lbz 23, 279(1)
+; PPC64BE-NEXT:    add 23, 21, 23
+; PPC64BE-NEXT:    lbz 21, 279(1)
 ; PPC64BE-NEXT:    lbz 25, 143(1)
 ; PPC64BE-NEXT:    add 11, 11, 22
 ; PPC64BE-NEXT:    lbz 22, 271(1)
 ; PPC64BE-NEXT:    lbz 24, 135(1)
 ; PPC64BE-NEXT:    add 10, 12, 10
 ; PPC64BE-NEXT:    lbz 12, 263(1)
 ; PPC64BE-NEXT:    lbz 30, 175(1)
 ; PPC64BE-NEXT:    lbz 29, 303(1)
-; PPC64BE-NEXT:    add 26, 23, 26
-; PPC64BE-NEXT:    lbz 23, 311(1)
+; PPC64BE-NEXT:    add 26, 21, 26
+; PPC64BE-NEXT:    lbz 21, 311(1)
 ; PPC64BE-NEXT:    std 28, -32(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    add 25, 22, 25
 ; PPC64BE-NEXT:    lbz 28, 167(1)
 ; PPC64BE-NEXT:    lbz 22, 295(1)
 ; PPC64BE-NEXT:    std 27, -40(1) # 8-byte Folded Spill
 ; PPC64BE-NEXT:    add 12, 12, 24
 ; PPC64BE-NEXT:    lbz 27, 159(1)
 ; PPC64BE-NEXT:    lbz 24, 287(1)
 ; PPC64BE-NEXT:    add 30, 29, 30
-; PPC64BE-NEXT:    add 29, 23, 0
+; PPC64BE-NEXT:    add 29, 21, 0
 ; PPC64BE-NEXT:    addi 0, 29, 1
 ; PPC64BE-NEXT:    add 28, 22, 28
 ; PPC64BE-NEXT:    stb 0, 15(3)
 ; PPC64BE-NEXT:    addi 0, 30, 1
 ; PPC64BE-NEXT:    add 27, 24, 27
 ; PPC64BE-NEXT:    stb 0, 14(3)
 ; PPC64BE-NEXT:    addi 0, 28, 1
 ; PPC64BE-NEXT:    stb 0, 13(3)
 ; PPC64BE-NEXT:    addi 0, 27, 1
 ; PPC64BE-NEXT:    stb 0, 12(3)
 ; PPC64BE-NEXT:    addi 0, 26, 1
 ; PPC64BE-NEXT:    addi 12, 12, 1
 ; PPC64BE-NEXT:    stb 0, 11(3)
 ; PPC64BE-NEXT:    addi 0, 25, 1
 ; PPC64BE-NEXT:    stb 12, 9(3)
-; PPC64BE-NEXT:    addi 12, 2, 1
+; PPC64BE-NEXT:    addi 12, 23, 1
 ; PPC64BE-NEXT:    addi 11, 11, 1
 ; PPC64BE-NEXT:    addi 10, 10, 1
 ; PPC64BE-NEXT:    addi 9, 9, 1
 ; PPC64BE-NEXT:    addi 8, 8, 1
 ; PPC64BE-NEXT:    addi 7, 7, 1
 ; PPC64BE-NEXT:    addi 6, 6, 1
 ; PPC64BE-NEXT:    addi 5, 5, 1
 ; PPC64BE-NEXT:    addi 4, 4, 1
 ; PPC64BE-NEXT:    stb 0, 10(3)
 ; PPC64BE-NEXT:    stb 12, 8(3)
 ; PPC64BE-NEXT:    stb 11, 7(3)
 ; PPC64BE-NEXT:    stb 10, 6(3)
 ; PPC64BE-NEXT:    stb 9, 5(3)
 ; PPC64BE-NEXT:    stb 8, 4(3)
 ; PPC64BE-NEXT:    stb 7, 3(3)
 ; PPC64BE-NEXT:    stb 6, 2(3)
 ; PPC64BE-NEXT:    stb 5, 1(3)
 ; PPC64BE-NEXT:    stb 4, 0(3)
-; PPC64BE-NEXT:    ld 2, -96(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 27, -40(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 26, -48(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 25, -56(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 24, -64(1) # 8-byte Folded Reload
 ; PPC64BE-NEXT:    ld 23, -72(1) # 8-byte Folded Reload