This is an archive of the discontinued LLVM Phabricator instance.

[ARM] Add patterns for VSUB with q and r registers
ClosedPublic

Authored by oliverlars on Sep 6 2019, 5:56 AM.

Download Raw Diff

Details

Reviewers

dmgreen
SjoerdMeijer
samparker
simon_tatham
t.p.northover

Summary

Added patterns for VSUB to support q and r registers, which reduces pressure on q registers.

Diff Detail

Repository: rL LLVM

Event Timeline

oliverlars created this revision.Sep 6 2019, 5:56 AM

Herald added a project: Restricted Project. · View Herald TranscriptSep 6 2019, 5:56 AM

Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar. · View Herald Transcript

re-added run line and added tests for swapping %src and %sp

LGTM. Nice one.

llvm/lib/Target/ARM/ARMInstrMVE.td
3628	You could combine this into the same Predicates block (it doesn't matter a lot either way). Up to you.

This revision is now accepted and ready to land.Sep 6 2019, 8:17 AM

rGa050307c0572

Revision Contents

Path

Size

llvm/

lib/

Target/

ARM/

ARMInstrMVE.td

9 lines

test/

CodeGen/

Thumb2/

mve-vsubqr.ll

36 lines

Diff 219079

llvm/lib/Target/ARM/ARMInstrMVE.td

Show First 20 Lines • Show All 3,619 Lines • ▼ Show 20 Lines	let Predicates = [HasMVEInt] in {
def : Pat<(v16i8 (add (v16i8 MQPR:$val1), (v16i8 (ARMvdup GPR:$val2)))),		def : Pat<(v16i8 (add (v16i8 MQPR:$val1), (v16i8 (ARMvdup GPR:$val2)))),
(v16i8 (MVE_VADD_qr_i8 (v16i8 MQPR:$val1), (i32 GPR:$val2)))>;		(v16i8 (MVE_VADD_qr_i8 (v16i8 MQPR:$val1), (i32 GPR:$val2)))>;
def : Pat<(v8i16 (add (v8i16 MQPR:$val1), (v8i16 (ARMvdup GPR:$val2)))),		def : Pat<(v8i16 (add (v8i16 MQPR:$val1), (v8i16 (ARMvdup GPR:$val2)))),
(v8i16 (MVE_VADD_qr_i16 (v8i16 MQPR:$val1), (i32 GPR:$val2)))>;		(v8i16 (MVE_VADD_qr_i16 (v8i16 MQPR:$val1), (i32 GPR:$val2)))>;
def : Pat<(v4i32 (add (v4i32 MQPR:$val1), (v4i32 (ARMvdup GPR:$val2)))),		def : Pat<(v4i32 (add (v4i32 MQPR:$val1), (v4i32 (ARMvdup GPR:$val2)))),
(v4i32 (MVE_VADD_qr_i32 (v4i32 MQPR:$val1), (i32 GPR:$val2)))>;		(v4i32 (MVE_VADD_qr_i32 (v4i32 MQPR:$val1), (i32 GPR:$val2)))>;
}		}

		let Predicates = [HasMVEInt] in {
		dmgreenUnsubmitted Not Done Reply Inline Actions You could combine this into the same Predicates block (it doesn't matter a lot either way). Up to you. dmgreen: You could combine this into the same Predicates block (it doesn't matter a lot either way). Up…
		def : Pat<(v16i8 (sub (v16i8 MQPR:$val1), (v16i8 (ARMvdup GPR:$val2)))),
		(v16i8 (MVE_VSUB_qr_i8 (v16i8 MQPR:$val1), (i32 GPR:$val2)))>;
		def : Pat<(v8i16 (sub (v8i16 MQPR:$val1), (v8i16 (ARMvdup GPR:$val2)))),
		(v8i16 (MVE_VSUB_qr_i16 (v8i16 MQPR:$val1), (i32 GPR:$val2)))>;
		def : Pat<(v4i32 (sub (v4i32 MQPR:$val1), (v4i32 (ARMvdup GPR:$val2)))),
		(v4i32 (MVE_VSUB_qr_i32 (v4i32 MQPR:$val1), (i32 GPR:$val2)))>;
		}

class MVE_VQDMULL_qr<string iname, string suffix, bit size,		class MVE_VQDMULL_qr<string iname, string suffix, bit size,
bit T, list<dag> pattern=[]>		bit T, list<dag> pattern=[]>
: MVE_qDest_rSrc<iname, suffix, pattern> {		: MVE_qDest_rSrc<iname, suffix, pattern> {

let Inst{28} = size;		let Inst{28} = size;
let Inst{21-20} = 0b11;		let Inst{21-20} = 0b11;
let Inst{16} = 0b0;		let Inst{16} = 0b0;
let Inst{12} = T;		let Inst{12} = T;
▲ Show 20 Lines • Show All 1,550 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vsubqr.ll

This file was added.

				; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
				define arm_aapcs_vfpcc <4 x i32> @vsubqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
				; CHECK-LABEL: vsubqr_v4i32:
				; CHECK: @ %bb.0: @ %entry
				; CHECK-NEXT: vsub.i32 q0, q0, r0
				; CHECK-NEXT: bx lr
				entry:
				%i = insertelement <4 x i32> undef, i32 %src2, i32 0
				%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
				%c = sub <4 x i32> %src, %sp
				ret <4 x i32> %c
				}

				define arm_aapcs_vfpcc <8 x i16> @vsubqr_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
				; CHECK-LABEL: vsubqr_v8i16:
				; CHECK: @ %bb.0: @ %entry
				; CHECK-NEXT: vsub.i16 q0, q0, r0
				; CHECK-NEXT: bx lr
				entry:
				%i = insertelement <8 x i16> undef, i16 %src2, i32 0
				%sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
				%c = sub <8 x i16> %src, %sp
				ret <8 x i16> %c
				}

				define arm_aapcs_vfpcc <16 x i8> @vsubqr_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
				; CHECK-LABEL: vsubqr_v16i8:
				; CHECK: @ %bb.0: @ %entry
				; CHECK-NEXT: vsub.i8 q0, q0, r0
				; CHECK-NEXT: bx lr
				entry:
				%i = insertelement <16 x i8> undef, i8 %src2, i32 0
				%sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
				%c = sub <16 x i8> %src, %sp
				ret <16 x i8> %c
				}