[ARM] Remove some spurious MVE reduction instructions.

[simon_tatham]

Summary

The family of 'dual-accumulating' vector multiply-add instructions
(VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and
unsigned integer types, and they all have an 'exchange' variant (with
an X in the name) that modifies which pairs of vector lanes in the two
inputs are multiplied together. But there's a clause in the spec that
says that the X variants don't operate on unsigned integer types,
only signed. You can have X, or unsigned, or neither, but not both.

We didn't notice that clause when we implemented the MC support for
these instructions, so LLVM believes that things like VMLADAVX.U8 do
exist, contradicting the spec. Here I fix that by conditioning them
out in Tablegen.

In order to do that, I've reversed the nesting order of the Tablegen
multiclasses for those instructions. Previously, the innermost
multiclass generated the X and not-X variants, and the one outside
that generated the A and not-A variants. Now X is done by the outer
multiclass, which allows me to bypass that one when I only want the
two not-X variants.

Changing the multiclass nesting order also changes the names of the
instruction ids unless I make a special effort not to. I decided that
while I was changing them anyway I'd make them look nicer; so now the
instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32,
instead of cumbersome _noacc_noexch suffixes.

The corresponding multiply-subtract instructions are unaffected. Those
don't accept unsigned types at all, either in the spec or in LLVM.

[dmgreen]

Change looks sensible to me, but how difficult would this be to do without the, umm, creative use of foreach?

[ostannard]

LGTM

[simon_tatham]

Reworked the patch to reverse the multiclass nesting order, avoiding the need to fake a Tablegen if using foreach.

[dmgreen]

Nice one. LGTM.

llvm/lib/Target/ARM/ARMInstrMVE.td

class MVE_VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
   let Inst{0} = bit_0;
 }
 
 multiclass MVE_VMLAMLSDAV_X<string iname, string suffix, dag iops, string cstr,
                           bit sz, bit bit_28, bit A, bit bit_8, bit bit_0,
                           list<dag> pattern=[]> {
   def _noexch : MVE_VMLAMLSDAV<iname, suffix, iops, cstr, sz,
                             bit_28, A, 0b0, bit_8, bit_0, pattern>;
+
+  // Architectural restriction: the add instructions in this family
+  // (with bit_0 == 0) can't both use the exchange variant (with an
+  // 'x' in the name) *and* take an unsigned type.
+  //
+  // I use a 'foreach' to condition this out because Tablegen has no
+  // 'if' statement.
+  foreach dummy = !if(!and(bit_28,!eq(bit_0,0)), []<int>, [1]) in
   def _exch   : MVE_VMLAMLSDAV<iname # "x", suffix, iops, cstr, sz,
                             bit_28, A, 0b1, bit_8, bit_0, pattern>;
 }
 
 multiclass MVE_VMLAMLSDAV_XA<string iname, string suffix, bit sz, bit bit_28,
                            bit bit_8, bit bit_0, list<dag> pattern=[]> {
   defm _noacc : MVE_VMLAMLSDAV_X<iname, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
                               sz, bit_28, 0b0, bit_8, bit_0, pattern>;
class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
   let Inst{0} = bit_0;
 }
 
 multiclass MVE_VMLALDAVBase_X<string iname, string suffix, dag iops,
                               string cstr, bit sz, bit bit_28, bit A,
                               bit bit_8, bit bit_0, list<dag> pattern=[]> {
   def _noexch : MVE_VMLALDAVBase<iname, suffix, iops, cstr, sz,
                                bit_28, A, 0b0, bit_8, bit_0, pattern>;
+
+  // Similarly to MVE_VMLAMLSDAV_X, condition out the combination of
+  // addition, 'x' variant, and an unsigned type.
+  foreach dummy = !if(!and(bit_28,!eq(bit_0,0)), []<int>, [1]) in
   def _exch   : MVE_VMLALDAVBase<iname # "x", suffix, iops, cstr, sz,
                                bit_28, A, 0b1, bit_8, bit_0, pattern>;
 }
 
 multiclass MVE_VMLALDAVBase_XA<string iname, string suffix, bit sz, bit bit_28,
                              bit bit_8, bit bit_0, list<dag> pattern=[]> {
   defm _noacc : MVE_VMLALDAVBase_X<
      iname, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",

llvm/test/MC/ARM/mve-reductions.s

 vmladava.s16 lr, q0, q4
 
 # CHECK: vmladavx.s16 r0, q0, q7  @ encoding: [0xf0,0xee,0x0e,0x1e]
 vmladavx.s16 r0, q0, q7
 
 # CHECK: vmladavax.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x2e,0xfe]
 vmladavax.s16 lr, q0, q7
 
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavax.u16 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavx.u16 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavax.u32 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavx.u32 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavax.u8 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavx.u8 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavax.u16 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavx.u16 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavax.u32 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavx.u32 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavhax.u32 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavhx.u32 r2, r3, q4, q5
+
 # CHECK: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
 vmladav.s8 lr, q3, q0
 
 # CHECK: vmlav.u8 lr, q1, q7  @ encoding: [0xf2,0xfe,0x0e,0xef]
 vmladav.u8 lr, q1, q7
 
 # CHECK: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
 vrmlaldavh.s32 lr, r1, q6, q2

llvm/test/MC/Disassembler/ARM/mve-reductions.txt

-# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
 
 [0x82 0xee 0x07 0x0f]
 # CHECK: vabav.s8  r0, q1, q3
 # CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
 
 [0x92 0xee 0x07 0x0f]

 # CHECK: vmladavx.s16 r0, q0, q7  @ encoding: [0xf0,0xee,0x0e,0x1e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0xf0,0xee,0x0e,0x1e]
 
 # CHECK: vmladavax.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x2e,0xfe]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0xf0,0xee,0x2e,0xfe]
 
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x2a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x0a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf9,0xfe,0x2a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf9,0xfe,0x0a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x2a,0x1f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x0a,0x1f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x2a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x0a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfe,0x2a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfe,0x0a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x2a,0x3f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x0a,0x3f]
+
 # CHECK: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0xf6,0xee,0x00,0xef]
 
 # CHECK: vmlav.u8 lr, q1, q7  @ encoding: [0xf2,0xfe,0x0e,0xef]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0xf2,0xfe,0x0e,0xef]