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statham-armstatham-arm
committedSep 9, 2019
[ARM] Remove some spurious MVE reduction instructions.
The family of 'dual-accumulating' vector multiply-add instructions (VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and unsigned integer types, and they all have an 'exchange' variant (with an X in the name) that modifies which pairs of vector lanes in the two inputs are multiplied together. But there's a clause in the spec that says that the X variants //don't// operate on unsigned integer types, only signed. You can have X, or unsigned, or neither, but not both. We didn't notice that clause when we implemented the MC support for these instructions, so LLVM believes that things like VMLADAVX.U8 do exist, contradicting the spec. Here I fix that by conditioning them out in Tablegen. In order to do that, I've reversed the nesting order of the Tablegen multiclasses for those instructions. Previously, the innermost multiclass generated the X and not-X variants, and the one outside that generated the A and not-A variants. Now X is done by the outer multiclass, which allows me to bypass that one when I only want the two not-X variants. Changing the multiclass nesting order also changes the names of the instruction ids unless I make a special effort not to. I decided that while I was changing them anyway I'd make them look nicer; so now the instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32, instead of cumbersome _noacc_noexch suffixes. The corresponding multiply-subtract instructions are unaffected. Those don't accept unsigned types at all, either in the spec or in LLVM. Reviewers: ostannard, dmgreen Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67214 llvm-svn: 371405
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‎llvm/lib/Target/ARM/ARMInstrMVE.td

+80-79
Original file line numberDiff line numberDiff line change
@@ -700,57 +700,57 @@ class MVE_VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
700700
let Inst{0} = bit_0;
701701
}
702702

703-
multiclass MVE_VMLAMLSDAV_X<string iname, string suffix, dag iops, string cstr,
704-
bit sz, bit bit_28, bit A, bit bit_8, bit bit_0,
705-
list<dag> pattern=[]> {
706-
def _noexch : MVE_VMLAMLSDAV<iname, suffix, iops, cstr, sz,
707-
bit_28, A, 0b0, bit_8, bit_0, pattern>;
708-
def _exch : MVE_VMLAMLSDAV<iname # "x", suffix, iops, cstr, sz,
709-
bit_28, A, 0b1, bit_8, bit_0, pattern>;
703+
multiclass MVE_VMLAMLSDAV_A<string iname, string x, string suffix,
704+
bit sz, bit bit_28, bit X, bit bit_8, bit bit_0,
705+
list<dag> pattern=[]> {
706+
def ""#x#suffix : MVE_VMLAMLSDAV<iname # x, suffix,
707+
(ins MQPR:$Qn, MQPR:$Qm), "",
708+
sz, bit_28, 0b0, X, bit_8, bit_0, pattern>;
709+
def "a"#x#suffix : MVE_VMLAMLSDAV<iname # "a" # x, suffix,
710+
(ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
711+
"$RdaDest = $RdaSrc",
712+
sz, bit_28, 0b1, X, bit_8, bit_0, pattern>;
713+
}
714+
715+
multiclass MVE_VMLAMLSDAV_AX<string iname, string suffix, bit sz, bit bit_28,
716+
bit bit_8, bit bit_0, list<dag> pattern=[]> {
717+
defm "" : MVE_VMLAMLSDAV_A<iname, "", suffix, sz, bit_28,
718+
0b0, bit_8, bit_0, pattern>;
719+
defm "" : MVE_VMLAMLSDAV_A<iname, "x", suffix, sz, bit_28,
720+
0b1, bit_8, bit_0, pattern>;
710721
}
711722

712-
multiclass MVE_VMLAMLSDAV_XA<string iname, string suffix, bit sz, bit bit_28,
713-
bit bit_8, bit bit_0, list<dag> pattern=[]> {
714-
defm _noacc : MVE_VMLAMLSDAV_X<iname, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
715-
sz, bit_28, 0b0, bit_8, bit_0, pattern>;
716-
defm _acc : MVE_VMLAMLSDAV_X<iname # "a", suffix,
717-
(ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
718-
"$RdaDest = $RdaSrc",
719-
sz, bit_28, 0b1, bit_8, bit_0, pattern>;
723+
multiclass MVE_VMLADAV_multi<string suffix, bit sz, bit bit_8,
724+
list<dag> pattern=[]> {
725+
defm "" : MVE_VMLAMLSDAV_AX<"vmladav", "s"#suffix,
726+
sz, 0b0, bit_8, 0b0, pattern>;
727+
defm "" : MVE_VMLAMLSDAV_A<"vmladav", "", "u"#suffix,
728+
sz, 0b1, 0b0, bit_8, 0b0, pattern>;
720729
}
721730

722-
multiclass MVE_VMLADAV_multi<string suffix, bit sz, bit U, bit bit_8,
723-
list<dag> pattern=[]> {
724-
defm "" : MVE_VMLAMLSDAV_XA<"vmladav", suffix, sz, U, bit_8, 0b0, pattern>;
731+
multiclass MVE_VMLSDAV_multi<string suffix, bit sz, bit bit_28,
732+
list<dag> pattern=[]> {
733+
defm "" : MVE_VMLAMLSDAV_AX<"vmlsdav", "s"#suffix,
734+
sz, bit_28, 0b0, 0b1, pattern>;
725735
}
726736

727-
defm MVE_VMLADAVs16 : MVE_VMLADAV_multi<"s16", 0b0, 0b0, 0b0>;
728-
defm MVE_VMLADAVs32 : MVE_VMLADAV_multi<"s32", 0b1, 0b0, 0b0>;
729-
defm MVE_VMLADAVu16 : MVE_VMLADAV_multi<"u16", 0b0, 0b1, 0b0>;
730-
defm MVE_VMLADAVu32 : MVE_VMLADAV_multi<"u32", 0b1, 0b1, 0b0>;
737+
defm MVE_VMLADAV : MVE_VMLADAV_multi< "8", 0b0, 0b1>;
738+
defm MVE_VMLADAV : MVE_VMLADAV_multi<"16", 0b0, 0b0>;
739+
defm MVE_VMLADAV : MVE_VMLADAV_multi<"32", 0b1, 0b0>;
731740

732-
defm MVE_VMLADAVs8 : MVE_VMLADAV_multi<"s8", 0b0, 0b0, 0b1>;
733-
defm MVE_VMLADAVu8 : MVE_VMLADAV_multi<"u8", 0b0, 0b1, 0b1>;
741+
defm MVE_VMLSDAV : MVE_VMLSDAV_multi< "8", 0b0, 0b1>;
742+
defm MVE_VMLSDAV : MVE_VMLSDAV_multi<"16", 0b0, 0b0>;
743+
defm MVE_VMLSDAV : MVE_VMLSDAV_multi<"32", 0b1, 0b0>;
734744

735745
// vmlav aliases vmladav
736-
foreach acc = ["_acc", "_noacc"] in {
746+
foreach acc = ["", "a"] in {
737747
foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in {
738-
def : MVEInstAlias<!strconcat("vmlav", !if(!eq(acc, "_acc"), "a", ""),
739-
"${vp}.", suffix, "\t$RdaDest, $Qn, $Qm"),
740-
(!cast<Instruction>("MVE_VMLADAV"#suffix#acc#"_noexch")
748+
def : MVEInstAlias<"vmlav"#acc#"${vp}."#suffix#"\t$RdaDest, $Qn, $Qm",
749+
(!cast<Instruction>("MVE_VMLADAV"#acc#suffix)
741750
tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
742751
}
743752
}
744753

745-
multiclass MVE_VMLSDAV_multi<string suffix, bit sz, bit bit_28,
746-
list<dag> pattern=[]> {
747-
defm "" : MVE_VMLAMLSDAV_XA<"vmlsdav", suffix, sz, bit_28, 0b0, 0b1, pattern>;
748-
}
749-
750-
defm MVE_VMLSDAVs8 : MVE_VMLSDAV_multi<"s8", 0, 0b1>;
751-
defm MVE_VMLSDAVs16 : MVE_VMLSDAV_multi<"s16", 0, 0b0>;
752-
defm MVE_VMLSDAVs32 : MVE_VMLSDAV_multi<"s32", 1, 0b0>;
753-
754754
// Base class for VMLALDAV and VMLSLDAV, VRMLALDAVH, VRMLSLDAVH
755755
class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
756756
bit sz, bit bit_28, bit A, bit X, bit bit_8, bit bit_0,
@@ -775,82 +775,83 @@ class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
775775
let Inst{0} = bit_0;
776776
}
777777

778-
multiclass MVE_VMLALDAVBase_X<string iname, string suffix, dag iops,
779-
string cstr, bit sz, bit bit_28, bit A,
780-
bit bit_8, bit bit_0, list<dag> pattern=[]> {
781-
def _noexch : MVE_VMLALDAVBase<iname, suffix, iops, cstr, sz,
782-
bit_28, A, 0b0, bit_8, bit_0, pattern>;
783-
def _exch : MVE_VMLALDAVBase<iname # "x", suffix, iops, cstr, sz,
784-
bit_28, A, 0b1, bit_8, bit_0, pattern>;
778+
multiclass MVE_VMLALDAVBase_A<string iname, string x, string suffix,
779+
bit sz, bit bit_28, bit X, bit bit_8, bit bit_0,
780+
list<dag> pattern=[]> {
781+
def ""#x#suffix : MVE_VMLALDAVBase<
782+
iname # x, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
783+
sz, bit_28, 0b0, X, bit_8, bit_0, pattern>;
784+
def "a"#x#suffix : MVE_VMLALDAVBase<
785+
iname # "a" # x, suffix,
786+
(ins tGPREven:$RdaLoSrc, tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm),
787+
"$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
788+
sz, bit_28, 0b1, X, bit_8, bit_0, pattern>;
785789
}
786790

787-
multiclass MVE_VMLALDAVBase_XA<string iname, string suffix, bit sz, bit bit_28,
788-
bit bit_8, bit bit_0, list<dag> pattern=[]> {
789-
defm _noacc : MVE_VMLALDAVBase_X<
790-
iname, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
791-
sz, bit_28, 0b0, bit_8, bit_0, pattern>;
792-
defm _acc : MVE_VMLALDAVBase_X<
793-
iname # "a", suffix, (ins tGPREven:$RdaLoSrc, tGPROdd:$RdaHiSrc,
794-
MQPR:$Qn, MQPR:$Qm),
795-
"$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
796-
sz, bit_28, 0b1, bit_8, bit_0, pattern>;
791+
792+
multiclass MVE_VMLALDAVBase_AX<string iname, string suffix, bit sz, bit bit_28,
793+
bit bit_8, bit bit_0, list<dag> pattern=[]> {
794+
defm "" : MVE_VMLALDAVBase_A<iname, "", suffix, sz,
795+
bit_28, 0b0, bit_8, bit_0, pattern>;
796+
defm "" : MVE_VMLALDAVBase_A<iname, "x", suffix, sz,
797+
bit_28, 0b1, bit_8, bit_0, pattern>;
797798
}
798799

799-
multiclass MVE_VRMLALDAVH_multi<string suffix, bit U, list<dag> pattern=[]> {
800-
defm "" : MVE_VMLALDAVBase_XA<
801-
"vrmlaldavh", suffix, 0b0, U, 0b1, 0b0, pattern>;
800+
multiclass MVE_VRMLALDAVH_multi<string suffix, list<dag> pattern=[]> {
801+
defm "" : MVE_VMLALDAVBase_AX<"vrmlaldavh", "s"#suffix,
802+
0b0, 0b0, 0b1, 0b0, pattern>;
803+
defm "" : MVE_VMLALDAVBase_A<"vrmlaldavh", "", "u"#suffix,
804+
0b0, 0b1, 0b0, 0b1, 0b0, pattern>;
802805
}
803806

804-
defm MVE_VRMLALDAVHs32 : MVE_VRMLALDAVH_multi<"s32", 0>;
805-
defm MVE_VRMLALDAVHu32 : MVE_VRMLALDAVH_multi<"u32", 1>;
807+
defm MVE_VRMLALDAVH : MVE_VRMLALDAVH_multi<"32">;
806808

807809
// vrmlalvh aliases for vrmlaldavh
808810
def : MVEInstAlias<"vrmlalvh${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
809-
(MVE_VRMLALDAVHs32_noacc_noexch
811+
(MVE_VRMLALDAVHs32
810812
tGPREven:$RdaLo, tGPROdd:$RdaHi,
811813
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
812814
def : MVEInstAlias<"vrmlalvha${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
813-
(MVE_VRMLALDAVHs32_acc_noexch
815+
(MVE_VRMLALDAVHas32
814816
tGPREven:$RdaLo, tGPROdd:$RdaHi,
815817
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
816818
def : MVEInstAlias<"vrmlalvh${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
817-
(MVE_VRMLALDAVHu32_noacc_noexch
819+
(MVE_VRMLALDAVHu32
818820
tGPREven:$RdaLo, tGPROdd:$RdaHi,
819821
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
820822
def : MVEInstAlias<"vrmlalvha${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
821-
(MVE_VRMLALDAVHu32_acc_noexch
823+
(MVE_VRMLALDAVHau32
822824
tGPREven:$RdaLo, tGPROdd:$RdaHi,
823825
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
824826

825-
multiclass MVE_VMLALDAV_multi<string suffix, bit sz, bit U,
826-
list<dag> pattern=[]> {
827-
defm "" : MVE_VMLALDAVBase_XA<"vmlaldav", suffix, sz, U, 0b0, 0b0, pattern>;
827+
multiclass MVE_VMLALDAV_multi<string suffix, bit sz, list<dag> pattern=[]> {
828+
defm "" : MVE_VMLALDAVBase_AX<"vmlaldav", "s"#suffix, sz, 0b0, 0b0, 0b0, pattern>;
829+
defm "" : MVE_VMLALDAVBase_A<"vmlaldav", "", "u"#suffix,
830+
sz, 0b1, 0b0, 0b0, 0b0, pattern>;
828831
}
829832

830-
defm MVE_VMLALDAVs16 : MVE_VMLALDAV_multi<"s16", 0b0, 0b0>;
831-
defm MVE_VMLALDAVs32 : MVE_VMLALDAV_multi<"s32", 0b1, 0b0>;
832-
defm MVE_VMLALDAVu16 : MVE_VMLALDAV_multi<"u16", 0b0, 0b1>;
833-
defm MVE_VMLALDAVu32 : MVE_VMLALDAV_multi<"u32", 0b1, 0b1>;
833+
defm MVE_VMLALDAV : MVE_VMLALDAV_multi<"16", 0b0>;
834+
defm MVE_VMLALDAV : MVE_VMLALDAV_multi<"32", 0b1>;
834835

835836
// vmlalv aliases vmlaldav
836-
foreach acc = ["_acc", "_noacc"] in {
837+
foreach acc = ["", "a"] in {
837838
foreach suffix = ["s16", "s32", "u16", "u32"] in {
838-
def : MVEInstAlias<!strconcat("vmlalv", !if(!eq(acc, "_acc"), "a", ""),
839-
"${vp}.", suffix, "\t$RdaLoDest, $RdaHiDest, $Qn, $Qm"),
840-
(!cast<Instruction>("MVE_VMLALDAV"#suffix#acc#"_noexch")
839+
def : MVEInstAlias<"vmlalv" # acc # "${vp}." # suffix #
840+
"\t$RdaLoDest, $RdaHiDest, $Qn, $Qm",
841+
(!cast<Instruction>("MVE_VMLALDAV"#acc#suffix)
841842
tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest,
842843
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
843844
}
844845
}
845846

846847
multiclass MVE_VMLSLDAV_multi<string iname, string suffix, bit sz,
847-
bit bit_28, list<dag> pattern=[]> {
848-
defm "" : MVE_VMLALDAVBase_XA<iname, suffix, sz, bit_28, 0b0, 0b1, pattern>;
848+
bit bit_28, list<dag> pattern=[]> {
849+
defm "" : MVE_VMLALDAVBase_AX<iname, suffix, sz, bit_28, 0b0, 0b1, pattern>;
849850
}
850851

851-
defm MVE_VMLSLDAVs16 : MVE_VMLSLDAV_multi<"vmlsldav", "s16", 0b0, 0b0>;
852-
defm MVE_VMLSLDAVs32 : MVE_VMLSLDAV_multi<"vmlsldav", "s32", 0b1, 0b0>;
853-
defm MVE_VRMLSLDAVHs32 : MVE_VMLSLDAV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
852+
defm MVE_VMLSLDAV : MVE_VMLSLDAV_multi<"vmlsldav", "s16", 0b0, 0b0>;
853+
defm MVE_VMLSLDAV : MVE_VMLSLDAV_multi<"vmlsldav", "s32", 0b1, 0b0>;
854+
defm MVE_VRMLSLDAVH : MVE_VMLSLDAV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
854855

855856
// end of mve_rDest instructions
856857

‎llvm/test/MC/ARM/mve-reductions.s

+36
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,42 @@ vmladavx.s16 r0, q0, q7
130130
# CHECK: vmladavax.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x2e,0xfe]
131131
vmladavax.s16 lr, q0, q7
132132

133+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
134+
vmladavax.u16 r0, q4, q5
135+
136+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
137+
vmladavx.u16 r0, q4, q5
138+
139+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
140+
vmladavax.u32 r0, q4, q5
141+
142+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
143+
vmladavx.u32 r0, q4, q5
144+
145+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
146+
vmladavax.u8 r0, q4, q5
147+
148+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
149+
vmladavx.u8 r0, q4, q5
150+
151+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
152+
vmlaldavax.u16 r2, r3, q4, q5
153+
154+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
155+
vmlaldavx.u16 r2, r3, q4, q5
156+
157+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
158+
vmlaldavax.u32 r2, r3, q4, q5
159+
160+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
161+
vmlaldavx.u32 r2, r3, q4, q5
162+
163+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
164+
vrmlaldavhax.u32 r2, r3, q4, q5
165+
166+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
167+
vrmlaldavhx.u32 r2, r3, q4, q5
168+
133169
# CHECK: vmlav.s8 lr, q3, q0 @ encoding: [0xf6,0xee,0x00,0xef]
134170
vmladav.s8 lr, q3, q0
135171

‎llvm/test/MC/Disassembler/ARM/mve-reductions.txt

+38-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
1-
# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
1+
# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s
2+
# RUN: FileCheck --check-prefix=ERROR < %t %s
23
# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
34
# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
45

@@ -182,6 +183,42 @@
182183
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
183184
[0xf0,0xee,0x2e,0xfe]
184185

186+
# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
187+
[0xf8,0xfe,0x2a,0x1e]
188+
189+
# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
190+
[0xf8,0xfe,0x0a,0x1e]
191+
192+
# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
193+
[0xf9,0xfe,0x2a,0x1e]
194+
195+
# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
196+
[0xf9,0xfe,0x0a,0x1e]
197+
198+
# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
199+
[0xf8,0xfe,0x2a,0x1f]
200+
201+
# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
202+
[0xf8,0xfe,0x0a,0x1f]
203+
204+
# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
205+
[0x98,0xfe,0x2a,0x3e]
206+
207+
# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
208+
[0x98,0xfe,0x0a,0x3e]
209+
210+
# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
211+
[0x99,0xfe,0x2a,0x3e]
212+
213+
# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
214+
[0x99,0xfe,0x0a,0x3e]
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# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
217+
[0x98,0xfe,0x2a,0x3f]
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# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
220+
[0x98,0xfe,0x0a,0x3f]
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185222
# CHECK: vmlav.s8 lr, q3, q0 @ encoding: [0xf6,0xee,0x00,0xef]
186223
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
187224
[0xf6,0xee,0x00,0xef]

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