[MIR] MIR Namer pass

[plotfi]

Summary

This is a pass for rewriting the names of vregs of MIR code.
I think it could be handy for authoring and reducing tests.

[paquette]

llvm/lib/CodeGen/MIRNamerPass.cpp

9 ↗

(On Diff #218835)

s/renames/rename/

Might want to explain what the use-cases for this are too. E.g. test development

41 ↗

(On Diff #218835)

I don't think these usually have a period at the end?

58 ↗

(On Diff #218835)

auto &MBB?

llvm/test/CodeGen/MIR/AArch64/mirnamer.mir

1 ↗

(On Diff #218835)

-verify-machineinstrs?

[plotfi]

addressing @paquette's feedback

[paquette]

LGTM

[uabelho]

Hi,

I did a minor change to the test case in r371171 since the

;CHECK: bb

checks matched on the line

;ModuleID = '/repo/bb/

in the output instead of the wanted "bb.0:".

I fixed it by reading input from stdin instead of from the file to make the change as small as possible, but perhaps the
;CHECK: bb
lines should be changed to
;CHECK-LABEL: bb.0:
etc instead.

[plotfi]

In D67209#1660346, @uabelho wrote:

Hi,

I did a minor change to the test case in r371171 since the

;CHECK: bb

checks matched on the line

;ModuleID = '/repo/bb/

in the output instead of the wanted "bb.0:".

I fixed it by reading input from stdin instead of from the file to make the change as small as possible, but perhaps the
;CHECK: bb
lines should be changed to
;CHECK-LABEL: bb.0:
etc instead.

Thank you 🙏

llvm/trunk/include/llvm/InitializePasses.h

 void initializeLowerExpectIntrinsicPass(PassRegistry&);
 void initializeLowerGuardIntrinsicLegacyPassPass(PassRegistry&);
 void initializeLowerWidenableConditionLegacyPassPass(PassRegistry&);
 void initializeLowerIntrinsicsPass(PassRegistry&);
 void initializeLowerInvokeLegacyPassPass(PassRegistry&);
 void initializeLowerSwitchPass(PassRegistry&);
 void initializeLowerTypeTestsPass(PassRegistry&);
 void initializeMIRCanonicalizerPass(PassRegistry &);
+void initializeMIRNamerPass(PassRegistry &);
 void initializeMIRPrintingPassPass(PassRegistry&);
 void initializeMachineBlockFrequencyInfoPass(PassRegistry&);
 void initializeMachineBlockPlacementPass(PassRegistry&);
 void initializeMachineBlockPlacementStatsPass(PassRegistry&);
 void initializeMachineBranchProbabilityInfoPass(PassRegistry&);
 void initializeMachineCSEPass(PassRegistry&);
 void initializeMachineCombinerPass(PassRegistry&);
 void initializeMachineCopyPropagationPass(PassRegistry&);

llvm/trunk/lib/CodeGen/CMakeLists.txt

add_llvm_library(LLVMCodeGen
   RegAllocGreedy.cpp
   RegAllocPBQP.cpp
   RegisterClassInfo.cpp
   RegisterCoalescer.cpp
   RegisterPressure.cpp
   RegisterScavenging.cpp
   RenameIndependentSubregs.cpp
   MIRVRegNamerUtils.cpp
+  MIRNamerPass.cpp
   MIRCanonicalizerPass.cpp
   RegisterUsageInfo.cpp
   RegUsageInfoCollector.cpp
   RegUsageInfoPropagate.cpp
   ResetMachineFunctionPass.cpp
   SafeStack.cpp
   SafeStackColoring.cpp
   SafeStackLayout.cpp

llvm/trunk/lib/CodeGen/CodeGen.cpp

void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeLiveDebugVariablesPass(Registry);
   initializeLiveIntervalsPass(Registry);
   initializeLiveRangeShrinkPass(Registry);
   initializeLiveStacksPass(Registry);
   initializeLiveVariablesPass(Registry);
   initializeLocalStackSlotPassPass(Registry);
   initializeLowerIntrinsicsPass(Registry);
   initializeMIRCanonicalizerPass(Registry);
+  initializeMIRNamerPass(Registry);
   initializeMachineBlockFrequencyInfoPass(Registry);
   initializeMachineBlockPlacementPass(Registry);
   initializeMachineBlockPlacementStatsPass(Registry);
   initializeMachineCSEPass(Registry);
   initializeMachineCombinerPass(Registry);
   initializeMachineCopyPropagationPass(Registry);
   initializeMachineDominatorTreePass(Registry);
   initializeMachineFunctionPrinterPassPass(Registry);

llvm/trunk/lib/CodeGen/MIRNamerPass.cpp

+//===----------------------- MIRNamer.cpp - MIR Namer ---------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// The purpose of this pass is to rename virtual register operands with the goal
+// of making it easier to author easier to read tests for MIR. This pass reuses
+// the vreg renamer used by MIRCanonicalizerPass.
+//
+// Basic Usage:
+//
+// llc -o - -run-pass mir-namer example.mir
+//
+//===----------------------------------------------------------------------===//
+
+#include "MIRVRegNamerUtils.h"
+#include "llvm/ADT/PostOrderIterator.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
+
+using namespace llvm;
+
+namespace llvm {
+extern char &MIRNamerID;
+} // namespace llvm
+
+#define DEBUG_TYPE "mir-namer"
+
+namespace {
+
+class MIRNamer : public MachineFunctionPass {
+public:
+  static char ID;
+  MIRNamer() : MachineFunctionPass(ID) {}
+
+  StringRef getPassName() const override {
+    return "Rename virtual register operands";
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override {
+    bool Changed = false;
+
+    if (MF.empty())
+      return Changed;
+
+    NamedVRegCursor NVC(MF.getRegInfo());
+
+    ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
+    for (auto &MBB : RPOT)
+      Changed |= NVC.renameVRegs(MBB);
+
+    return Changed;
+  }
+};
+
+} // end anonymous namespace
+
+char MIRNamer::ID;
+
+char &llvm::MIRNamerID = MIRNamer::ID;
+
+INITIALIZE_PASS_BEGIN(MIRNamer, "mir-namer", "Rename Register Operands", false,
+                      false)
+
+INITIALIZE_PASS_END(MIRNamer, "mir-namer", "Rename Register Operands", false,
+                    false)

llvm/trunk/test/CodeGen/MIR/AArch64/mirnamer.mir

+# RUN: llc -mtriple aarch64-apple-ios -run-pass mir-namer -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: foo
+body:             |
+  bb.0:
+
+    ;CHECK: bb
+    ;CHECK-NEXT: %namedVReg1353:_(p0) = COPY $d0
+    ;CHECK-NEXT: %namedVReg1352:_(<4 x s32>) = COPY $q0
+    ;CHECK-NEXT: G_STORE %namedVReg1352(<4 x s32>), %namedVReg1353
+
+    liveins: $q0, $d0
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<4 x s32>) = COPY $q0
+    G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
+...
+---
+name: bar
+stack:
+  - { id: 0, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+body:             |
+  bb.0:
+
+    ;CHECK: bb
+    ;CHECK-NEXT: %namedVReg1370:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1371:gpr32 = MOVi32imm 1
+    ;CHECK-NEXT: %namedVReg1372:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1373:gpr32 = MOVi32imm 2
+    ;CHECK-NEXT: %namedVReg1359:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1360:gpr32 = MOVi32imm 3
+    ;CHECK-NEXT: %namedVReg1365:gpr32 = nsw ADDWrr
+    ;CHECK-NEXT: %namedVReg1361:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1366:gpr32 = nsw ADDWrr
+    ;CHECK-NEXT: %namedVReg1362:gpr32 = MOVi32imm 4
+    ;CHECK-NEXT: %namedVReg1355:gpr32 = nsw ADDWrr
+    ;CHECK-NEXT: %namedVReg1363:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1364:gpr32 = MOVi32imm 5
+
+    %0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %1:gpr32 = MOVi32imm 1
+    %2:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %3:gpr32 = MOVi32imm 2
+    %4:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %5:gpr32 = MOVi32imm 3
+    %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32
+    %6:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32
+    %7:gpr32 = MOVi32imm 4
+    %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32
+    %8:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %9:gpr32 = MOVi32imm 5
+    %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32
+    %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32
+    %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32
+    %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32
+    %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+    %18:gpr32 = nsw ADDWrr %16:gpr32, %17:gpr32
+    $w0 = COPY %18
+    RET_ReallyLR implicit $w0
+...
+---
+name: baz
+stack:
+  - { id: 0, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+body:             |
+  bb.0:
+    liveins: $x0, $x1, $d0, $d1
+
+    ;CHECK: bb
+    ;CHECK-NEXT: %namedVReg1355:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1354:gpr32 = COPY %namedVReg1355
+    ;CHECK-NEXT: %namedVReg1353:gpr32 = COPY %namedVReg1354
+    ;CHECK-NEXT: %namedVReg1352:gpr32 = COPY %namedVReg1353
+    ;CHECK-NEXT: $w0 = COPY %namedVReg1352
+
+    %0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %1:gpr32 = COPY %0
+    %2:gpr32 = COPY %1
+    %3:gpr32 = COPY %2
+    $w0 = COPY %3
+    RET_ReallyLR implicit $w0
+...
+