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[MIR] MIR Namer pass
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Authored by plotfi on Sep 4 2019, 10:00 PM.

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Summary

This is a pass for rewriting the names of vregs of MIR code.
I think it could be handy for authoring and reducing tests.

Diff Detail

Repository
rL LLVM

Event Timeline

plotfi created this revision.Sep 4 2019, 10:00 PM
paquette added inline comments.Sep 5 2019, 10:54 AM
llvm/lib/CodeGen/MIRNamerPass.cpp
9 ↗(On Diff #218835)

s/renames/rename/

Might want to explain what the use-cases for this are too. E.g. test development

41 ↗(On Diff #218835)

I don't think these usually have a period at the end?

58 ↗(On Diff #218835)

auto &MBB?

llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
1 ↗(On Diff #218835)

-verify-machineinstrs?

plotfi updated this revision to Diff 218964.Sep 5 2019, 12:12 PM
plotfi marked 3 inline comments as done.

addressing @paquette's feedback

plotfi marked an inline comment as done.Sep 5 2019, 12:13 PM
This revision is now accepted and ready to land.Sep 5 2019, 12:48 PM
This revision was automatically updated to reflect the committed changes.

Hi,

I did a minor change to the test case in r371171 since the

;CHECK: bb

checks matched on the line

;ModuleID = '/repo/bb/

in the output instead of the wanted "bb.0:".

I fixed it by reading input from stdin instead of from the file to make the change as small as possible, but perhaps the
;CHECK: bb
lines should be changed to
;CHECK-LABEL: bb.0:
etc instead.

Hi,

I did a minor change to the test case in r371171 since the

;CHECK: bb

checks matched on the line

;ModuleID = '/repo/bb/

in the output instead of the wanted "bb.0:".

I fixed it by reading input from stdin instead of from the file to make the change as small as possible, but perhaps the

;CHECK: bb

lines should be changed to

;CHECK-LABEL: bb.0:

etc instead.

Thank you 🙏