[PowerPC] Support extended mnemonics mffprwz etc.

[jsji]

Summary

Reported in https://github.com/opencv/opencv/issues/15413.

We have serveral extended mnemonics for Move To/From Vector-Scalar Register Instructions
eg: mffprd,mtfprd etc.

We only support one of them, this patch add the others.

[hfinkel]

mfvrwz RA,VRS is mfvsrwz RA,VRS+32

The '+32' bit is covered by the added CodeGen/PowerPC/inlineasm-extendedmne.ll test, but I'd really like to see direct encoding tests for all of the instructions. Can you please make sure that they all appear in MC/PowerPC/vsx.s and MC/Disassembler/PowerPC/vsx.txt?

[jsji]

Added encoding tests.

[jsji]

In D66963#1651477, @hfinkel wrote:

mfvrwz RA,VRS is mfvsrwz RA,VRS+32

The '+32' bit is covered by the added CodeGen/PowerPC/inlineasm-extendedmne.ll test, but I'd really like to see direct encoding tests for all of the instructions. Can you please make sure that they all appear in MC/PowerPC/vsx.s and MC/Disassembler/PowerPC/vsx.txt?

Good point, and updated.

[hfinkel]

In D66963#1651566, @jsji wrote:

In D66963#1651477, @hfinkel wrote:

mfvrwz RA,VRS is mfvsrwz RA,VRS+32

The '+32' bit is covered by the added CodeGen/PowerPC/inlineasm-extendedmne.ll test, but I'd really like to see direct encoding tests for all of the instructions. Can you please make sure that they all appear in MC/PowerPC/vsx.s and MC/Disassembler/PowerPC/vsx.txt?

Good point, and updated.

LGTM

llvm/lib/Target/PowerPC/P9InstrResources.td

 
 // Standard Dispatch ALU operation for 2 cycles. Only one slice used.
 def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
       (instrs
     (instregex "S(L|R)D$"),
     (instregex "SRAD(I)?$"),
     (instregex "EXTSWSLI_32_64$"),
     (instregex "MFV(S)?RD$"),
-    (instregex "MTVSRD$"),
-    (instregex "MTVSRW(A|Z)$"),
+    (instregex "MTV(S)?RD$"),
+    (instregex "MTV(S)?RW(A|Z)$"),
     (instregex "CMP(WI|LWI|W|LW)(8)?$"),
     (instregex "CMP(L)?D(I)?$"),
     (instregex "SUBF(I)?C(8)?$"),
     (instregex "ANDI(S)?o(8)?$"),
     (instregex "ADDC(8)?$"),
     (instregex "ADDIC(8)?(o)?$"),
     (instregex "ADD(8|4)(o)?$"),
     (instregex "ADD(E|ME|ZE)(8)?(o)?$"),
def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
     MCRF,
     MCRXRX,
     XSNABSDP,
     XSXEXPDP,
     XSABSDP,
     XSNEGDP,
     XSCPSGNDP,
     MFVSRWZ,
+    MFVRWZ,
     EXTSWSLI,
     SRADI_32,
     RLDIC,
     RFEBB,
     LA,
     TBEGIN,
     TRECHKPT,
     NOP,

llvm/lib/Target/PowerPC/PPCInstrVSX.td

let Predicates = [HasDirectMove] in {
   let isCodeGenOnly = 1 in
   def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT),
                              "mfvsrd $rA, $XT", IIC_VecGeneral,
                              []>,
       Requires<[In64BitMode]>;
   def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
                                "mfvsrwz $rA, $XT", IIC_VecGeneral,
                                [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
+  let isCodeGenOnly = 1 in
+  def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
+                               "mfvsrwz $rA, $XT", IIC_VecGeneral,
+                               []>;
   def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
                               "mtvsrd $XT, $rA", IIC_VecGeneral,
                               [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
       Requires<[In64BitMode]>;
+  let isCodeGenOnly = 1 in
+  def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$rA),
+                              "mtvsrd $XT, $rA", IIC_VecGeneral,
+                              []>,
+      Requires<[In64BitMode]>;
   def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
                                "mtvsrwa $XT, $rA", IIC_VecGeneral,
                                [(set f64:$XT, (PPCmtvsra i32:$rA))]>;
+  let isCodeGenOnly = 1 in
+  def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$rA),
+                               "mtvsrwa $XT, $rA", IIC_VecGeneral,
+                               []>;
   def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
                                "mtvsrwz $XT, $rA", IIC_VecGeneral,
                                [(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
+  let isCodeGenOnly = 1 in
+  def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$rA),
+                               "mtvsrwz $XT, $rA", IIC_VecGeneral,
+                               []>;
 } // HasDirectMove
 
 let Predicates = [IsISA3_0, HasDirectMove] in {
   def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA),
                               "mtvsrws $XT, $rA", IIC_VecGeneral, []>;
 
   def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$rA, g8rc:$rB),
                        "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
                        []>, Requires<[In64BitMode]>;
 
   def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT),
                               "mfvsrld $rA, $XT", IIC_VecGeneral,
                               []>, Requires<[In64BitMode]>;
 
 } // IsISA3_0, HasDirectMove
 } // AddedComplexity = 400
 
 // We want to parse this from asm, but we don't want to emit this as it would
 // be emitted with a VSX reg. So leave Emit = 0 here.
 def : InstAlias<"mfvrd $rA, $XT",
                 (MFVRD g8rc:$rA, vrrc:$XT), 0>;
 def : InstAlias<"mffprd $rA, $src",
                 (MFVSRD g8rc:$rA, f8rc:$src)>;
+def : InstAlias<"mtvrd $XT, $rA",
+                (MTVRD vrrc:$XT, g8rc:$rA), 0>;
+def : InstAlias<"mtfprd $dst, $rA",
+                (MTVSRD f8rc:$dst, g8rc:$rA)>;
+def : InstAlias<"mfvrwz $rA, $XT",
+                (MFVRWZ gprc:$rA, vrrc:$XT), 0>;
+def : InstAlias<"mffprwz $rA, $src",
+                (MFVSRWZ gprc:$rA, f8rc:$src)>;
+def : InstAlias<"mtvrwa $XT, $rA",
+                (MTVRWA vrrc:$XT, gprc:$rA), 0>;
+def : InstAlias<"mtfprwa $dst, $rA",
+                (MTVSRWA f8rc:$dst, gprc:$rA)>;
+def : InstAlias<"mtvrwz $XT, $rA",
+                (MTVRWZ vrrc:$XT, gprc:$rA), 0>;
+def : InstAlias<"mtfprwz $dst, $rA",
+                (MTVSRWZ f8rc:$dst, gprc:$rA)>;
 
 /*  Direct moves of various widths from GPR's into VSR's. Each move lines
     the value up into element 0 (both BE and LE). Namely, entities smaller than
     a doubleword are shifted left and moved for BE. For LE, they're moved, then
     swapped to go into the least significant element of the VSR.
 */
 def MovesToVSR {
   dag BE_BYTE_0 =

llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll

 }
 
 define double @i64tof64(i64 %a) {
 entry:
   %0 = bitcast i64 %a to double
   ret double %0
 ; CHECK-P7: std 3,
 ; CHECK-P7: lfd 1,
-; CHECK: mtvsrd 1, 3
+; CHECK: mtfprd 1, 3
 }
 
 define zeroext i32 @f32toi32u(float %a) {
 entry:
   %0 = bitcast float %a to i32
   ret i32 %0
 ; CHECK-P7: stfs 1,
 ; CHECK-P7: lwz 3,

 }
 
 define double @i64utof64(i64 %a) {
 entry:
   %0 = bitcast i64 %a to double
   ret double %0
 ; CHECK-P7: std 3,
 ; CHECK-P7: lfd 1,
-; CHECK: mtvsrd 1, 3
+; CHECK: mtfprd 1, 3
 }

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

 entry:
   %b.addr = alloca i64, align 8
   store i64 %b, i64* %b.addr, align 8
   %0 = load fp128, fp128* @A, align 16
   %1 = load i64, i64* %b.addr, align 8
   %2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1)
   ret fp128 %2
 ; CHECK-LABEL: insert_exp_qp
-; CHECK-DAG: mtvsrd [[FPREG:f[0-9]+]], r3
+; CHECK-DAG: mtfprd [[FPREG:f[0-9]+]], r3
 ; CHECK-DAG: lxvx [[VECREG:v[0-9]+]]
 ; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]]
 ; CHECK: blr
 }
 
 ; Function Attrs: nounwind readnone
 declare fp128 @llvm.ppc.scalar.insert.exp.qp(fp128, i64)
 

llvm/test/CodeGen/PowerPC/direct-move-profit.ll

entry:
   %arrayidx2 = getelementptr inbounds float, float* %a, i64 %idxprom
   store float %mul, float* %arrayidx2, align 4, !tbaa !5
   %arrayidx6 = getelementptr inbounds i32, i32* %c, i64 %idxprom
   %1 = load i32, i32* %arrayidx6, align 4, !tbaa !1
   %add = add nsw i32 %1, %0
   store i32 %add, i32* %arrayidx6, align 4, !tbaa !1
   ret void
 
-; CHECK: mtvsrwa
+; CHECK: mtfprwa
 ; CHECK: blr
 
 }
 
 !0 = !{!"clang version 3.9.0"}
 !1 = !{!2, !2, i64 0}
 !2 = !{!"int", !3, i64 0}
 !3 = !{!"omnipotent char", !4, i64 0}
 !4 = !{!"Simple C++ TBAA"}
 !5 = !{!6, !6, i64 0}
 !6 = !{!"float", !3, i64 0}

llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll

entry:
   %conv = fptoui float %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: nounwind
 define float @_Z6testfcc(i8 zeroext %arg) {
 ; CHECK-LABEL: _Z6testfcc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stb r3, -1(r1)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i8, align 1
   store i8 %arg, i8* %arg.addr, align 1
   %0 = load i8, i8* %arg.addr, align 1
   %conv = uitofp i8 %0 to float
entry:
   %conv = fptoui double %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: nounwind
 define double @_Z6testdcc(i8 zeroext %arg) {
 ; CHECK-LABEL: _Z6testdcc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stb r3, -1(r1)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i8, align 1
   store i8 %arg, i8* %arg.addr, align 1
   %0 = load i8, i8* %arg.addr, align 1
   %conv = uitofp i8 %0 to double
entry:
   %conv = fptoui float %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: nounwind
 define float @_Z7testfuch(i8 zeroext %arg) {
 ; CHECK-LABEL: _Z7testfuch:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stb r3, -1(r1)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i8, align 1
   store i8 %arg, i8* %arg.addr, align 1
   %0 = load i8, i8* %arg.addr, align 1
   %conv = uitofp i8 %0 to float
entry:
   %conv = fptoui double %0 to i8
   ret i8 %conv
 }
 
 ; Function Attrs: nounwind
 define double @_Z7testduch(i8 zeroext %arg) {
 ; CHECK-LABEL: _Z7testduch:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stb r3, -1(r1)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i8, align 1
   store i8 %arg, i8* %arg.addr, align 1
   %0 = load i8, i8* %arg.addr, align 1
   %conv = uitofp i8 %0 to double
   ret double %conv
 }
 
 ; Function Attrs: nounwind
 define signext i16 @_Z6testsff(float %arg) {
 ; CHECK-LABEL: _Z6testsff:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca float, align 4
   store float %arg, float* %arg.addr, align 4
   %0 = load float, float* %arg.addr, align 4
   %conv = fptosi float %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nounwind
 define float @_Z6testfss(i16 signext %arg) {
 ; CHECK-LABEL: _Z6testfss:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwa f0, r3
+; CHECK-NEXT:    mtfprwa f0, r3
 ; CHECK-NEXT:    sth r3, -2(r1)
 ; CHECK-NEXT:    xscvsxdsp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i16, align 2
   store i16 %arg, i16* %arg.addr, align 2
   %0 = load i16, i16* %arg.addr, align 2
   %conv = sitofp i16 %0 to float
   ret float %conv
 }
 
 ; Function Attrs: nounwind
 define signext i16 @_Z6testsdd(double %arg) {
 ; CHECK-LABEL: _Z6testsdd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca double, align 8
   store double %arg, double* %arg.addr, align 8
   %0 = load double, double* %arg.addr, align 8
   %conv = fptosi double %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nounwind
 define double @_Z6testdss(i16 signext %arg) {
 ; CHECK-LABEL: _Z6testdss:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwa f0, r3
+; CHECK-NEXT:    mtfprwa f0, r3
 ; CHECK-NEXT:    sth r3, -2(r1)
 ; CHECK-NEXT:    xscvsxddp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i16, align 2
   store i16 %arg, i16* %arg.addr, align 2
   %0 = load i16, i16* %arg.addr, align 2
   %conv = sitofp i16 %0 to double
entry:
   %conv = fptoui float %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nounwind
 define float @_Z7testfust(i16 zeroext %arg) {
 ; CHECK-LABEL: _Z7testfust:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    sth r3, -2(r1)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i16, align 2
   store i16 %arg, i16* %arg.addr, align 2
   %0 = load i16, i16* %arg.addr, align 2
   %conv = uitofp i16 %0 to float
entry:
   %conv = fptoui double %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nounwind
 define double @_Z7testdust(i16 zeroext %arg) {
 ; CHECK-LABEL: _Z7testdust:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    sth r3, -2(r1)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i16, align 2
   store i16 %arg, i16* %arg.addr, align 2
   %0 = load i16, i16* %arg.addr, align 2
   %conv = uitofp i16 %0 to double
   ret double %conv
 }
 
 ; Function Attrs: nounwind
 define signext i32 @_Z6testiff(float %arg) {
 ; CHECK-LABEL: _Z6testiff:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca float, align 4
   store float %arg, float* %arg.addr, align 4
   %0 = load float, float* %arg.addr, align 4
   %conv = fptosi float %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nounwind
 define float @_Z6testfii(i32 signext %arg) {
 ; CHECK-LABEL: _Z6testfii:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwa f0, r3
+; CHECK-NEXT:    mtfprwa f0, r3
 ; CHECK-NEXT:    stw r3, -4(r1)
 ; CHECK-NEXT:    xscvsxdsp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i32, align 4
   store i32 %arg, i32* %arg.addr, align 4
   %0 = load i32, i32* %arg.addr, align 4
   %conv = sitofp i32 %0 to float
   ret float %conv
 }
 
 ; Function Attrs: nounwind
 define signext i32 @_Z6testidd(double %arg) {
 ; CHECK-LABEL: _Z6testidd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca double, align 8
   store double %arg, double* %arg.addr, align 8
   %0 = load double, double* %arg.addr, align 8
   %conv = fptosi double %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nounwind
 define double @_Z6testdii(i32 signext %arg) {
 ; CHECK-LABEL: _Z6testdii:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwa f0, r3
+; CHECK-NEXT:    mtfprwa f0, r3
 ; CHECK-NEXT:    stw r3, -4(r1)
 ; CHECK-NEXT:    xscvsxddp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i32, align 4
   store i32 %arg, i32* %arg.addr, align 4
   %0 = load i32, i32* %arg.addr, align 4
   %conv = sitofp i32 %0 to double
entry:
   %conv = fptoui float %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nounwind
 define float @_Z7testfuij(i32 zeroext %arg) {
 ; CHECK-LABEL: _Z7testfuij:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stw r3, -4(r1)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i32, align 4
   store i32 %arg, i32* %arg.addr, align 4
   %0 = load i32, i32* %arg.addr, align 4
   %conv = uitofp i32 %0 to float
entry:
   %conv = fptoui double %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nounwind
 define double @_Z7testduij(i32 zeroext %arg) {
 ; CHECK-LABEL: _Z7testduij:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stw r3, -4(r1)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i32, align 4
   store i32 %arg, i32* %arg.addr, align 4
   %0 = load i32, i32* %arg.addr, align 4
   %conv = uitofp i32 %0 to double
entry:
   %conv = fptosi float %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nounwind
 define float @_Z7testfllx(i64 %arg) {
 ; CHECK-LABEL: _Z7testfllx:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    xscvsxdsp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i64, align 8
   store i64 %arg, i64* %arg.addr, align 8
   %0 = load i64, i64* %arg.addr, align 8
   %conv = sitofp i64 %0 to float
entry:
   %conv = fptosi double %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nounwind
 define double @_Z7testdllx(i64 %arg) {
 ; CHECK-LABEL: _Z7testdllx:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    xscvsxddp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i64, align 8
   store i64 %arg, i64* %arg.addr, align 8
   %0 = load i64, i64* %arg.addr, align 8
   %conv = sitofp i64 %0 to double
entry:
   %conv = fptoui float %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nounwind
 define float @_Z8testfully(i64 %arg) {
 ; CHECK-LABEL: _Z8testfully:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i64, align 8
   store i64 %arg, i64* %arg.addr, align 8
   %0 = load i64, i64* %arg.addr, align 8
   %conv = uitofp i64 %0 to float
entry:
   %conv = fptoui double %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nounwind
 define double @_Z8testdully(i64 %arg) {
 ; CHECK-LABEL: _Z8testdully:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca i64, align 8
   store i64 %arg, i64* %arg.addr, align 8
   %0 = load i64, i64* %arg.addr, align 8
   %conv = uitofp i64 %0 to double
   ret double %conv
 }

llvm/test/CodeGen/PowerPC/fp64-to-int16.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O0 < %s | FileCheck %s
 target triple = "powerpc64le--linux-gnu"
 
 define i1 @Test(double %a) {
 ; CHECK-LABEL: Test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws 0, 1
-; CHECK-NEXT:    mfvsrwz 3, 0
+; CHECK-NEXT:    mffprwz 3, 0
 ; CHECK-NEXT:    xori 3, 3, 65534
 ; CHECK-NEXT:    cntlzw 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 5
 ; CHECK-NEXT:    # implicit-def: $x4
 ; CHECK-NEXT:    mr 4, 3
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
 entry:
   %conv = fptoui double %a to i16
   %cmp = icmp eq i16 %conv, -2
   ret i1 %cmp
 }

llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll

if.then:                                          ; preds = %entry
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
   %e.0 = phi i32 [ %tmp, %if.then ], [ undef, %entry ]
   ret i32 %e.0
 ; CHECK: @foo
 ; CHECK: mr [[NEWREG:[0-9]+]], 3
 ; CHECK: mr [[REG1:[0-9]+]], 4
-; CHECK: mtvsrd [[NEWREG2:[0-9]+]], 4
+; CHECK: mtfprd [[NEWREG2:[0-9]+]], 4
 ; CHECK: add {{[0-9]+}}, [[NEWREG]], [[REG1]]
 ; CHECK: mffprd [[REG2:[0-9]+]], [[NEWREG2]]
 ; CHECK: add {{[0-9]+}}, [[REG2]], [[NEWREG]]
 }

llvm/test/CodeGen/PowerPC/inlineasm-extendedmne.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names  \
+; RUN:     -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+define dso_local void @foo()  {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mfvsrd r0, vs33
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mffprd r0, f3
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mfvsrd r0, vs34
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mfvsrwz r0, vs33
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mffprwz r0, f3
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mfvsrwz r0, vs34
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrd vs33, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtfprd f3, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrd vs34, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrwa vs33, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtfprwa f3, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrwa vs34, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrwz vs33, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtfprwz f3, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrwz vs34, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    blr
+entry:
+  call void asm sideeffect "mfvsrd 0,33", ""()
+  call void asm sideeffect "mffprd 0,3", ""()
+  call void asm sideeffect "mfvrd  0,2", ""()
+  call void asm sideeffect "mfvsrwz 0,33", ""()
+  call void asm sideeffect "mffprwz 0,3", ""()
+  call void asm sideeffect "mfvrwz  0,2", ""()
+  call void asm sideeffect "mtvsrd 33,0", ""()
+  call void asm sideeffect "mtfprd 3,0", ""()
+  call void asm sideeffect "mtvrd  2,0", ""()
+  call void asm sideeffect "mtvsrwa 33,0", ""()
+  call void asm sideeffect "mtfprwa 3,0", ""()
+  call void asm sideeffect "mtvrwa  2,0", ""()
+  call void asm sideeffect "mtvsrwz 33,0", ""()
+  call void asm sideeffect "mtfprwz 3,0", ""()
+  call void asm sideeffect "mtvrwz  2,0", ""()
+  ret void
+}
+

llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll

 ; CHECK-VSX-NEXT:    std 5, -16(1)
 ; CHECK-VSX-NEXT:    std 6, -8(1)
 ; CHECK-VSX-NEXT:    lfd 1, -16(1)
 ; CHECK-VSX-NEXT:    lfd 2, -8(1)
 ; CHECK-VSX-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd 1, 5
-; CHECK-P9-NEXT:    mtvsrd 2, 6
+; CHECK-P9-NEXT:    mtfprd 1, 5
+; CHECK-P9-NEXT:    mtfprd 2, 6
 ; CHECK-P9-NEXT:    std 6, 72(1)
 ; CHECK-P9-NEXT:    std 5, 64(1)
 ; CHECK-P9-NEXT:    std 3, 48(1)
 ; CHECK-P9-NEXT:    std 4, 56(1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %b = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1
   %0 = load ppc_fp128, ppc_fp128* %b, align 16
   ret ppc_fp128 %0
 }
 

llvm/test/CodeGen/PowerPC/pr26180.ll

 ; RUN: llc -mcpu=generic -mtriple=powerpc64le-unknown-unknown -O0 < %s \ 
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefix=GENERIC
 ; RUN: llc -mcpu=ppc -mtriple=powerpc64le-unknown-unknown -O0 < %s \
 ; RUN:   -verify-machineinstrs | FileCheck %s
 
 define i32 @bad(double %x) {
   %1 = fptoui double %x to i32
   ret i32 %1
 
 ; CHECK: fctidz [[REG0:[0-9]+]], 1
 ; CHECK: stfd [[REG0]], [[OFF:.*]](1)
 ; CHECK: lwz {{[0-9]*}}, [[OFF]](1)
 ; GENERIC: xscvdpuxws [[REG0:[0-9]+]], 1
-; GENERIC: mfvsrwz  {{[0-9]*}}, [[REG0]]
+; GENERIC: mffprwz  {{[0-9]*}}, [[REG0]]
 }
 
 define i32 @bad1(float %x) {
 entry:
   %0 = fptosi float %x to i32
   ret i32 %0
 
 ; CHECK: fctiwz [[REG0:[0-9]+]], 1
 ; CHECK: stfd [[REG0]], [[OFF:.*]](1)
 ; CHECK: lwa {{[0-9]*}}, [[OFF]](1)
 ; GENERIC: xscvdpsxws [[REG0:[0-9]+]], 1
-; GENERIC: mfvsrwz  {{[0-9]*}}, [[REG0]]
+; GENERIC: mffprwz  {{[0-9]*}}, [[REG0]]
 }

llvm/test/CodeGen/PowerPC/pr31144.ll

 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx < %s | FileCheck %s --implicit-check-not lxsiwzx
 
 declare void @bar(double)
 
 define void @foo1(i8* %p) {
 entry:
   %0 = load i8, i8* %p, align 1
   %conv = uitofp i8 %0 to double
   call void @bar(double %conv)
   ret void
 
 ; CHECK-LABEL: @foo1
-; CHECK:     mtvsrwz
+; CHECK:     mtfprwz
 }
 
 define void @foo2(i16* %p) {
 entry:
   %0 = load i16, i16* %p, align 2
   %conv = uitofp i16 %0 to double
   call void @bar(double %conv)
   ret void
 
 ; CHECK-LABEL: @foo2
-; CHECK:       mtvsrwz
+; CHECK:       mtfprwz
 }
 

llvm/test/CodeGen/PowerPC/select-addrRegRegOnly.ll

 
 ; Function Attrs: norecurse nounwind readonly
 define float @testMultipleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 {
 ; CHECK-LABEL: testMultipleAccess:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz 4, 8(3)
 ; CHECK-NEXT:    lwz 3, 12(3)
 ; CHECK-NEXT:    add 3, 3, 4
-; CHECK-NEXT:    mtvsrwa 0, 3
+; CHECK-NEXT:    mtfprwa 0, 3
 ; CHECK-NEXT:    xscvsxdsp 1, 0
 ; CHECK-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %arr, i64 2
   %0 = load i32, i32* %arrayidx, align 4
   %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 3
   %1 = load i32, i32* %arrayidx1, align 4
   %add = add nsw i32 %1, %0
   %conv = sitofp i32 %add to float
   ret float %conv
 }

llvm/test/CodeGen/PowerPC/setrnd.ll

entry:
   %0 = tail call double @llvm.ppc.setrnd(i32 %x)
   ret double %0
 
 ; CHECK-LABEL: @test_setrnd
 ; CHECK:      # %bb.0:
 ; CHECK-DAG:   mffs 1 
 ; CHECK-DAG:   mffprd [[REG1:[0-9]+]], 1 
 ; CHECK-DAG:   rldimi [[REG1]], 3, 0, 62
-; CHECK-DAG:   mtvsrd [[REG2:[0-9]+]], [[REG1]]
+; CHECK-DAG:   mtfprd [[REG2:[0-9]+]], [[REG1]]
 ; CHECK-DAG:   mtfsf 255, [[REG2]] 
 ; CHECK:       blr
 
 ; CHECK-PWR7-LABEL: @test_setrnd
 ; CHECK-PWR7:      # %bb.0:
 ; CHECK-PWR7-DAG:   mffs 1 
 ; CHECK-PWR7-DAG:   stfd 1, -8(1) 
 ; CHECK-PWR7-DAG:   ld [[REG1:[0-9]+]], -8(1) 

llvm/test/CodeGen/PowerPC/store_fptoi.ll

 ; CHECK: lfd [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsihx [[CONV]], 0, 4
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2shw
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @dpConv2sb(double* nocapture readonly %a, i8* nocapture %b) {
 entry:
   %0 = load double, double* %a, align 8
   %conv = fptosi double %0 to i8
   store i8 %conv, i8* %b, align 1
   ret void
 
 ; CHECK-LABEL: dpConv2sb
 ; CHECK: lfd [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsibx [[CONV]], 0, 4
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2sb
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @spConv2sdw(float* nocapture readonly %a, i64* nocapture %b) {
 entry:
   %0 = load float, float* %a, align 4

 ; CHECK: lfs [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsihx [[CONV]], 0, 4
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: spConv2shw
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @spConv2sb(float* nocapture readonly %a, i8* nocapture %b) {
 entry:
   %0 = load float, float* %a, align 4
   %conv = fptosi float %0 to i8
   store i8 %conv, i8* %b, align 1
   ret void
 
 ; CHECK-LABEL: spConv2sb
 ; CHECK: lfs [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsibx [[CONV]], 0, 4
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: spConv2sb
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @dpConv2sdw_x(double* nocapture readonly %a, i64* nocapture %b,
                           i32 signext %idx) {
 entry:

 ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2shw_x
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @dpConv2sb_x(double* nocapture readonly %a, i8* nocapture %b,
                           i32 signext %idx) {
 entry:
   %0 = load double, double* %a, align 8
   %conv = fptosi double %0 to i8
   %idxprom = sext i32 %idx to i64
   %arrayidx = getelementptr inbounds i8, i8* %b, i64 %idxprom
   store i8 %conv, i8* %arrayidx, align 1
   ret void
 
 ; CHECK-LABEL: dpConv2sb_x
 ; CHECK: lfd [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsibx [[CONV]], 4, 5
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2sb_x
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @spConv2sdw_x(float* nocapture readonly %a, i64* nocapture %b,
                           i32 signext %idx) {
 entry:

 ; CHECK-DAG: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: spConv2shw_x
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]]
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @spConv2sb_x(float* nocapture readonly %a, i8* nocapture %b,
                           i32 signext %idx) {
 entry:
   %0 = load float, float* %a, align 4
   %conv = fptosi float %0 to i8
   %idxprom = sext i32 %idx to i64
   %arrayidx = getelementptr inbounds i8, i8* %b, i64 %idxprom
   store i8 %conv, i8* %arrayidx, align 1
   ret void
 
 ; CHECK-LABEL: spConv2sb_x
 ; CHECK: lfs [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsibx [[CONV]], 4, 5
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: spConv2sb_x
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; ==========================================
 ; Tests for store of fp_to_uint converstions
 ; ==========================================
 

 ; CHECK: lfd [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsihx [[CONV]], 0, 4
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2uhw
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @dpConv2ub(double* nocapture readonly %a, i8* nocapture %b) {
 entry:
   %0 = load double, double* %a, align 8
   %conv = fptoui double %0 to i8
   store i8 %conv, i8* %b, align 1
   ret void
 
 ; CHECK-LABEL: dpConv2ub
 ; CHECK: lfd [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsibx [[CONV]], 0, 4
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2ub
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @spConv2udw(float* nocapture readonly %a, i64* nocapture %b) {
 entry:
   %0 = load float, float* %a, align 4

 ; CHECK: lfs [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsihx [[CONV]], 0, 4
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: spConv2uhw
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @spConv2ub(float* nocapture readonly %a, i8* nocapture %b) {
 entry:
   %0 = load float, float* %a, align 4
   %conv = fptoui float %0 to i8
   store i8 %conv, i8* %b, align 1
   ret void
 
 ; CHECK-LABEL: spConv2ub
 ; CHECK: lfs [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsibx [[CONV]], 0, 4
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: spConv2ub
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @dpConv2udw_x(double* nocapture readonly %a, i64* nocapture %b,
                           i32 zeroext %idx) {
 entry:

 ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2uhw_x
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @dpConv2ub_x(double* nocapture readonly %a, i8* nocapture %b,
                           i32 zeroext %idx) {
 entry:
   %0 = load double, double* %a, align 8
   %conv = fptoui double %0 to i8
   %idxprom = zext i32 %idx to i64
   %arrayidx = getelementptr inbounds i8, i8* %b, i64 %idxprom
   store i8 %conv, i8* %arrayidx, align 1
   ret void
 
 ; CHECK-LABEL: dpConv2ub_x
 ; CHECK: lfd [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsibx [[CONV]], 4, 5
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2ub_x
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @spConv2udw_x(float* nocapture readonly %a, i64* nocapture %b,
                           i32 zeroext %idx) {
 entry:

 ; CHECK-DAG: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: spConv2uhw_x
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]]
 ; CHECK-PWR8-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @spConv2ub_x(float* nocapture readonly %a, i8* nocapture %b,
                           i32 zeroext %idx) {
 entry:
   %0 = load float, float* %a, align 4
   %conv = fptoui float %0 to i8
   %idxprom = zext i32 %idx to i64
   %arrayidx = getelementptr inbounds i8, i8* %b, i64 %idxprom
   store i8 %conv, i8* %arrayidx, align 1
   ret void
 
 ; CHECK-LABEL: spConv2ub_x
 ; CHECK: lfs [[LD:[0-9]+]], 0(3)
 ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-NEXT: stxsibx [[CONV]], 4, 5
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: spConv2ub_x
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }

llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll

 ; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \
 ; RUN:   -check-prefix=P8LE
 define dso_local <2 x double> @test1(<8 x i16> %a) {
 ; P9BE-LABEL: test1:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P9BE-NEXT:    mtvsrwz f0, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P9BE-NEXT:    mtvsrwz f1, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    xscvuxddp f0, f0
 ; P9BE-NEXT:    xscvuxddp f1, f1
 ; P9BE-NEXT:    xxmrghd v2, vs0, vs1
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: test1:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P9LE-NEXT:    mtvsrwz f0, r3
+; P9LE-NEXT:    mtfprwz f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P9LE-NEXT:    mtvsrwz f1, r3
+; P9LE-NEXT:    mtfprwz f1, r3
 ; P9LE-NEXT:    xscvuxddp f0, f0
 ; P9LE-NEXT:    xscvuxddp f1, f1
 ; P9LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: test1:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    mfvsrd r3, v2
 ; P8BE-NEXT:    rldicl r4, r3, 16, 48
 ; P8BE-NEXT:    rldicl r3, r3, 32, 48
 ; P8BE-NEXT:    rlwinm r4, r4, 0, 16, 31
 ; P8BE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P8BE-NEXT:    mtvsrwz f0, r4
-; P8BE-NEXT:    mtvsrwz f1, r3
+; P8BE-NEXT:    mtfprwz f0, r4
+; P8BE-NEXT:    mtfprwz f1, r3
 ; P8BE-NEXT:    xscvuxddp f0, f0
 ; P8BE-NEXT:    xscvuxddp f1, f1
 ; P8BE-NEXT:    xxmrghd v2, vs0, vs1
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: test1:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    mfvsrd r3, f0
 ; P8LE-NEXT:    clrldi r4, r3, 48
 ; P8LE-NEXT:    rldicl r3, r3, 48, 48
 ; P8LE-NEXT:    rlwinm r4, r4, 0, 16, 31
 ; P8LE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P8LE-NEXT:    mtvsrwz f0, r4
-; P8LE-NEXT:    mtvsrwz f1, r3
+; P8LE-NEXT:    mtfprwz f0, r4
+; P8LE-NEXT:    mtfprwz f1, r3
 ; P8LE-NEXT:    xscvuxddp f0, f0
 ; P8LE-NEXT:    xscvuxddp f1, f1
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %a, i32 0
   %conv = uitofp i16 %vecext to double
   %vecinit = insertelement <2 x double> undef, double %conv, i32 0

 ; P9LE-NEXT:    xscvuxddp f1, f1
 ; P9LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: test2:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; P8BE-NEXT:    mfvsrwz r4, v3
-; P8BE-NEXT:    mtvsrwz f1, r4
+; P8BE-NEXT:    mtfprwz f1, r4
 ; P8BE-NEXT:    mfvsrwz r3, f0
 ; P8BE-NEXT:    xscvuxddp f1, f1
-; P8BE-NEXT:    mtvsrwz f0, r3
+; P8BE-NEXT:    mtfprwz f0, r3
 ; P8BE-NEXT:    xscvuxddp f0, f0
 ; P8BE-NEXT:    xxmrghd v2, vs0, vs1
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: test2:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    xxsldwi vs1, v3, v3, 1
 ; P8LE-NEXT:    mfvsrwz r3, f0
 ; P8LE-NEXT:    mfvsrwz r4, f1
-; P8LE-NEXT:    mtvsrwz f0, r3
-; P8LE-NEXT:    mtvsrwz f1, r4
+; P8LE-NEXT:    mtfprwz f0, r3
+; P8LE-NEXT:    mtfprwz f1, r4
 ; P8LE-NEXT:    xscvuxddp f0, f0
 ; P8LE-NEXT:    xscvuxddp f1, f1
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %a, i32 0
   %conv = uitofp i32 %vecext to double
   %vecinit = insertelement <2 x double> undef, double %conv, i32 0
   %vecext1 = extractelement <4 x i32> %b, i32 1
   %conv2 = uitofp i32 %vecext1 to double
   %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
   ret <2 x double> %vecinit3
 }

llvm/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 \
 ; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 ; Ensure we don't crash by trying to convert directly from a subword load
 ; to a ppc_fp128 as we do for conversions to f32/f64.
 define ppc_fp128 @test(i16* nocapture readonly %Ptr) {
 entry:
   %0 = load i16, i16* %Ptr, align 2
   %conv = uitofp i16 %0 to ppc_fp128
   ret ppc_fp128 %conv
 ; CHECK: lhz [[LD:[0-9]+]], 0(3)
-; CHECK: mtvsrwa [[MV:[0-9]+]], [[LD]]
+; CHECK: mtfprwa [[MV:[0-9]+]], [[LD]]
 ; CHECK: xscvsxddp [[CONV:[0-9]+]], [[MV]]
 ; CHECK: bl __gcc_qadd
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

 ; CHECK-P8-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpuxws f0, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
+; CHECK-P9-NEXT:    mffprwz r3, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    mtvsrws v3, r3
 ; CHECK-P9-NEXT:    xscvdpuxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
+; CHECK-P9-NEXT:    mffprwz r3, f0
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpuxws f0, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    mtvsrws v3, r3
 ; CHECK-BE-NEXT:    xscvdpuxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <2 x double> %a to <2 x i32>
   %1 = bitcast <2 x i32> %0 to i64
   ret i64 %1

 ; CHECK-P8-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
+; CHECK-P9-NEXT:    mffprwz r3, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    mtvsrws v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
+; CHECK-P9-NEXT:    mffprwz r3, f0
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    mtvsrws v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <2 x double> %a to <2 x i32>
   %1 = bitcast <2 x i32> %0 to i64
   ret i64 %1

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mtvsrd f0, r3
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 48
 ; CHECK-P8-NEXT:    rldicl r3, r3, 48, 48
 ; CHECK-P8-NEXT:    rlwinm r4, r4, 0, 16, 31
 ; CHECK-P8-NEXT:    rlwinm r3, r3, 0, 16, 31
-; CHECK-P8-NEXT:    mtvsrwz f0, r4
-; CHECK-P8-NEXT:    mtvsrwz f1, r3
+; CHECK-P8-NEXT:    mtfprwz f0, r4
+; CHECK-P8-NEXT:    mtfprwz f1, r3
 ; CHECK-P8-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P8-NEXT:    xscvuxdsp f1, f1
 ; CHECK-P8-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P8-NEXT:    xscvdpspn vs1, f1
 ; CHECK-P8-NEXT:    xxsldwi v2, vs0, vs0, 1
 ; CHECK-P8-NEXT:    xxsldwi v3, vs1, vs1, 1
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 16, 31
-; CHECK-P9-NEXT:    mtvsrwz f0, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    li r3, 2
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 1
-; CHECK-P9-NEXT:    mtvsrwz f0, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 1
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    li r3, 2
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
 ; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; CHECK-BE-NEXT:    mtvsrwz f0, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
 ; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtvsrwz f0, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = uitofp <2 x i16> %0 to <2 x float>

 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mtvsrd f0, r3
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 48
 ; CHECK-P8-NEXT:    rldicl r3, r3, 48, 48
 ; CHECK-P8-NEXT:    extsh r4, r4
 ; CHECK-P8-NEXT:    extsh r3, r3
-; CHECK-P8-NEXT:    mtvsrwa f0, r4
-; CHECK-P8-NEXT:    mtvsrwa f1, r3
+; CHECK-P8-NEXT:    mtfprwa f0, r4
+; CHECK-P8-NEXT:    mtfprwa f1, r3
 ; CHECK-P8-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P8-NEXT:    xscvsxdsp f1, f1
 ; CHECK-P8-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P8-NEXT:    xscvdpspn vs1, f1
 ; CHECK-P8-NEXT:    xxsldwi v2, vs0, vs0, 1
 ; CHECK-P8-NEXT:    xxsldwi v3, vs1, vs1, 1
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
 ; CHECK-P9-NEXT:    extsh r3, r3
-; CHECK-P9-NEXT:    mtvsrwa f0, r3
+; CHECK-P9-NEXT:    mtfprwa f0, r3
 ; CHECK-P9-NEXT:    li r3, 2
 ; CHECK-P9-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
 ; CHECK-P9-NEXT:    extsh r3, r3
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 1
-; CHECK-P9-NEXT:    mtvsrwa f0, r3
+; CHECK-P9-NEXT:    mtfprwa f0, r3
 ; CHECK-P9-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 1
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    li r3, 2
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
 ; CHECK-BE-NEXT:    extsh r3, r3
-; CHECK-BE-NEXT:    mtvsrwa f0, r3
+; CHECK-BE-NEXT:    mtfprwa f0, r3
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
 ; CHECK-BE-NEXT:    extsh r3, r3
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtvsrwa f0, r3
+; CHECK-BE-NEXT:    mtfprwa f0, r3
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = sitofp <2 x i16> %0 to <2 x float>

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mtvsrd f0, r3
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 56
 ; CHECK-P8-NEXT:    rldicl r3, r3, 56, 56
 ; CHECK-P8-NEXT:    rlwinm r4, r4, 0, 24, 31
 ; CHECK-P8-NEXT:    rlwinm r3, r3, 0, 24, 31
-; CHECK-P8-NEXT:    mtvsrwz f0, r4
-; CHECK-P8-NEXT:    mtvsrwz f1, r3
+; CHECK-P8-NEXT:    mtfprwz f0, r4
+; CHECK-P8-NEXT:    mtfprwz f1, r3
 ; CHECK-P8-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P8-NEXT:    xscvuxdsp f1, f1
 ; CHECK-P8-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P8-NEXT:    xscvdpspn vs1, f1
 ; CHECK-P8-NEXT:    xxsldwi v2, vs0, vs0, 1
 ; CHECK-P8-NEXT:    xxsldwi v3, vs1, vs1, 1
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vextubrx r3, r3, v2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 24, 31
-; CHECK-P9-NEXT:    mtvsrwz f0, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    li r3, 1
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    vextubrx r3, r3, v2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 24, 31
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 1
-; CHECK-P9-NEXT:    mtvsrwz f0, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 1
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    li r3, 1
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
 ; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 24, 31
-; CHECK-BE-NEXT:    mtvsrwz f0, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
 ; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 24, 31
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtvsrwz f0, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = uitofp <2 x i8> %0 to <2 x float>

 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mtvsrd f0, r3
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 56
 ; CHECK-P8-NEXT:    rldicl r3, r3, 56, 56
 ; CHECK-P8-NEXT:    extsb r4, r4
 ; CHECK-P8-NEXT:    extsb r3, r3
-; CHECK-P8-NEXT:    mtvsrwa f0, r4
-; CHECK-P8-NEXT:    mtvsrwa f1, r3
+; CHECK-P8-NEXT:    mtfprwa f0, r4
+; CHECK-P8-NEXT:    mtfprwa f1, r3
 ; CHECK-P8-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P8-NEXT:    xscvsxdsp f1, f1
 ; CHECK-P8-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P8-NEXT:    xscvdpspn vs1, f1
 ; CHECK-P8-NEXT:    xxsldwi v2, vs0, vs0, 1
 ; CHECK-P8-NEXT:    xxsldwi v3, vs1, vs1, 1
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vextubrx r3, r3, v2
 ; CHECK-P9-NEXT:    extsb r3, r3
-; CHECK-P9-NEXT:    mtvsrwa f0, r3
+; CHECK-P9-NEXT:    mtfprwa f0, r3
 ; CHECK-P9-NEXT:    li r3, 1
 ; CHECK-P9-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    vextubrx r3, r3, v2
 ; CHECK-P9-NEXT:    extsb r3, r3
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 1
-; CHECK-P9-NEXT:    mtvsrwa f0, r3
+; CHECK-P9-NEXT:    mtfprwa f0, r3
 ; CHECK-P9-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 1
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    li r3, 1
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
 ; CHECK-BE-NEXT:    extsb r3, r3
-; CHECK-BE-NEXT:    mtvsrwa f0, r3
+; CHECK-BE-NEXT:    mtfprwa f0, r3
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
 ; CHECK-BE-NEXT:    extsb r3, r3
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtvsrwa f0, r3
+; CHECK-BE-NEXT:    mtfprwa f0, r3
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = sitofp <2 x i8> %0 to <2 x float>

llvm/test/MC/Disassembler/PowerPC/vsx.txt

 0xf0 0xe3 0xda 0x90
 
 # CHECK: xxswapd 7, 63
 0xf0 0xff 0xfa 0x56
 
 # CHECK: mfvsrd 3, 40
 0x7d 0x03 0x00 0x67
 
-# CHECK: mfvsrwz 5, 0
+# CHECK: mffprwz 5, 0
 0x7c 0x05 0x00 0xe6
 
-# CHECK: mtvsrd 0, 3
+# CHECK: mtfprd 0, 3
 0x7c 0x03 0x01 0x66
 
-# CHECK: mtvsrwa 0, 3
+# CHECK: mtfprwa 0, 3
 0x7c 0x03 0x01 0xa6
 
-# CHECK: mtvsrwz 0, 3
+# CHECK: mtfprwz 0, 3
 0x7c 0x03 0x01 0xe6
 
 # Power9 Instructions:
 
 # CHECK: xscpsgnqp 7, 31, 27
 0xfc 0xff 0xd8 0xc8
 
 # CHECK: xsabsqp 7, 27

llvm/test/MC/PowerPC/vsx.s

 
 # Move to/from VSR
 # CHECK-BE: mfvsrd 3, 40                       # encoding: [0x7d,0x03,0x00,0x67]
 # CHECK-LE: mfvsrd 3, 40                       # encoding: [0x67,0x00,0x03,0x7d]
             mfvsrd 3, 40
 # CHECK-BE: mfvsrd 3, 40                       # encoding: [0x7d,0x03,0x00,0x67]
 # CHECK-LE: mfvsrd 3, 40                       # encoding: [0x67,0x00,0x03,0x7d]
             mfvrd 3, 8
-# CHECK-BE: mfvsrwz 5, 0                       # encoding: [0x7c,0x05,0x00,0xe6]
-# CHECK-LE: mfvsrwz 5, 0                       # encoding: [0xe6,0x00,0x05,0x7c]
+# CHECK-BE: mffprwz 5, 0                       # encoding: [0x7c,0x05,0x00,0xe6]
+# CHECK-LE: mffprwz 5, 0                       # encoding: [0xe6,0x00,0x05,0x7c]
             mfvsrwz 5, 0
-# CHECK-BE: mtvsrd 0, 3                        # encoding: [0x7c,0x03,0x01,0x66]
-# CHECK-LE: mtvsrd 0, 3                        # encoding: [0x66,0x01,0x03,0x7c]
+# CHECK-BE: mtfprd 0, 3                        # encoding: [0x7c,0x03,0x01,0x66]
+# CHECK-LE: mtfprd 0, 3                        # encoding: [0x66,0x01,0x03,0x7c]
             mtvsrd 0, 3
-# CHECK-BE: mtvsrwa 0, 3                       # encoding: [0x7c,0x03,0x01,0xa6]
-# CHECK-LE: mtvsrwa 0, 3                       # encoding: [0xa6,0x01,0x03,0x7c]
+# CHECK-BE: mtfprwa 0, 3                       # encoding: [0x7c,0x03,0x01,0xa6]
+# CHECK-LE: mtfprwa 0, 3                       # encoding: [0xa6,0x01,0x03,0x7c]
             mtvsrwa 0, 3
-# CHECK-BE: mtvsrwz 0, 3                       # encoding: [0x7c,0x03,0x01,0xe6]
-# CHECK-LE: mtvsrwz 0, 3                       # encoding: [0xe6,0x01,0x03,0x7c]
+# CHECK-BE: mtfprwz 0, 3                       # encoding: [0x7c,0x03,0x01,0xe6]
+# CHECK-LE: mtfprwz 0, 3                       # encoding: [0xe6,0x01,0x03,0x7c]
             mtvsrwz 0, 3
 
 # Power9 Instructions:
 
 # Copy Sign
 # CHECK-BE: xscpsgnqp 7, 31, 27                # encoding: [0xfc,0xff,0xd8,0xc8]
 # CHECK-LE: xscpsgnqp 7, 31, 27                # encoding: [0xc8,0xd8,0xff,0xfc]
             xscpsgnqp 7, 31, 27