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author
Jinsong Ji
committedAug 29, 2019
[PowerPC] Support extended mnemonics mffprwz etc.
Summary: Reported in opencv/opencv#15413. We have serveral extended mnemonics for Move To/From Vector-Scalar Register Instructions eg: mffprd,mtfprd etc. We only support one of them, this patch add the others. Reviewers: nemanjai, steven.zhang, hfinkel, #powerpc Reviewed By: hfinkel Subscribers: wuzish, qcolombet, hiraditya, kbarton, MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66963 llvm-svn: 370411
·
llvmorg-21-initllvmorg-10.0.0-rc1
1 parent 04e657b commit 1ed7d21

22 files changed

+276
-109
lines changed
 

‎llvm/lib/Target/PowerPC/P9InstrResources.td

+3-2
Original file line numberDiff line numberDiff line change
@@ -125,8 +125,8 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
125125
(instregex "SRAD(I)?$"),
126126
(instregex "EXTSWSLI_32_64$"),
127127
(instregex "MFV(S)?RD$"),
128-
(instregex "MTVSRD$"),
129-
(instregex "MTVSRW(A|Z)$"),
128+
(instregex "MTV(S)?RD$"),
129+
(instregex "MTV(S)?RW(A|Z)$"),
130130
(instregex "CMP(WI|LWI|W|LW)(8)?$"),
131131
(instregex "CMP(L)?D(I)?$"),
132132
(instregex "SUBF(I)?C(8)?$"),
@@ -159,6 +159,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
159159
XSNEGDP,
160160
XSCPSGNDP,
161161
MFVSRWZ,
162+
MFVRWZ,
162163
EXTSWSLI,
163164
SRADI_32,
164165
RLDIC,

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

+33
Original file line numberDiff line numberDiff line change
@@ -1593,16 +1593,33 @@ let Predicates = [HasDirectMove] in {
15931593
def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
15941594
"mfvsrwz $rA, $XT", IIC_VecGeneral,
15951595
[(set i32:$rA, (PPCmfvsr f64:$XT))]>;
1596+
let isCodeGenOnly = 1 in
1597+
def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
1598+
"mfvsrwz $rA, $XT", IIC_VecGeneral,
1599+
[]>;
15961600
def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
15971601
"mtvsrd $XT, $rA", IIC_VecGeneral,
15981602
[(set f64:$XT, (PPCmtvsra i64:$rA))]>,
15991603
Requires<[In64BitMode]>;
1604+
let isCodeGenOnly = 1 in
1605+
def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$rA),
1606+
"mtvsrd $XT, $rA", IIC_VecGeneral,
1607+
[]>,
1608+
Requires<[In64BitMode]>;
16001609
def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
16011610
"mtvsrwa $XT, $rA", IIC_VecGeneral,
16021611
[(set f64:$XT, (PPCmtvsra i32:$rA))]>;
1612+
let isCodeGenOnly = 1 in
1613+
def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$rA),
1614+
"mtvsrwa $XT, $rA", IIC_VecGeneral,
1615+
[]>;
16031616
def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
16041617
"mtvsrwz $XT, $rA", IIC_VecGeneral,
16051618
[(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
1619+
let isCodeGenOnly = 1 in
1620+
def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$rA),
1621+
"mtvsrwz $XT, $rA", IIC_VecGeneral,
1622+
[]>;
16061623
} // HasDirectMove
16071624

16081625
let Predicates = [IsISA3_0, HasDirectMove] in {
@@ -1626,6 +1643,22 @@ def : InstAlias<"mfvrd $rA, $XT",
16261643
(MFVRD g8rc:$rA, vrrc:$XT), 0>;
16271644
def : InstAlias<"mffprd $rA, $src",
16281645
(MFVSRD g8rc:$rA, f8rc:$src)>;
1646+
def : InstAlias<"mtvrd $XT, $rA",
1647+
(MTVRD vrrc:$XT, g8rc:$rA), 0>;
1648+
def : InstAlias<"mtfprd $dst, $rA",
1649+
(MTVSRD f8rc:$dst, g8rc:$rA)>;
1650+
def : InstAlias<"mfvrwz $rA, $XT",
1651+
(MFVRWZ gprc:$rA, vrrc:$XT), 0>;
1652+
def : InstAlias<"mffprwz $rA, $src",
1653+
(MFVSRWZ gprc:$rA, f8rc:$src)>;
1654+
def : InstAlias<"mtvrwa $XT, $rA",
1655+
(MTVRWA vrrc:$XT, gprc:$rA), 0>;
1656+
def : InstAlias<"mtfprwa $dst, $rA",
1657+
(MTVSRWA f8rc:$dst, gprc:$rA)>;
1658+
def : InstAlias<"mtvrwz $XT, $rA",
1659+
(MTVRWZ vrrc:$XT, gprc:$rA), 0>;
1660+
def : InstAlias<"mtfprwz $dst, $rA",
1661+
(MTVSRWZ f8rc:$dst, gprc:$rA)>;
16291662

16301663
/* Direct moves of various widths from GPR's into VSR's. Each move lines
16311664
the value up into element 0 (both BE and LE). Namely, entities smaller than

‎llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ entry:
4040
ret double %0
4141
; CHECK-P7: std 3,
4242
; CHECK-P7: lfd 1,
43-
; CHECK: mtvsrd 1, 3
43+
; CHECK: mtfprd 1, 3
4444
}
4545

4646
define zeroext i32 @f32toi32u(float %a) {
@@ -80,5 +80,5 @@ entry:
8080
ret double %0
8181
; CHECK-P7: std 3,
8282
; CHECK-P7: lfd 1,
83-
; CHECK: mtvsrd 1, 3
83+
; CHECK: mtfprd 1, 3
8484
}

‎llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ entry:
112112
%2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1)
113113
ret fp128 %2
114114
; CHECK-LABEL: insert_exp_qp
115-
; CHECK-DAG: mtvsrd [[FPREG:f[0-9]+]], r3
115+
; CHECK-DAG: mtfprd [[FPREG:f[0-9]+]], r3
116116
; CHECK-DAG: lxvx [[VECREG:v[0-9]+]]
117117
; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]]
118118
; CHECK: blr

‎llvm/test/CodeGen/PowerPC/direct-move-profit.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ entry:
6969
store i32 %add, i32* %arrayidx6, align 4, !tbaa !1
7070
ret void
7171

72-
; CHECK: mtvsrwa
72+
; CHECK: mtfprwa
7373
; CHECK: blr
7474

7575
}

‎llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll

+20-20
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ entry:
2525
define float @_Z6testfcc(i8 zeroext %arg) {
2626
; CHECK-LABEL: _Z6testfcc:
2727
; CHECK: # %bb.0: # %entry
28-
; CHECK-NEXT: mtvsrwz f0, r3
28+
; CHECK-NEXT: mtfprwz f0, r3
2929
; CHECK-NEXT: stb r3, -1(r1)
3030
; CHECK-NEXT: xscvuxdsp f1, f0
3131
; CHECK-NEXT: blr
@@ -58,7 +58,7 @@ entry:
5858
define double @_Z6testdcc(i8 zeroext %arg) {
5959
; CHECK-LABEL: _Z6testdcc:
6060
; CHECK: # %bb.0: # %entry
61-
; CHECK-NEXT: mtvsrwz f0, r3
61+
; CHECK-NEXT: mtfprwz f0, r3
6262
; CHECK-NEXT: stb r3, -1(r1)
6363
; CHECK-NEXT: xscvuxddp f1, f0
6464
; CHECK-NEXT: blr
@@ -91,7 +91,7 @@ entry:
9191
define float @_Z7testfuch(i8 zeroext %arg) {
9292
; CHECK-LABEL: _Z7testfuch:
9393
; CHECK: # %bb.0: # %entry
94-
; CHECK-NEXT: mtvsrwz f0, r3
94+
; CHECK-NEXT: mtfprwz f0, r3
9595
; CHECK-NEXT: stb r3, -1(r1)
9696
; CHECK-NEXT: xscvuxdsp f1, f0
9797
; CHECK-NEXT: blr
@@ -124,7 +124,7 @@ entry:
124124
define double @_Z7testduch(i8 zeroext %arg) {
125125
; CHECK-LABEL: _Z7testduch:
126126
; CHECK: # %bb.0: # %entry
127-
; CHECK-NEXT: mtvsrwz f0, r3
127+
; CHECK-NEXT: mtfprwz f0, r3
128128
; CHECK-NEXT: stb r3, -1(r1)
129129
; CHECK-NEXT: xscvuxddp f1, f0
130130
; CHECK-NEXT: blr
@@ -142,7 +142,7 @@ define signext i16 @_Z6testsff(float %arg) {
142142
; CHECK: # %bb.0: # %entry
143143
; CHECK-NEXT: xscvdpsxws f0, f1
144144
; CHECK-NEXT: stfs f1, -4(r1)
145-
; CHECK-NEXT: mfvsrwz r3, f0
145+
; CHECK-NEXT: mffprwz r3, f0
146146
; CHECK-NEXT: extsw r3, r3
147147
; CHECK-NEXT: blr
148148
entry:
@@ -157,7 +157,7 @@ entry:
157157
define float @_Z6testfss(i16 signext %arg) {
158158
; CHECK-LABEL: _Z6testfss:
159159
; CHECK: # %bb.0: # %entry
160-
; CHECK-NEXT: mtvsrwa f0, r3
160+
; CHECK-NEXT: mtfprwa f0, r3
161161
; CHECK-NEXT: sth r3, -2(r1)
162162
; CHECK-NEXT: xscvsxdsp f1, f0
163163
; CHECK-NEXT: blr
@@ -175,7 +175,7 @@ define signext i16 @_Z6testsdd(double %arg) {
175175
; CHECK: # %bb.0: # %entry
176176
; CHECK-NEXT: xscvdpsxws f0, f1
177177
; CHECK-NEXT: stfd f1, -8(r1)
178-
; CHECK-NEXT: mfvsrwz r3, f0
178+
; CHECK-NEXT: mffprwz r3, f0
179179
; CHECK-NEXT: extsw r3, r3
180180
; CHECK-NEXT: blr
181181
entry:
@@ -190,7 +190,7 @@ entry:
190190
define double @_Z6testdss(i16 signext %arg) {
191191
; CHECK-LABEL: _Z6testdss:
192192
; CHECK: # %bb.0: # %entry
193-
; CHECK-NEXT: mtvsrwa f0, r3
193+
; CHECK-NEXT: mtfprwa f0, r3
194194
; CHECK-NEXT: sth r3, -2(r1)
195195
; CHECK-NEXT: xscvsxddp f1, f0
196196
; CHECK-NEXT: blr
@@ -223,7 +223,7 @@ entry:
223223
define float @_Z7testfust(i16 zeroext %arg) {
224224
; CHECK-LABEL: _Z7testfust:
225225
; CHECK: # %bb.0: # %entry
226-
; CHECK-NEXT: mtvsrwz f0, r3
226+
; CHECK-NEXT: mtfprwz f0, r3
227227
; CHECK-NEXT: sth r3, -2(r1)
228228
; CHECK-NEXT: xscvuxdsp f1, f0
229229
; CHECK-NEXT: blr
@@ -256,7 +256,7 @@ entry:
256256
define double @_Z7testdust(i16 zeroext %arg) {
257257
; CHECK-LABEL: _Z7testdust:
258258
; CHECK: # %bb.0: # %entry
259-
; CHECK-NEXT: mtvsrwz f0, r3
259+
; CHECK-NEXT: mtfprwz f0, r3
260260
; CHECK-NEXT: sth r3, -2(r1)
261261
; CHECK-NEXT: xscvuxddp f1, f0
262262
; CHECK-NEXT: blr
@@ -274,7 +274,7 @@ define signext i32 @_Z6testiff(float %arg) {
274274
; CHECK: # %bb.0: # %entry
275275
; CHECK-NEXT: xscvdpsxws f0, f1
276276
; CHECK-NEXT: stfs f1, -4(r1)
277-
; CHECK-NEXT: mfvsrwz r3, f0
277+
; CHECK-NEXT: mffprwz r3, f0
278278
; CHECK-NEXT: extsw r3, r3
279279
; CHECK-NEXT: blr
280280
entry:
@@ -289,7 +289,7 @@ entry:
289289
define float @_Z6testfii(i32 signext %arg) {
290290
; CHECK-LABEL: _Z6testfii:
291291
; CHECK: # %bb.0: # %entry
292-
; CHECK-NEXT: mtvsrwa f0, r3
292+
; CHECK-NEXT: mtfprwa f0, r3
293293
; CHECK-NEXT: stw r3, -4(r1)
294294
; CHECK-NEXT: xscvsxdsp f1, f0
295295
; CHECK-NEXT: blr
@@ -307,7 +307,7 @@ define signext i32 @_Z6testidd(double %arg) {
307307
; CHECK: # %bb.0: # %entry
308308
; CHECK-NEXT: xscvdpsxws f0, f1
309309
; CHECK-NEXT: stfd f1, -8(r1)
310-
; CHECK-NEXT: mfvsrwz r3, f0
310+
; CHECK-NEXT: mffprwz r3, f0
311311
; CHECK-NEXT: extsw r3, r3
312312
; CHECK-NEXT: blr
313313
entry:
@@ -322,7 +322,7 @@ entry:
322322
define double @_Z6testdii(i32 signext %arg) {
323323
; CHECK-LABEL: _Z6testdii:
324324
; CHECK: # %bb.0: # %entry
325-
; CHECK-NEXT: mtvsrwa f0, r3
325+
; CHECK-NEXT: mtfprwa f0, r3
326326
; CHECK-NEXT: stw r3, -4(r1)
327327
; CHECK-NEXT: xscvsxddp f1, f0
328328
; CHECK-NEXT: blr
@@ -355,7 +355,7 @@ entry:
355355
define float @_Z7testfuij(i32 zeroext %arg) {
356356
; CHECK-LABEL: _Z7testfuij:
357357
; CHECK: # %bb.0: # %entry
358-
; CHECK-NEXT: mtvsrwz f0, r3
358+
; CHECK-NEXT: mtfprwz f0, r3
359359
; CHECK-NEXT: stw r3, -4(r1)
360360
; CHECK-NEXT: xscvuxdsp f1, f0
361361
; CHECK-NEXT: blr
@@ -388,7 +388,7 @@ entry:
388388
define double @_Z7testduij(i32 zeroext %arg) {
389389
; CHECK-LABEL: _Z7testduij:
390390
; CHECK: # %bb.0: # %entry
391-
; CHECK-NEXT: mtvsrwz f0, r3
391+
; CHECK-NEXT: mtfprwz f0, r3
392392
; CHECK-NEXT: stw r3, -4(r1)
393393
; CHECK-NEXT: xscvuxddp f1, f0
394394
; CHECK-NEXT: blr
@@ -420,7 +420,7 @@ entry:
420420
define float @_Z7testfllx(i64 %arg) {
421421
; CHECK-LABEL: _Z7testfllx:
422422
; CHECK: # %bb.0: # %entry
423-
; CHECK-NEXT: mtvsrd f0, r3
423+
; CHECK-NEXT: mtfprd f0, r3
424424
; CHECK-NEXT: std r3, -8(r1)
425425
; CHECK-NEXT: xscvsxdsp f1, f0
426426
; CHECK-NEXT: blr
@@ -452,7 +452,7 @@ entry:
452452
define double @_Z7testdllx(i64 %arg) {
453453
; CHECK-LABEL: _Z7testdllx:
454454
; CHECK: # %bb.0: # %entry
455-
; CHECK-NEXT: mtvsrd f0, r3
455+
; CHECK-NEXT: mtfprd f0, r3
456456
; CHECK-NEXT: std r3, -8(r1)
457457
; CHECK-NEXT: xscvsxddp f1, f0
458458
; CHECK-NEXT: blr
@@ -484,7 +484,7 @@ entry:
484484
define float @_Z8testfully(i64 %arg) {
485485
; CHECK-LABEL: _Z8testfully:
486486
; CHECK: # %bb.0: # %entry
487-
; CHECK-NEXT: mtvsrd f0, r3
487+
; CHECK-NEXT: mtfprd f0, r3
488488
; CHECK-NEXT: std r3, -8(r1)
489489
; CHECK-NEXT: xscvuxdsp f1, f0
490490
; CHECK-NEXT: blr
@@ -516,7 +516,7 @@ entry:
516516
define double @_Z8testdully(i64 %arg) {
517517
; CHECK-LABEL: _Z8testdully:
518518
; CHECK: # %bb.0: # %entry
519-
; CHECK-NEXT: mtvsrd f0, r3
519+
; CHECK-NEXT: mtfprd f0, r3
520520
; CHECK-NEXT: std r3, -8(r1)
521521
; CHECK-NEXT: xscvuxddp f1, f0
522522
; CHECK-NEXT: blr

‎llvm/test/CodeGen/PowerPC/fp64-to-int16.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ define i1 @Test(double %a) {
66
; CHECK-LABEL: Test:
77
; CHECK: # %bb.0: # %entry
88
; CHECK-NEXT: xscvdpsxws 0, 1
9-
; CHECK-NEXT: mfvsrwz 3, 0
9+
; CHECK-NEXT: mffprwz 3, 0
1010
; CHECK-NEXT: xori 3, 3, 65534
1111
; CHECK-NEXT: cntlzw 3, 3
1212
; CHECK-NEXT: srwi 3, 3, 5

‎llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ if.end: ; preds = %if.then, %entry
1717
; CHECK: @foo
1818
; CHECK: mr [[NEWREG:[0-9]+]], 3
1919
; CHECK: mr [[REG1:[0-9]+]], 4
20-
; CHECK: mtvsrd [[NEWREG2:[0-9]+]], 4
20+
; CHECK: mtfprd [[NEWREG2:[0-9]+]], 4
2121
; CHECK: add {{[0-9]+}}, [[NEWREG]], [[REG1]]
2222
; CHECK: mffprd [[REG2:[0-9]+]], [[NEWREG2]]
2323
; CHECK: add {{[0-9]+}}, [[REG2]], [[NEWREG]]

‎llvm/test/CodeGen/PowerPC/inlineasm-extendedmne.ll

+72
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,72 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \
3+
; RUN: -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
4+
5+
define dso_local void @foo() {
6+
; CHECK-LABEL: foo:
7+
; CHECK: # %bb.0: # %entry
8+
; CHECK-NEXT: #APP
9+
; CHECK-NEXT: mfvsrd r0, vs33
10+
; CHECK-NEXT: #NO_APP
11+
; CHECK-NEXT: #APP
12+
; CHECK-NEXT: mffprd r0, f3
13+
; CHECK-NEXT: #NO_APP
14+
; CHECK-NEXT: #APP
15+
; CHECK-NEXT: mfvsrd r0, vs34
16+
; CHECK-NEXT: #NO_APP
17+
; CHECK-NEXT: #APP
18+
; CHECK-NEXT: mfvsrwz r0, vs33
19+
; CHECK-NEXT: #NO_APP
20+
; CHECK-NEXT: #APP
21+
; CHECK-NEXT: mffprwz r0, f3
22+
; CHECK-NEXT: #NO_APP
23+
; CHECK-NEXT: #APP
24+
; CHECK-NEXT: mfvsrwz r0, vs34
25+
; CHECK-NEXT: #NO_APP
26+
; CHECK-NEXT: #APP
27+
; CHECK-NEXT: mtvsrd vs33, r0
28+
; CHECK-NEXT: #NO_APP
29+
; CHECK-NEXT: #APP
30+
; CHECK-NEXT: mtfprd f3, r0
31+
; CHECK-NEXT: #NO_APP
32+
; CHECK-NEXT: #APP
33+
; CHECK-NEXT: mtvsrd vs34, r0
34+
; CHECK-NEXT: #NO_APP
35+
; CHECK-NEXT: #APP
36+
; CHECK-NEXT: mtvsrwa vs33, r0
37+
; CHECK-NEXT: #NO_APP
38+
; CHECK-NEXT: #APP
39+
; CHECK-NEXT: mtfprwa f3, r0
40+
; CHECK-NEXT: #NO_APP
41+
; CHECK-NEXT: #APP
42+
; CHECK-NEXT: mtvsrwa vs34, r0
43+
; CHECK-NEXT: #NO_APP
44+
; CHECK-NEXT: #APP
45+
; CHECK-NEXT: mtvsrwz vs33, r0
46+
; CHECK-NEXT: #NO_APP
47+
; CHECK-NEXT: #APP
48+
; CHECK-NEXT: mtfprwz f3, r0
49+
; CHECK-NEXT: #NO_APP
50+
; CHECK-NEXT: #APP
51+
; CHECK-NEXT: mtvsrwz vs34, r0
52+
; CHECK-NEXT: #NO_APP
53+
; CHECK-NEXT: blr
54+
entry:
55+
call void asm sideeffect "mfvsrd 0,33", ""()
56+
call void asm sideeffect "mffprd 0,3", ""()
57+
call void asm sideeffect "mfvrd 0,2", ""()
58+
call void asm sideeffect "mfvsrwz 0,33", ""()
59+
call void asm sideeffect "mffprwz 0,3", ""()
60+
call void asm sideeffect "mfvrwz 0,2", ""()
61+
call void asm sideeffect "mtvsrd 33,0", ""()
62+
call void asm sideeffect "mtfprd 3,0", ""()
63+
call void asm sideeffect "mtvrd 2,0", ""()
64+
call void asm sideeffect "mtvsrwa 33,0", ""()
65+
call void asm sideeffect "mtfprwa 3,0", ""()
66+
call void asm sideeffect "mtvrwa 2,0", ""()
67+
call void asm sideeffect "mtvsrwz 33,0", ""()
68+
call void asm sideeffect "mtfprwz 3,0", ""()
69+
call void asm sideeffect "mtvrwz 2,0", ""()
70+
ret void
71+
}
72+

‎llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -45,8 +45,8 @@ define ppc_fp128 @test(%struct.S* byval %x) nounwind {
4545
;
4646
; CHECK-P9-LABEL: test:
4747
; CHECK-P9: # %bb.0: # %entry
48-
; CHECK-P9-NEXT: mtvsrd 1, 5
49-
; CHECK-P9-NEXT: mtvsrd 2, 6
48+
; CHECK-P9-NEXT: mtfprd 1, 5
49+
; CHECK-P9-NEXT: mtfprd 2, 6
5050
; CHECK-P9-NEXT: std 6, 72(1)
5151
; CHECK-P9-NEXT: std 5, 64(1)
5252
; CHECK-P9-NEXT: std 3, 48(1)

‎llvm/test/CodeGen/PowerPC/pr26180.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ define i32 @bad(double %x) {
1111
; CHECK: stfd [[REG0]], [[OFF:.*]](1)
1212
; CHECK: lwz {{[0-9]*}}, [[OFF]](1)
1313
; GENERIC: xscvdpuxws [[REG0:[0-9]+]], 1
14-
; GENERIC: mfvsrwz {{[0-9]*}}, [[REG0]]
14+
; GENERIC: mffprwz {{[0-9]*}}, [[REG0]]
1515
}
1616

1717
define i32 @bad1(float %x) {
@@ -23,5 +23,5 @@ entry:
2323
; CHECK: stfd [[REG0]], [[OFF:.*]](1)
2424
; CHECK: lwa {{[0-9]*}}, [[OFF]](1)
2525
; GENERIC: xscvdpsxws [[REG0:[0-9]+]], 1
26-
; GENERIC: mfvsrwz {{[0-9]*}}, [[REG0]]
26+
; GENERIC: mffprwz {{[0-9]*}}, [[REG0]]
2727
}

‎llvm/test/CodeGen/PowerPC/pr31144.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ entry:
1010
ret void
1111

1212
; CHECK-LABEL: @foo1
13-
; CHECK: mtvsrwz
13+
; CHECK: mtfprwz
1414
}
1515

1616
define void @foo2(i16* %p) {
@@ -21,6 +21,6 @@ entry:
2121
ret void
2222

2323
; CHECK-LABEL: @foo2
24-
; CHECK: mtvsrwz
24+
; CHECK: mtfprwz
2525
}
2626

‎llvm/test/CodeGen/PowerPC/select-addrRegRegOnly.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ define float @testMultipleAccess(i32* nocapture readonly %arr) local_unnamed_add
2323
; CHECK-NEXT: lwz 4, 8(3)
2424
; CHECK-NEXT: lwz 3, 12(3)
2525
; CHECK-NEXT: add 3, 3, 4
26-
; CHECK-NEXT: mtvsrwa 0, 3
26+
; CHECK-NEXT: mtfprwa 0, 3
2727
; CHECK-NEXT: xscvsxdsp 1, 0
2828
; CHECK-NEXT: blr
2929
entry:

‎llvm/test/CodeGen/PowerPC/setrnd.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ entry:
2626
; CHECK-DAG: mffs 1
2727
; CHECK-DAG: mffprd [[REG1:[0-9]+]], 1
2828
; CHECK-DAG: rldimi [[REG1]], 3, 0, 62
29-
; CHECK-DAG: mtvsrd [[REG2:[0-9]+]], [[REG1]]
29+
; CHECK-DAG: mtfprd [[REG2:[0-9]+]], [[REG1]]
3030
; CHECK-DAG: mtfsf 255, [[REG2]]
3131
; CHECK: blr
3232

‎llvm/test/CodeGen/PowerPC/store_fptoi.ll

+16-16
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ entry:
6666
; CHECK-PWR8-LABEL: dpConv2shw
6767
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
6868
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
69-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
69+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
7070
; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
7171
; CHECK-PWR8-NEXT: blr
7272
}
@@ -88,7 +88,7 @@ entry:
8888
; CHECK-PWR8-LABEL: dpConv2sb
8989
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
9090
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
91-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
91+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
9292
; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
9393
; CHECK-PWR8-NEXT: blr
9494
}
@@ -152,7 +152,7 @@ entry:
152152
; CHECK-PWR8-LABEL: spConv2shw
153153
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
154154
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
155-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
155+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
156156
; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
157157
; CHECK-PWR8-NEXT: blr
158158
}
@@ -174,7 +174,7 @@ entry:
174174
; CHECK-PWR8-LABEL: spConv2sb
175175
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
176176
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
177-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
177+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
178178
; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
179179
; CHECK-PWR8-NEXT: blr
180180
}
@@ -253,7 +253,7 @@ entry:
253253
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
254254
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
255255
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
256-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
256+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
257257
; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
258258
; CHECK-PWR8-NEXT: blr
259259
}
@@ -278,7 +278,7 @@ entry:
278278
; CHECK-PWR8-LABEL: dpConv2sb_x
279279
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
280280
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
281-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
281+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
282282
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
283283
; CHECK-PWR8-NEXT: blr
284284
}
@@ -357,7 +357,7 @@ entry:
357357
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
358358
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
359359
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
360-
; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
360+
; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]]
361361
; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]]
362362
; CHECK-PWR8-NEXT: blr
363363
}
@@ -382,7 +382,7 @@ entry:
382382
; CHECK-PWR8-LABEL: spConv2sb_x
383383
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
384384
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
385-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
385+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
386386
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
387387
; CHECK-PWR8-NEXT: blr
388388
}
@@ -450,7 +450,7 @@ entry:
450450
; CHECK-PWR8-LABEL: dpConv2uhw
451451
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
452452
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
453-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
453+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
454454
; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
455455
; CHECK-PWR8-NEXT: blr
456456
}
@@ -472,7 +472,7 @@ entry:
472472
; CHECK-PWR8-LABEL: dpConv2ub
473473
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
474474
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
475-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
475+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
476476
; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
477477
; CHECK-PWR8-NEXT: blr
478478
}
@@ -536,7 +536,7 @@ entry:
536536
; CHECK-PWR8-LABEL: spConv2uhw
537537
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
538538
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
539-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
539+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
540540
; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
541541
; CHECK-PWR8-NEXT: blr
542542
}
@@ -558,7 +558,7 @@ entry:
558558
; CHECK-PWR8-LABEL: spConv2ub
559559
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
560560
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
561-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
561+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
562562
; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
563563
; CHECK-PWR8-NEXT: blr
564564
}
@@ -637,7 +637,7 @@ entry:
637637
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
638638
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
639639
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
640-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
640+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
641641
; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
642642
; CHECK-PWR8-NEXT: blr
643643
}
@@ -662,7 +662,7 @@ entry:
662662
; CHECK-PWR8-LABEL: dpConv2ub_x
663663
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
664664
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
665-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
665+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
666666
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
667667
; CHECK-PWR8-NEXT: blr
668668
}
@@ -741,7 +741,7 @@ entry:
741741
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
742742
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
743743
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
744-
; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
744+
; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]]
745745
; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]]
746746
; CHECK-PWR8-NEXT: blr
747747
}
@@ -766,7 +766,7 @@ entry:
766766
; CHECK-PWR8-LABEL: spConv2ub_x
767767
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
768768
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
769-
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
769+
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
770770
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
771771
; CHECK-PWR8-NEXT: blr
772772
}

‎llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll

+12-12
Original file line numberDiff line numberDiff line change
@@ -17,11 +17,11 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
1717
; P9BE-NEXT: li r3, 0
1818
; P9BE-NEXT: vextuhlx r3, r3, v2
1919
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
20-
; P9BE-NEXT: mtvsrwz f0, r3
20+
; P9BE-NEXT: mtfprwz f0, r3
2121
; P9BE-NEXT: li r3, 2
2222
; P9BE-NEXT: vextuhlx r3, r3, v2
2323
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
24-
; P9BE-NEXT: mtvsrwz f1, r3
24+
; P9BE-NEXT: mtfprwz f1, r3
2525
; P9BE-NEXT: xscvuxddp f0, f0
2626
; P9BE-NEXT: xscvuxddp f1, f1
2727
; P9BE-NEXT: xxmrghd v2, vs0, vs1
@@ -32,11 +32,11 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
3232
; P9LE-NEXT: li r3, 0
3333
; P9LE-NEXT: vextuhrx r3, r3, v2
3434
; P9LE-NEXT: rlwinm r3, r3, 0, 16, 31
35-
; P9LE-NEXT: mtvsrwz f0, r3
35+
; P9LE-NEXT: mtfprwz f0, r3
3636
; P9LE-NEXT: li r3, 2
3737
; P9LE-NEXT: vextuhrx r3, r3, v2
3838
; P9LE-NEXT: rlwinm r3, r3, 0, 16, 31
39-
; P9LE-NEXT: mtvsrwz f1, r3
39+
; P9LE-NEXT: mtfprwz f1, r3
4040
; P9LE-NEXT: xscvuxddp f0, f0
4141
; P9LE-NEXT: xscvuxddp f1, f1
4242
; P9LE-NEXT: xxmrghd v2, vs1, vs0
@@ -49,8 +49,8 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
4949
; P8BE-NEXT: rldicl r3, r3, 32, 48
5050
; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31
5151
; P8BE-NEXT: rlwinm r3, r3, 0, 16, 31
52-
; P8BE-NEXT: mtvsrwz f0, r4
53-
; P8BE-NEXT: mtvsrwz f1, r3
52+
; P8BE-NEXT: mtfprwz f0, r4
53+
; P8BE-NEXT: mtfprwz f1, r3
5454
; P8BE-NEXT: xscvuxddp f0, f0
5555
; P8BE-NEXT: xscvuxddp f1, f1
5656
; P8BE-NEXT: xxmrghd v2, vs0, vs1
@@ -64,8 +64,8 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
6464
; P8LE-NEXT: rldicl r3, r3, 48, 48
6565
; P8LE-NEXT: rlwinm r4, r4, 0, 16, 31
6666
; P8LE-NEXT: rlwinm r3, r3, 0, 16, 31
67-
; P8LE-NEXT: mtvsrwz f0, r4
68-
; P8LE-NEXT: mtvsrwz f1, r3
67+
; P8LE-NEXT: mtfprwz f0, r4
68+
; P8LE-NEXT: mtfprwz f1, r3
6969
; P8LE-NEXT: xscvuxddp f0, f0
7070
; P8LE-NEXT: xscvuxddp f1, f1
7171
; P8LE-NEXT: xxmrghd v2, vs1, vs0
@@ -103,10 +103,10 @@ define dso_local <2 x double> @test2(<4 x i32> %a, <4 x i32> %b) {
103103
; P8BE: # %bb.0: # %entry
104104
; P8BE-NEXT: xxsldwi vs0, v2, v2, 3
105105
; P8BE-NEXT: mfvsrwz r4, v3
106-
; P8BE-NEXT: mtvsrwz f1, r4
106+
; P8BE-NEXT: mtfprwz f1, r4
107107
; P8BE-NEXT: mfvsrwz r3, f0
108108
; P8BE-NEXT: xscvuxddp f1, f1
109-
; P8BE-NEXT: mtvsrwz f0, r3
109+
; P8BE-NEXT: mtfprwz f0, r3
110110
; P8BE-NEXT: xscvuxddp f0, f0
111111
; P8BE-NEXT: xxmrghd v2, vs0, vs1
112112
; P8BE-NEXT: blr
@@ -117,8 +117,8 @@ define dso_local <2 x double> @test2(<4 x i32> %a, <4 x i32> %b) {
117117
; P8LE-NEXT: xxsldwi vs1, v3, v3, 1
118118
; P8LE-NEXT: mfvsrwz r3, f0
119119
; P8LE-NEXT: mfvsrwz r4, f1
120-
; P8LE-NEXT: mtvsrwz f0, r3
121-
; P8LE-NEXT: mtvsrwz f1, r4
120+
; P8LE-NEXT: mtfprwz f0, r3
121+
; P8LE-NEXT: mtfprwz f1, r4
122122
; P8LE-NEXT: xscvuxddp f0, f0
123123
; P8LE-NEXT: xscvuxddp f1, f1
124124
; P8LE-NEXT: xxmrghd v2, vs1, vs0

‎llvm/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ entry:
99
%conv = uitofp i16 %0 to ppc_fp128
1010
ret ppc_fp128 %conv
1111
; CHECK: lhz [[LD:[0-9]+]], 0(3)
12-
; CHECK: mtvsrwa [[MV:[0-9]+]], [[LD]]
12+
; CHECK: mtfprwa [[MV:[0-9]+]], [[LD]]
1313
; CHECK: xscvsxddp [[CONV:[0-9]+]], [[MV]]
1414
; CHECK: bl __gcc_qadd
1515
}

‎llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

+8-8
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,11 @@ define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
2929
; CHECK-P9-LABEL: test2elt:
3030
; CHECK-P9: # %bb.0: # %entry
3131
; CHECK-P9-NEXT: xscvdpuxws f0, v2
32-
; CHECK-P9-NEXT: mfvsrwz r3, f0
32+
; CHECK-P9-NEXT: mffprwz r3, f0
3333
; CHECK-P9-NEXT: xxswapd vs0, v2
3434
; CHECK-P9-NEXT: mtvsrws v3, r3
3535
; CHECK-P9-NEXT: xscvdpuxws f0, f0
36-
; CHECK-P9-NEXT: mfvsrwz r3, f0
36+
; CHECK-P9-NEXT: mffprwz r3, f0
3737
; CHECK-P9-NEXT: mtvsrws v2, r3
3838
; CHECK-P9-NEXT: vmrglw v2, v3, v2
3939
; CHECK-P9-NEXT: mfvsrld r3, v2
@@ -42,11 +42,11 @@ define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
4242
; CHECK-BE-LABEL: test2elt:
4343
; CHECK-BE: # %bb.0: # %entry
4444
; CHECK-BE-NEXT: xscvdpuxws f0, v2
45-
; CHECK-BE-NEXT: mfvsrwz r3, f0
45+
; CHECK-BE-NEXT: mffprwz r3, f0
4646
; CHECK-BE-NEXT: xxswapd vs0, v2
4747
; CHECK-BE-NEXT: mtvsrws v3, r3
4848
; CHECK-BE-NEXT: xscvdpuxws f0, f0
49-
; CHECK-BE-NEXT: mfvsrwz r3, f0
49+
; CHECK-BE-NEXT: mffprwz r3, f0
5050
; CHECK-BE-NEXT: mtvsrws v2, r3
5151
; CHECK-BE-NEXT: vmrghw v2, v3, v2
5252
; CHECK-BE-NEXT: mfvsrd r3, v2
@@ -323,11 +323,11 @@ define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
323323
; CHECK-P9-LABEL: test2elt_signed:
324324
; CHECK-P9: # %bb.0: # %entry
325325
; CHECK-P9-NEXT: xscvdpsxws f0, v2
326-
; CHECK-P9-NEXT: mfvsrwz r3, f0
326+
; CHECK-P9-NEXT: mffprwz r3, f0
327327
; CHECK-P9-NEXT: xxswapd vs0, v2
328328
; CHECK-P9-NEXT: mtvsrws v3, r3
329329
; CHECK-P9-NEXT: xscvdpsxws f0, f0
330-
; CHECK-P9-NEXT: mfvsrwz r3, f0
330+
; CHECK-P9-NEXT: mffprwz r3, f0
331331
; CHECK-P9-NEXT: mtvsrws v2, r3
332332
; CHECK-P9-NEXT: vmrglw v2, v3, v2
333333
; CHECK-P9-NEXT: mfvsrld r3, v2
@@ -336,11 +336,11 @@ define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
336336
; CHECK-BE-LABEL: test2elt_signed:
337337
; CHECK-BE: # %bb.0: # %entry
338338
; CHECK-BE-NEXT: xscvdpsxws f0, v2
339-
; CHECK-BE-NEXT: mfvsrwz r3, f0
339+
; CHECK-BE-NEXT: mffprwz r3, f0
340340
; CHECK-BE-NEXT: xxswapd vs0, v2
341341
; CHECK-BE-NEXT: mtvsrws v3, r3
342342
; CHECK-BE-NEXT: xscvdpsxws f0, f0
343-
; CHECK-BE-NEXT: mfvsrwz r3, f0
343+
; CHECK-BE-NEXT: mffprwz r3, f0
344344
; CHECK-BE-NEXT: mtvsrws v2, r3
345345
; CHECK-BE-NEXT: vmrghw v2, v3, v2
346346
; CHECK-BE-NEXT: mfvsrd r3, v2

‎llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

+12-12
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,8 @@ define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
1818
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
1919
; CHECK-P8-NEXT: rlwinm r4, r4, 0, 16, 31
2020
; CHECK-P8-NEXT: rlwinm r3, r3, 0, 16, 31
21-
; CHECK-P8-NEXT: mtvsrwz f0, r4
22-
; CHECK-P8-NEXT: mtvsrwz f1, r3
21+
; CHECK-P8-NEXT: mtfprwz f0, r4
22+
; CHECK-P8-NEXT: mtfprwz f1, r3
2323
; CHECK-P8-NEXT: xscvuxdsp f0, f0
2424
; CHECK-P8-NEXT: xscvuxdsp f1, f1
2525
; CHECK-P8-NEXT: xscvdpspn vs0, f0
@@ -37,14 +37,14 @@ define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
3737
; CHECK-P9-NEXT: li r3, 0
3838
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
3939
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
40-
; CHECK-P9-NEXT: mtvsrwz f0, r3
40+
; CHECK-P9-NEXT: mtfprwz f0, r3
4141
; CHECK-P9-NEXT: li r3, 2
4242
; CHECK-P9-NEXT: xscvuxdsp f0, f0
4343
; CHECK-P9-NEXT: xscvdpspn vs0, f0
4444
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
4545
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
4646
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
47-
; CHECK-P9-NEXT: mtvsrwz f0, r3
47+
; CHECK-P9-NEXT: mtfprwz f0, r3
4848
; CHECK-P9-NEXT: xscvuxdsp f0, f0
4949
; CHECK-P9-NEXT: xscvdpspn vs0, f0
5050
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
@@ -58,13 +58,13 @@ define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
5858
; CHECK-BE-NEXT: li r3, 2
5959
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
6060
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
61-
; CHECK-BE-NEXT: mtvsrwz f0, r3
61+
; CHECK-BE-NEXT: mtfprwz f0, r3
6262
; CHECK-BE-NEXT: li r3, 0
6363
; CHECK-BE-NEXT: xscvuxdsp f0, f0
6464
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
6565
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
6666
; CHECK-BE-NEXT: xscvdpspn v3, f0
67-
; CHECK-BE-NEXT: mtvsrwz f0, r3
67+
; CHECK-BE-NEXT: mtfprwz f0, r3
6868
; CHECK-BE-NEXT: xscvuxdsp f0, f0
6969
; CHECK-BE-NEXT: xscvdpspn v2, f0
7070
; CHECK-BE-NEXT: vmrghw v2, v2, v3
@@ -270,8 +270,8 @@ define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
270270
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
271271
; CHECK-P8-NEXT: extsh r4, r4
272272
; CHECK-P8-NEXT: extsh r3, r3
273-
; CHECK-P8-NEXT: mtvsrwa f0, r4
274-
; CHECK-P8-NEXT: mtvsrwa f1, r3
273+
; CHECK-P8-NEXT: mtfprwa f0, r4
274+
; CHECK-P8-NEXT: mtfprwa f1, r3
275275
; CHECK-P8-NEXT: xscvsxdsp f0, f0
276276
; CHECK-P8-NEXT: xscvsxdsp f1, f1
277277
; CHECK-P8-NEXT: xscvdpspn vs0, f0
@@ -289,14 +289,14 @@ define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
289289
; CHECK-P9-NEXT: li r3, 0
290290
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
291291
; CHECK-P9-NEXT: extsh r3, r3
292-
; CHECK-P9-NEXT: mtvsrwa f0, r3
292+
; CHECK-P9-NEXT: mtfprwa f0, r3
293293
; CHECK-P9-NEXT: li r3, 2
294294
; CHECK-P9-NEXT: xscvsxdsp f0, f0
295295
; CHECK-P9-NEXT: xscvdpspn vs0, f0
296296
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
297297
; CHECK-P9-NEXT: extsh r3, r3
298298
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
299-
; CHECK-P9-NEXT: mtvsrwa f0, r3
299+
; CHECK-P9-NEXT: mtfprwa f0, r3
300300
; CHECK-P9-NEXT: xscvsxdsp f0, f0
301301
; CHECK-P9-NEXT: xscvdpspn vs0, f0
302302
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
@@ -310,13 +310,13 @@ define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
310310
; CHECK-BE-NEXT: li r3, 2
311311
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
312312
; CHECK-BE-NEXT: extsh r3, r3
313-
; CHECK-BE-NEXT: mtvsrwa f0, r3
313+
; CHECK-BE-NEXT: mtfprwa f0, r3
314314
; CHECK-BE-NEXT: li r3, 0
315315
; CHECK-BE-NEXT: xscvsxdsp f0, f0
316316
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
317317
; CHECK-BE-NEXT: extsh r3, r3
318318
; CHECK-BE-NEXT: xscvdpspn v3, f0
319-
; CHECK-BE-NEXT: mtvsrwa f0, r3
319+
; CHECK-BE-NEXT: mtfprwa f0, r3
320320
; CHECK-BE-NEXT: xscvsxdsp f0, f0
321321
; CHECK-BE-NEXT: xscvdpspn v2, f0
322322
; CHECK-BE-NEXT: vmrghw v2, v2, v3

‎llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

+12-12
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,8 @@ define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
1818
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
1919
; CHECK-P8-NEXT: rlwinm r4, r4, 0, 24, 31
2020
; CHECK-P8-NEXT: rlwinm r3, r3, 0, 24, 31
21-
; CHECK-P8-NEXT: mtvsrwz f0, r4
22-
; CHECK-P8-NEXT: mtvsrwz f1, r3
21+
; CHECK-P8-NEXT: mtfprwz f0, r4
22+
; CHECK-P8-NEXT: mtfprwz f1, r3
2323
; CHECK-P8-NEXT: xscvuxdsp f0, f0
2424
; CHECK-P8-NEXT: xscvuxdsp f1, f1
2525
; CHECK-P8-NEXT: xscvdpspn vs0, f0
@@ -37,14 +37,14 @@ define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
3737
; CHECK-P9-NEXT: li r3, 0
3838
; CHECK-P9-NEXT: vextubrx r3, r3, v2
3939
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
40-
; CHECK-P9-NEXT: mtvsrwz f0, r3
40+
; CHECK-P9-NEXT: mtfprwz f0, r3
4141
; CHECK-P9-NEXT: li r3, 1
4242
; CHECK-P9-NEXT: xscvuxdsp f0, f0
4343
; CHECK-P9-NEXT: xscvdpspn vs0, f0
4444
; CHECK-P9-NEXT: vextubrx r3, r3, v2
4545
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
4646
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
47-
; CHECK-P9-NEXT: mtvsrwz f0, r3
47+
; CHECK-P9-NEXT: mtfprwz f0, r3
4848
; CHECK-P9-NEXT: xscvuxdsp f0, f0
4949
; CHECK-P9-NEXT: xscvdpspn vs0, f0
5050
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
@@ -58,13 +58,13 @@ define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
5858
; CHECK-BE-NEXT: li r3, 1
5959
; CHECK-BE-NEXT: vextublx r3, r3, v2
6060
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
61-
; CHECK-BE-NEXT: mtvsrwz f0, r3
61+
; CHECK-BE-NEXT: mtfprwz f0, r3
6262
; CHECK-BE-NEXT: li r3, 0
6363
; CHECK-BE-NEXT: xscvuxdsp f0, f0
6464
; CHECK-BE-NEXT: vextublx r3, r3, v2
6565
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
6666
; CHECK-BE-NEXT: xscvdpspn v3, f0
67-
; CHECK-BE-NEXT: mtvsrwz f0, r3
67+
; CHECK-BE-NEXT: mtfprwz f0, r3
6868
; CHECK-BE-NEXT: xscvuxdsp f0, f0
6969
; CHECK-BE-NEXT: xscvdpspn v2, f0
7070
; CHECK-BE-NEXT: vmrghw v2, v2, v3
@@ -286,8 +286,8 @@ define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
286286
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
287287
; CHECK-P8-NEXT: extsb r4, r4
288288
; CHECK-P8-NEXT: extsb r3, r3
289-
; CHECK-P8-NEXT: mtvsrwa f0, r4
290-
; CHECK-P8-NEXT: mtvsrwa f1, r3
289+
; CHECK-P8-NEXT: mtfprwa f0, r4
290+
; CHECK-P8-NEXT: mtfprwa f1, r3
291291
; CHECK-P8-NEXT: xscvsxdsp f0, f0
292292
; CHECK-P8-NEXT: xscvsxdsp f1, f1
293293
; CHECK-P8-NEXT: xscvdpspn vs0, f0
@@ -305,14 +305,14 @@ define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
305305
; CHECK-P9-NEXT: li r3, 0
306306
; CHECK-P9-NEXT: vextubrx r3, r3, v2
307307
; CHECK-P9-NEXT: extsb r3, r3
308-
; CHECK-P9-NEXT: mtvsrwa f0, r3
308+
; CHECK-P9-NEXT: mtfprwa f0, r3
309309
; CHECK-P9-NEXT: li r3, 1
310310
; CHECK-P9-NEXT: xscvsxdsp f0, f0
311311
; CHECK-P9-NEXT: xscvdpspn vs0, f0
312312
; CHECK-P9-NEXT: vextubrx r3, r3, v2
313313
; CHECK-P9-NEXT: extsb r3, r3
314314
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
315-
; CHECK-P9-NEXT: mtvsrwa f0, r3
315+
; CHECK-P9-NEXT: mtfprwa f0, r3
316316
; CHECK-P9-NEXT: xscvsxdsp f0, f0
317317
; CHECK-P9-NEXT: xscvdpspn vs0, f0
318318
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
@@ -326,13 +326,13 @@ define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
326326
; CHECK-BE-NEXT: li r3, 1
327327
; CHECK-BE-NEXT: vextublx r3, r3, v2
328328
; CHECK-BE-NEXT: extsb r3, r3
329-
; CHECK-BE-NEXT: mtvsrwa f0, r3
329+
; CHECK-BE-NEXT: mtfprwa f0, r3
330330
; CHECK-BE-NEXT: li r3, 0
331331
; CHECK-BE-NEXT: xscvsxdsp f0, f0
332332
; CHECK-BE-NEXT: vextublx r3, r3, v2
333333
; CHECK-BE-NEXT: extsb r3, r3
334334
; CHECK-BE-NEXT: xscvdpspn v3, f0
335-
; CHECK-BE-NEXT: mtvsrwa f0, r3
335+
; CHECK-BE-NEXT: mtfprwa f0, r3
336336
; CHECK-BE-NEXT: xscvsxdsp f0, f0
337337
; CHECK-BE-NEXT: xscvdpspn v2, f0
338338
; CHECK-BE-NEXT: vmrghw v2, v2, v3

‎llvm/test/MC/Disassembler/PowerPC/vsx.txt

+19-4
Original file line numberDiff line numberDiff line change
@@ -528,16 +528,31 @@
528528
# CHECK: mfvsrd 3, 40
529529
0x7d 0x03 0x00 0x67
530530

531-
# CHECK: mfvsrwz 5, 0
531+
# CHECK: mffprd 3, 0
532+
0x7c 0x03 0x00 0x66
533+
534+
# CHECK: mfvsrwz 5, 40
535+
0x7d 0x05 0x00 0xe7
536+
537+
# CHECK: mffprwz 5, 0
532538
0x7c 0x05 0x00 0xe6
533539

534-
# CHECK: mtvsrd 0, 3
540+
# CHECK: mtvsrd 40, 3
541+
0x7d 0x03 0x01 0x67
542+
543+
# CHECK: mtfprd 0, 3
535544
0x7c 0x03 0x01 0x66
536545

537-
# CHECK: mtvsrwa 0, 3
546+
# CHECK: mtvsrwa 40, 3
547+
0x7d 0x03 0x01 0xa7
548+
549+
# CHECK: mtfprwa 0, 3
538550
0x7c 0x03 0x01 0xa6
539551

540-
# CHECK: mtvsrwz 0, 3
552+
# CHECK: mtvsrwz 40, 3
553+
0x7d 0x03 0x01 0xe7
554+
555+
# CHECK: mtfprwz 0, 3
541556
0x7c 0x03 0x01 0xe6
542557

543558
# Power9 Instructions:

‎llvm/test/MC/PowerPC/vsx.s

+54-8
Original file line numberDiff line numberDiff line change
@@ -538,18 +538,64 @@
538538
# CHECK-BE: mfvsrd 3, 40 # encoding: [0x7d,0x03,0x00,0x67]
539539
# CHECK-LE: mfvsrd 3, 40 # encoding: [0x67,0x00,0x03,0x7d]
540540
mfvrd 3, 8
541-
# CHECK-BE: mfvsrwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6]
542-
# CHECK-LE: mfvsrwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c]
541+
# CHECK-BE: mffprd 0, 3 # encoding: [0x7c,0x60,0x00,0x66]
542+
# CHECK-LE: mffprd 0, 3 # encoding: [0x66,0x00,0x60,0x7c]
543+
mfvsrd 0, 3
544+
# CHECK-BE: mffprd 0, 3 # encoding: [0x7c,0x60,0x00,0x66]
545+
# CHECK-LE: mffprd 0, 3 # encoding: [0x66,0x00,0x60,0x7c]
546+
mffprd 0, 3
547+
548+
# CHECK-BE: mfvsrwz 5, 40 # encoding: [0x7d,0x05,0x00,0xe7]
549+
# CHECK-LE: mfvsrwz 5, 40 # encoding: [0xe7,0x00,0x05,0x7d]
550+
mfvsrwz 5, 40
551+
# CHECK-BE: mfvsrwz 5, 40 # encoding: [0x7d,0x05,0x00,0xe7]
552+
# CHECK-LE: mfvsrwz 5, 40 # encoding: [0xe7,0x00,0x05,0x7d]
553+
mfvrwz 5, 8
554+
# CHECK-BE: mffprwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6]
555+
# CHECK-LE: mffprwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c]
543556
mfvsrwz 5, 0
544-
# CHECK-BE: mtvsrd 0, 3 # encoding: [0x7c,0x03,0x01,0x66]
545-
# CHECK-LE: mtvsrd 0, 3 # encoding: [0x66,0x01,0x03,0x7c]
557+
# CHECK-BE: mffprwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6]
558+
# CHECK-LE: mffprwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c]
559+
mffprwz 5, 0
560+
561+
# CHECK-BE: mtvsrd 40, 3 # encoding: [0x7d,0x03,0x01,0x67]
562+
# CHECK-LE: mtvsrd 40, 3 # encoding: [0x67,0x01,0x03,0x7d]
563+
mtvsrd 40, 3
564+
# CHECK-BE: mtvsrd 40, 3 # encoding: [0x7d,0x03,0x01,0x67]
565+
# CHECK-LE: mtvsrd 40, 3 # encoding: [0x67,0x01,0x03,0x7d]
566+
mtvrd 8, 3
567+
# CHECK-BE: mtfprd 0, 3 # encoding: [0x7c,0x03,0x01,0x66]
568+
# CHECK-LE: mtfprd 0, 3 # encoding: [0x66,0x01,0x03,0x7c]
546569
mtvsrd 0, 3
547-
# CHECK-BE: mtvsrwa 0, 3 # encoding: [0x7c,0x03,0x01,0xa6]
548-
# CHECK-LE: mtvsrwa 0, 3 # encoding: [0xa6,0x01,0x03,0x7c]
570+
# CHECK-BE: mtfprd 0, 3 # encoding: [0x7c,0x03,0x01,0x66]
571+
# CHECK-LE: mtfprd 0, 3 # encoding: [0x66,0x01,0x03,0x7c]
572+
mtfprd 0, 3
573+
574+
# CHECK-BE: mtvsrwa 40, 3 # encoding: [0x7d,0x03,0x01,0xa7]
575+
# CHECK-LE: mtvsrwa 40, 3 # encoding: [0xa7,0x01,0x03,0x7d]
576+
mtvsrwa 40, 3
577+
# CHECK-BE: mtvsrwa 40, 3 # encoding: [0x7d,0x03,0x01,0xa7]
578+
# CHECK-LE: mtvsrwa 40, 3 # encoding: [0xa7,0x01,0x03,0x7d]
579+
mtvrwa 8, 3
580+
# CHECK-BE: mtfprwa 0, 3 # encoding: [0x7c,0x03,0x01,0xa6]
581+
# CHECK-LE: mtfprwa 0, 3 # encoding: [0xa6,0x01,0x03,0x7c]
549582
mtvsrwa 0, 3
550-
# CHECK-BE: mtvsrwz 0, 3 # encoding: [0x7c,0x03,0x01,0xe6]
551-
# CHECK-LE: mtvsrwz 0, 3 # encoding: [0xe6,0x01,0x03,0x7c]
583+
# CHECK-BE: mtfprwa 0, 3 # encoding: [0x7c,0x03,0x01,0xa6]
584+
# CHECK-LE: mtfprwa 0, 3 # encoding: [0xa6,0x01,0x03,0x7c]
585+
mtfprwa 0, 3
586+
587+
# CHECK-BE: mtvsrwz 40, 3 # encoding: [0x7d,0x03,0x01,0xe7]
588+
# CHECK-LE: mtvsrwz 40, 3 # encoding: [0xe7,0x01,0x03,0x7d]
589+
mtvsrwz 40, 3
590+
# CHECK-BE: mtvsrwz 40, 3 # encoding: [0x7d,0x03,0x01,0xe7]
591+
# CHECK-LE: mtvsrwz 40, 3 # encoding: [0xe7,0x01,0x03,0x7d]
592+
mtvrwz 8, 3
593+
# CHECK-BE: mtfprwz 0, 3 # encoding: [0x7c,0x03,0x01,0xe6]
594+
# CHECK-LE: mtfprwz 0, 3 # encoding: [0xe6,0x01,0x03,0x7c]
552595
mtvsrwz 0, 3
596+
# CHECK-BE: mtfprwz 0, 3 # encoding: [0x7c,0x03,0x01,0xe6]
597+
# CHECK-LE: mtfprwz 0, 3 # encoding: [0xe6,0x01,0x03,0x7c]
598+
mtfprwz 0, 3
553599

554600
# Power9 Instructions:
555601

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