AMDGPU/GlobalISel: Legalize constant 32-bit loads

[arsenm]

Summary

Legalize by casting to a 64-bit constant address. This isn't how the
DAG implements it, but it should.

[arsenm]

ping

[arsenm]

ping

[tstellar]

LGTM.

[arsenm]

r371535

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
     return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
   }
 
   /// Build and insert \p Dst = G_BITCAST \p Src
   MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
     return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
   }
 
+    /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
+  MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src) {
+    return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
+  }
+
   /// \return The opcode of the extension the target wants to use for boolean
   /// values.
   unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
 
   // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
   // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
   MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
                                    bool IsFP);

lib/Target/AMDGPU/AMDGPULegalizerInfo.h

bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
                             MachineIRBuilder &MIRBuilder) const;
   bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
                                 MachineIRBuilder &MIRBuilder) const;
   bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
                                MachineIRBuilder &MIRBuilder) const;
 
   bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
                            MachineIRBuilder &MIRBuilder) const;
+  bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
+                    MachineIRBuilder &MIRBuilder,
+                    GISelChangeObserver &Observer) const;
 
   Register getLiveInRegister(MachineRegisterInfo &MRI,
                              Register Reg, LLT Ty) const;
 
   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
                       const ArgDescriptor *Arg) const;
   bool legalizePreloadedArgIntrin(
     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Actions.legalForTypesWithMemDesc({{S32, GlobalPtr, 32, GlobalAlign32},
                                       {S32, ConstantPtr, 32, GlobalAlign32},
                                       {V2S32, ConstantPtr, 64, GlobalAlign32},
                                       {V3S32, ConstantPtr, 96, GlobalAlign32},
                                       {V4S32, ConstantPtr, 128, GlobalAlign32},
                                       {S64, ConstantPtr, 64, GlobalAlign32},
                                       {S128, ConstantPtr, 128, GlobalAlign32},
                                       {V2S32, ConstantPtr, 32, GlobalAlign32}});
     Actions
+        .customIf(typeIs(1, Constant32Ptr))
         .narrowScalarIf(
             [=](const LegalityQuery &Query) -> bool {
               return !Query.Types[0].isVector() && needToSplitLoad(Query);
             },
             [=](const LegalityQuery &Query) -> std::pair<unsigned, LLT> {
               const LLT DstTy = Query.Types[0];
               const LLT PtrTy = Query.Types[1];
 
bool AMDGPULegalizerInfo::legalizeCustom(MachineInstr &MI,
   case TargetOpcode::G_FMAXNUM_IEEE:
     return legalizeMinNumMaxNum(MI, MRI, MIRBuilder);
   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
     return legalizeExtractVectorElt(MI, MRI, MIRBuilder);
   case TargetOpcode::G_INSERT_VECTOR_ELT:
     return legalizeInsertVectorElt(MI, MRI, MIRBuilder);
   case TargetOpcode::G_GLOBAL_VALUE:
     return legalizeGlobalValue(MI, MRI, MIRBuilder);
+  case TargetOpcode::G_LOAD:
+    return legalizeLoad(MI, MRI, MIRBuilder, Observer);
   default:
     return false;
   }
 
   llvm_unreachable("expected switch to return");
 }
 
 Register AMDGPULegalizerInfo::getSegmentAperture(
bool AMDGPULegalizerInfo::legalizeGlobalValue(
 
   const Function &Fn = MF.getFunction();
   DiagnosticInfoUnsupported BadInit(
     Fn, "unsupported initializer for address space", MI.getDebugLoc());
   Fn.getContext().diagnose(BadInit);
   return true;
 }
 
+bool AMDGPULegalizerInfo::legalizeLoad(
+  MachineInstr &MI, MachineRegisterInfo &MRI,
+  MachineIRBuilder &B, GISelChangeObserver &Observer) const {
+  B.setInstr(MI);
+  LLT ConstPtr = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
+  auto Cast = B.buildAddrSpaceCast(ConstPtr, MI.getOperand(1).getReg());
+  Observer.changingInstr(MI);
+  MI.getOperand(1).setReg(Cast.getReg(0));
+  Observer.changedInstr(MI);
+  return true;
+}
+
 // Return the use branch instruction, otherwise null if the usage is invalid.
 static MachineInstr *verifyCFIntrinsic(MachineInstr &MI,
                                        MachineRegisterInfo &MRI) {
   Register CondDef = MI.getOperand(0).getReg();
   if (!MRI.hasOneNonDBGUse(CondDef))
     return nullptr;
 
   MachineInstr &UseMI = *MRI.use_instr_nodbg_begin(CondDef);

test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -O0 -run-pass=legalizer -global-isel-abort=0  %s -o - | FileCheck -check-prefix=CI %s
+
+---
+name: test_load_constant32bit_s32_align1
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CI-LABEL: name: test_load_constant32bit_s32_align1
+    ; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $vgpr0
+    ; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
+    ; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
+    ; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load 1, addrspace 6)
+    ; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[MV]], [[C1]](s64)
+    ; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p4) :: (load 1, addrspace 6)
+    ; CI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+    ; CI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[MV]], [[C2]](s64)
+    ; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p4) :: (load 1, addrspace 6)
+    ; CI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+    ; CI: [[GEP2:%[0-9]+]]:_(p4) = G_GEP [[MV]], [[C3]](s64)
+    ; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p4) :: (load 1, addrspace 6)
+    ; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
+    ; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
+    ; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+    ; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+    ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
+    ; CI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
+    ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+    ; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32)
+    ; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+    ; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]]
+    ; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
+    ; CI: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC]]
+    ; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+    ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
+    ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+    ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[AND4]](s32)
+    ; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+    ; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC4]]
+    ; CI: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16)
+    ; CI: $vgpr0 = COPY [[MV1]](s32)
+    %0:_(p6) = COPY $vgpr0
+    %1:_(s32) = G_LOAD %0 :: (load 4, align 1, addrspace 6)
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_load_constant32bit_s32_align4
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CI-LABEL: name: test_load_constant32bit_s32_align4
+    ; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $vgpr0
+    ; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
+    ; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
+    ; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load 4, addrspace 6)
+    ; CI: $vgpr0 = COPY [[LOAD]](s32)
+    %0:_(p6) = COPY $vgpr0
+    %1:_(s32) = G_LOAD %0 :: (load 4, align 4, addrspace 6)
+    $vgpr0 = COPY %1
+...