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Differential D66222

[ARM] Fix alignment checks for BE VLDRH
ClosedPublic

Authored by dmgreen on Aug 14 2019, 8:33 AM.

Details

Reviewers
t.p.northover
samparker
SjoerdMeijer
simon_tatham
ostannard
Commits
rG3a99101812de: [ARM] Fix alignment checks for BE VLDRH
rL368996: [ARM] Fix alignment checks for BE VLDRH
Summary

We need to allow any alignment at least 2, not just exactly 2, so that the big endian loads and stores can be selected successfully. I've also added extra BE testing for the load and store tests.

Thanks to Oliver for the report.

Diff Detail

Event Timeline

dmgreen created this revision.Aug 14 2019, 8:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 14 2019, 8:33 AM
Herald added subscribers: hiraditya, kristof.beyls, javed.absar. · View Herald Transcript
ostannard accepted this revision.Aug 15 2019, 2:37 AM

LGTM

This revision is now accepted and ready to land.Aug 15 2019, 2:37 AM
Closed by commit rL368996: [ARM] Fix alignment checks for BE VLDRH (authored by dmgreen). · Explain WhyAug 15 2019, 5:55 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
4 lines
test/
CodeGen/
Thumb2/
185 lines
353 lines
353 lines

Diff 215130

llvm/lib/Target/ARM/ARMInstrMVE.td

Show First 20 Lines • Show All 4,804 Lines • ▼ Show 20 Linesdef aligned32_pre_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
return cast<StoreSDNode>(N)->getAlignment() >= 4; return cast<StoreSDNode>(N)->getAlignment() >= 4;
}]>; }]>;
def aligned32_post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), def aligned32_post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
(post_store node:$val, node:$ptr, node:$offset), [{ (post_store node:$val, node:$ptr, node:$offset), [{
return cast<StoreSDNode>(N)->getAlignment() >= 4; return cast<StoreSDNode>(N)->getAlignment() >= 4;
}]>; }]>;
def aligned16_pre_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), def aligned16_pre_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
(pre_store node:$val, node:$ptr, node:$offset), [{ (pre_store node:$val, node:$ptr, node:$offset), [{
return cast<StoreSDNode>(N)->getAlignment() == 2; return cast<StoreSDNode>(N)->getAlignment() >= 2;
}]>; }]>;
def aligned16_post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), def aligned16_post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
(post_store node:$val, node:$ptr, node:$offset), [{ (post_store node:$val, node:$ptr, node:$offset), [{
return cast<StoreSDNode>(N)->getAlignment() == 2; return cast<StoreSDNode>(N)->getAlignment() >= 2;
}]>; }]>;
def alignedmaskedload32 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru), def alignedmaskedload32 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
(masked_ld node:$ptr, node:$pred, node:$passthru), [{ (masked_ld node:$ptr, node:$pred, node:$passthru), [{
return cast<MaskedLoadSDNode>(N)->getAlignment() >= 4; return cast<MaskedLoadSDNode>(N)->getAlignment() >= 4;
}]>; }]>;
def alignedmaskedload16 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru), def alignedmaskedload16 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
(masked_ld node:$ptr, node:$pred, node:$passthru), [{ (masked_ld node:$ptr, node:$pred, node:$passthru), [{
▲ Show 20 Lines • Show All 373 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-ldst-offset.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
define i8* @ldrwu32_4(i8* %x, i8* %y) { define i8* @ldrwu32_4(i8* %x, i8* %y) {
; CHECK-LABEL: ldrwu32_4: ; CHECK-LABEL: ldrwu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0, #4] ; CHECK-NEXT: vldrw.u32 q0, [r0, #4]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
▲ Show 20 Lines • Show All 704 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %z to <8 x half>* %0 = bitcast i8* %z to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 2 %1 = load <8 x half>, <8 x half>* %0, align 2
%2 = bitcast i8* %y to <8 x half>* %2 = bitcast i8* %y to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 2 store <8 x half> %1, <8 x half>* %2, align 2
ret i8* %x ret i8* %x
} }
define i8* @ldrwi32_align1(i8* %x, i8* %y) { define i8* @ldrwi32_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrwi32_align1: ; CHECK-LE-LABEL: ldrwi32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #3] ; CHECK-LE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrwi32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrw.32 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i32>* %0 = bitcast i8* %z to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 1 %1 = load <4 x i32>, <4 x i32>* %0, align 1
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %x ret i8* %x
} }
define i8* @ldrhi16_align1(i8* %x, i8* %y) { define i8* @ldrhi16_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrhi16_align1: ; CHECK-LE-LABEL: ldrhi16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #3] ; CHECK-LE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrhi16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <8 x i16>* %0 = bitcast i8* %z to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 1 %1 = load <8 x i16>, <8 x i16>* %0, align 1
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %x ret i8* %x
} }
Show All 16 Linesentry:
%0 = bitcast i8* %z to <4 x i16>* %0 = bitcast i8* %z to <4 x i16>*
%1 = load <4 x i16>, <4 x i16>* %0, align 1 %1 = load <4 x i16>, <4 x i16>* %0, align 1
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
%3 = sext <4 x i16> %1 to <4 x i32> %3 = sext <4 x i16> %1 to <4 x i32>
store <4 x i32> %3, <4 x i32>* %2, align 4 store <4 x i32> %3, <4 x i32>* %2, align 4
ret i8* %x ret i8* %x
} }
define i8* @ldrwf32_align1(i8* %x, i8* %y) { define i8* @ldrf32_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrwf32_align1: ; CHECK-LE-LABEL: ldrf32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #3] ; CHECK-LE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrf32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrw.32 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x float>* %0 = bitcast i8* %z to <4 x float>*
%1 = load <4 x float>, <4 x float>* %0, align 1 %1 = load <4 x float>, <4 x float>* %0, align 1
%2 = bitcast i8* %y to <4 x float>* %2 = bitcast i8* %y to <4 x float>*
store <4 x float> %1, <4 x float>* %2, align 4 store <4 x float> %1, <4 x float>* %2, align 4
ret i8* %x ret i8* %x
} }
define i8* @ldrwf16_align1(i8* %x, i8* %y) { define i8* @ldrf16_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrwf16_align1: ; CHECK-LE-LABEL: ldrf16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #3] ; CHECK-LE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrf16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <8 x half>* %0 = bitcast i8* %z to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 1 %1 = load <8 x half>, <8 x half>* %0, align 1
%2 = bitcast i8* %y to <8 x half>* %2 = bitcast i8* %y to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 2 store <8 x half> %1, <8 x half>* %2, align 2
ret i8* %x ret i8* %x
} }
define i8* @ldrh16_align8(i8* %x, i8* %y) {
; CHECK-LE-LABEL: ldrh16_align8:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldrw.u32 q0, [r0, #4]
; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrh16_align8:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r0, #4]
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry:
%z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 8
%2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %x
}
define i8* @strw32_4(i8* %y, i8* %x) { define i8* @strw32_4(i8* %y, i8* %x) {
; CHECK-LABEL: strw32_4: ; CHECK-LABEL: strw32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-NEXT: vldrw.u32 q0, [r1]
▲ Show 20 Lines • Show All 476 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %x to <8 x half>* %0 = bitcast i8* %x to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 2 %1 = load <8 x half>, <8 x half>* %0, align 2
%2 = bitcast i8* %z to <8 x half>* %2 = bitcast i8* %z to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 2 store <8 x half> %1, <8 x half>* %2, align 2
ret i8* %y ret i8* %y
} }
define i8* @strwi32_align1(i8* %y, i8* %x) { define i8* @strwi32_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strwi32_align1: ; CHECK-LE-LABEL: strwi32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #3] ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strwi32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %z to <4 x i32>* %2 = bitcast i8* %z to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 1 store <4 x i32> %1, <4 x i32>* %2, align 1
ret i8* %y ret i8* %y
} }
define i8* @strhi16_align1(i8* %y, i8* %x) { define i8* @strhi16_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strhi16_align1: ; CHECK-LE-LABEL: strhi16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #3] ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strhi16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %z to <8 x i16>* %2 = bitcast i8* %z to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 1 store <8 x i16> %1, <8 x i16>* %2, align 1
ret i8* %y ret i8* %y
} }
Show All 17 Linesentry:
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
%3 = trunc <4 x i32> %1 to <4 x i16> %3 = trunc <4 x i32> %1 to <4 x i16>
store <4 x i16> %3, <4 x i16>* %2, align 1 store <4 x i16> %3, <4 x i16>* %2, align 1
ret i8* %y ret i8* %y
} }
define i8* @strf32_align1(i8* %y, i8* %x) { define i8* @strf32_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strf32_align1: ; CHECK-LE-LABEL: strf32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #3] ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x float>* %0 = bitcast i8* %x to <4 x float>*
%1 = load <4 x float>, <4 x float>* %0, align 4 %1 = load <4 x float>, <4 x float>* %0, align 4
%2 = bitcast i8* %z to <4 x float>* %2 = bitcast i8* %z to <4 x float>*
store <4 x float> %1, <4 x float>* %2, align 1 store <4 x float> %1, <4 x float>* %2, align 1
ret i8* %y ret i8* %y
} }
define i8* @strf16_align1(i8* %y, i8* %x) { define i8* @strf16_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strf16_align1: ; CHECK-LE-LABEL: strf16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #3] ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x half>* %0 = bitcast i8* %x to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 2 %1 = load <8 x half>, <8 x half>* %0, align 2
%2 = bitcast i8* %z to <8 x half>* %2 = bitcast i8* %z to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 1 store <8 x half> %1, <8 x half>* %2, align 1
ret i8* %y ret i8* %y
} }
define i8* @strf16_align8(i8* %y, i8* %x) {
; CHECK-LE-LABEL: strf16_align8:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-LE-NEXT: vstrw.32 q0, [r0, #16]
; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf16_align8:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0, #16]
; CHECK-BE-NEXT: bx lr
entry:
%z = getelementptr inbounds i8, i8* %y, i32 16
%0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %z to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 8
ret i8* %y
}

llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
define i8* @ldrwu32_4(i8* %x, i8* %y) { define i8* @ldrwu32_4(i8* %x, i8* %y) {
; CHECK-LABEL: ldrwu32_4: ; CHECK-LABEL: ldrwu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0], #4 ; CHECK-NEXT: vldrw.u32 q0, [r0], #4
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @ldrwu32_3(i8* %x, i8* %y) { define i8* @ldrwu32_3(i8* %x, i8* %y) {
; CHECK-LABEL: ldrwu32_3: ; CHECK-LE-LABEL: ldrwu32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0], #3 ; CHECK-LE-NEXT: vldrb.u8 q0, [r0], #3
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrwu32_3:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vstrw.32 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
▲ Show 20 Lines • Show All 253 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @ldrhu16_3(i8* %x, i8* %y) { define i8* @ldrhu16_3(i8* %x, i8* %y) {
; CHECK-LABEL: ldrhu16_3: ; CHECK-LE-LABEL: ldrhu16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0], #3 ; CHECK-LE-NEXT: vldrb.u8 q0, [r0], #3
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrhu16_3:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
▲ Show 20 Lines • Show All 396 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %x to <8 x half>* %0 = bitcast i8* %x to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 2 %1 = load <8 x half>, <8 x half>* %0, align 2
%2 = bitcast i8* %y to <8 x half>* %2 = bitcast i8* %y to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 2 store <8 x half> %1, <8 x half>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @ldrwi32_align1(i8* %x, i8* %y) { define i8* @ldrwi32_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrwi32_align1: ; CHECK-LE-LABEL: ldrwi32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0], #3 ; CHECK-LE-NEXT: vldrb.u8 q0, [r0], #3
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrwi32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrw.32 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 1 %1 = load <4 x i32>, <4 x i32>* %0, align 1
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @ldrhi16_align1(i8* %x, i8* %y) { define i8* @ldrhi16_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrhi16_align1: ; CHECK-LE-LABEL: ldrhi16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0], #3 ; CHECK-LE-NEXT: vldrb.u8 q0, [r0], #3
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrhi16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 1 %1 = load <8 x i16>, <8 x i16>* %0, align 1
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
Show All 18 Linesentry:
%1 = load <4 x i16>, <4 x i16>* %0, align 1 %1 = load <4 x i16>, <4 x i16>* %0, align 1
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
%3 = sext <4 x i16> %1 to <4 x i32> %3 = sext <4 x i16> %1 to <4 x i32>
store <4 x i32> %3, <4 x i32>* %2, align 4 store <4 x i32> %3, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @ldrf32_align1(i8* %x, i8* %y) { define i8* @ldrf32_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrf32_align1: ; CHECK-LE-LABEL: ldrf32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0], #3 ; CHECK-LE-NEXT: vldrb.u8 q0, [r0], #3
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrf32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrw.32 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <4 x float>* %0 = bitcast i8* %x to <4 x float>*
%1 = load <4 x float>, <4 x float>* %0, align 1 %1 = load <4 x float>, <4 x float>* %0, align 1
%2 = bitcast i8* %y to <4 x float>* %2 = bitcast i8* %y to <4 x float>*
store <4 x float> %1, <4 x float>* %2, align 4 store <4 x float> %1, <4 x float>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @ldrf16_align1(i8* %x, i8* %y) { define i8* @ldrf16_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrf16_align1: ; CHECK-LE-LABEL: ldrf16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0], #3 ; CHECK-LE-NEXT: vldrb.u8 q0, [r0], #3
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrf16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %x to <8 x half>* %0 = bitcast i8* %x to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 1 %1 = load <8 x half>, <8 x half>* %0, align 1
%2 = bitcast i8* %y to <8 x half>* %2 = bitcast i8* %y to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 2 store <8 x half> %1, <8 x half>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @ldrh16_align8(i8* %x, i8* %y) {
; CHECK-LE-LABEL: ldrh16_align8:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldrw.u32 q0, [r0], #4
; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrh16_align8:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r0], #4
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry:
%z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 8
%2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z
}
define i8* @strw32_4(i8* %y, i8* %x) { define i8* @strw32_4(i8* %y, i8* %x) {
; CHECK-LABEL: strw32_4: ; CHECK-LE-LABEL: strw32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #4 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #4
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strw32_4:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vstrw.32 q0, [r0], #4
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @strw32_3(i8* %y, i8* %x) { define i8* @strw32_3(i8* %y, i8* %x) {
; CHECK-LABEL: strw32_3: ; CHECK-LE-LABEL: strw32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #3 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #3
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strw32_3:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vstrw.32 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @strw32_m4(i8* %y, i8* %x) { define i8* @strw32_m4(i8* %y, i8* %x) {
; CHECK-LABEL: strw32_m4: ; CHECK-LE-LABEL: strw32_m4:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #-4 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #-4
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strw32_m4:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vstrw.32 q0, [r0], #-4
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 -4 %z = getelementptr inbounds i8, i8* %y, i32 -4
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Linesentry:
%1 = load <4 x i16>, <4 x i16>* %0, align 2 %1 = load <4 x i16>, <4 x i16>* %0, align 2
%2 = bitcast i8* %y to <4 x i16>* %2 = bitcast i8* %y to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 2 store <4 x i16> %1, <4 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @strh16_4(i8* %y, i8* %x) { define i8* @strh16_4(i8* %y, i8* %x) {
; CHECK-LABEL: strh16_4: ; CHECK-LE-LABEL: strh16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #4 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #4
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strh16_4:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0], #4
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @strh16_3(i8* %y, i8* %x) { define i8* @strh16_3(i8* %y, i8* %x) {
; CHECK-LABEL: strh16_3: ; CHECK-LE-LABEL: strh16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #3 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #3
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strh16_3:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @strh16_2(i8* %y, i8* %x) { define i8* @strh16_2(i8* %y, i8* %x) {
; CHECK-LABEL: strh16_2: ; CHECK-LE-LABEL: strh16_2:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #2 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #2
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strh16_2:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0], #2
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 2 %z = getelementptr inbounds i8, i8* %y, i32 2
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
▲ Show 20 Lines • Show All 211 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %x to <16 x i8>* %0 = bitcast i8* %x to <16 x i8>*
%1 = load <16 x i8>, <16 x i8>* %0, align 1 %1 = load <16 x i8>, <16 x i8>* %0, align 1
%2 = bitcast i8* %y to <16 x i8>* %2 = bitcast i8* %y to <16 x i8>*
store <16 x i8> %1, <16 x i8>* %2, align 1 store <16 x i8> %1, <16 x i8>* %2, align 1
ret i8* %z ret i8* %z
} }
define i8* @strf32_4(i8* %y, i8* %x) { define i8* @strf32_4(i8* %y, i8* %x) {
; CHECK-LABEL: strf32_4: ; CHECK-LE-LABEL: strf32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #4 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #4
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf32_4:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vstrw.32 q0, [r0], #4
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x float>* %0 = bitcast i8* %x to <4 x float>*
%1 = load <4 x float>, <4 x float>* %0, align 4 %1 = load <4 x float>, <4 x float>* %0, align 4
%2 = bitcast i8* %y to <4 x float>* %2 = bitcast i8* %y to <4 x float>*
store <4 x float> %1, <4 x float>* %2, align 4 store <4 x float> %1, <4 x float>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @strf16_4(i8* %y, i8* %x) { define i8* @strf16_4(i8* %y, i8* %x) {
; CHECK-LABEL: strf16_4: ; CHECK-LE-LABEL: strf16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #4 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #4
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf16_4:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0], #4
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x half>* %0 = bitcast i8* %x to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 2 %1 = load <8 x half>, <8 x half>* %0, align 2
%2 = bitcast i8* %y to <8 x half>* %2 = bitcast i8* %y to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 2 store <8 x half> %1, <8 x half>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @strwi32_align1(i8* %y, i8* %x) { define i8* @strwi32_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strwi32_align1: ; CHECK-LE-LABEL: strwi32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #3 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #3
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strwi32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 1 store <4 x i32> %1, <4 x i32>* %2, align 1
ret i8* %z ret i8* %z
} }
define i8* @strhi16_align1(i8* %y, i8* %x) { define i8* @strhi16_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strhi16_align1: ; CHECK-LE-LABEL: strhi16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #3 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #3
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strhi16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 1 store <8 x i16> %1, <8 x i16>* %2, align 1
ret i8* %z ret i8* %z
} }
Show All 18 Linesentry:
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %y to <4 x i16>* %2 = bitcast i8* %y to <4 x i16>*
%3 = trunc <4 x i32> %1 to <4 x i16> %3 = trunc <4 x i32> %1 to <4 x i16>
store <4 x i16> %3, <4 x i16>* %2, align 1 store <4 x i16> %3, <4 x i16>* %2, align 1
ret i8* %z ret i8* %z
} }
define i8* @strf32_align1(i8* %y, i8* %x) { define i8* @strf32_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strf32_align1: ; CHECK-LE-LABEL: strf32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #3 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #3
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x float>* %0 = bitcast i8* %x to <4 x float>*
%1 = load <4 x float>, <4 x float>* %0, align 4 %1 = load <4 x float>, <4 x float>* %0, align 4
%2 = bitcast i8* %y to <4 x float>* %2 = bitcast i8* %y to <4 x float>*
store <4 x float> %1, <4 x float>* %2, align 1 store <4 x float> %1, <4 x float>* %2, align 1
ret i8* %z ret i8* %z
} }
define i8* @strf16_align1(i8* %y, i8* %x) { define i8* @strf16_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strf16_align1: ; CHECK-LE-LABEL: strf16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0], #3 ; CHECK-LE-NEXT: vstrb.8 q0, [r0], #3
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x half>* %0 = bitcast i8* %x to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 2 %1 = load <8 x half>, <8 x half>* %0, align 2
%2 = bitcast i8* %y to <8 x half>* %2 = bitcast i8* %y to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 1 store <8 x half> %1, <8 x half>* %2, align 1
ret i8* %z ret i8* %z
} }
define i8* @strf16_align8(i8* %y, i8* %x) {
; CHECK-LE-LABEL: strf16_align8:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-LE-NEXT: vstrb.8 q0, [r0], #16
; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf16_align8:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0], #16
; CHECK-BE-NEXT: bx lr
entry:
%z = getelementptr inbounds i8, i8* %y, i32 16
%0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 8
ret i8* %z
}

llvm/test/CodeGen/Thumb2/mve-ldst-preinc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
define i8* @ldrwu32_4(i8* %x, i8* %y) { define i8* @ldrwu32_4(i8* %x, i8* %y) {
; CHECK-LABEL: ldrwu32_4: ; CHECK-LABEL: ldrwu32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0, #4]! ; CHECK-NEXT: vldrw.u32 q0, [r0, #4]!
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 4 %z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <4 x i32>* %0 = bitcast i8* %z to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @ldrwu32_3(i8* %x, i8* %y) { define i8* @ldrwu32_3(i8* %x, i8* %y) {
; CHECK-LABEL: ldrwu32_3: ; CHECK-LE-LABEL: ldrwu32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]! ; CHECK-LE-NEXT: vldrb.u8 q0, [r0, #3]!
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrwu32_3:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vldrw.u32 q0, [r0]
; CHECK-BE-NEXT: vstrw.32 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i32>* %0 = bitcast i8* %z to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
▲ Show 20 Lines • Show All 253 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %z to <8 x i16>* %0 = bitcast i8* %z to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @ldrhu16_3(i8* %x, i8* %y) { define i8* @ldrhu16_3(i8* %x, i8* %y) {
; CHECK-LABEL: ldrhu16_3: ; CHECK-LE-LABEL: ldrhu16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]! ; CHECK-LE-NEXT: vldrb.u8 q0, [r0, #3]!
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrhu16_3:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vldrh.u16 q0, [r0]
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <8 x i16>* %0 = bitcast i8* %z to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
▲ Show 20 Lines • Show All 396 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %z to <8 x half>* %0 = bitcast i8* %z to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 2 %1 = load <8 x half>, <8 x half>* %0, align 2
%2 = bitcast i8* %y to <8 x half>* %2 = bitcast i8* %y to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 2 store <8 x half> %1, <8 x half>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @ldrwi32_align1(i8* %x, i8* %y) { define i8* @ldrwi32_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrwi32_align1: ; CHECK-LE-LABEL: ldrwi32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]! ; CHECK-LE-NEXT: vldrb.u8 q0, [r0, #3]!
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrwi32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrw.32 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x i32>* %0 = bitcast i8* %z to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 1 %1 = load <4 x i32>, <4 x i32>* %0, align 1
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @ldrhi16_align1(i8* %x, i8* %y) { define i8* @ldrhi16_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrhi16_align1: ; CHECK-LE-LABEL: ldrhi16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]! ; CHECK-LE-NEXT: vldrb.u8 q0, [r0, #3]!
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrhi16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <8 x i16>* %0 = bitcast i8* %z to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 1 %1 = load <8 x i16>, <8 x i16>* %0, align 1
%2 = bitcast i8* %y to <8 x i16>* %2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
Show All 18 Linesentry:
%1 = load <4 x i16>, <4 x i16>* %0, align 1 %1 = load <4 x i16>, <4 x i16>* %0, align 1
%2 = bitcast i8* %y to <4 x i32>* %2 = bitcast i8* %y to <4 x i32>*
%3 = sext <4 x i16> %1 to <4 x i32> %3 = sext <4 x i16> %1 to <4 x i32>
store <4 x i32> %3, <4 x i32>* %2, align 4 store <4 x i32> %3, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @ldrf32_align1(i8* %x, i8* %y) { define i8* @ldrf32_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrf32_align1: ; CHECK-LE-LABEL: ldrf32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]! ; CHECK-LE-NEXT: vldrb.u8 q0, [r0, #3]!
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-LE-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrf32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrw.32 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <4 x float>* %0 = bitcast i8* %z to <4 x float>*
%1 = load <4 x float>, <4 x float>* %0, align 1 %1 = load <4 x float>, <4 x float>* %0, align 1
%2 = bitcast i8* %y to <4 x float>* %2 = bitcast i8* %y to <4 x float>*
store <4 x float> %1, <4 x float>* %2, align 4 store <4 x float> %1, <4 x float>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @ldrf16_align1(i8* %x, i8* %y) { define i8* @ldrf16_align1(i8* %x, i8* %y) {
; CHECK-LABEL: ldrf16_align1: ; CHECK-LE-LABEL: ldrf16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]! ; CHECK-LE-NEXT: vldrb.u8 q0, [r0, #3]!
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrf16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrb.u8 q0, [r0, #3]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %x, i32 3 %z = getelementptr inbounds i8, i8* %x, i32 3
%0 = bitcast i8* %z to <8 x half>* %0 = bitcast i8* %z to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 1 %1 = load <8 x half>, <8 x half>* %0, align 1
%2 = bitcast i8* %y to <8 x half>* %2 = bitcast i8* %y to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 2 store <8 x half> %1, <8 x half>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @ldrh16_align8(i8* %x, i8* %y) {
; CHECK-LE-LABEL: ldrh16_align8:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldrw.u32 q0, [r0, #4]!
; CHECK-LE-NEXT: vstrh.16 q0, [r1]
; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: ldrh16_align8:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r0, #4]!
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
; CHECK-BE-NEXT: bx lr
entry:
%z = getelementptr inbounds i8, i8* %x, i32 4
%0 = bitcast i8* %z to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 8
%2 = bitcast i8* %y to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z
}
define i8* @strw32_4(i8* %y, i8* %x) { define i8* @strw32_4(i8* %y, i8* %x) {
; CHECK-LABEL: strw32_4: ; CHECK-LE-LABEL: strw32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #4]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #4]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strw32_4:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vstrw.32 q0, [r0, #4]!
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %z to <4 x i32>* %2 = bitcast i8* %z to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @strw32_3(i8* %y, i8* %x) { define i8* @strw32_3(i8* %y, i8* %x) {
; CHECK-LABEL: strw32_3: ; CHECK-LE-LABEL: strw32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #3]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #3]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strw32_3:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vstrw.32 q0, [r0]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %z to <4 x i32>* %2 = bitcast i8* %z to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @strw32_m4(i8* %y, i8* %x) { define i8* @strw32_m4(i8* %y, i8* %x) {
; CHECK-LABEL: strw32_m4: ; CHECK-LE-LABEL: strw32_m4:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #-4]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #-4]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strw32_m4:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vstrw.32 q0, [r0, #-4]!
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 -4 %z = getelementptr inbounds i8, i8* %y, i32 -4
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %z to <4 x i32>* %2 = bitcast i8* %z to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 4 store <4 x i32> %1, <4 x i32>* %2, align 4
ret i8* %z ret i8* %z
} }
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Linesentry:
%1 = load <4 x i16>, <4 x i16>* %0, align 2 %1 = load <4 x i16>, <4 x i16>* %0, align 2
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
store <4 x i16> %1, <4 x i16>* %2, align 2 store <4 x i16> %1, <4 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @strh16_4(i8* %y, i8* %x) { define i8* @strh16_4(i8* %y, i8* %x) {
; CHECK-LABEL: strh16_4: ; CHECK-LE-LABEL: strh16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #4]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #4]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strh16_4:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0, #4]!
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %z to <8 x i16>* %2 = bitcast i8* %z to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @strh16_3(i8* %y, i8* %x) { define i8* @strh16_3(i8* %y, i8* %x) {
; CHECK-LABEL: strh16_3: ; CHECK-LE-LABEL: strh16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #3]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #3]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strh16_3:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0]
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %z to <8 x i16>* %2 = bitcast i8* %z to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @strh16_2(i8* %y, i8* %x) { define i8* @strh16_2(i8* %y, i8* %x) {
; CHECK-LABEL: strh16_2: ; CHECK-LE-LABEL: strh16_2:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #2]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #2]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strh16_2:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0, #2]!
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 2 %z = getelementptr inbounds i8, i8* %y, i32 2
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %z to <8 x i16>* %2 = bitcast i8* %z to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 2 store <8 x i16> %1, <8 x i16>* %2, align 2
ret i8* %z ret i8* %z
} }
▲ Show 20 Lines • Show All 211 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %x to <16 x i8>* %0 = bitcast i8* %x to <16 x i8>*
%1 = load <16 x i8>, <16 x i8>* %0, align 1 %1 = load <16 x i8>, <16 x i8>* %0, align 1
%2 = bitcast i8* %z to <16 x i8>* %2 = bitcast i8* %z to <16 x i8>*
store <16 x i8> %1, <16 x i8>* %2, align 1 store <16 x i8> %1, <16 x i8>* %2, align 1
ret i8* %z ret i8* %z
} }
define i8* @strf32_4(i8* %y, i8* %x) { define i8* @strf32_4(i8* %y, i8* %x) {
; CHECK-LABEL: strf32_4: ; CHECK-LE-LABEL: strf32_4:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #4]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #4]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf32_4:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vstrw.32 q0, [r0, #4]!
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x float>* %0 = bitcast i8* %x to <4 x float>*
%1 = load <4 x float>, <4 x float>* %0, align 4 %1 = load <4 x float>, <4 x float>* %0, align 4
%2 = bitcast i8* %z to <4 x float>* %2 = bitcast i8* %z to <4 x float>*
store <4 x float> %1, <4 x float>* %2, align 4 store <4 x float> %1, <4 x float>* %2, align 4
ret i8* %z ret i8* %z
} }
define i8* @strf16_4(i8* %y, i8* %x) { define i8* @strf16_4(i8* %y, i8* %x) {
; CHECK-LABEL: strf16_4: ; CHECK-LE-LABEL: strf16_4:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #4]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #4]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf16_4:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0, #4]!
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x half>* %0 = bitcast i8* %x to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 2 %1 = load <8 x half>, <8 x half>* %0, align 2
%2 = bitcast i8* %z to <8 x half>* %2 = bitcast i8* %z to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 2 store <8 x half> %1, <8 x half>* %2, align 2
ret i8* %z ret i8* %z
} }
define i8* @strwi32_align1(i8* %y, i8* %x) { define i8* @strwi32_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strwi32_align1: ; CHECK-LE-LABEL: strwi32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #3]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #3]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strwi32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %z to <4 x i32>* %2 = bitcast i8* %z to <4 x i32>*
store <4 x i32> %1, <4 x i32>* %2, align 1 store <4 x i32> %1, <4 x i32>* %2, align 1
ret i8* %z ret i8* %z
} }
define i8* @strhi16_align1(i8* %y, i8* %x) { define i8* @strhi16_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strhi16_align1: ; CHECK-LE-LABEL: strhi16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #3]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #3]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strhi16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %z to <8 x i16>* %2 = bitcast i8* %z to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 1 store <8 x i16> %1, <8 x i16>* %2, align 1
ret i8* %z ret i8* %z
} }
Show All 17 Linesentry:
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %z to <4 x i16>* %2 = bitcast i8* %z to <4 x i16>*
%3 = trunc <4 x i32> %1 to <4 x i16> %3 = trunc <4 x i32> %1 to <4 x i16>
store <4 x i16> %3, <4 x i16>* %2, align 1 store <4 x i16> %3, <4 x i16>* %2, align 1
ret i8* %z ret i8* %z
} }
define i8* @strf32_align1(i8* %y, i8* %x) { define i8* @strf32_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strf32_align1: ; CHECK-LE-LABEL: strf32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-LE-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #3]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #3]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf32_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrw.u32 q0, [r1]
; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <4 x float>* %0 = bitcast i8* %x to <4 x float>*
%1 = load <4 x float>, <4 x float>* %0, align 4 %1 = load <4 x float>, <4 x float>* %0, align 4
%2 = bitcast i8* %z to <4 x float>* %2 = bitcast i8* %z to <4 x float>*
store <4 x float> %1, <4 x float>* %2, align 1 store <4 x float> %1, <4 x float>* %2, align 1
ret i8* %z ret i8* %z
} }
define i8* @strf16_align1(i8* %y, i8* %x) { define i8* @strf16_align1(i8* %y, i8* %x) {
; CHECK-LABEL: strf16_align1: ; CHECK-LE-LABEL: strf16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r1] ; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-NEXT: vstrb.8 q0, [r0, #3]! ; CHECK-LE-NEXT: vstrb.8 q0, [r0, #3]!
; CHECK-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf16_align1:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vrev16.8 q0, q0
; CHECK-BE-NEXT: vstrb.8 q0, [r0, #3]
; CHECK-BE-NEXT: adds r0, #3
; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 3 %z = getelementptr inbounds i8, i8* %y, i32 3
%0 = bitcast i8* %x to <8 x half>* %0 = bitcast i8* %x to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 2 %1 = load <8 x half>, <8 x half>* %0, align 2
%2 = bitcast i8* %z to <8 x half>* %2 = bitcast i8* %z to <8 x half>*
store <8 x half> %1, <8 x half>* %2, align 1 store <8 x half> %1, <8 x half>* %2, align 1
ret i8* %z ret i8* %z
} }
define i8* @strf16_align8(i8* %y, i8* %x) {
; CHECK-LE-LABEL: strf16_align8:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldrh.u16 q0, [r1]
; CHECK-LE-NEXT: vstrb.8 q0, [r0, #16]!
; CHECK-LE-NEXT: bx lr
;
; CHECK-BE-LABEL: strf16_align8:
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldrh.u16 q0, [r1]
; CHECK-BE-NEXT: vstrh.16 q0, [r0, #16]!
; CHECK-BE-NEXT: bx lr
entry:
%z = getelementptr inbounds i8, i8* %y, i32 16
%0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i8* %z to <8 x i16>*
store <8 x i16> %1, <8 x i16>* %2, align 8
ret i8* %z
}