[X86] Support -march=tigerlake

[xiangzhangllvm]

Summary

Support -march=tigerlake for x86.
Compare with Icelake Client, It include 4 more new features ,they are avx512vp2intersect, movdiri, movdir64b, shstk.

[RKSimon]

clang/lib/Basic/Targets/X86.cpp

170

Are we ok with introducing this kind of thing again or should we use goto?

clang/test/Preprocessor/predefined-arch-macros.c

1569

You test for no-wbnoinvd - do we need to do the same for pconfig?

llvm/lib/Support/Host.cpp

749

Check for tigerlake with avx512vp2intersect cpuid bit? @craig.topper any suggestions?

[xiangzhangllvm]

clang/lib/Basic/Targets/X86.cpp

170

Sorry, not quite understand, How to introducing it again?

clang/test/Preprocessor/predefined-arch-macros.c

1569

I am not much sure about the -wbnoinvd, The tigerlake succeed to icelake, So I write the check follow the icelake.

[craig.topper]

clang/lib/Basic/Targets/X86.cpp

170

We had a bunch of ifs like this in the switch before and turned into a maintenance issue because multiple ifs needed to be updated everytime someone added something to the stop of the switch. They were removed in https://reviews.llvm.org/D63018

clang/test/Preprocessor/predefined-arch-macros.c

1535

Missing a check for AVX512VP2INTERSECT

1569

I think icelake ended up like that because we had a bug once due to the ifs in the switch. Go ahead and add a NOT for PCONFIG

llvm/lib/Support/Host.cpp

749

Sounds good to me.

[xiangzhangllvm]

All changed, Thank you very much!

[craig.topper]

clang/test/Preprocessor/predefined-arch-macros.c

1571

This is only effective if its alphabetically where PCONFIG should be.

llvm/include/llvm/Support/X86TargetParser.def

164

The COMPAT macro is for things implemented in libgcc. I don't know if this one is yet. So it should be at position 70 instead.

llvm/lib/Support/Host.cpp

750

There 3 variables Features, Features2, and Feature3. Each are 32 bits. The current bit position you have would put it in Features2, but when you move it to 70 it will be Features3.

[xiangzhangllvm]

clang/test/Preprocessor/predefined-arch-macros.c

1571

Yes!

llvm/include/llvm/Support/X86TargetParser.def

164

Make sense!

llvm/lib/Support/Host.cpp

750

Oh! Yes! I ignored it! Thank you very much!!

[xiangzhangllvm]

Done again, thank you again!!

[craig.topper]

llvm/lib/Support/Host.cpp

1088

This also needs HasAVX512Save. Sorry I didn't catch that earlier.

[xiangzhangllvm]

llvm/lib/Support/Host.cpp

1088

OK, seems all AVX512 features AND the HasAVX512Save, but I check the SPEC of avxvp2intersect, it just show CPUID.7.0.EDX[8].

[craig.topper]

llvm/lib/Support/Host.cpp

1088

It's in the E4NF table where it says "State requirement, Table 2-37 not met"

[craig.topper]

LGTM

clang/include/clang/Basic/X86Target.def

 /// \name Icelake Client
 /// Icelake client microarchitecture based processors.
 PROC(IcelakeClient, "icelake-client", PROC_64_BIT)
 
 /// \name Icelake Server
 /// Icelake server microarchitecture based processors.
 PROC(IcelakeServer, "icelake-server", PROC_64_BIT)
 
+/// \name Tigerlake Server
+/// Tigerlake Server microarchitecture based processors.
+PROC(Tigerlake, "tigerlake", PROC_64_BIT)
+
 /// \name Knights Landing
 /// Knights Landing processor.
 PROC_WITH_FEAT(KNL, "knl", PROC_64_BIT, FEATURE_AVX512F)
 
 /// \name Knights Mill
 /// Knights Mill processor.
 PROC_WITH_FEAT(KNM, "knm", PROC_64_BIT, FEATURE_AVX5124FMAPS)
 

 FEATURE(FEATURE_AVX5124FMAPS)
 FEATURE(FEATURE_AVX512VPOPCNTDQ)
 FEATURE(FEATURE_AVX512VBMI2)
 FEATURE(FEATURE_GFNI)
 FEATURE(FEATURE_VPCLMULQDQ)
 FEATURE(FEATURE_AVX512VNNI)
 FEATURE(FEATURE_AVX512BITALG)
 FEATURE(FEATURE_AVX512BF16)
+FEATURE(FEATURE_AVX512VP2INTERSECT)
 
 
 // FIXME: When commented out features are supported in LLVM, enable them here.
 CPU_SPECIFIC("generic", 'A', "")
 CPU_SPECIFIC("pentium", 'B', "")
 CPU_SPECIFIC("pentium_pro", 'C', "+cmov")
 CPU_SPECIFIC("pentium_mmx", 'D', "+mmx")
 CPU_SPECIFIC("pentium_ii", 'E', "+cmov,+mmx")

clang/lib/Basic/Targets/X86.cpp

case CK_SkylakeServer:
     setFeatureEnabledImpl(Features, "avx512dq", true);
     setFeatureEnabledImpl(Features, "avx512bw", true);
     setFeatureEnabledImpl(Features, "avx512vl", true);
     setFeatureEnabledImpl(Features, "clwb", true);
     setFeatureEnabledImpl(Features, "pku", true);
     // SkylakeServer cores inherits all SKL features, except SGX
     goto SkylakeCommon;
 
+  case CK_Tigerlake:
+    setFeatureEnabledImpl(Features, "avx512vp2intersect", true);
+    setFeatureEnabledImpl(Features, "movdiri", true);
+    setFeatureEnabledImpl(Features, "movdir64b", true);
+    setFeatureEnabledImpl(Features, "shstk", true);
+    // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd
+    goto IcelakeCommon;
+
   case CK_IcelakeServer:
     setFeatureEnabledImpl(Features, "pconfig", true);
     setFeatureEnabledImpl(Features, "wbnoinvd", true);
     LLVM_FALLTHROUGH;
   case CK_IcelakeClient:
+IcelakeCommon:
     setFeatureEnabledImpl(Features, "vaes", true);
     setFeatureEnabledImpl(Features, "gfni", true);
     setFeatureEnabledImpl(Features, "vpclmulqdq", true);
     setFeatureEnabledImpl(Features, "avx512bitalg", true);
     setFeatureEnabledImpl(Features, "avx512vbmi2", true);
     setFeatureEnabledImpl(Features, "avx512vnni", true);
     setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
     setFeatureEnabledImpl(Features, "rdpid", true);
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   case CK_Broadwell:
   case CK_SkylakeClient:
   case CK_SkylakeServer:
   case CK_Cascadelake:
   case CK_Cooperlake:
   case CK_Cannonlake:
   case CK_IcelakeClient:
   case CK_IcelakeServer:
+  case CK_Tigerlake:
     // FIXME: Historically, we defined this legacy name, it would be nice to
     // remove it at some point. We've never exposed fine-grained names for
     // recent primary x86 CPUs, and we should keep it that way.
     defineCPUMacros(Builder, "corei7");
     break;
   case CK_KNL:
     defineCPUMacros(Builder, "knl");
     break;

clang/test/Driver/x86-march.c

 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=icelake-client 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=icelake-client
 // icelake-client: "-target-cpu" "icelake-client"
 //
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=icelake-server 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=icelake-server
 // icelake-server: "-target-cpu" "icelake-server"
 //
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=tigerlake 2>&1 \
+// RUN:   | FileCheck %s -check-prefix=tigerlake
+// tigerlake: "-target-cpu" "tigerlake"
+//
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=lakemont 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=lakemont
 // lakemont: "-target-cpu" "lakemont"
 //
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=bonnell 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=bonnell
 // bonnell: "-target-cpu" "bonnell"
 //

clang/test/Misc/target-invalid-cpu-note.c

 // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
 // X86: error: unknown target CPU 'not-a-cpu'
 // X86: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3,
 // X86-SAME: i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3,
 // X86-SAME: pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott,
 // X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
 // X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
 // X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
-// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, knl, knm, lakemont, k6, k6-2, k6-3,
+// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, knl, knm, lakemont, k6, k6-2, k6-3,
 // X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
 // X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
 // X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2,
 // X86-SAME: x86-64, geode
 
 // RUN: not %clang_cc1 -triple x86_64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86_64
 // X86_64: error: unknown target CPU 'not-a-cpu'
 // X86_64: note: valid target CPU values are: nocona, core2, penryn, bonnell,
 // X86_64-SAME: atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere,
 // X86_64-SAME: sandybridge, corei7-avx, ivybridge, core-avx-i, haswell,
 // X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake,
-// X86_64-SAME: icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
+// X86_64-SAME: icelake-client, icelake-server, tigerlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
 // X86_64-SAME: athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1,
 // X86_64-SAME: btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, x86-64
 
 // RUN: not %clang_cc1 -triple nvptx--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix NVPTX
 // NVPTX: error: unknown target CPU 'not-a-cpu'
 // NVPTX: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, sm_35,
 // NVPTX-SAME: sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72
 

clang/test/Preprocessor/predefined-arch-macros.c

 // CHECK_ICX_M64: #define __amd64 1
 // CHECK_ICX_M64: #define __amd64__ 1
 // CHECK_ICX_M64: #define __corei7 1
 // CHECK_ICX_M64: #define __corei7__ 1
 // CHECK_ICX_M64: #define __tune_corei7__ 1
 // CHECK_ICX_M64: #define __x86_64 1
 // CHECK_ICX_M64: #define __x86_64__ 1
 
+// RUN: %clang -march=tigerlake -m32 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_TGL_M32
+// CHECK_TGL_M32: #define __AES__ 1
+// CHECK_TGL_M32: #define __AVX2__ 1
+// CHECK_TGL_M32: #define __AVX512BITALG__ 1
+// CHECK_TGL_M32: #define __AVX512BW__ 1
+// CHECK_TGL_M32: #define __AVX512CD__ 1
+// CHECK_TGL_M32: #define __AVX512DQ__ 1
+// CHECK_TGL_M32: #define __AVX512F__ 1
+// CHECK_TGL_M32: #define __AVX512IFMA__ 1
+// CHECK_TGL_M32: #define __AVX512VBMI2__ 1
+// CHECK_TGL_M32: #define __AVX512VBMI__ 1
+// CHECK_TGL_M32: #define __AVX512VL__ 1
+// CHECK_TGL_M32: #define __AVX512VNNI__ 1
+// CHECK_TGL_M32: #define __AVX512VP2INTERSECT__ 1
+// CHECK_TGL_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_TGL_M32: #define __AVX__ 1
+// CHECK_TGL_M32: #define __BMI2__ 1
+// CHECK_TGL_M32: #define __BMI__ 1
+// CHECK_TGL_M32: #define __CLFLUSHOPT__ 1
+// CHECK_TGL_M32: #define __CLWB__ 1
+// CHECK_TGL_M32: #define __F16C__ 1
+// CHECK_TGL_M32: #define __FMA__ 1
+// CHECK_TGL_M32: #define __GFNI__ 1
+// CHECK_TGL_M32: #define __INVPCID__ 1
+// CHECK_TGL_M32: #define __LZCNT__ 1
+// CHECK_TGL_M32: #define __MMX__ 1
+// CHECK_TGL_M32: #define __MOVBE__ 1
+// CHECK_TGL_M32: #define __MOVDIR64B__ 1
+// CHECK_TGL_M32: #define __MOVDIRI__ 1
+// CHECK_TGL_M32: #define __MPX__ 1
+// CHECK_TGL_M32: #define __PCLMUL__ 1
+// CHECK_TGL_M32: #define __PKU__ 1
+// CHECK_TGL_M32: #define __POPCNT__ 1
+// CHECK_TGL_M32: #define __PRFCHW__ 1
+// CHECK_TGL_M32: #define __RDPID__ 1
+// CHECK_TGL_M32: #define __RDRND__ 1
+// CHECK_TGL_M32: #define __RDSEED__ 1
+// CHECK_TGL_M32: #define __SGX__ 1
+// CHECK_TGL_M32: #define __SHA__ 1
+// CHECK_TGL_M32: #define __SHSTK__ 1
+// CHECK_TGL_M32: #define __SSE2__ 1
+// CHECK_TGL_M32: #define __SSE3__ 1
+// CHECK_TGL_M32: #define __SSE4_1__ 1
+// CHECK_TGL_M32: #define __SSE4_2__ 1
+// CHECK_TGL_M32: #define __SSE__ 1
+// CHECK_TGL_M32: #define __SSSE3__ 1
+// CHECK_TGL_M32: #define __VAES__ 1
+// CHECK_TGL_M32: #define __VPCLMULQDQ__ 1
+// CHECK_TGL_M32-NOT: #define __WBNOINVD__ 1
+// CHECK_TGL_M32-NOT: #define __PCONFIG__ 1
+// CHECK_TGL_M32: #define __XSAVEC__ 1
+// CHECK_TGL_M32: #define __XSAVEOPT__ 1
+// CHECK_TGL_M32: #define __XSAVES__ 1
+// CHECK_TGL_M32: #define __XSAVE__ 1
+// CHECK_TGL_M32: #define __corei7 1
+// CHECK_TGL_M32: #define __corei7__ 1
+// CHECK_TGL_M32: #define __i386 1
+// CHECK_TGL_M32: #define __i386__ 1
+// CHECK_TGL_M32: #define __tune_corei7__ 1
+// CHECK_TGL_M32: #define i386 1
+
+// RUN: %clang -march=tigerlake -m64 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_TGL_M64
+// CHECK_TGL_M64: #define __AES__ 1
+// CHECK_TGL_M64: #define __AVX2__ 1
+// CHECK_TGL_M64: #define __AVX512BITALG__ 1
+// CHECK_TGL_M64: #define __AVX512BW__ 1
+// CHECK_TGL_M64: #define __AVX512CD__ 1
+// CHECK_TGL_M64: #define __AVX512DQ__ 1
+// CHECK_TGL_M64: #define __AVX512F__ 1
+// CHECK_TGL_M64: #define __AVX512IFMA__ 1
+// CHECK_TGL_M64: #define __AVX512VBMI2__ 1
+// CHECK_TGL_M64: #define __AVX512VBMI__ 1
+// CHECK_TGL_M64: #define __AVX512VL__ 1
+// CHECK_TGL_M64: #define __AVX512VNNI__ 1
+// CHECK_TGL_M64: #define __AVX512VP2INTERSECT__ 1
+// CHECK_TGL_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_TGL_M64: #define __AVX__ 1
+// CHECK_TGL_M64: #define __BMI2__ 1
+// CHECK_TGL_M64: #define __BMI__ 1
+// CHECK_TGL_M64: #define __CLFLUSHOPT__ 1
+// CHECK_TGL_M64: #define __CLWB__ 1
+// CHECK_TGL_M64: #define __F16C__ 1
+// CHECK_TGL_M64: #define __FMA__ 1
+// CHECK_TGL_M64: #define __GFNI__ 1
+// CHECK_TGL_M64: #define __INVPCID__ 1
+// CHECK_TGL_M64: #define __LZCNT__ 1
+// CHECK_TGL_M64: #define __MMX__ 1
+// CHECK_TGL_M64: #define __MOVBE__ 1
+// CHECK_TGL_M64: #define __MOVDIR64B__ 1
+// CHECK_TGL_M64: #define __MOVDIRI__ 1
+// CHECK_TGL_M64: #define __MPX__ 1
+// CHECK_TGL_M64: #define __PCLMUL__ 1
+// CHECK_TGL_M64: #define __PKU__ 1
+// CHECK_TGL_M64: #define __POPCNT__ 1
+// CHECK_TGL_M64: #define __PRFCHW__ 1
+// CHECK_TGL_M64: #define __RDPID__ 1
+// CHECK_TGL_M64: #define __RDRND__ 1
+// CHECK_TGL_M64: #define __RDSEED__ 1
+// CHECK_TGL_M64: #define __SGX__ 1
+// CHECK_TGL_M64: #define __SHA__ 1
+// CHECK_TGL_M64: #define __SHSTK__ 1
+// CHECK_TGL_M64: #define __SSE2__ 1
+// CHECK_TGL_M64: #define __SSE3__ 1
+// CHECK_TGL_M64: #define __SSE4_1__ 1
+// CHECK_TGL_M64: #define __SSE4_2__ 1
+// CHECK_TGL_M64: #define __SSE__ 1
+// CHECK_TGL_M64: #define __SSSE3__ 1
+// CHECK_TGL_M64: #define __VAES__ 1
+// CHECK_TGL_M64: #define __VPCLMULQDQ__ 1
+// CHECK_TGL_M64-NOT: #define __WBNOINVD__ 1
+// CHECK_TGL_M64-NOT: #define __PCONFIG__ 1
+// CHECK_TGL_M64: #define __XSAVEC__ 1
+// CHECK_TGL_M64: #define __XSAVEOPT__ 1
+// CHECK_TGL_M64: #define __XSAVES__ 1
+// CHECK_TGL_M64: #define __XSAVE__ 1
+// CHECK_TGL_M64: #define __amd64 1
+// CHECK_TGL_M64: #define __amd64__ 1
+// CHECK_TGL_M64: #define __corei7 1
+// CHECK_TGL_M64: #define __corei7__ 1
+// CHECK_TGL_M64: #define __tune_corei7__ 1
+// CHECK_TGL_M64: #define __x86_64 1
+// CHECK_TGL_M64: #define __x86_64__ 1
+
 // RUN: %clang -march=atom -m32 -E -dM %s -o - 2>&1 \
 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_ATOM_M32
 // CHECK_ATOM_M32: #define __MMX__ 1
 // CHECK_ATOM_M32: #define __MOVBE__ 1
 // CHECK_ATOM_M32: #define __SSE2__ 1
 // CHECK_ATOM_M32: #define __SSE3__ 1
 // CHECK_ATOM_M32: #define __SSE__ 1

llvm/include/llvm/Support/X86TargetParser.def

 // Entries below this are not in libgcc/compiler-rt.
 X86_CPU_SUBTYPE       ("core2",          INTEL_CORE2_65)
 X86_CPU_SUBTYPE       ("penryn",         INTEL_CORE2_45)
 X86_CPU_SUBTYPE       ("k6",             AMDPENTIUM_K6)
 X86_CPU_SUBTYPE       ("k6-2",           AMDPENTIUM_K62)
 X86_CPU_SUBTYPE       ("k6-3",           AMDPENTIUM_K63)
 X86_CPU_SUBTYPE       ("geode",          AMDPENTIUM_GEODE)
 X86_CPU_SUBTYPE       ("cooperlake",     INTEL_COREI7_COOPERLAKE)
+X86_CPU_SUBTYPE       ("tigerlake",      INTEL_COREI7_TIGERLAKE)
 #undef X86_CPU_SUBTYPE_COMPAT
 #undef X86_CPU_SUBTYPE
 
 
 // This macro is used for cpu types present in compiler-rt/libgcc.
 #ifndef X86_FEATURE_COMPAT
 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) X86_FEATURE(VAL, ENUM)
 #endif

 X86_FEATURE_COMPAT(28, FEATURE_AVX5124VNNIW,    "avx5124vnniw")
 X86_FEATURE_COMPAT(29, FEATURE_AVX5124FMAPS,    "avx5124fmaps")
 X86_FEATURE_COMPAT(30, FEATURE_AVX512VPOPCNTDQ, "avx512vpopcntdq")
 X86_FEATURE_COMPAT(31, FEATURE_AVX512VBMI2,     "avx512vbmi2")
 X86_FEATURE_COMPAT(32, FEATURE_GFNI,            "gfni")
 X86_FEATURE_COMPAT(33, FEATURE_VPCLMULQDQ,      "vpclmulqdq")
 X86_FEATURE_COMPAT(34, FEATURE_AVX512VNNI,      "avx512vnni")
 X86_FEATURE_COMPAT(35, FEATURE_AVX512BITALG,    "avx512bitalg")
+X86_FEATURE_COMPAT(36, FEATURE_AVX512VP2INTERSECT, "avx512vp2intersect")
 // Features below here are not in libgcc/compiler-rt.
 X86_FEATURE       (64, FEATURE_MOVBE)
 X86_FEATURE       (65, FEATURE_ADX)
 X86_FEATURE       (66, FEATURE_EM64T)
 X86_FEATURE       (67, FEATURE_CLFLUSHOPT)
 X86_FEATURE       (68, FEATURE_SHA)
 X86_FEATURE       (69, FEATURE_AVX512BF16)
 #undef X86_FEATURE_COMPAT
 #undef X86_FEATURE

llvm/lib/Support/Host.cpp

case 0x57:
       *Type = X86::INTEL_KNL; // knl
       break;
 
     case 0x85:
       *Type = X86::INTEL_KNM; // knm
       break;
 
     default: // Unknown family 6 CPU, try to guess.
+      // TODO detect tigerlake host
+      if (Features & (1 << X86::FEATURE_AVX512VP2INTERSECT)) {
+        *Type = X86::INTEL_COREI7;
+        *Subtype = X86::INTEL_COREI7_TIGERLAKE;
+        break;
+      }
+
       if (Features & (1 << X86::FEATURE_AVX512VBMI2)) {
         *Type = X86::INTEL_COREI7;
         *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
         break;
       }
 
       if (Features & (1 << X86::FEATURE_AVX512VBMI)) {
         *Type = X86::INTEL_COREI7;
if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
     setFeature(X86::FEATURE_AVX512BITALG);
   if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
     setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
 
   if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
     setFeature(X86::FEATURE_AVX5124VNNIW);
   if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
     setFeature(X86::FEATURE_AVX5124FMAPS);
+  if (HasLeaf7 && ((EDX >> 8) & 1))
+    setFeature(X86::FEATURE_AVX512VP2INTERSECT);
 
   unsigned MaxExtLevel;
   getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
 
   bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
                      !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
   if (HasExtLeaf1 && ((ECX >> 6) & 1))
     setFeature(X86::FEATURE_SSE4_A);

llvm/lib/Target/X86/X86.td

def ProcessorFeatures {
 
   // Icelake Server
   list<SubtargetFeature> ICXSpecificFeatures = [FeaturePCONFIG,
                                                 FeatureWBNOINVD,
                                                 FeatureHasFastGather];
   list<SubtargetFeature> ICXFeatures =
     !listconcat(ICLInheritableFeatures, ICXSpecificFeatures);
 
+  //Tigerlake
+  list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,
+                                                  FeatureMOVDIRI,
+                                                  FeatureMOVDIR64B,
+                                                  FeatureSHSTK];
+  list<SubtargetFeature> TGLSpecificFeatures = [FeatureHasFastGather];
+  list<SubtargetFeature> TGLInheritableFeatures =
+    !listconcat(TGLAdditionalFeatures ,TGLSpecificFeatures);
+  list<SubtargetFeature> TGLFeatures =
+    !listconcat(ICLFeatures, TGLInheritableFeatures );
+
   // Atom
   list<SubtargetFeature> AtomInheritableFeatures = [FeatureX87,
                                                     FeatureCMPXCHG8B,
                                                     FeatureCMOV,
                                                     FeatureMMX,
                                                     FeatureSSSE3,
                                                     FeatureFXSR,
                                                     FeatureNOPL,

 def : ProcessorModel<"cooperlake", SkylakeServerModel,
                      ProcessorFeatures.CPXFeatures>;
 def : ProcessorModel<"cannonlake", SkylakeServerModel,
                      ProcessorFeatures.CNLFeatures>;
 def : ProcessorModel<"icelake-client", SkylakeServerModel,
                      ProcessorFeatures.ICLFeatures>;
 def : ProcessorModel<"icelake-server", SkylakeServerModel,
                      ProcessorFeatures.ICXFeatures>;
+def : ProcessorModel<"tigerlake", SkylakeServerModel,
+                     ProcessorFeatures.TGLFeatures>;
 
 // AMD CPUs.
 
 def : Proc<"k6",   [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
                     FeatureMMX]>;
 def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
                     Feature3DNow]>;
 def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,

llvm/test/CodeGen/X86/cpus-intel.ll

 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=skylake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=skx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cascadelake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=atom 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=slm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont-plus 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tremont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knl 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
 }