[PowerPC] Use xxleqv to set all one vector IMM(-1).

[jsji]

Summary

xxspltib/vspltisb are 3 cycle PM instructions,
xxleqv is 2 cycle ALU instruction.

We should use xxleqv to set all one vectors.

[• wuzish]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1320

Has immAllOnesV contained bitcast semantic? It's equal to ISD::isBuildVectorAllOnes.

4111

If we don't enum all the type, just use v4i32 version. Are other types bitcast/canonical into v4i32 automatically?

[jsji]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1320

No, it doesn't.

4111

We will canonize isBuildVectorAllOnes into v16i8, we don't need to enum all types.

[jsji]

Ping..

[steven.zhang]

Only v4i32 is handled. We need to handle all the valid vector type.

llvm/lib/Target/PowerPC/PPCInstrFormats.td

1212 ↗

(On Diff #212635)

Can you commit another NFC patch to do the rename and the XX3Form_SetZero seems to be completely the same as this one. I have no idea why we have two forms. We need to remove it.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1320

You are matching the pattern for v4i32, but miss to catch the other type of pattern. i.e. v8i16 etc. We won't canonical all the vector type to v4i32 during the type legalize. Even we do that, it is better to add all the match rules in td file as we cannot depend on the legalization implementation.

Your patch cannot handle the other vector type except the v4i32.

define dso_local <8 x i16> @_Z3foov() local_unnamed_addr #0 {
entry:
  ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1,i16 -1, i16 -1, i16 -1, i16 -1>
}

We need add some pattern like:

def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),
            (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
...

2450

extra space.

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

761 ↗

(On Diff #212635)

Add some tests to test v1i128, v2i64, v8i16 v16i8

[jsji]

Thanks @steven.zhang and @wuzish.

llvm/lib/Target/PowerPC/PPCInstrFormats.td

1212 ↗

(On Diff #212635)

Sure, done in https://reviews.llvm.org/rL368856

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1320

I should say, isBuildVectorAllOnes can see through bitcast, the bitconvert here is mostly the trick to get complexity up, so that we can prefer this over other patterns.

1320

Agree. Will do that.

4111

Ah, my bad, yes, you are right, I mis-read the condition of lowering, we did not really canonize.

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

761 ↗

(On Diff #212635)

I will add those in another file, this file is far too big.

[jsji]

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

761 ↗

(On Diff #212635)

Added a new test file for different vector types in https://reviews.llvm.org/rL368859

[jsji]

Added patterns for other type and rebased to pick up new tests.

[steven.zhang]

LGTM except some minor comments.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

390

line too long. immAnyExt8NonAllOnes or immNonAllOnesAnyExt8?

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1328

Can we put these pattern in line 4112 to match the build vector in the same place ?

[• wuzish]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

390

I think no need to modify this to exclude all ones. So long as its position which is blow all ones Pat, it would not be selected before all ones. Can have a try.

[jsji]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

390

No, ISEL select the pattern according to complexity , not the position of where the pattern defined.
And yes, I did try before modifying this pattern, if we don't exclude all ones here, this pattern will be selected first, as it is complexity is far larger than others.
eg: 477 vs. 407.

[jsji]

Fix long line and move the patterns.

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
     VORC,
     VSEL,
     VXOR,
     XVNEGDP,
     XVNEGSP,
     XXLAND,
     XXLANDC,
     XXLEQV,
+    XXLEQVOnes,
     XXLNAND,
     XXLNOR,
     XXLOR,
     XXLORf,
     XXLORC,
     XXLXOR,
     XXLXORdpz,
     XXLXORspz,

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
   case PPC::LIS8:
   case PPC::QVGPCI:
   case PPC::ADDIStocHA8:
   case PPC::ADDItocL:
   case PPC::LOAD_STACK_GUARD:
   case PPC::XXLXORz:
   case PPC::XXLXORspz:
   case PPC::XXLXORdpz:
+  case PPC::XXLEQVOnes:
   case PPC::V_SET0B:
   case PPC::V_SET0H:
   case PPC::V_SET0:
   case PPC::V_SETALLONESB:
   case PPC::V_SETALLONESH:
   case PPC::V_SETALLONES:
   case PPC::CRSET:
   case PPC::CRUNSET:

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
   // sign extended field.  Used by instructions like 'addi'.
   return (int64_t)Imm == (short)Imm;
 }]>;
 def immZExt16  : PatLeaf<(imm), [{
   // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
   // field.  Used by instructions like 'ori'.
   return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
 }], LO16>;
-def immAnyExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm) || isUInt<8>(Imm); }]>;
+def immAnyExt8NonAllOne : ImmLeaf<i32, [{ return (isInt<8>(Imm) && (Imm != -1))
+                                              || (isUInt<8>(Imm) && (Imm != 0xFF)); }]>;
 def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>;
 
 // imm16Shifted* - These match immediates where the low 16-bits are zero.  There
 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt.  These two forms are
 // identical in 32-bit mode, but in 64-bit mode, they return true if the
 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
 // clear).
 def imm16ShiftedZExt : PatLeaf<(imm), [{

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def XXLNAND : XX3Form<60, 178,
                           "xxlnand $XT, $XA, $XB", IIC_VecGeneral,
                           [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA,
                                                     v4i32:$XB)))]>;
   } // isCommutable
 
   def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
             (XXLEQV $A, $B)>;
 
+  let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
+      isReMaterializable = 1 in {
+    def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins),
+                         "xxleqv $XT, $XT, $XT", IIC_VecGeneral,
+                         [(set v4i32:$XT, (v4i32 immAllOnesV))]>;
+  }
+
+  def : Pat<(v4i32 (bitconvert (v16i8 immAllOnesV))),
+            (XXLEQVOnes)>;
+  def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))),
+            (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+  def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))),
+            (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+  def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),
+            (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+  def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
+            (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+
   def XXLORC : XX3Form<60, 170,
                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                        "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
                        [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
 
   // VSX scalar loads introduced in ISA 2.07
   let mayLoad = 1, mayStore = 0 in {
     let CodeSize = 3 in

 // (move to FPR, nothing else needed)
 def : Pat<(f64 (bitconvert i64:$S)),
           (f64 (MTVSRD $S))>;
 }
 
 // Materialize a zero-vector of long long
 def : Pat<(v2i64 immAllZerosV),
           (v2i64 (XXLXORz))>;
 }
 
 def AlignValues {
   dag F32_TO_BE_WORD1 = (v4f32 (XXSLDWI (XSCVDPSPN $B), (XSCVDPSPN $B), 3));
   dag I32_TO_BE_WORD1 = (COPY_TO_REGCLASS (MTVSRWZ $B), VSRC);
 }
 
 // The following VSX instructions were introduced in Power ISA 3.0
 def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">;
let AddedComplexity = 400 in {
   }
 
   let Predicates = [HasP9Vector] in {
     // Endianness-neutral patterns for const splats with ISA 3.0 instructions.
     def : Pat<(v4i32 (scalar_to_vector i32:$A)),
               (v4i32 (MTVSRWS $A))>;
     def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
               (v4i32 (MTVSRWS $A))>;
-    def : Pat<(v16i8 (build_vector immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
-                                   immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
-                                   immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
-                                   immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
-                                   immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
-                                   immAnyExt8:$A)),
+    def : Pat<(v16i8 (build_vector immAnyExt8NonAllOne:$A, immAnyExt8NonAllOne:$A,
+                                   immAnyExt8NonAllOne:$A, immAnyExt8NonAllOne:$A,
+                                   immAnyExt8NonAllOne:$A, immAnyExt8NonAllOne:$A,
+                                   immAnyExt8NonAllOne:$A, immAnyExt8NonAllOne:$A,
+                                   immAnyExt8NonAllOne:$A, immAnyExt8NonAllOne:$A,
+                                   immAnyExt8NonAllOne:$A, immAnyExt8NonAllOne:$A,
+                                   immAnyExt8NonAllOne:$A, immAnyExt8NonAllOne:$A,
+                                   immAnyExt8NonAllOne:$A, immAnyExt8NonAllOne:$A)),
               (v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>;
-    def : Pat<(v16i8 immAllOnesV),
-              (v16i8 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
-    def : Pat<(v8i16 immAllOnesV),
-              (v8i16 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
-    def : Pat<(v4i32 immAllOnesV),
-              (v4i32 (XXSPLTIB 255))>;
-    def : Pat<(v2i64 immAllOnesV),
-              (v2i64 (XXSPLTIB 255))>;
     def : Pat<(v4i32 (scalar_to_vector FltToIntLoad.A)),
               (v4i32 (XVCVSPSXWS (LXVWSX xoaddr:$A)))>;
     def : Pat<(v4i32 (scalar_to_vector FltToUIntLoad.A)),
               (v4i32 (XVCVSPUXWS (LXVWSX xoaddr:$A)))>;
     def : Pat<(v4i32 (scalar_to_vector DblToIntLoadP9.A)),
               (v4i32 (XXSPLTW (COPY_TO_REGCLASS
                                 (XSCVDPSXWS (DFLOADf64 iaddrX4:$A)), VSRC), 1))>;
     def : Pat<(v4i32 (scalar_to_vector DblToUIntLoadP9.A)),

llvm/test/CodeGen/PowerPC/build-vector-allones.ll

 ; P7BE-LABEL: One1i128:
 ; P7BE:       # %bb.0: # %entry
 ; P7BE-NEXT:    li r3, -1
 ; P7BE-NEXT:    li r4, -1
 ; P7BE-NEXT:    blr
 ;
 ; P8LE-LABEL: One1i128:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    vspltisb v2, -1
+; P8LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P8LE-NEXT:    blr
 ;
 ; P9LE-LABEL: One1i128:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    xxspltib vs34, 255
+; P9LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P9LE-NEXT:    blr
 entry:
   ret <1 x i128> <i128 -1>
 }
 
 define <2 x i64> @One2i64() {
 ; P7BE-LABEL: One2i64:
 ; P7BE:       # %bb.0: # %entry
 ; P7BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; P7BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; P7BE-NEXT:    lxvd2x vs34, 0, r3
 ; P7BE-NEXT:    blr
 ;
 ; P8LE-LABEL: One2i64:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    vspltisb v2, -1
+; P8LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P8LE-NEXT:    blr
 ;
 ; P9LE-LABEL: One2i64:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    xxspltib vs34, 255
+; P9LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P9LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 -1, i64 -1>
 }
 
 define <4 x i32> @One4i32() {
 ; P7BE-LABEL: One4i32:
 ; P7BE:       # %bb.0: # %entry
 ; P7BE-NEXT:    vspltisb v2, -1
 ; P7BE-NEXT:    blr
 ;
 ; P8LE-LABEL: One4i32:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    vspltisb v2, -1
+; P8LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P8LE-NEXT:    blr
 ;
 ; P9LE-LABEL: One4i32:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    xxspltib vs34, 255
+; P9LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P9LE-NEXT:    blr
 entry:
   ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
 }
 
 define <8 x i16> @One8i16() {
 ; P7BE-LABEL: One8i16:
 ; P7BE:       # %bb.0: # %entry
 ; P7BE-NEXT:    vspltisb v2, -1
 ; P7BE-NEXT:    blr
 ;
 ; P8LE-LABEL: One8i16:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    vspltisb v2, -1
+; P8LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P8LE-NEXT:    blr
 ;
 ; P9LE-LABEL: One8i16:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    xxspltib vs34, 255
+; P9LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P9LE-NEXT:    blr
 entry:
   ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
 }
 
 define <16 x i8> @One16i8() {
 ; P7BE-LABEL: One16i8:
 ; P7BE:       # %bb.0: # %entry
 ; P7BE-NEXT:    vspltisb v2, -1
 ; P7BE-NEXT:    blr
 ;
 ; P8LE-LABEL: One16i8:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    vspltisb v2, -1
+; P8LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P8LE-NEXT:    blr
 ;
 ; P9LE-LABEL: One16i8:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    xxspltib vs34, 255
+; P9LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P9LE-NEXT:    blr
 entry:
   ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
 }

llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll

 
 entry:
   ret <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
 }
 
 define <16 x i8> @test12() {
 ; CHECK-LABEL: test12:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxspltib v2, 255
+; CHECK-NEXT:    xxleqv v2, v2, v2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test12:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxspltib v2, 255
+; CHECK-BE-NEXT:    xxleqv v2, v2, v2
 ; CHECK-BE-NEXT:    blr
 
 entry:
   ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
 }
 
 define <16 x i8> @test13() {
 ; CHECK-LABEL: test13:

llvm/test/CodeGen/PowerPC/sat-add.ll

; CHECK-NEXT:    blr
   %r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
   ret <16 x i8> %r
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    addi 3, 3, .LCPI25_0@toc@l
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vaddubm 3, 2, 3
 ; CHECK-NEXT:    vcmpgtub 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 35, 36, 34
+; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
   %c = icmp ugt <16 x i8> %x, %a
   %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
   ret <16 x i8> %r
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI26_1@toc@ha
-; CHECK-NEXT:    vspltisb 5, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    addi 3, 3, .LCPI26_1@toc@l
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI26_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI26_0@toc@l
 ; CHECK-NEXT:    vcmpgtub 3, 2, 3
 ; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    vaddubm 2, 2, 4
-; CHECK-NEXT:    xxsel 34, 34, 37, 35
+; CHECK-NEXT:    xxsel 34, 34, 0, 35
 ; CHECK-NEXT:    blr
   %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
   %c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
   %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
   ret <16 x i8> %r
 }
 
 define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {
; CHECK-NEXT:    blr
   %r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
   ret <8 x i16> %r
 }
 
 define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI28_0@toc@ha
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    addi 3, 3, .LCPI28_0@toc@l
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduhm 3, 2, 3
 ; CHECK-NEXT:    vcmpgtuh 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 35, 36, 34
+; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
   %c = icmp ugt <8 x i16> %x, %a
   %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
   ret <8 x i16> %r
 }
 
 define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI29_1@toc@ha
-; CHECK-NEXT:    vspltisb 5, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    addi 3, 3, .LCPI29_1@toc@l
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI29_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI29_0@toc@l
 ; CHECK-NEXT:    vcmpgtuh 3, 2, 3
 ; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    vadduhm 2, 2, 4
-; CHECK-NEXT:    xxsel 34, 34, 37, 35
+; CHECK-NEXT:    xxsel 34, 34, 0, 35
 ; CHECK-NEXT:    blr
   %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
   %c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
   %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
   ret <8 x i16> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) {
; CHECK-NEXT:    blr
   %r = add <4 x i32> %s, <i32 42, i32 42, i32 42, i32 42>
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    addi 3, 3, .LCPI31_0@toc@l
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 3, 2, 3
 ; CHECK-NEXT:    vcmpgtuw 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 35, 36, 34
+; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
   %c = icmp ugt <4 x i32> %x, %a
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI32_1@toc@ha
-; CHECK-NEXT:    vspltisb 5, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    addi 3, 3, .LCPI32_1@toc@l
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI32_0@toc@l
 ; CHECK-NEXT:    vcmpgtuw 3, 2, 3
 ; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 4
-; CHECK-NEXT:    xxsel 34, 34, 37, 35
+; CHECK-NEXT:    xxsel 34, 34, 0, 35
 ; CHECK-NEXT:    blr
   %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
   %c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
 define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
; CHECK-NEXT:    blr
   %r = add <2 x i64> %s, <i64 42, i64 42>
   ret <2 x i64> %r
 }
 
 define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI34_0@toc@ha
-; CHECK-NEXT:    vspltisb 4, -1
 ; CHECK-NEXT:    addi 3, 3, .LCPI34_0@toc@l
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vaddudm 3, 2, 3
 ; CHECK-NEXT:    vcmpgtud 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 35, 36, 34
+; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <2 x i64> %x, <i64 42, i64 42>
   %c = icmp ugt <2 x i64> %x, %a
   %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
   ret <2 x i64> %r
 }
 
 define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
-; CHECK-NEXT:    vspltisb 5, -1
 ; CHECK-NEXT:    addi 3, 3, .LCPI35_1@toc@l
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI35_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI35_0@toc@l
+; CHECK-NEXT:    lxvd2x 1, 0, 3
 ; CHECK-NEXT:    xxswapd 35, 0
-; CHECK-NEXT:    lxvd2x 0, 0, 3
+; CHECK-NEXT:    xxleqv 0, 0, 0
+; CHECK-NEXT:    xxswapd 36, 1
 ; CHECK-NEXT:    vcmpgtud 3, 2, 3
-; CHECK-NEXT:    xxswapd 36, 0
 ; CHECK-NEXT:    vaddudm 2, 2, 4
-; CHECK-NEXT:    xxsel 34, 34, 37, 35
+; CHECK-NEXT:    xxsel 34, 34, 0, 35
 ; CHECK-NEXT:    blr
   %a = add <2 x i64> %x, <i64 42, i64 42>
   %c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>
   %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
   ret <2 x i64> %r
 }
 
 define <16 x i8> @unsigned_sat_variable_v16i8_using_min(<16 x i8> %x, <16 x i8> %y) {
; CHECK-NEXT:    blr
   %r = add <16 x i8> %s, %y
   ret <16 x i8> %r
 }
 
 define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_sum(<16 x i8> %x, <16 x i8> %y) {
 ; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddubm 3, 2, 3
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtub 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 35, 36, 34
+; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <16 x i8> %x, %y
   %c = icmp ugt <16 x i8> %x, %a
   %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
   ret <16 x i8> %r
 }
 
 define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_notval(<16 x i8> %x, <16 x i8> %y) {
 ; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxlnor 36, 35, 35
-; CHECK-NEXT:    vspltisb 5, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtub 4, 2, 4
 ; CHECK-NEXT:    vaddubm 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 34, 37, 36
+; CHECK-NEXT:    xxsel 34, 34, 0, 36
 ; CHECK-NEXT:    blr
   %noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %a = add <16 x i8> %x, %y
   %c = icmp ugt <16 x i8> %x, %noty
   %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
   ret <16 x i8> %r
 }
 
; CHECK-NEXT:    blr
   %r = add <8 x i16> %s, %y
   ret <8 x i16> %r
 }
 
 define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_sum(<8 x i16> %x, <8 x i16> %y) {
 ; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vadduhm 3, 2, 3
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtuh 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 35, 36, 34
+; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <8 x i16> %x, %y
   %c = icmp ugt <8 x i16> %x, %a
   %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
   ret <8 x i16> %r
 }
 
 define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8 x i16> %y) {
 ; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxlnor 36, 35, 35
-; CHECK-NEXT:    vspltisb 5, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtuh 4, 2, 4
 ; CHECK-NEXT:    vadduhm 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 34, 37, 36
+; CHECK-NEXT:    xxsel 34, 34, 0, 36
 ; CHECK-NEXT:    blr
   %noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
   %a = add <8 x i16> %x, %y
   %c = icmp ugt <8 x i16> %x, %noty
   %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
   ret <8 x i16> %r
 }
 
; CHECK-NEXT:    blr
   %r = add <4 x i32> %s, %y
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_sum(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vadduwm 3, 2, 3
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtuw 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 35, 36, 34
+; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <4 x i32> %x, %y
   %c = icmp ugt <4 x i32> %x, %a
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxlnor 36, 35, 35
-; CHECK-NEXT:    vspltisb 5, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtuw 4, 2, 4
 ; CHECK-NEXT:    vadduwm 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 34, 37, 36
+; CHECK-NEXT:    xxsel 34, 34, 0, 36
 ; CHECK-NEXT:    blr
   %noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
   %a = add <4 x i32> %x, %y
   %c = icmp ugt <4 x i32> %x, %noty
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
; CHECK-NEXT:    blr
   %r = add <2 x i64> %s, %y
   ret <2 x i64> %r
 }
 
 define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_sum(<2 x i64> %x, <2 x i64> %y) {
 ; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddudm 3, 2, 3
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtud 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 35, 36, 34
+; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <2 x i64> %x, %y
   %c = icmp ugt <2 x i64> %x, %a
   %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
   ret <2 x i64> %r
 }
 
 define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2 x i64> %y) {
 ; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxlnor 36, 35, 35
-; CHECK-NEXT:    vspltisb 5, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtud 4, 2, 4
 ; CHECK-NEXT:    vaddudm 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 34, 37, 36
+; CHECK-NEXT:    xxsel 34, 34, 0, 36
 ; CHECK-NEXT:    blr
   %noty = xor <2 x i64> %y, <i64 -1, i64 -1>
   %a = add <2 x i64> %x, %y
   %c = icmp ugt <2 x i64> %x, %noty
   %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
   ret <2 x i64> %r
 }
 

llvm/test/CodeGen/PowerPC/setcc-logic.ll

; CHECK-NEXT:    blr
   %b = icmp eq <4 x i32> %Q, zeroinitializer
   %c = and <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_sign_bits_clear_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 36, 36, 36
 ; CHECK-NEXT:    xxlor 34, 34, 35
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 4
 ; CHECK-NEXT:    blr
   %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = and <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_bits_set_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 36, 36, 36
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
 ; CHECK-NEXT:    blr
   %a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = and <4 x i1> %a, %b
   ret <4 x i1> %c
 }
; CHECK-NEXT:    blr
   %b = icmp slt <4 x i32> %Q, zeroinitializer
   %c = or <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_bits_clear_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 36, 36, 36
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
 ; CHECK-NEXT:    xxlnor 34, 34, 34
 ; CHECK-NEXT:    blr
   %a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = or <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_sign_bits_clear_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 36, 36, 36
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 4
 ; CHECK-NEXT:    blr
   %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = or <4 x i1> %a, %b
   ret <4 x i1> %c
 }

llvm/test/CodeGen/PowerPC/signbit-shift.ll

; CHECK-NEXT:    blr
   %e = zext i1 %c to i32
   %r = add i32 %e, 41
   ret i32 %r
 }
 
 define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: add_zext_ifpos_vec_splat:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 3, -1
+; CHECK-NEXT:    xxleqv 35, 35, 35
 ; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI2_0@toc@l
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vsubuwm 2, 3, 2
 ; CHECK-NEXT:    blr
   %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = zext <4 x i1> %c to <4 x i32>
; CHECK-NEXT:    blr
   %e = sext i1 %c to i32
   %r = add i32 %e, 42
   ret i32 %r
 }
 
 define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: add_sext_ifpos_vec_splat:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 3, -1
+; CHECK-NEXT:    xxleqv 35, 35, 35
 ; CHECK-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI6_0@toc@l
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = sext <4 x i1> %c to <4 x i32>

llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll

 ; ALL-NEXT:    blr
   %result = sub <2 x i64> %x, %y
   ret <2 x i64> %result
 }
 
 define <2 x i64> @decrement_by_one(<2 x i64> %x) nounwind {
 ; VSX-LABEL: decrement_by_one:
 ; VSX:       # %bb.0:
-; VSX-NEXT:    vspltisb 3, -1
+; VSX-NEXT:    xxleqv 35, 35, 35
 ; VSX-NEXT:    vsubudm 2, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NOVSX-LABEL: decrement_by_one:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
 ; NOVSX-NEXT:    addi 3, 3, .LCPI4_0@toc@l
 ; NOVSX-NEXT:    lvx 3, 0, 3

llvm/test/CodeGen/PowerPC/vselect-constants.ll

; CHECK-NEXT:    blr
   %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_0_or_minus1_vec:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, 1
-; CHECK-NEXT:    vspltisb 4, -1
 ; CHECK-NEXT:    xxland 34, 34, 35
-; CHECK-NEXT:    vadduwm 2, 2, 4
+; CHECK-NEXT:    xxleqv 35, 35, 35
+; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_0_or_minus1_vec:
 ; CHECK:       # %bb.0: