[PowerPC] Use xxleqv to set all one vector IMM(-1).

[jsji]

Summary

xxspltib/vspltisb are 3 cycle PM instructions,
xxleqv is 2 cycle ALU instruction.

We should use xxleqv to set all one vectors.

[• wuzish]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1298

Has immAllOnesV contained bitcast semantic? It's equal to ISD::isBuildVectorAllOnes.

4079

If we don't enum all the type, just use v4i32 version. Are other types bitcast/canonical into v4i32 automatically?

[jsji]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1298

No, it doesn't.

4079

We will canonize isBuildVectorAllOnes into v16i8, we don't need to enum all types.

[jsji]

Ping..

[steven.zhang]

Only v4i32 is handled. We need to handle all the valid vector type.

llvm/lib/Target/PowerPC/PPCInstrFormats.td

1212

Can you commit another NFC patch to do the rename and the XX3Form_SetZero seems to be completely the same as this one. I have no idea why we have two forms. We need to remove it.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1298

You are matching the pattern for v4i32, but miss to catch the other type of pattern. i.e. v8i16 etc. We won't canonical all the vector type to v4i32 during the type legalize. Even we do that, it is better to add all the match rules in td file as we cannot depend on the legalization implementation.

Your patch cannot handle the other vector type except the v4i32.

define dso_local <8 x i16> @_Z3foov() local_unnamed_addr #0 {
entry:
  ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1,i16 -1, i16 -1, i16 -1, i16 -1>
}

We need add some pattern like:

def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),
            (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
...

2420

extra space.

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

761

Add some tests to test v1i128, v2i64, v8i16 v16i8

[jsji]

Thanks @steven.zhang and @wuzish.

llvm/lib/Target/PowerPC/PPCInstrFormats.td

1212

Sure, done in https://reviews.llvm.org/rL368856

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1298

I should say, isBuildVectorAllOnes can see through bitcast, the bitconvert here is mostly the trick to get complexity up, so that we can prefer this over other patterns.

1298

Agree. Will do that.

4079

Ah, my bad, yes, you are right, I mis-read the condition of lowering, we did not really canonize.

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

761

I will add those in another file, this file is far too big.

[jsji]

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

761

Added a new test file for different vector types in https://reviews.llvm.org/rL368859

[jsji]

Added patterns for other type and rebased to pick up new tests.

[steven.zhang]

LGTM except some minor comments.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

390 ↗

(On Diff #215233)

line too long. immAnyExt8NonAllOnes or immNonAllOnesAnyExt8?

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1306

Can we put these pattern in line 4112 to match the build vector in the same place ?

[• wuzish]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

390 ↗

(On Diff #215233)

I think no need to modify this to exclude all ones. So long as its position which is blow all ones Pat, it would not be selected before all ones. Can have a try.

[jsji]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

390 ↗

(On Diff #215233)

No, ISEL select the pattern according to complexity , not the position of where the pattern defined.
And yes, I did try before modifying this pattern, if we don't exclude all ones here, this pattern will be selected first, as it is complexity is far larger than others.
eg: 477 vs. 407.

[jsji]

Fix long line and move the patterns.

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
     VORC,
     VSEL,
     VXOR,
     XVNEGDP,
     XVNEGSP,
     XXLAND,
     XXLANDC,
     XXLEQV,
+    XXLEQVOnes,
     XXLNAND,
     XXLNOR,
     XXLOR,
     XXLORf,
     XXLORC,
     XXLXOR,
     XXLXORdpz,
     XXLXORspz,

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
   let Inst{11-15} = XA{4-0};
   let Inst{16-20} = XB{4-0};
   let Inst{21-28} = xo;
   let Inst{29}    = XA{5};
   let Inst{30}    = XB{5};
   let Inst{31}    = XT{5};
 }
 
-class XX3Form_Zero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
+class XX3Form_SameOp<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
   : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
   let XA = XT;
   let XB = XT;
 }
 
 class XX3Form_SetZero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern>

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
   case PPC::LIS8:
   case PPC::QVGPCI:
   case PPC::ADDIStocHA8:
   case PPC::ADDItocL:
   case PPC::LOAD_STACK_GUARD:
   case PPC::XXLXORz:
   case PPC::XXLXORspz:
   case PPC::XXLXORdpz:
+  case PPC::XXLEQVOnes:
   case PPC::V_SET0B:
   case PPC::V_SET0H:
   case PPC::V_SET0:
   case PPC::V_SETALLONESB:
   case PPC::V_SETALLONESH:
   case PPC::V_SETALLONES:
   case PPC::CRSET:
   case PPC::CRUNSET:

llvm/lib/Target/PowerPC/PPCInstrVSX.td

let Uses = [RM] in {
   def XXLXOR : XX3Form<60, 154,
                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                        "xxlxor $XT, $XA, $XB", IIC_VecGeneral,
                        [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
   } // isCommutable
 
   let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
       isReMaterializable = 1 in {
-    def XXLXORz : XX3Form_Zero<60, 154, (outs vsrc:$XT), (ins),
+    def XXLXORz : XX3Form_SameOp<60, 154, (outs vsrc:$XT), (ins),
                        "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
                        [(set v4i32:$XT, (v4i32 immAllZerosV))]>;
     def XXLXORdpz : XX3Form_SetZero<60, 154,
                          (outs vsfrc:$XT), (ins),
                          "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
                          [(set f64:$XT, (fpimm0))]>;
     def XXLXORspz : XX3Form_SetZero<60, 154,
                          (outs vssrc:$XT), (ins),
def XXLEQV : XX3Form<60, 186,
                          "xxleqv $XT, $XA, $XB", IIC_VecGeneral,
                          [(set v4i32:$XT, (vnot_ppc (xor v4i32:$XA, v4i32:$XB)))]>;
     def XXLNAND : XX3Form<60, 178,
                           (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                           "xxlnand $XT, $XA, $XB", IIC_VecGeneral,
                           [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA,
                                                     v4i32:$XB)))]>;
   } // isCommutable
   
   def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
             (XXLEQV $A, $B)>;
 
+  let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
+      isReMaterializable = 1 in {
+    def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins),
+                         "xxleqv $XT, $XT, $XT", IIC_VecGeneral,
+                         [(set v4i32:$XT, (v4i32 immAllOnesV))]>;
+  }
+  
+  def : Pat<(v4i32 (bitconvert (v16i8 immAllOnesV))),
+            (XXLEQVOnes)>;
+
   def XXLORC : XX3Form<60, 170,
                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                        "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
                        [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
 
   // VSX scalar loads introduced in ISA 2.07
   let mayLoad = 1, mayStore = 0 in {
     let CodeSize = 3 in
     def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins memrr:$src),
                          "lxsspx $XT, $src", IIC_LdStLFD, []>;
     def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins memrr:$src),
                           "lxsiwax $XT, $src", IIC_LdStLFD, []>;
     def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src),
                           "lxsiwzx $XT, $src", IIC_LdStLFD, []>;

 // (move to FPR, nothing else needed)
 def : Pat<(f64 (bitconvert i64:$S)),
           (f64 (MTVSRD $S))>;
 }
 
 // Materialize a zero-vector of long long
 def : Pat<(v2i64 immAllZerosV),
           (v2i64 (XXLXORz))>;
+
 }
 
 def AlignValues {
   dag F32_TO_BE_WORD1 = (v4f32 (XXSLDWI (XSCVDPSPN $B), (XSCVDPSPN $B), 3));
   dag I32_TO_BE_WORD1 = (COPY_TO_REGCLASS (MTVSRWZ $B), VSRC);
 }
 
 // The following VSX instructions were introduced in Power ISA 3.0
def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
               (v4i32 (MTVSRWS $A))>;
     def : Pat<(v16i8 (build_vector immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
                                    immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
                                    immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
                                    immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
                                    immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
                                    immAnyExt8:$A)),
               (v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>;
-    def : Pat<(v16i8 immAllOnesV),
-              (v16i8 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
-    def : Pat<(v8i16 immAllOnesV),
-              (v8i16 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
-    def : Pat<(v4i32 immAllOnesV),
-              (v4i32 (XXSPLTIB 255))>;
-    def : Pat<(v2i64 immAllOnesV),
-              (v2i64 (XXSPLTIB 255))>;
     def : Pat<(v4i32 (scalar_to_vector FltToIntLoad.A)),
               (v4i32 (XVCVSPSXWS (LXVWSX xoaddr:$A)))>;
     def : Pat<(v4i32 (scalar_to_vector FltToUIntLoad.A)),
               (v4i32 (XVCVSPUXWS (LXVWSX xoaddr:$A)))>;
     def : Pat<(v4i32 (scalar_to_vector DblToIntLoadP9.A)),
               (v4i32 (XXSPLTW (COPY_TO_REGCLASS
                                 (XSCVDPSXWS (DFLOADf64 iaddrX4:$A)), VSRC), 1))>;
     def : Pat<(v4i32 (scalar_to_vector DblToUIntLoadP9.A)),

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

 entry:
   ret <4 x i32> zeroinitializer
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <4 x i32> @allOnei() {
 ; P9BE-LABEL: allOnei:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    xxspltib v2, 255
+; P9BE-NEXT:    xxleqv v2, v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: allOnei:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    xxspltib v2, 255
+; P9LE-NEXT:    xxleqv v2, v2, v2
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: allOnei:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    vspltisb v2, -1
+; P8BE-NEXT:    xxleqv v2, v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: allOnei:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    vspltisb v2, -1
+; P8LE-NEXT:    xxleqv v2, v2, v2
 ; P8LE-NEXT:    blr
 entry:
   ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <4 x i32> @spltConst1i() {
 ; P9BE-LABEL: spltConst1i:

 entry:
   ret <4 x i32> zeroinitializer
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <4 x i32> @allOneui() {
 ; P9BE-LABEL: allOneui:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    xxspltib v2, 255
+; P9BE-NEXT:    xxleqv v2, v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: allOneui:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    xxspltib v2, 255
+; P9LE-NEXT:    xxleqv v2, v2, v2
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: allOneui:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    vspltisb v2, -1
+; P8BE-NEXT:    xxleqv v2, v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: allOneui:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    vspltisb v2, -1
+; P8LE-NEXT:    xxleqv v2, v2, v2
 ; P8LE-NEXT:    blr
 entry:
   ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <4 x i32> @spltConst1ui() {
 ; P9BE-LABEL: spltConst1ui:

llvm/test/CodeGen/PowerPC/sat-add.ll

; CHECK-NEXT:    blr
   %r = add <4 x i32> %s, <i32 42, i32 42, i32 42, i32 42>
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    addi 3, 3, .LCPI31_0@toc@l
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 3, 2, 3
 ; CHECK-NEXT:    vcmpgtuw 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 35, 36, 34
+; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
   %c = icmp ugt <4 x i32> %x, %a
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI32_1@toc@ha
-; CHECK-NEXT:    vspltisb 5, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    addi 3, 3, .LCPI32_1@toc@l
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI32_0@toc@l
 ; CHECK-NEXT:    vcmpgtuw 3, 2, 3
 ; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 4
-; CHECK-NEXT:    xxsel 34, 34, 37, 35
+; CHECK-NEXT:    xxsel 34, 34, 0, 35
 ; CHECK-NEXT:    blr
   %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
   %c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
 define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
; CHECK-NEXT:    blr
   %r = add <4 x i32> %s, %y
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_sum(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vadduwm 3, 2, 3
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtuw 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 35, 36, 34
+; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <4 x i32> %x, %y
   %c = icmp ugt <4 x i32> %x, %a
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxlnor 36, 35, 35
-; CHECK-NEXT:    vspltisb 5, -1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtuw 4, 2, 4
 ; CHECK-NEXT:    vadduwm 2, 2, 3
-; CHECK-NEXT:    xxsel 34, 34, 37, 36
+; CHECK-NEXT:    xxsel 34, 34, 0, 36
 ; CHECK-NEXT:    blr
   %noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
   %a = add <4 x i32> %x, %y
   %c = icmp ugt <4 x i32> %x, %noty
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 

llvm/test/CodeGen/PowerPC/setcc-logic.ll

; CHECK-NEXT:    blr
   %b = icmp eq <4 x i32> %Q, zeroinitializer
   %c = and <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_sign_bits_clear_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 36, 36, 36
 ; CHECK-NEXT:    xxlor 34, 34, 35
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 4
 ; CHECK-NEXT:    blr
   %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = and <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_bits_set_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 36, 36, 36
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
 ; CHECK-NEXT:    blr
   %a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = and <4 x i1> %a, %b
   ret <4 x i1> %c
 }
; CHECK-NEXT:    blr
   %b = icmp slt <4 x i32> %Q, zeroinitializer
   %c = or <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_bits_clear_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 36, 36, 36
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
 ; CHECK-NEXT:    xxlnor 34, 34, 34
 ; CHECK-NEXT:    blr
   %a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = or <4 x i1> %a, %b
   ret <4 x i1> %c
 }
 
 define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_sign_bits_clear_vec:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 4, -1
+; CHECK-NEXT:    xxleqv 36, 36, 36
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 4
 ; CHECK-NEXT:    blr
   %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
   %c = or <4 x i1> %a, %b
   ret <4 x i1> %c
 }

llvm/test/CodeGen/PowerPC/signbit-shift.ll

; CHECK-NEXT:    blr
   %e = zext i1 %c to i32
   %r = add i32 %e, 41
   ret i32 %r
 }
 
 define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: add_zext_ifpos_vec_splat:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 3, -1
+; CHECK-NEXT:    xxleqv 35, 35, 35
 ; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI2_0@toc@l
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vsubuwm 2, 3, 2
 ; CHECK-NEXT:    blr
   %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = zext <4 x i1> %c to <4 x i32>
; CHECK-NEXT:    blr
   %e = sext i1 %c to i32
   %r = add i32 %e, 42
   ret i32 %r
 }
 
 define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: add_sext_ifpos_vec_splat:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vspltisb 3, -1
+; CHECK-NEXT:    xxleqv 35, 35, 35
 ; CHECK-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI6_0@toc@l
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = sext <4 x i1> %c to <4 x i32>

llvm/test/CodeGen/PowerPC/vselect-constants.ll

; CHECK-NEXT:    blr
   %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_0_or_minus1_vec:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, 1
-; CHECK-NEXT:    vspltisb 4, -1
 ; CHECK-NEXT:    xxland 34, 34, 35
-; CHECK-NEXT:    vadduwm 2, 2, 4
+; CHECK-NEXT:    xxleqv 35, 35, 35
+; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_0_or_minus1_vec:
 ; CHECK:       # %bb.0: