[NFC][PowerPC]Change ADDIStocHA to ADDIStocHA8 to follow 64-bit naming convention

[Xiangling_L]

Summary

Since we are planning to add ADDIStocHA for 32bit in later patch, we decided to change 64bit one first to follow naming convention with 8 behind opcode.

[jsji]

Please also remember to add [PowerPC] to title for all powerpc related patches. Thanks.

Should also update one comments .
lib/Target/PowerPC/PPCISelLowering.cpp:14316: // is that for large code model we have ADDISTocHa + LDtocL and for

llvm/lib/Target/PowerPC/P9InstrResources.td

151

Do we have plan to add ADDItocL8 as well?
Why not use (8)? so that we don't need to update this again for ADDItocL8 ?

[sfertile]

llvm/lib/Target/PowerPC/P9InstrResources.td

151

Do we have plan to add ADDItocL8 as well?

Not in the near term, although from what I understand of AIX we will need to add one if we add an option similar to XL's -qtocdata for 32-bit code.

Why not use (8)? so that we don't need to update this again for ADDItocL8 ?

I think this is a good suggestion

[Xiangling_L]

use (8)? + update a comment

llvm/lib/Target/PowerPC/P9InstrResources.td

151

Thank you for your suggestion, I will update it to use (8)?. And we haven't spot any place where ADDItocL is needed on AIX since AIX is always toc-referenced. So I guess probably we don't need to update it for now.

[Xiangling_L]

minor change

[sfertile]

LGTM.

[jsji]

LGTM, sorry for late response.

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
     (instregex "NAND(8)?(o)?$"),
     (instregex "AND(C)?(8)?(o)?$"),
     (instregex "NOR(8)?(o)?$"),
     (instregex "OR(C)?(8)?(o)?$"),
     (instregex "EQV(8)?(o)?$"),
     (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(o)?$"),
     (instregex "ADD(4|8)(TLS)?(_)?$"),
     (instregex "NEG(8)?$"),
-    (instregex "ADDI(S)?toc(HA|L)$"),
+    (instregex "ADDI(S)?toc(HA8|HA|L)$"),
     COPY,
     MCRF,
     MCRXRX,
     XSNABSDP,
     XSXEXPDP,
     XSABSDP,
     XSNEGDP,
     XSCPSGNDP,

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

case PPC::LDtoc: {
     const MCExpr *Exp =
       MCSymbolRefExpr::create(TOCEntry, MCSymbolRefExpr::VK_PPC_TOC,
                               OutContext);
     TmpInst.getOperand(1) = MCOperand::createExpr(Exp);
     EmitToStreamer(*OutStreamer, TmpInst);
     return;
   }
 
-  case PPC::ADDIStocHA: {
-    // Transform %xd = ADDIStocHA %x2, @sym
+  case PPC::ADDIStocHA8: {
+    // Transform %xd = ADDIStocHA8 %x2, @sym
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
 
     // Change the opcode to ADDIS8.  If the global address is external, has
     // common linkage, is a non-local function address, or is a jump table
     // address, then generate a TOC entry and reference that.  Otherwise
     // reference the symbol directly.
     TmpInst.setOpcode(PPC::ADDIS8);
     const MachineOperand &MO = MI->getOperand(2);
     assert((MO.isGlobal() || MO.isCPI() || MO.isJTI() ||
             MO.isBlockAddress()) &&
-           "Invalid operand for ADDIStocHA!");
+           "Invalid operand for ADDIStocHA8!");
     MCSymbol *MOSymbol = nullptr;
     bool GlobalToc = false;
 
     if (MO.isGlobal()) {
       const GlobalValue *GV = MO.getGlobal();
       MOSymbol = getSymbol(GV);
       unsigned char GVFlags = Subtarget->classifyGlobalReference(GV);
       GlobalToc = (GVFlags & PPCII::MO_NLP_FLAG);
case PPC::LDtocL: {
     }
     else if (MO.isGlobal()) {
       const GlobalValue *GV = MO.getGlobal();
       MOSymbol = getSymbol(GV);
       LLVM_DEBUG(
           unsigned char GVFlags = Subtarget->classifyGlobalReference(GV);
           assert((GVFlags & PPCII::MO_NLP_FLAG) &&
                  "LDtocL used on symbol that could be accessed directly is "
-                 "invalid. Must match ADDIStocHA."));
+                 "invalid. Must match ADDIStocHA8."));
       MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
     }
 
     const MCExpr *Exp =
       MCSymbolRefExpr::create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_LO,
                               OutContext);
     TmpInst.getOperand(1) = MCOperand::createExpr(Exp);
     EmitToStreamer(*OutStreamer, TmpInst);

llvm/lib/Target/PowerPC/PPCFastISel.cpp

unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
   // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
   if (CModel == CodeModel::Small) {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
             TmpReg)
       .addConstantPoolIndex(Idx).addReg(PPC::X2);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
       .addImm(0).addReg(TmpReg).addMemOperand(MMO);
   } else {
-    // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
+    // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA8(X2, Idx)).
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
             TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
     // But for large code model, we must generate a LDtocL followed
     // by the LF[SD].
     if (CModel == CodeModel::Large) {
       unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
               TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
             DestReg)
         .addGlobalAddress(GV)
         .addReg(PPC::X2);
   else {
     // If the address is an externally defined symbol, a symbol with common
     // or externally available linkage, a non-local function address, or a
     // jump table address (not yet needed), or if we are generating code
     // for large code model, we generate:
-    //       LDtocL(GV, ADDIStocHA(%x2, GV))
+    //       LDtocL(GV, ADDIStocHA8(%x2, GV))
     // Otherwise we generate:
-    //       ADDItocL(ADDIStocHA(%x2, GV), GV)
-    // Either way, start with the ADDIStocHA:
+    //       ADDItocL(ADDIStocHA8(%x2, GV), GV)
+    // Either way, start with the ADDIStocHA8:
     unsigned HighPartReg = createResultReg(RC);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
             HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
 
     unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
     if (GVFlags & PPCII::MO_NLP_FLAG) {
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
               DestReg).addGlobalAddress(GV).addReg(HighPartReg);
     } else {
       // Otherwise generate the ADDItocL.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

case PPCISD::TOC_ENTRY: {
     // described below.  Otherwise we allow SelectCodeCommon to handle this,
     // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
     CodeModel::Model CModel = TM.getCodeModel();
     if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
       break;
 
     // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
     // If it must be toc-referenced according to PPCSubTarget, we generate:
-    //   LDtocL(@sym, ADDIStocHA(%x2, @sym))
+    //   LDtocL(@sym, ADDIStocHA8(%x2, @sym))
     // Otherwise we generate:
-    //   ADDItocL(ADDIStocHA(%x2, @sym), @sym)
+    //   ADDItocL(ADDIStocHA8(%x2, @sym), @sym)
     SDValue GA = N->getOperand(0);
     SDValue TOCbase = N->getOperand(1);
-    SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
+    SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA8, dl, MVT::i64,
                                          TOCbase, GA);
     if (PPCLowering->isAccessedAsGotIndirect(GA)) {
       // If it is access as got-indirect, we need an extra LD to load
       // the address.
       SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
                                           SDValue(Tmp, 0));
       transferMemOperands(N, MN);
       ReplaceNode(N, MN);
if (ReplaceFlags) {
       if (Offset < 0 || Offset > MaxDisplacement) {
         // If we have a addi(toc@l)/addis(toc@ha) pair, and the addis has only
         // one use, then we can do this for any offset, we just need to also
         // update the offset (i.e. the symbol addend) on the addis also.
         if (Base.getMachineOpcode() != PPC::ADDItocL)
           continue;
 
         if (!HBase.isMachineOpcode() ||
-            HBase.getMachineOpcode() != PPC::ADDIStocHA)
+            HBase.getMachineOpcode() != PPC::ADDIStocHA8)
           continue;
 
         if (!Base.hasOneUse() || !HBase.hasOneUse())
           continue;
 
         SDValue HImmOpnd = HBase.getOperand(1);
         if (HImmOpnd != ImmOpnd)
           continue;

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src),
                    "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64,
                    Requires<[IsISA3_0]>;
 }
 }
 
 // Support for medium and large code model.
 let hasSideEffects = 0 in {
 let isReMaterializable = 1 in {
-def ADDIStocHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
-                       "#ADDIStocHA", []>, isPPC64;
+def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
+                       "#ADDIStocHA8", []>, isPPC64;
 def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
                      "#ADDItocL", []>, isPPC64;
 }
 let mayLoad = 1 in
 def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
                    "#LDtocL", []>, isPPC64;
 }
 

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

default:
     // flag set.
     llvm_unreachable("Unknown rematerializable operation!");
     break;
   case PPC::LI:
   case PPC::LI8:
   case PPC::LIS:
   case PPC::LIS8:
   case PPC::QVGPCI:
-  case PPC::ADDIStocHA:
+  case PPC::ADDIStocHA8:
   case PPC::ADDItocL:
   case PPC::LOAD_STACK_GUARD:
   case PPC::XXLXORz:
   case PPC::XXLXORspz:
   case PPC::XXLXORdpz:
   case PPC::V_SET0B:
   case PPC::V_SET0H:
   case PPC::V_SET0:

llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir

 ...
 ---
 name:            func_7
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x2
 
-    %0:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @g_51
+    %0:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @g_51
     %1:g8rc_and_g8rc_nox0 = LDtocL @g_51, killed %0, implicit $x2 :: (load 8)
     %2:gprc = LI 0
     %3:crrc = CMPLWI killed %2, 0
     BCC 76, killed %3, %bb.2
 
   bb.1:
     %4:g8rc = ADDI8 killed %1, 24
     B %bb.4

 
 # Original TR (and 2013-07-01-PHIElimBug.ll) was about verifier errors for bb.3.
 #
 # I got a feeling that we also need to have some checks to see that # the code
 # is correct in some way. Hopefully this test case is stable enough to verify
 # the full MIR like this.
 #
 # CHECK:       bb.0:
-# CHECK:         %0:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @g_51
+# CHECK:         %0:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @g_51
 # CHECK-NEXT:    %1:g8rc_and_g8rc_nox0 = LDtocL @g_51, killed %0, implicit killed $x2 :: (load 8)
 # CHECK-NEXT:    %2:gprc = LI 0
 # CHECK-NEXT:    %3:crrc = CMPLWI killed %2, 0
 # CHECK-NEXT:    BCC 76, killed %3, %bb.2
 # CHECK:       bb.1:
 # CHECK:         %4:g8rc = ADDI8 killed %1, 24
 # CHECK-NEXT:    %16:g8rc_and_g8rc_nox0 = COPY killed %4
 # CHECK-NEXT:    B %bb.4

llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir

bb.0.entry:
     $x0 = MFLR8 implicit $lr8
     STD $x0, 16, $x1
     $x1 = STDU $x1, -144, $x1
     STD killed $x29, 120, $x1 :: (store 8 into %fixed-stack.1)
     STD killed $x30, 128, $x1 :: (store 8 into %fixed-stack.0, align 16)
     $x30 = OR8 $x4, $x4
     $x3 = LD 0, killed $x3 :: (load 8 from %ir.p1)
     $x29 = ADDI8 killed $x3, -48
-    $x3 = ADDIStocHA $x2, @tasklist_lock
+    $x3 = ADDIStocHA8 $x2, @tasklist_lock
     $x3 = LDtocL @tasklist_lock, killed $x3, implicit $x2 :: (load 8 from got)
     BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
     $r3 = LI 0
     STW killed $r3, 0, killed $x30 :: (volatile store 4 into %ir.p2)
     INLINEASM &"#compiler barrier", 25
     INLINEASM &"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber $r3, 851977, killed $x29, 12, implicit-def dead early-clobber $cr0
     ; CHECK-LABEL: @mm_update_next_owner
     ; CHECK-NOT: lwarx 29, 0, 29

llvm/test/CodeGen/PowerPC/licm-tocReg.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
-; The instructions ADDIStocHA/LDtocL are used to calculate the address of
+; The instructions ADDIStocHA8/LDtocL are used to calculate the address of
 ; globals. The ones that are in bb.3.if.end could not be hoisted by Machine
 ; LICM due to BCTRL_LDinto_toc in bb2.if.then.  This call causes the compiler
 ; to insert a save TOC to stack before the call and load into X2 to restore TOC
 ; after. By communicating to Machine LICM that X2 is guaranteed to have the
 ; same value before and after BCTRL_LDinto_toc, these instructions can be
 ; hoisted out of bb.3.if.end to outside of the loop.
 
 ; Pre Machine LICM MIR
 ;
 ;body:
 ;  bb.0.entry:
 ;    successors: %bb.2.if.then(0x40000000), %bb.3.if.end(0x40000000)
 ;    liveins: %x3
 ;
 ;    %4 = COPY %x3
-;    %5 = ADDIStocHA %x2, @ga
+;    %5 = ADDIStocHA8 %x2, @ga
 ;    %6 = LDtocL @ga, killed %5 :: (load 8 from got)
 ;    %7 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
-;    %8 = ADDIStocHA %x2, @gb
+;    %8 = ADDIStocHA8 %x2, @gb
 ;    %9 = LDtocL @gb, killed %8 :: (load 8 from got)
 ;    %10 = LWZ 0, killed %9 :: (volatile dereferenceable load 4 from @gb)
 ;    %0 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
 ;    %11 = CMPW killed %7, killed %10
 ;    BCC 44, killed %11, %bb.2.if.then
 ;    B %bb.3.if.end
 ;
 ;  bb.2.if.then:

 ;    %x3 = COPY %22
 ;    BLR8 implicit %lr8, implicit %rm, implicit %x3
 ;
 ;  bb.3.if.end:
 ;    successors: %bb.2.if.then(0x04000000), %bb.3.if.end(0x7c000000)
 ;
 ;    %2 = PHI %0, %bb.0.entry, %3, %bb.3.if.end
 ;    %12 = ADDI %2, 1
-;    %13 = ADDIStocHA %x2, @ga
+;    %13 = ADDIStocHA8 %x2, @ga
 ;    %14 = LDtocL @ga, killed %13 :: (load 8 from got)
 ;    STW killed %12, 0, %14 :: (volatile store 4 into @ga)
 ;    %15 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
-;    %16 = ADDIStocHA %x2, @gb
+;    %16 = ADDIStocHA8 %x2, @gb
 ;    %17 = LDtocL @gb, killed %16 :: (load 8 from got)
 ;    %18 = LWZ 0, killed %17 :: (volatile dereferenceable load 4 from @gb)
 ;    %3 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
 ;    %19 = CMPW killed %15, killed %18
 ;    BCC 44, killed %19, %bb.2.if.then
 ;    B %bb.3.if.end
 
 @ga = external global i32, align 4

llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir

frameInfo:
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.entry:
     liveins: $x2
 
-    %0 = ADDIStocHA $x2, @b
+    %0 = ADDIStocHA8 $x2, @b
     %1 = LD target-flags(ppc-toc-lo) @b, killed %0 :: (load 8 from @b)
     %2 = LWZ 0, %1 :: (load 4 from %ir.0)
     %3 = LI 0
     %4 = RLWIMI %3, killed %2, 0, 0, 31
     ; CHECK-LABEL: name: main
     ; CHECK: %[[REG1:[0-9]+]]:gprc = LI 0
     ; CHECK: %[[REG2:[0-9]+]]:gprc = COPY %[[REG1]]
     ; CHECK: %[[REG2]]:gprc = RLWIMI %[[REG2]], killed %2, 0, 0, 31
     %8 = RLWIMI %3, %4, 0, 0, 31
     STW %4, 0, %1 :: (store 4 into %ir.0)
     %10 = EXTSW_32_64 %8
     STW %8, 0, %1 :: (store 4 into %ir.0)
     $x3 = COPY %10
     BLR8 implicit $x3, implicit $lr8, implicit $rm
 
 ...

llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir

 stack:           []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.5(0x30000000), %bb.1(0x50000000)
     liveins: $x2
 
-    %3:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @b
+    %3:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @b
     %4:gprc = LWZ target-flags(ppc-toc-lo) @b, killed %3, implicit $x2 :: (dereferenceable load 4 from @b)
     %5:crrc = CMPLWI killed %4, 0
     BCC 76, killed %5, %bb.5
     B %bb.1
 
   bb.1.while.body.preheader:
     successors: %bb.2(0x80000000)
     liveins: $x2
 
-    %6:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @d
+    %6:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @d
     %7:gprc = LWZ target-flags(ppc-toc-lo) @d, killed %6, implicit $x2 :: (dereferenceable load 4 from @d)
     %8:crrc = CMPWI killed %7, 0
     %0:crbitrc = COPY killed %8.sub_eq
     %9:crbitrc = CRUNSET
     %19:gprc_and_gprc_nor0 = LI 0
     %20:gprc_and_gprc_nor0 = LI 1
-    %22:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @c
-    %10:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @e
-    %13:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @a
+    %22:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @c
+    %10:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @e
+    %13:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @a
     %14:g8rc_and_g8rc_nox0 = ADDItocL killed %13, @a, implicit $x2
 
   bb.2.while.body:
     successors: %bb.4(0x30000000), %bb.3(0x50000000)
     liveins: $x2
 
     %24:crbitrc = COPY %9
     BC %0, %bb.4